28. Audio digital filter (ADF)

This section applies only to STM32U375/385 and STM32U3B5/3C5 devices.

28.1 ADF introduction

The audio digital filter (ADF) is a high-performance module dedicated to the connection of external sigma-delta ( \( \Sigma\Delta \) ) modulators. It is mainly targeted for the following applications:

• • audio capture signals
• • metering

The ADF features one digital serial interface (SITF0) and one digital filter (DFLT0) with flexible digital processing options in order to offer up to 24-bit final resolution.

The ADF serial interface supports several standards allowing the connection of various \( \Sigma\Delta \) modulator sensors:

• • SPI interface
• • Manchester coded 1-wire interface
• • PDM interface

The ADF converts an input data stream into clean decimated digital data words. This conversion is done thanks to low-pass digital filters and decimation blocks. In addition, it is possible to insert a high-pass filter.

The conversion speed and resolution are adjustable according to configurable parameters for digital processing: filter bypass, filter order, decimation ratio. The maximum output data resolution is up to 24 bits. There are two conversion modes: single conversion and continuous modes. The data can be automatically stored in a system RAM buffer through DMA, thus reducing the software overhead.

A sound activity detector (SAD) is available for the detection of sounds or voice signals. The SAD is connected at the output of the DFLT0. Several parameters can be programmed in order to adjust properly the SAD to the sound environment. The SAD strongly reduces the power consumption by preventing the storage of samples into the system memory, as long as the observed signal does not match the programmed criteria.

The digital processing is performed using only the kernel clock. The ADF requests the bus interface clock (AHB clock) only when data must be transferred or when a specific event requests the attention of the system processor.

28.2 ADF main features

• • AHB Interface
• • 1 serial digital input:
  • – configurable SPI interface to connect various digital sensors
  • – configurable Manchester coded interface support
  • – compatible with PDM interface to support digital microphones
• • 2 common clocks input/output for \( \Sigma\Delta \) modulators
• • 1 flexible digital filter path including:

• – A MCIC filter configurable in Sinc ⁴ or Sinc ⁵ filter with an adjustable decimation ratio
• – A reshape filter to improve the out-of band rejection and in-band ripple
• – A high-pass filter to cancel the DC offset
• – Gain control
• – Saturation blocks
• • Clock absence detector
• • Sound activity detector
• • 24-bit signed output data resolution
• • Continuous or single conversion
• • Possibility to delay the selected bitstream
• • One trigger input
• • Autonomous functionality in Stop mode(s)
• • DMA can be used to read the conversion data
• • Interrupts services

28.3 ADF implementation

Table 250. ADF features ⁽¹⁾

1. 'X' = supported, '-' = not supported.

2. Only Stop 0 and Stop 1 modes.

28.4 ADF functional description

28.4.1 ADF block diagram

Figure 253. ADF block diagram

1. 1. Refer to Section 28.3: ADF implementation to check if the SAD is available.
2. 2. Refer to Section 28.3: ADF implementation to check if the ADCITF is available, and which ADCs are connected.
3. 3. The number of trigger inputs depends on the product. Refer to Table 253 for details.

28.4.2 ADF pins and internal signals

Table 251. ADF external pins

Table 252. ADF internal signals

1. Only available on STM32U3B5/3C5 devices.

1. This section applies only to STM32U375/385 and STM32U3B5/3C5 devices.

28.4.3 Serial input interface (SITF)

The SITF0 input interface allows the connection of the external sensor to the digital filter via the bitstream matrix (BSMX). The SITF0 can be configured in the following modes:

• • LF_MASTER SPI mode (low-frequency)
• • normal SPI mode
• • Manchester mode

The data from the serial interface is routed to the filter in order to perform the PDM to PCM conversion and the sound activity detection.

The serial interface is enabled by setting the SITFEN bit to 1. Once the interface is enabled, it receives serial data from the external \( \Sigma\Delta \) modulator.

Note: Before enabling the serial interface, the user must insure that the adf_proc_ck is already enabled (see Section 28.4.5: Clock generator (CKGEN) for details).

The SITF0 is controlled via the ADF serial interface control register 0 (ADF_SITF0CR) .

As shown in the Figure 254 , ADF_CCK0 or ADF_CCK1 can be selected as clock source, in order to sample the incoming bitstream:

• • If the serial interface is programmed in SPI mode, the selected clock source is a copy of the clock present on the ADF_CCK0 or ADF_CCK1 pin.
• • If the serial interface is programmed in LF_MASTER SPI mode, the selected clock source is the clock directly provided by the CCKDIV to the ADF_CCK0 or ADF_CCK1 pin.

See Table 255 for additional information.

Figure 254. SITF overview

LF_MASTER and normal SPI modes

The LF_MASTER SPI mode is a special mode allowing the use of an adf_proc_ck clock frequency, only two times bigger than the sensor clock. This mode is dedicated to low-power use-cases, using low-speed sensors.

In LF_MASTER SPI mode, the ADF must provide the bitstream clock to the external sensors via ADF_CCK0 and ADF_CCK1 pins. The ADF receives the bitstream data via the serial data input ADF_SDI0.

For the SITF0, the application must select the same clock than the one provided to the external sensor (ADF_CCK0 or ADF_CCK1), in order to guarantee optimal timing performances. This selection is done via SCKSRC[1:0].

The normal SPI interface is a more flexible interface than the LF_MASTER SPI, but the adf_proc_ck frequency must be at least four times higher than the sensor clock.

The application can select ADF_CCK0 or ADF_CCK1 clock for the capture of the data received via the ADF_SDI0 pin.

The ADF can generate a clock to the sensors via ADF_CCK0 or ADF_CCK1 if needed.

For all SPI modes, the serial data is captured using the rising and the falling edge of the selected clock. The SITF0 always provides the following bitstreams:

• • bitstream received using the bitstream clock falling edge (bs0_f)
• • bitstream received using the bitstream clock rising edge (bs0_r)

According to the sensors connected, one of the two bitstreams may not be available.

The application can select the wanted stream via the BSMX matrix.

Figure 255. SPI timing example

To properly synchronize/receive the data stream, the adf_proc_ck frequency must be adjusted according to the constraints listed in Table 256 .

Clock absence detection

A no-clock-transition period may be detected when the serial interface works in normal SPI mode. This feature can be used to detect a clock failure in the SPI link.

The application can program a timeout value via the STH[4:0] bitfield of the SITF0. If the ADF does not detect clock transitions for a duration of \( STH[4:0] \times T_{\text{adf\_proc\_ck}} \) , then the CKABF flag is set.

An interrupt can be generated if CKABIE is set to 1. The STH[4:0] bitfield is in the ADF serial interface control register 0 (ADF_SITF0CR) .

When the serial interface is enabled, the CKABF flag remains to 1 until a first clock transition is detected.

To avoid spurious clock absence detection, the following sequence must be respected:

1. 1. Configure the serial interface in normal SPI mode and enable it.
2. 2. Clear the CKABF flag by writing CKABF bit to 1.

If no clock transition is detected on the serial interface, the hardware immediately sets the CKABF flag to 1.

1. 3. Read the CKABF flag:
   • – If CKABF = 1, go back to step 2.
   • – If CKABF = 0, a clock has been detected. The CKABIE bit can be set to 1 if the application wants an interrupt on detection of a clock absence.

Note: The clock absence detection feature is not available in the LF_MASTER SPI mode.

Manchester mode

In Manchester coded format, the ADF receives data stream from the external sensor via the ADF_SDI0 pin only.

The ADF_CCK0 and ADF_CCK1 pins are not needed in this mode.

Decoded data and clock signals are recovered from serial stream after Manchester decoding. They are available on bs0_r. There are two possible settings of Manchester codings:

• • signal rising edge decoded as 0 and signal falling edge decoded as 1
• • signal rising edge decoded as 1 and signal falling edge decoded as 0

Figure 256. Manchester timing example (SITFMOD = 11)

To decode the incoming Manchester stream, the user must program STH[4:0] in the ADF serial interface control register 0 (ADF_SITF0CR) . The STH[4:0] bitfield is used by the SITF0 to estimate the Manchester symbol length and to detect a clock absence. An internal counter (MCNT) is restarted every time a transition is detected in the ADF_SDI0 input. It is used to detect short transitions, long transitions or clock absence. A long transition indicates that the data value changed. Figure 256 shows a case where the OVR is around height and STH[4:0] = 5.

The estimated Manchester symbol rate ( \( T_{SYMB} \) ) must respect the following formula:

It is recommended to compute STH as follows:

where OVR represents the ratio between the adf_proc_ck frequency and the expected Manchester symbol frequency. OVR must be higher than five, and the adf_proc_ck clock must be adjusted according to the constraints listed in Table 256 .

The clock absence flag CKABF is set to 1 when no transition is detected during more than \( 2 \times STH[4:0] \times T_{adf\_proc\_ck} \) , or when the SITF0 is not yet synchronized to the incoming Manchester stream. In addition, an interrupt can be generated if the bit CKABIE is set to 1.

When the serial interface is enabled, the ADF must first be synchronized to the incoming Manchester stream. The synchronization ends when a data transition from 0 to 1 or from 1 to 0 (pink circle in the Figure 256 ) is detected.

The end of the synchronization phase can be checked by following the software sequence:

1. 1. Clear the CKABF flag in the ADF DFLT0 interrupt status register 0 (ADF_DFLT0ISR) by writing CKABF bit to 1. If the serial interface is not yet synchronized the hardware immediately set the CKABF flag to 1.
2. 2. Read the CKABF flag:
   • – If CKABF= 1, go back to step 1.
   • – If CKABF = 0, the Manchester interface is synchronized and provides valid data.

Programming example

In the following example, the ADF kernel clock frequency ( \( F_{\text{adf\_ker\_ck}} \) ) is 100 MHz and the received Manchester stream is at about 6 MHz ( \( F_{\text{SYMB}} \) ):

1. 1. Provide a valid \( \text{adf\_proc\_ck} \) to the SITF0.

The \( \text{adf\_proc\_ck} \) frequency must be at least six times higher than the Manchester symbol frequency (means at least 36 MHz).

PROCDIV is programmed to 1 to perform a division by two of the kernel clock. In that case, \( F_{\text{adf\_proc\_ck}} = 50 \) MHz (8.33 times higher than the Manchester symbol frequency).

1. 2. Compute STH.

OVR is given by: \( \text{OVR} = F_{\text{adf\_proc\_ck}} / F_{\text{SYMB}} = 50 \text{ MHz} / 6 \text{ MHz} = 8.33 \) .

The minimum allowed frequency for the Manchester stream is then:

The maximum allowed frequency for the Manchester stream is then:

28.4.4 ADC slave interface (ADCITF)

The ADCs are not always connected to the ADF. Refer to Section 28.3 to check the situation for this product.

The ADF allows the connection of up to two ADCs to the filter path. For the filter, the DATSRC[1:0] bitfield in the ADF digital filter configuration register 0 (ADF_DFLT0ICR) allows the application to select data from the ADCs.

Warning: The ADF does not support receiving interleaved data from one of the ADCITF input.

28.4.5 Clock generator (CKGEN)

The RCC (reset and clock controller) provides the following clocks to the ADF:

• • AHB clock (adf_hclk) used for the register interface
• • kernel clock (adf_ker_ck) mainly used by all other parts of the circuit via the CKGEN

These clocks are not supposed to be phase locked, so all signals crossing those clock domains are resynchronized.

The clock generator (CKGEN) is responsible of the generation of the processing clock, and the clock provided to the ADF_CCK0 and ADF_CCK1 pins. All those clocks are generated from the adf_ker_ck.

The processing clock (adf_proc_ck) is used to run all the signal processing and to re-sample the incoming serial or parallel stream.

To adapt the kernel clock frequency provided by the RCC, the following dividers are available:

• • PROCDIV[6:0] used to adapt the kernel clock frequency to the constraints of the parallel and serial interfaces, and to the processing blocks
• • CCKDIV[3:0] used to adapt the frequency of the ADF_CCK0 and ADF_CCK1 clocks

PROCDIV[6:0] and CCKDIV[3:0] must be programmed when no clock is provided to the dividers (CKGDEN = 0).

The adf_proc_ck generation is controlled by CKGDEN.

In addition, the CKGMOD bit allows the application to define the way to trigger the CCKDIV divider:

• • When CKGMOD = 0, the CCKDIV divider is started as soon as CKGDEN is set to 1.
• • When CKGMOD = 1, the CCKDIV divider is started when CKGDEN is set to 1 and the programmed trigger condition occurred.

All the bits and fields controlling the CKGEN are in the ADF clock generator control register (ADF_CKGCR) .

Figure 257. CKGEN overview

The trigger logic for CKGEN is handled by the block TRG_CK. As shown in Figure 262 , the CCKDIV divider can be triggered on the rising or falling edge of an external trigger source. When the proper trigger condition occurs, the cck_trg signal goes to high, allowing the CCKDIV divider to start. The TRG_CK logic is reset when CKGDEN is set to 0.

This feature can be helpful to synchronize the ADF_CCKy (y = 0,1) clock of several ADF instances, or to synchronize the clock generation to a timer event.

The application can control the activation of the ADF_CCK0 or ADF_CCK1 pin thanks to CCK0EN/CCK1EN and CCK0DIR/CCK1DIR bits:

• • CCKyEN is used to enable the CCKDIV, and thus generates a clock for the external sensors.
• • CCKyDIR is used to control the direction of the ADF_CCKy pin (input or output)

Table 255. Control of the common clock generation ⁽¹⁾

1. The configuration with CCKyEN = 1 and CCKyDIR = 0 is not shown must be avoided (no interest).

Note: The adf_proc_ck must be enabled (by CKGDEN = 1) before enabling other blocks (such as SITF0 or DFLT0).

CKGEN activation sequence example

1. 1. Set CKGDEN to 0.
2. 2. Wait for CKGACTIVE = 0. If CKGDEN was previously enabled, this phase can take two periods of adf_hclk, and two periods of adf_proc_ck.
3. 3. Program PROCDIV[6:0], CKGMOD, CCKDIV[3:0], TRGSRC[3:0], TRGSENS, CCK1EN and CCK0EN.
4. 4. Set CKGDEN to 1.

When needed, at any moment, CCK[1:0]EN bitfield value can be changed without disabling the clock generator.

Clock frequency constraints

Table 256 shows the frequency constraints to receive and process properly the samples.

Note: The reshape filter (RSFLT) needs up to 24 cycles of adf_proc_ck clock to process one sample.

Table 256. Clock constraints with respect to the incoming stream ⁽¹⁾

1. F _{ADF_CCKy} represents the frequency of clock received via ADF_CCKy, or generated via ADF_CCKy. F _SYMB represents the frequency of the received symbol rate for Manchester mode.

28.4.6 Bitstream matrix (BSMX)

The BSMX receives the bitstreams from the serial interface SITF0 and provides the selected stream to the digital filter DFLT0.

As shown in Figure 253 , the SITF0 provides two bitstreams (bs0_r and bs0_f) to the BSMX.

The application to select the wanted stream via the ADF bitstream matrix control register 0 (ADF_BSMX0CR) . This selection is intended to be static.

Figure 258. BSMX overview

BSMX programming sequence example

The BSSEL[4:0] bitfield cannot be changed if the DFLT0 is enabled. The following steps are needed to change the value of BSMX:

1. 1. Set DFLTEN of DFLT0 to 0.
2. 2. Wait for BSMXACTIVE = 0.
3. 3. Program BSSEL[4:0].
4. 4. Set DFLTEN of DFLT0 to 1.

28.4.7 Digital filter processing (DFLT)

The digital filter processing includes the following sub-blocks:

• • symbol remap (SBR)
• • clock skipper delay (DLY)
• • MCIC decimation filter that can be configured in Sinc ⁴ or Sinc ⁵
• • gain control (SCALE)
• • signal saturation (SAT)
• • reshape filter (RSFLT)
• • high-pass filter (HPF)
• • receive RXFIFO

Figure 259 shows the filter path configuration according to CICMOD[2:0]. Several configuration bits are available to configure the digital filter to the application needs.

Figure 259. DFLT overview

Symbol remap and source selection

The symbol remap (SBR) converts the bitstream selected by the BSMX into data usable by the filter path. More especially:

• • The high levels are converted into a 16-bit signed number + 1.
• • The low levels are converted into a 16-bit signed number - 1.

The signal source of the digital filter can be selected via DATSRC[1:0] between the two following:

• • data coming from the BSMX
• • data coming from one of the ADC interfaces (ADCITF2 or 1)

Programmable micro-delay control (DLY)

The digital filter has a delay line that allows the timing adjustment of each stream with the resolution of the bitstream clock.

This feature is particularly helpful in the case of microphone beam forming applications where delays smaller than the final sampling rate must be applied to the incoming stream. This feature can be used when the ADF is synchronized with another MDF instance (if present in the product) for a beam forming application for example.

The delay is performed by discarding a given number of samples from the selected input stream, before samples enter into the CIC filter. This data discarding is done by skipping a given number of data strobe, preventing the CIC filter to take into account those data.

When the wanted amount of data strobe has been skipped, the next incoming samples are strobed normally.

Table 260 shows an example on how to apply dynamically small delay to an incoming stream. For simplification, the CIC filter performs a decimation by height in this example. CIC1 represents the CIC included in the ADF and CIC0 represents a filter from another MDF instance (if present in the product).

Figure 260. Programmable delay

The CIC of the ADF (CIC1) receives a command in order to skip three incoming samples. So the input samples named b10, b11 and b12 are not processed by CIC1. As a consequence, the output sample N+1 generated by CIC0 is built from input samples a[23:16] while the sample N+1 of CIC1 is built from input samples b[26:19].

Finally, the non-skipped data stream looks delayed by three bitstream periods.

Note: When the input data strobes are skipped, the decimation counter remains frozen. As a consequence, the samples delivered by the CIC1 are a bit delayed.

The following steps are needed to program the amount of bitstream clock periods to be skipped:

1. 1. Wait for SKPBF equal to 0.

1. 2. Write SKPDLY[6:0] to the wanted number of bitstream clock periods to be skipped. The SKPBF flag goes immediately to 1, indicating that the delay value entered into SKPDLY[6:0] is under process.
   • – If the DFLT0 is not yet enabled (DFLTEN = 0), then the DLY logic waits for DFLTEN = 1. When the application sets DFLTEN to 1, the DLY logic starts to skip the amount of wanted data strobes.
   • – If the DFLT0 is already enabled (DFLTEN = 1), then the DLY logic immediately starts to skip the amount of wanted data strobes.

When the ADF skipped the amount of wanted data strobes, then SKPBF goes back to 0.

1. 3. If the application needs to skip more data strobes, then the operation must be restarted from step 1.

The effect of the delay performed with this mechanism is cumulative as long as the ADF is enabled. If the application performs a D1 delay followed by a D2 delay, then all other active filters are delayed by D1 + D2.

Note: If SKPDLY[6:0] is written when SKPBF = 1, the write operation is ignored.

Cascaded-integrator-comb (CIC) filter

The CIC digital filters are an efficient implementation of low-pass filters, often used for decimation and interpolation. The CIC frequency response is equal to a \( \text{Sinc}^N \) function, this is why they are often called Sinc filters.

The \( \text{Sinc}^N \) digital filter embedded into the ADF can be configurable in \( \text{Sinc}^4 \) or \( \text{Sinc}^5 \) , according to CICMOD:

• • If CICMOD[2:0] = 4, \( \text{Sinc}^4 \) is selected.
• • If CICMOD[2:0] = 5, \( \text{Sinc}^5 \) is selected.

The filters have the following transfer function:

where N can be 4 or 5, and D is the decimation ratio. D is equal to MCICD+1.

Figure 261. CIC4 and CIC5 frequency response with decimation ratio = 32 or 16

CIC output data size

The size of samples delivered by the CIC ( \( DS_{CIC} \) ), depends on the following parameters:

• • CIC order (N)
• • CIC decimation ratio (D)
• • data size of the input stream ( \( DS_{IN} \) )

The CIC order and decimation ratio must be programmed in order to insure that the data size does not exceed the 26-bit CIC capability.

The following formula gives the output data size ( \( DS_{CIC} \) ) according to the parameters above.

and the CIC gain is given by this formula:

The decimation ratio can be adjusted from 2 to 512 for the CIC filter.

Table 257 gives some data output size in bits for some decimation values, when the data source is a full-scale signal coming from the serial interface or from a 12-bit ADC.

Note: \( DS_{IN} = 1 \) bit for a serial bitstream, but can be up to 16 bits when coming from the ADCITF.

Table 257. Data size according to CIC order and CIC decimation values

Note: For a full-scale input signal, the decimation ratio must not exceed 76 for a Sinc ⁴ and 32 for a Sinc ⁵ .

The LSB parts of the data provided by the CIC is not necessarily significant: it depends on the sensor performances and the ability of the CIC to reject the out-of band noise.

The sample size at CIC output can be adjusted thanks to the SCALE block.

Scaling (SCALE) and saturation (SAT)

The SCALE block allows the application to adjust the amplitude of the signal provided by the CIC, by steps of 3 dB ( \( \pm 0.5 \) dB).

The signal amplitude can be decreased by up to 8 bits ( \( - 48.2 \) dB), and can be increased by up to 12 bits ( \( + 72.2 \) dB).

The gain is adjusted by the SCALE[5:0] bitfield in the ADF digital filter configuration register 0 (ADF_DFLT0C/CR) .

SCALE[5:0] can be changed even if the DFLT0 is enabled. During the gain transition, the signal provided by the filter is disturbed.

Due to internal resynchronization, there is a delay of some cycles of adf_proc_ck clock between the moment where the application writes the new gain, and the moment where the gain is effectively applied to the samples. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back SCALE[5:0] informs the application on the current gain value.

Table 258 shows the possible gain values.

Table 258. Possible gain values

The SAT blocks avoid having a wrap-around of the binary code when the code exceeds its maximal or minimal value.

The ADF performs saturation operations at the following levels:

• • after the SCALE block (performed by the SAT block): The signal is saturated at 24 bits.
• • inside the RSFLT, to insure a good filter behavior
• • at the output of the HPF, to insure that the output signal does not exceed 24 bits

The SATF bit informs the application that a saturation occurred either after the SCALE, inside the RSFLT or after the HPF. In addition, an interrupt can be generated if SATIE is set to 1. As soon as a saturation is detected, the SATF flag is set to 1. It is up to the application to clear this flag in order to be able to detect a new saturation.

Those bits are in the ADF DFLT0 interrupt enable register (ADF_DFLT0IER) and ADF DFLT0 interrupt status register 0 (ADF_DFLT0ISR) .

Gain adjustment policy

To get the best ADF performances, it is important to properly adjust the gain value via SCALE[5:0].

A usual way to adjust the gain is to select the SCALE[5:0] value that gives a final signal amplitude as close as possible to the 24-bit full-scale, for the maximum input signal.

A way to select the optimal gain is detailed below:

1. 1. Check that, for the expected input signal, the data size into the CIC filter does not exceed 26 bits. This can be checked using this formula:

where N represents the CIC order, D the decimation ratio and \( SIN_{pp} \) the maximum peak-to-peak amplitude of the input signal.

\( SIN_{pp} \) can take:

• – a maximum peak-to-peak amplitude of \( 2 (\pm 1) \) , for samples coming from SITF0
• – A maximum peak-to-peak amplitude of 4095 (+ 2047, - 2048), for samples coming from a 12-bit ADC

Example: a Sinc ⁴ can be used with a decimation ratio of 96, if the maximum input signal does not exceed \( \pm 0.35 \) . Indeed:

2. Adjust the SCALE value.

To select the most appropriate SCALE value, the user must check if the RSFLT is used or not. If the RSFLT is used, the data size at SCALE output must not exceed 22 bits, otherwise the data size can be up to 24 bits.

The SCALE value in dB must be selected using this formula:

where NB is equal to 22 if RSFLT is enabled, or 24 if RSFLT is bypassed. \( SCALE_{dB} \) represents the gain value selected by SCALE[5:0].

Example: For a Sinc ⁴ with a decimation ratio of 96 and a \( SIN_{pp} \) of 0.7.

• – If the RSFLT is bypassed:

\( SCALE_{dB} \) value must be lower than - 11 dB, the closest lower value is - 12dB (SCALE[5:0] = 0x2C).

• – If the RSFLT is enabled:

\( SCALE_{dB} \) value must be lower than - 23 dB, the closest lower value is - 24.1 dB (SCALE[5:0] = 0x28).

If SCALE[5:0] is set to a higher value, then a saturation may occur. An event flag informs the user if a saturation occurred.

Table 259 proposes gain values for different filter configurations, when the data comes from the SITF0, according to the MCIC order, and the MCIC decimation ratio. This table is not exhaustive and considers a full-scale input signal (see Section 28.7.5: Total ADF gain for details).

Reshaping filter (RSFLT)

In addition to the CIC, the ADF offers a reshaping IIR filter mainly dedicated to the audio application, but also usable in other applications.

When the RSFLT is used, the sample size at its input must not exceed 22 bits.

The samples at the RSFLT output can be decimated by four or not according to the RSFLTD bit in the ADF reshape filter configuration register 0 (ADF_DFLT0RSFR) .

The RSFLT can be bypassed by setting RSFBYP to 1 in the ADF reshape filter configuration register 0 (ADF_DFLT0RSFR) .

Table 260 shows which sampling rate must be provided to the RSFLT in order to process the most common audio streams.

The RSFLT cutoff frequency ( \( F_C \) ) depends on the sample rates at its input ( \( F_{RS} \) ), and is given by the following formula:

Table 262 shows the frequency response of the reshape filter.

Figure 262. Reshape filter frequency response normalized ( \( F_{RS} / 2 = 1 \) )

The RSFLT gain is close to 9.3 dB, so the output data size is a little bit lower than 24 bits for a 22-bit wide input signal.

The RSFLT takes 24 clock cycles of adf_proc_ck clock to process one sample at \( F_{RS} \) . When the RSFLT is enabled, the application must insure that the adf_proc_ck is at least 24 times faster \( F_{RS} \) .

The RSFLT generates an event ( rfov_evt ) and sets the RFOVRF flag, if the RSFLT receives a new samples while the previous one is still under processing.

When RFOVRF is set, the samples provided by the RSFLT are invalid. The application must then stop the data acquisition and provides a faster adf_proc_ck clock to the RSFLT.

High-pass filter (HPF)

The high-pass filter suppresses the low-frequency content from the final output data stream in case of continuous conversion mode. The high-pass filter can be enabled or disabled via HPFBYP in the ADF reshape filter configuration register 0 (ADF_DFLT0RSFR) .

The HPF is useful when there is parasitic low-frequency noise (or DC signal) in the input data source that must be removed from the final data.

The HPF is a first order IIR filter and the cut-off frequency can be selected via HPFC[1:0] in the ADF reshape filter configuration register 0 (ADF_DFLT0RSFR) , among the following values:

• • \( 0.000625 \times F_{PCM} \)
• • \( 0.00125 \times F_{PCM} \)
• • \( 0.00250 \times F_{PCM} \)
• • \( 0.00950 \times F_{PCM} \)

Table 261. HPF 3 dB cut-off frequency examples

The HPF output is saturated at 24 bits. The SATF flag is set if a sample is saturated.

28.4.8 Digital filter acquisition modes

The ADF offers the following modes to perform a data capture:

• • asynchronous continuous acquisition mode
• • asynchronous single-shot acquisition mode
• • synchronous continuous acquisition mode
• • synchronous single-shot acquisition mode
• • window continuous acquisition mode

Note: To perform a data capture, the filter, the interface providing the data (SITF0 or ADCITF) and the CKGEN must be enabled. If needed, the ADF_CCK0 or ADF_CCK1 must be enabled as well.

The filter can be stopped immediately when DFLTEN is set to 0. This action resets the filter and flushes the RXFIFO. The DFLTACTIVE flag also goes back to 0 when the RXFIFO and the filter is reset.

Table 263 shows a simplified view of the trigger logic available for each filter and for the clock generator.

Figure 263. Trigger logic for DFLT and CKGEN

A block common to all TRIG blocks performs the rising and falling edges detection and the resynchronization of the input trigger to the adf_ker_ck clock domain. This implementation allows the application to use triggers with pulse width smaller than the adf_ker_ck period.

In synchronous modes, the TRIG block offers the possibility to select adf_trgi or TRGO bit as trigger sources. The TRGO bit is in the ADF global control register (ADF_GCR) .

The edge sensitivity can also be selected.

Asynchronous continuous acquisition mode

This mode allows the application to start a continuous acquisition by simply writing the DFLTEN bit to 1.

The asynchronous continuous acquisition mode is selected when ACQMOD[2:0] = 0.

The sequence below shows the most important programming steps (assuming that DFLTEN is set to 0):

1. 1. Configure and enable the clock generator (CKGEN) so that the adf_proc_ck frequency is compatible with the targeted application (see examples in Table 265 ).
2. 2. Enable the CKGEN (CKGDEN = 1) and, if needed, enable the ADF_CCK0 and ADF_CCK1 clocks.
3. 3. Program the filter configuration and set the ACQMOD[2:0] to 0.
4. 4. Set to 1 the SITFEN bit of the serial data interface.
5. 5. Before setting DFLTEN to 1, wait for DFLTACTIVE = 0: it insures that the previous filter deactivation sequence terminated properly.
6. 6. When DFLTEN is set to 1, the acquisition sequence starts immediately.

Figure 264 shows a simplified example of the samples generated by the DFLT0.

Figure 264. Asynchronous continuous mode (ACQMOD[2:0] = 0)

Note: The acquisition can be stopped by setting DFLTEN back to 0. This resets the filter and flushes the RXFIFO, so the samples located into the RXFIFO are lost. The ongoing DMA transfer is properly terminated. DFLTACTIVE goes back to 0 when the filter chain is reset and the RXFIFO flushed.

Asynchronous single-shot acquisition mode

This mode allows the application to start the acquisition of one sample by simply writing the DFLTEN bit to 1.

The asynchronous single-shot acquisition mode is selected when ACQMOD[2:0] = 001.

The sequence below shows the most important programming steps (assuming that DFLTEN is set to 0):

1. 1. Configure and enable the clock generator (CKGEN), so that the adf_proc_ck frequency is compatible with the targeted application (see examples in Table 265 ).
2. 2. Enable the CKGEN (CKGDEN = 1) and, if needed, enable the ADF_CCK0 and ADF_CCK1 clocks.
3. 3. Program the filter configuration, and set the ACQMOD[2:0] to 001.
4. 4. Set to 1 the SITFEN bit.
5. 5. Before setting DFLTEN to 1, wait for DFLTACTIVE = 0: it insures that the previous filter deactivation sequence terminated properly.
6. 6. When DFLTEN is set to 1, the filter provides one data to the RXFIFO and stops the acquisition.

To trigger a new acquisition, the application must:

1. 1. Check that the previous acquisition is completed, by waiting that DFLTRUN = 0.
2. 2. Set again DFLTEN to 1.

This sequence can be repeated every time a new data must be converted.

As shown in Figure 264 , every time DFLTEN is set to 1, an acquisition sequence is triggered. The first samples provided by the filter can be discarded if needed. At the end of each conversion, the decimation counters and filter taps are reset, and the filter is ready to start a new conversion.

If DFLTEN is set to 0 while an acquisition is ongoing, the ongoing conversion is stopped (in the example, S3 is lost). This situation can be avoided with the following steps:

1. 1. Wait for DFLTRUN = 0.
2. 2. Read the sample from the RXFIFO.
3. 3. Set DFLTEN to 0.

Figure 265. Asynchronous single-shot mode (ACQMOD[2:0] = 001)

Note: The acquisition can be stopped by setting DFLTEN back to 0. This resets the filter and flushes the RXFIFO, so the samples located into the RXFIFO are lost. The ongoing DMA transfer is properly terminated. DFLTACTIVE goes back to 0 when the filter chain is reset and the RXFIFO flushed.

Synchronous continuous acquisition mode

This mode allows the application to start a continuous acquisition by using one of the following trigger sources:

• • adf_trgi signal
• • TRGO bit

The Synchronous continuous acquisition mode is selected when ACQMOD[2:0] = 010.

The sequence below shows the most important programming steps (assuming that DFLTEN is set to 0):

1. 1. Configure and enable the clock generator (CKGEN), so that the frequency of adf_proc_ck clock is compatible with the targeted application (see examples in Table 265 ).
2. 2. Enable the CKGEN (CKGDEN = 1) and, if needed, enable the ADF_CCK0 and ADF_CCK1 clocks.
3. 3. Program the filter configuration and set the ACQMOD[2:0] to 010.
4. 4. Set to 1 the bit SITFEN.
5. 5. Select the proper trigger source and sensitivity.
6. 6. Before setting DFLTEN to 1, wait for DFLTACTIVE = 0: it insures that the previous filter deactivation sequence terminated properly.
7. 7. Set DFLTEN to 1.
8. 8. When the trigger condition is met, the filter starts the acquisition.

The TRGSENS bit allows the selection of the trigger edge (rising or falling). The trigger is ignored if an acquisition is ongoing or if DFLTEN is set to 0.

Figure 266 shows a simplified example where the trigger logic is sensitive to a rising edge trigger (TRGSENS = 0). The first rising edge of the trigger signal is ignored because DFLTEN = 0. Then the next rising edge is taken into account and starts the acquisition. All other rising edges are ignored. The trigger logic is re-initialized when DFLTRUN goes back to 0.

Figure 266. Synchronous continuous mode (ACQMOD[2:0] = 010)

Note: The acquisition can be stopped by setting DFLTEN back to 0. This resets the filter and flushes the RXFIFO, so the samples located into the RXFIFO are lost. The ongoing DMA transfer is properly terminated. DFLTACTIVE goes back to 0 when the filter chain is reset and the RXFIFO flushed.

Synchronous single-shot acquisition mode

This mode allows the application to start a single acquisition by using one of the following trigger sources:

• • adf_trgi signal
• • TRGO bit

The Synchronous single-shot acquisition mode is selected when ACQMOD[2:0] = 011.

The sequence below shows the most important programming steps (assuming that DFLTEN is set to 0):

1. 1. Configure and enable the clock generator (CKGEN), so that the frequency of adf_proc_ck clock is compatible with the targeted application (see examples in Table 265 ).
2. 2. Enable the CKGEN and, if needed, enable the ADF_CCK0 and ADF_CCK1 clocks.
3. 3. Program the filter configuration, and set the ACQMOD[2:0] to 011.
4. 4. Set to 1 the SITFEN bit.
5. 5. Select the proper trigger source and sensitivity.
6. 6. Before setting DFLTEN to 1, wait for DFLTACTIVE = 0: it insures that the previous filter deactivation sequence terminated properly.
7. 7. Set DFLTEN to 1.
8. 8. When the trigger condition is met, the filter starts the acquisition and provides one data to the RXFIFO, then the filter is ready to accept a new trigger.

TRGSENS allows the selection of the trigger edge (rising or falling). The trigger is ignored if an acquisition is ongoing, or if DFLTEN is set to 0.

Figure 267 shows a simplified example where the trigger logic is sensitive to a rising edge trigger (TRGSENS = 0). Every-time a trigger rising edge is detected with DFLTEN = 1, an acquisition sequence is triggered. The first samples provided by the filter can be discarded if needed. At the end of each conversion, the decimation counters and filter taps are reset. DFLTRUN is set to 0 and the filter is ready to start a new conversion.

Figure 267. Synchronous single-shot mode (ACQMOD[2:0] = 011)

Note: The acquisition can be stopped by setting DFLTEN back to 0. This resets the filter and flushes the RXFIFO, so the samples located into the RXFIFO are lost. The ongoing DMA transfer is properly terminated. DFLTACTIVE goes back to 0 when the filter chain is reset and the RXFIFO flushed.

Figure 266 shows a case where the DFLTEN is set to 0 while an acquisition is ongoing (the sample S2 is lost). This situation can be avoided with the following steps:

1. 1. Wait for DFLTRUN = 0.
2. 2. Read the sample from the RXFIFO.
3. 3. Clear DFLTEN to 0.

Window continuous acquisition mode

This mode allows the application to start or stop a continuous acquisition controlled by consecutive edges of one of the following trigger sources:

• • adf_trgi signal
• • TRGO bit

The window continuous acquisition mode is selected when ACQMOD[2:0] = 100.

The sequence below shows the most important programming steps (assuming that DFLTEN is set to 0):

1. 1. Configure and enable the clock generator (CKGEN), so that the frequency of adf_proc_ck clock is compatible with the targeted application (see examples in Table 265 ).
2. 2. Enable the CKGEN and, if needed, enable the ADF_CCK0 and ADF_CCK1 clocks.
3. 3. Program the filter settings and set the ACQMOD[2:0] to 100.
4. 4. Set to 1 the SITFEN bit.
5. 5. Select the proper trigger source and sensitivity.
6. 6. Before setting DFLTEN to 1, wait for DFLTACTIVE = 0: it insures that the previous filter deactivation sequence terminated properly.
7. 7. Set DFLTEN to 1.
8. 8. If TRGSENS = 0, the acquisition starts on trigger rising edge and stops on trigger falling edge. If TRGSENS = 1, the acquisition starts on trigger falling edge and stops on trigger rising edge.

Note: The acquisition may restart if the trigger condition becomes again active.

Figure 268 shows a simplified example of window continuous acquisition mode, with TRGSENS = 1. Once DFLTEN is set to 1, the ADF waits for a falling edge on the selected trigger input. When the trigger condition is met, DFLTRUN goes to 1 and the acquisition starts. The acquisition stops if the ADF detects a rising edge on the selected trigger input. If DFLTEN is still set to 1, the ADF waits again for a falling edge on the selected trigger input.

Figure 268. Window continuous mode (ACQMOD[2:0] = 100)

Note: The acquisition can be stopped by setting DFLTEN back to 0. This resets the filter and flushes the RXFIFO, so the samples located into the RXFIFO are lost. The ongoing DMA transfer is properly terminated. DFLTACTIVE goes back to 0 when the filter chain is reset and the RXFIFO flushed.

Starting several filters synchronously

If the ADF is used with MDF instances (if present in the product), it is possible to start simultaneously the acquisition of all the filters. This synchronization capability depends on the way the triggers are connected in the product. Generally, an ADF is able to trigger MDF instances, if its adf_trgo signal is connected as trigger input to those blocks (see Section 28.4.2: ADF pins and internal signals to check trigger capabilities).

In the following programming example, one ADF has its adf_trgo signal connected to some MDFs. To start the acquisition of several filters synchronously, the following sequence must be performed (assuming that DFLTEN bits of the filters are set to 0):

On MDFs receiving the adf_trgo trigger:

1. 1. Enable the CKGEN (CKGDEN = 1) and, if needed, enable the ADF_CCK0 and ADF_CCK1 clocks.
2. 2. Set to 1 the SITFEN bit of the requested data interfaces.
3. 3. For each filter, set the acquisition mode to synchronous (ACQMOD[2:0] = 01x).
4. 4. For each filter, set TRGSRC[3:0] in order to select the adf_trgo trigger input.
5. 5. For each filter, set TRGSENS to 0 (rising edge).
6. 6. For each filter, set DFLTEN to 1.

On the ADF generating the adf_trgo trigger:

1. 1. Enable the CKGEN (CKGDEN = 1) and, if needed, enable the ADF_CCK[1:0] clocks.
2. 2. Set to 1 the SITFEN bit of the requested data interfaces.
3. 3. Set the acquisition mode to synchronous (ACQMOD[2:0] = 01x).
4. 4. Set TRGSRC[3:0] to 0 (TRGO selected).
5. 5. Set TRGSENS to 0 (rising edge).
6. 6. Set DFLTEN to 1.
7. 7. Read TRGO bit until it is read to 0.
8. 8. Set TRGO to 1. Then the acquisition sequence for all selected filters starts immediately.

To trigger a new acquisition (in case of single-shot) the application must do the following:

1. 1. Check that the previous acquisition is completed, by waiting DFLTRUN = 0.
2. 2. Read TRGO until it is read to 0.
3. 3. Set again the bit TRGO to 1.

Discarded samples

The ADF offers the possibility to program the amount of samples to be discarded after each restart:

• • to avoid capturing samples affected by the impulse response of the filter
• • to delay the acquisition of filters by a specific amount of samples

The discard function is controlled via NBDIS[7:0] as follows:

• • When NBDIS[7:0] = 0, the discard function is disabled.
• • When NBDIS[7:0] ≠ 0, the discard function is activated in one of the following condition:
  • – when the DFLTEN bit goes to 1
  • – every time an acquisition is started in (A)synchronous single-shot modes

Refer to Figure 263 to Figure 267 , and Figure 269 .

In the example shown in Figure 269, the discard function is used to drop the first five samples provided by the digital filter (S1 to S5). The first sample transferred to the RXFIFO is S6.

Figure 269. Discard function example

28.4.9 Start-up sequence examples

Figure 270 details a start of acquisition sequence of a digital filter triggered by DFLTEN (ACQMOD[2:0] = 000), with NBDIS[7:0] = 3 (three samples to discard before acquisition).

The DFLT0 is configured for audio application: MCIC, RSFLT and HPF activated. The data interface (SITF0 or ADCITF) is assumed to be already activated.

Note: NBDIS[7:0] is set on purpose to a small value to simplify the drawing.

Figure 270. Start sequence with DFLTEN, in continuous mode, audio configuration

The DFLTEN bit is re-sampled into the ADF processing clock domain. When DFLTEN is detected high, the filter chain is enabled, and the decimation counter of the MCIC filter is incremented at the rate of the bitstream clock.

When the MCIC decimation counter reached its programmed value N, a sample is available for the RSFLT.

The RSFLT processes all the samples provided by the MCIC, and delivers a sample to the HPF every-time it processes four samples (decimation by 4). The RSFLT needs up to 24 cycles of adf_proc_ck clock before delivering a sample (P1).

The HPF processes all the samples provided by the RSFLT, but the NBDIS function prevents the data writing in the RXFIFO as long as NBDIS_CNTR does not reach 0.

When NBDIS_CNTR reaches 0, the samples provided by the HPF are stored into the RXFIFO.

28.4.10 Sound activity detection (SAD)

The SAD is based on the computation of the ambient noise level (ANLVL) and of the short-term sound level (SDLVL). The SAD offers the following ways to detect a sound:

• • when the SDLVL reaches a threshold referenced to the ambient noise level
• • when the SDLVL reaches a fixed threshold
• • when the ANLVL reaches a fixed threshold

As shown in Figure 271 , the SAD takes the 16 MSB samples from the DFLT0 output.

Figure 271. SAD block diagram

The SAD is highly configurable, and the application can adjust several parameters:

• • SAD detection behavior (SADMOD)
• • number of samples used to compute the sound level (FRSIZE)
• • number of frames used to compute the ambient noise level during the learning phase (LFRNB)
• • slope of the ambient noise estimator (ANSLP)
• • minimum expected ambient noise level (ANMIN)
• • threshold level (SNTHR)
• • threshold hysteresis (HYSTEN)
• • hangover window in order to filter spurious transitions between DETECT and MONITOR states (HGOVR)
• • data capture mode (DATCAP)

SAD detection behavior

The SAD can use the following ways to detect a sound, selected by SADMOD[1:0]:

• • When SADMOD[1:0] = 0, the SAD works like a voice-activity detection. In this mode, the SAD estimates the ambient noise level according to the computed sound level values. The threshold of the trigger is elaborated from the estimated ambient noise. Finally the current sound level is compared to this threshold. In a first approximation, the SAD triggers if the peak-to-average value of the input signal reaches a level defined by SNTHR[3:0].
• • When SADMOD[1:0] = 01, the SAD compares the current sound level (SDLVL) to a fixed trigger value defined by the application via SNTHR[3:0] and ANMIN[12:0]. This mode allows a fast SAD reaction as the amount of samples used to compute the sound level can be configured via FRSIZE[2:0].
• • When SADMOD[1:0] = 1x, the SAD compares the estimated ambient noise level (ANLVL) to a fixed trigger value defined by the application via SNTHR[3:0] and ANMIN[12:0]. This mode avoids unwanted triggers, due to peak levels, but the SAD reacts more slowly to an input signal variation. It is nevertheless possible to adjust the reaction time via FRSIZE[2:0] and ANSLP[2:0].

SAD states

As shown in Figure 271 , the SAD works as follows:

1. 1. When enabled (SADEN = 1), the SAD is first in LEARN state to perform a first estimation of the ambient noise level.
2. 2. The SAD continuously computes the short-term sound level (SDLVL) using the samples provided by the DFLT0. The amount of samples used to compute the sound level is given by FRSIZE[2:0]. The samples processed by the DFLT0 can be transferred into the memory or not depending on DATCAP[1:0] value.
3. 3. The initial ambient noise level (ANLVL) is computed using the consecutive sound level values. The application can define how much sound level values are used to perform the computation of this initial ambient noise estimation (LFRNB).
4. 4. When the initial ambient noise level (ANLVL) is computed, the SAD switches to the MONITOR state.
5. 5. Every time a new short-term sound level value is available, the SAD updates the ambient noise level and the thresholds according to the selected detection mode.
6. 6. If the SAD triggers, then the following happens:
   • – The SAD switches to DETECT state.
   • – The sddet_evt event is asserted.
   • – The adf_sad_det signal is set to high.
7. 7. The hangover function insures that the DETECT state is maintained even if the sound level goes below the threshold level for a time given by HGOVR.

Figure 272. SAD flow diagram

Sound level computation (SDLVL)

Once enabled, the SAD computes continuously the sound level value. The sound level represents the average of the absolute value of an amount of PCM samples given by FRSIZE[2:0].

where \( N_{FRSIZE} \) is the amount of PCM samples given by FRSIZE[2:0].

Ambient noise estimation (ANLVL)

The ambient noise level (ANLVL) is computed when SADMOD[1:0] is 00 or 10.

The ambient noise level is computed differently according to the state of the SAD as detailed below:

• ANLVL computation during the LEARN state

Every time the SAD is enabled, a learning phase is initiated in order to estimate a first value of the ambient noise level. During this phase, the SAD cannot trigger.

During the LEARN phase, the ambient noise level is computed as follows:

where \( N_{\text{LFRNB}} \) is the amount of frames given by LFRNB[2:0] bitfield.

• ANLVL computation during the MONITOR or DETECT state

When the learning phase is completed, the SAD updates the ambient noise level in the following way:

• The SAD computes the new possible values for the ambient noise level:

• The ANLVL takes the ANLVL_DN value if the current sound level is lower than ANLVL_DN, otherwise ANLVL takes the value of ANLVL_UP.

The ANLVL is not updated if the current sound level is higher than the threshold level, except if SADMOD[1:0] = 10.

• When SADMOD[1:0] = 0, if the new ANLVL value is lower than ANMIN[12:0], ANLVL is replaced by ANMIN.

The slope of the noise estimator can be adjusted to optimize the detection of the wanted signal. This slope is adjusted via ANSLP[2:0] in the ADF SAD configuration register (ADF_SADCFGGR) .

Table 262 shows the allowed values according to the frame size and the sampling rate of the data observed by the SAD. The recommended values when the SADMOD[1:0] = 0 are the ones into the gray shaded cells.

Table 262. ANSLP values versus FRSIZE and sampling rates

1. 1. The slow slope is equal to - 8.5 dB/s for the negative slope and + 2.1 dB/s for the positive slope.
2. 2. The typical slope is equal to - 17.1 dB/s for the negative slope and + 4.2 dB/s for the positive slope.
3. 3. The fast slope is equal to - 34.2 dB/s for the negative slope and + 8.5 dB/s for the positive slope.

The slopes can also be computed using the following formulas:

where \( F_s \) is the sampling rate of the stream observed by the SAD and \( F_{SIZE} \) is the frame size defined by FRSIZE[2:0].

Threshold computation

The way the threshold value is computed depends on SADMOD[1:0]:

• • If SADMOD[1:0] = 0, THRH is obtained by multiplying the current ANLVL value with the gain defined in SNTHR[3:0].

This threshold value is then compared to the current sound level (SDLVL).

• • If SADMOD[1:0] = 01, THRH is obtained by multiplying the current ANMIN[12:0] with the gain defined by SNTHR[3:0].

This threshold value is then compared to the current sound level (SDLVL).

• • If SADMOD[1:0] = 1x, THRH is obtained by multiplying the current ANMIN[12:0] by 4.

This threshold value is then compared to:

The hysteresis mode can be enabled to reduce the spurious transitions between MONITOR and DETECT states. In hysteresis mode (HYSTEN = 1), the following threshold values are used:

• • THRH when the SAD is in MONITOR state.
• • THRL when the SAD is in DETECT state.

Table 263 shows the thresholds values according to SNTHR.

Table 263. Threshold values according SNTHR ⁽¹⁾

1. LVL must be replaced by ANLVL when SADMOD[1:0] = 0 and by ANMIN for other SADMOD[1:0] values.

When the hysteresis function is disabled, the SAD always use THRH.

Note: The hysteresis mode must not be used when SADMOD[1:0] = 1x.

Trigger logic

The signal compared to this threshold depends also on SADMOD[1:0].

The trigger condition is reached when the selected signal (SELSIG) is bigger than the threshold level.

If the trigger condition is met, the following happens:

• • The SAD switches to DETECT state.
• • The SAD refreshes the hangover counter with HGOVR.
• • The sddet_evt event is asserted if the SAD transits from MONITOR to DETECT.
• • The adf_sad_det signal is set to high.

The SAD remains in DETECT state as long as the trigger condition is met or the hangover down-counter is different from 0.

The sddet_evt event indicates when the SAD enters and/or exits the DETECT state. This event is used to generate an interrupt when a sound is detected or when a sound is no longer detected:

• • When DETCFG = 0, the application receives an event only when the SAD enters the DETECT state.
• • When DETCFG = 1, the application receives an event when the SAD enters or exits the DETECT state.

The adf_sad_det signal remains high as long as the SAD is in DETECT state.

The SAD also provides a flag indicating that a new sound level value is available (SDLVLF). The last computed sound level (SDLVL[14:0]) is available in the ADF SAD sound level register (ADF_SADSDLVR) , and the last computed ambient noise level (ANLVL[14:0]), in the ADF SAD ambient noise level register (ADF_SADANLVR) .

Note: The SAD can work even when the AHB clock is not present. In that case, the SAD does not update SDLVL[14:0] and ANLVL[14:0].

To get the latest valid SDLVL[14:0] and ANLVL[14:0] values, the application must read the ADF_SADSDLVR, and ADF_SADANLVR registers, when the SDLVLF flag goes high. This can be done in the following ways:

• • by polling the SDLVLF flag:
  1. a) Clear the SDLVLF flag by writing SDLVLF to 1.
  2. b) Wait for SDLVLF = 1, by reading ADF_DFLTxISR.
  3. c) Read ADF_SADSDLVR and ADF_SADANLVR.
  4. d) Clear SDLVLF by writing it to 1.
  5. e) Go to step 2 if other values must to be read.
• • by generating an interrupt:
  1. a) Read ADF_DFLTxISR.
  2. b) If SDLVLF = 1, read ADF_SADSDLVR and ADF_SADANLVR, and clear SDLVLF by writing it to 1.
  3. c) Handle other status flags and exit from ISR.

Sample transfer to memory

The SAD offers the following options to control the samples transfer from DFLT0 to the system memory:

• • If DATCAP[1:0] = 1x, the samples are transferred into the system memory as soon as DFLT0 and SAD are enabled. The transfer does not depend on the SAD state.
• • If DATCAP[1:0] = 01, the samples are transferred into the system memory when the SAD detects a sound (when the SAD is in DETECT state), assuming that DFLT0 and SAD are enabled.
• • If DATCAP[1:0] = 0, the samples are not transferred into the memory. This mode can be used if the application only wants to observe but does not need samples for other processing.

Note: DATCAP[1:0] is taken into account only when the SADEN = 1. For example, if the SAD configuration is DATCAP[1:0] = 0, SADEN = DFLTEN = 1, and if the application sets now SADEN to 0, the samples provided by the DFLT0 are transferred to the RXFIFO.

Programming recommendations

To make the SAD function working properly, the ADF must be programmed as follows:

1. 1. Provide the proper kernel clock (adf_ker_ck) to the ADF.
2. 2. Configure the CKGEN and enable it.
3. 3. Configure the SITF and enable it (note that microphones have a settling time of several milliseconds).
4. 4. Configure the DFLT0. A typical setting is the following:
   • – CIC5 with a decimation ratio of 12, 16 or 24
   • – RSFLT with a decimation ratio of 4
   • – HPF with HPFC = 2 or 3

For a very-low power implementation, the RSFLT can be bypassed.

1. 5. Set SADEN to 0.
2. 6. Wait for SADACTIVE = 0. If SADEN was previously enabled, this phase can take two periods of adf_hclk, and two periods of adf_proc_ck.
3. 7. Configure the SAD as follows:
   • – Set DATCAP[1:0] to 0, if the application does not want to store the samples into the system memory.
   • – Set DATCAP[1:0] to 01, if the application wants to store the samples into the system memory only when the SAD detects a sound.
   • – Set DATCAP[1:0] to 11, if the application wants to store the samples into the system memory continuously.
4. 8. Configure the DMA (optional).
5. 9. Enable the SAD.
6. 10. Enable the DFLT0.

Figure 272 shows a simplified timing diagram when the SAD works with DATCAP[1:0] = 01.

Thanks to the kernel clock (adf_ker_ck), the SAD continuously monitors the audio signal provided by the DFLT0. The threshold is also continuously updated according to the ambient noise level estimation.

• • When the SAD detects a sound higher than the programmed threshold (1), the ADF requests the bus clock (adf_bus_ckreq asserted).
• • When the bus clock is available (see 2 in Figure 272 ) then:
  • – The data transfer to the memory is triggered.
  • – The event interrupt (adf_evt_it) can be generated.
• • In this example, the event interrupt (adf_evt_it) is used to wake up the application. The interrupt line is released by clearing SDDETF by writing 1 to it.
• • As long as the SAD remains in DETECT state, the application waits to get enough samples and calls, for example the keyword recognition algorithm (see 3 in Figure 272 ).
• • In the case shown in Figure 273 , the SAD state (SADST) goes back to MONITOR before the keyword is recognized. If DETCFG is set to 1, an event signals when the SAD goes back to MONITOR state. The SAD stops the transfer of samples into the memory and the application can clean up the receive buffer for the next detection (see 4 in Figure 272 ).

Figure 273. SAD timing diagram example

28.4.11 Data transfer to memory

Data format

The samples processed by DFLT0 are stored into a RXFIFO. The application can read the samples stored into these FIFOs via the ADF digital filter data register 0 (ADF_DFLT0DR) . The samples inside this register are signed and left aligned. The bit 31 always represents the sign.

The ADF provides 24-bit left-aligned data. Performing a 16-bit access to ADF_DFLT0DR allows the application to get the 16 most significant bits. Performing a 32-bit access to ADF_DFLT0DR allows the application to get a 24-bit data size.

Figure 274. ADF_DFLTxDR data format

Data resynchronization

The samples stored into the RXFIFO can be transferred into the memory by using either DMA requests or interrupt signaling.

Note: The RXFIFO is located into the adf_ker_ck clock domain, while ADF_DFLT0DR is located into the adf_hclk (AHB) clock domain.

When the AHB clock is available, if ADF_DFLT0DR is empty and if a sample is available into the RXFIFO, this sample is transferred into ADF_DFLT0DR.

The sample transfer from the RXFIFO to ADF_DFLT0DR takes two periods of the AHB clock (adf_hclk) and two periods of the adf_ker_ck clock. The ADF inserts automatically wait-states if the application performs a read operation of ADF_DFLT0DR while the transfer of the new sample from the RXFIFO to ADF_DFLT0DR is not yet completed.

Figure 275. Data resynchronization

Data transfer

The content of the RXFIFO can be transferred to the memory either by using a DMA channel or interrupt services.

Both single and burst, DMA transfers are supported by the ADF, but the application has to care about the following points:

• • The RXFIFO must contain at least the same amount of samples than the burst size.
• • The burst mode efficiency may be reduced due to the data resynchronization explained in the previous section.

Note: The burst mode is not available in all products (see the DMA section to check if the product supports it).

In addition, the application can select the RXFIFO threshold (FTH bit) in order to trigger the data transfer: a data transfer can be triggered as soon as the RXFIFO is not empty, or when the RXFIFO is half-full (containing depth/2 samples).

For the DMA transfer, as soon as one of the RXFIFO reaches the threshold level, the DMA request is asserted in order to ask for data transfer. Successive DMA requests are performed as long as the RXFIFO is not empty.

The DMA mode of the RXFIFO is enabled via the DMAEN bit in ADF_DFLT0DR.

For the interrupt signaling, the following cases must be considered:

• • If FTH = 0, as soon as a data is available in ADF_DFLT0DR, the FTHF is set, allowing the generation of an interrupt. FTHF is released as soon as ADF_DFLT0DR is read.
• • If FTH = 1, as soon as the RXFIFO reaches the threshold level and a data is available in ADF_DFLT0DR, the FTHF is set, allowing the generation of an interrupt. FTHF is released as soon as one data is read. FTHF is set again if the threshold condition is

met again. In this mode, every time an interrupt occurs, the application is supposed to read FIFO_SIZE/2 data.

RXFIFO overrun

A RXFIFO overrun condition is detected when the RXFIFO is full, and a new sample from the DFLT0 must be written.

In this case, DOVRF is set and the new sample is dropped. When the RXFIFO has at least one location available, the new incoming sample is written into the RXFIFO.

Figure 276 shows an example based on a RXFIFO depth of four words and FTH set to 1, so that FTHF goes to 1 when the RXFIFO is half-full.

The S7 sample is lost due to an overrun: the RXFIFO is full while S7 must be written into the RXFIFO. The S7 write operation is not performed. DOVRF is set to 1 at the moment where the write operation was expected. The overflow event remains to 1 as long as it is not cleared by the application.

In this example, DOVRIE is set to 1 to have an interrupt if an overrun condition is detected.

After the S7 sample, the application manages to read data from the RXFIFO, and the ADF can write the S8 sample and consecutive. Later, the application clears DOVR, allowing the detection of a new overrun situation.

In the adf_hclk line, the gray boxes indicate that the ADF requested the AHB clock.

Figure 276 shows the AHB clock available only when the ADF requests it. In real applications, the AHB clock may also be present if the ADF does not request it.

Figure 276. Example of overflow and transfer to memory

28.4.12 Autonomous mode

The ADF can work even if the AHB bus clock is not available (Stop modes). The ADF uses the AHB clock only for the register interface. All the processing part is clocked with the kernel clock.

In Stop mode, the ADF receives a kernel clock if the following conditions are met:

• • The ADF autonomous mode is enabled in the RCC.
• • The selected kernel clock source is taken from an oscillator available in Stop mode.

In Stop mode, the ADF receives the AHB clock if the following conditions are met:

• • The ADF autonomous mode is enabled in the RCC.
• • The ADF requests the AHB clock in the following situations:
  • – when the ADF must transfer data into memory via the DMA
    The data is directly transferred to the SRAM thanks to the DMA while the product remains in Stop mode. The AHB clock request is maintained until the DMA transfer is completed.
  • – when the ADF needs to generate an interrupt
    An interrupt generally wakes up the device from Stop mode, as an action from the application is needed. Once the AHB clock is available, the interrupt is generated. The AHB clock request is maintained as long as an enabled interrupt flag is still active.

28.4.13 Register protection

The ADF embeds some hardware protection to prevent invalid situations.

Table 264 shows the list of write-protected and unprotected fields.

Table 264. Register protection summary

Table 264. Register protection summary (continued)

All the ADF processing is performed in the adf_proc_ck clock domain. For that reason, enabling or disabling an ADF sub-block may take some time due to the resynchronization between the AHB clock domain and the adf_proc_ck clock domain. XXXACTIVE flags are available to allow the application to check that the synchronization between the two clock domains is completed.

To change a write-protected bitfield, the application must follow this sequence:

1. 1. Set the enable bit of the sub-block to 0.
2. 2. Wait for corresponding flag XXXACTIVE = 0.
3. 3. Modify the wanted fields.
4. 4. Set the enable bit of the sub-block to 1.

Refer to the description of each sub-block for details.

28.5 ADF low-power modes

Table 265. Effect of low-power modes on ADF

1. Refer to Section 28.3: ADF implementation for details about Stop modes supported by the ADF.

28.6 ADF interrupts

To increase the CPU performance, the ADF offers an interrupt line (adf_flt0_it), sensitive to several events.

Note: The status flags are available even if the corresponding interrupt enable flag is not enabled.

The interrupt interface is controlled via the ADF_DFLT0 interrupt enable register (ADF_DFLT0IER) and the ADF_DFLT0 interrupt status register 0 (ADF_DFLT0ISR) .

Figure 277. ADF interrupt interface

(1) Only present if the SAD is implemented, refer to section ADF implementation for details.

MSV63668V2

Table 266 shows which interrupt line is affected by which event, and how to clear and activate each interrupt/event.

Table 266. ADF interrupt requests

1. 1. Refer to Section 28.3: ADF implementation for details.
2. 2. ADF_FLT0 vector corresponds to the assertion of adf_flt0_it signal.

28.7 ADF application information

28.7.1 ADF configuration examples for audio capture

Table 267 gives some examples of the ADF settings for the digital microphones, focusing on 16 and 48 kHz output data rate.

Configurations #1 and #2 are for very low-power use-cases and have a reduced signal-to-noise ratio. The user must also insure that the selected digital microphone can work properly at 512 kHz. These configurations can be used for sound detection. The RSFLT is not used to reduce as much as possible the frequency of the kernel clock (adf_ker_ck).

Configurations #3, #4, #9, #10, #11 give signal-to-noise ratios around 115 dB, with an ideal microphone model, with a sinus signal of 997 Hz. Using the RSFLT allows a good control on the in-band ripple, and a good image rejection.

Configurations #7, #8, #10 give signal-to-noise ratio around 120 dB, with an ideal microphone model, using a sinus signal of 997 Hz.

Table 267. Examples of ADF settings for microphone capture

1. CICMOD = 100 for CIC order equal to 4. CICMOD = 101 for CIC order equal to 5.

28.7.2 Programming examples

Example 1

This example describes the programming of ADF for the capture of a signal coming from a digital microphone, using only the CIC4, with a decimation of 48, assuming that the kernel clock is 1.536 MHz. Typically, this configuration can be used to detect sound using the SAD.

Table 268. Programming sequence (CIC4)

Table 268. Programming sequence (CIC4) (continued)

1. SNTHR and ANMIN values are computed using the same approach than in Threshold programming with SADMOD = 01 (detection of a sound higher than 63 dBSPL).

Example 2

This example describes the programming of ADF for the capture of a signal coming from a digital microphone, using the CIC5, and the RSFLT, with a total decimation of 64.

Table 269. Programming sequence (CIC5)

Table 269. Programming sequence (CIC5) (continued)

28.7.3 Connection examples

Figure 277 shows simple connection examples of the ADF to external sensors.

• • Picture on the left: two digital microphones connected to the ADF
  In this connection, the amount of connections is optimized; DMIC1 and DMIC2 are sharing the same data line, and the same clock line. BSMX allows the application to connect the digital filter either to DMIC1 or to DMIC2. In this configuration when one of the microphone is used, the other is activated as well, as they share the same clock.
• • Picture in the center: two digital microphones connected to the ADF
  In this connection, DMIC1 and DMIC2 are sharing the same data line, but have a dedicated clock line. BSMX allows the application to connect the filter either to DMIC1 or to DMIC2. When the application wants to use a microphone, it is possible to keep the other in low-power mode by forcing its clock line to 0 (CCKyEN = 0, CCKyDIR = 1).

• • Picture on the right: single sensor connected to the ADF
  It is also possible to configure the CCK0 and CCK1 pins to input in order to connect sensors providing the clock.

Figure 278. Sensor connection examples

28.7.4 Global frequency response

Figure 278 shows the global frequency response for a 16 kHz audio signal with a digital microphone working at 1.024 MHz. The filter configuration is the following:

• • CIC order 4 or 5, with a decimation ratio of 16
• • RSFLT enabled, with a decimation ratio of 4
• • HPF enabled with a cut-off frequency of 40 Hz

Figure 279 shows the theoretical frequency response using a CIC4 and a CIC5.

Figure 279. Global frequency response

Figure 280 shows the in-band ripple for a 16 kHz audio signal with a digital microphone working at 1.024 MHz. The filter configuration is the following:

• • CIC order 4 or 5, with a decimation ratio of 16
• • RSFLT enabled, with a decimation ratio of 4
• • HPF enabled with a cut-off frequency of 20 Hz

The resulting in-band ripple is \( \pm 0.41 \) dB for CIC5, and \( \pm 0.45 \) dB for CIC4.

The - 3 dB cut-off frequency is 7061 Hz.

Figure 280. Detailed frequency response

28.7.5 Total ADF gain

This section details how to compute the signal level provided by the ADF according to the filter settings.

A signal level may be expressed in dBFS (decibel full scale). A 0 dBFS level is assigned to the maximum possible digital level. For example, a signal that reaches 50 % of the maximum level, has a – 6 dBFS level (6 dB below full scale).

For example, for the ADF offering a final data width of 24 bits, a signal having an amplitude of \( 2 \cdot 10^6 \) LSB has a level of:

In addition, the data size of a signal having an amplitude (Amp) expressed in LSB is given by:

One bit need to be added for negative values.

So a signal having an amplitude of \( 2 \cdot 10^6 \) LSB, has a data size of 21.9 bits.

CIC gain

The CIC gain ( \( G_{\text{CIC}} \) and \( G_{\text{dBCIC}} \) ) can be deduced from the following formula giving data size in bits ( \( DS_{\text{CIC}} \) ).

where N represents the CIC order (selected by CICMOD[2:0]), and D1 is the decimation ratio (given by MCICD[8:0]).

\( DS_{\text{in}} \) represents the data size (in bits) of the signal at CIC input.

Warning: \( DS_{\text{CIC}} \) is very important for CIC filter. In order to work fine, \( DS_{\text{CIC}} \) must not exceed 26 bits.

The CIC gain \( G_{\text{CIC}} \) is given by:

which gives in decibels:

Data size at SCALE output

The data size at SCALE output (including the CIC gain), is a key information as the RSFLT starts to have some saturations, if the peak-to-peak signal amplitude at SCALE output is higher than 22 bits.

If the RSFLT is bypassed, then a peak-to-peak signal amplitude of 24 bits is accepted.

The signal amplitude at SCALE output is:

\( GdB_{SCALE} \) represents the gain selected by SCALE[5:0], in dB.

\( Asout_{SCALE} \) is the signal amplitude at SCALE output (in LSB), and \( Asin_{DFLT} \) is the signal amplitude at CIC input (LSB).

The data size at SCALE output ( \( DS_{SCALE} \) ) is expressed in bits.

RSFLT gain

The RSFLT gain in the useful bandwidth is typically 9.5 dB, but due to ripple a margin of about \( \pm 0.41 \) dB must be considered.

Note: The HPF filter has a gain of 0 dB.

SAD gain

The SAD is using only the 16 MSB on the signal, as a consequence, from the SAD point of view, the truncation from 24 to 16 bits can be seen as an attenuation.

and

The Figure 281 shows a simplified view of the filter path and gives, for each significant component, the expression of the bit growth and the gain.

Figure 281. Simplified DFLT view with gain information

Note: The SAD is not always implemented (see Section 28.3 for details).

Table 270 summarizes of the final data size for different filter configurations.

Table 270. Output signal levels

Example using the main filter chain

If the ADF filter is programmed as follows:

• • The input signal is coming from a serial interface ( \( Dsin_{RSFLT} = 1 \) bit).
• • CIC order = 5 (N), with a decimation value of 24 (D1).

• • SCALE[5:0] is set to - 12 dB.
• • RSFLT enabled, and the decimation by four is enabled.
• • HPF is enabled.

Check first the data size at CIC output:

The size is lower than 26 bits, so the CIC works in good conditions.

The data size at CIC output is very close to 24 bits, so the SCALE must be adjusted in order to provide a 22-bit max signal to the RSFLT. An attenuation of 12 dB is needed.

Then the signal level provided to the RSFLT is:

If a higher gain is used, the RSFLT may saturate the output signal for strong input signals.

At the end, the final signal amplitude is:

or:

28.7.6 How to compute SAD thresholds

The SAD does not compute the RMS value of the converted signal, but the average of the absolute values. As a consequence, the estimated level differs from the RMS value of the signal:

• • For a sine signal having an RMS value of 1, the SAD computes a level of 0.9.
• • For a white or pink noise signal having an RMS value of 1, the SAD computes a level of about 0.8.

Note: FRSIZE[2:0] has a big influence on the accuracy of the level estimation: big FRSIZE[2:0] values give better results.

Threshold programming with SADMOD = 01

Consider the case of a sound capture where the application wants to wake up the system when the captured sound is bigger than 63 dB SPL.

The sound capture can be performed with a digital microphone such as the MP45DT02.

The sensitivity of this microphone is typically -26 dBFS for an input signal of 94 dB SPL.

An acoustic signal at 63 dB SPL produces a digital signal of about:
\( -26 \text{ dBFS} - (94 - 63) = -57 \text{ dBFS} \) .

• • SCALE value adjustment

For this example, the filter configuration is the following:

• – CIC5 with a decimation by 16
• – RSFLT enabled with a decimation by 4
• – HPF enabled

A SCALE value of 3.5 dB is recommended for this configuration. As DFTL0 provides samples only used for a sound detection (samples not provided to the application), a bigger gain value can be applied: it increases the SAD accuracy and a saturation does not affect the SAD behavior (for example, a SCALE value of 15.6 dB).

• • Input signal amplitude

The input signal is \( -57 \text{ dBFS} \) , corresponding to an amplitude
\( A_{\text{sin}} = 10^{(-57/20)} = 0.00141 \text{ LSB} \) .

• • Signal level at SAD input

The total filter gain for the SAD is:

The signal amplitude received by the SAD is:

The gain can be increased if the expected amplitude is too small. For the targeted application, 104 LSB is fine.

If the input signal is expected to be a sine, the sound level for a signal amplitude of 104 LSB is:

where 0.9 is the correction factor to apply with respect to the RMS value.

• • Program the trigger value

ANMIN and SNTHR must be programmed to trigger the SAD when the input signal level reaches 66 LSB.

For \( \text{SADMOD}[1:0] = 01 \) , the threshold value is given by:

where \( \text{GdB}_{\text{SNTHR}} \) represents the decibel value selected by \( \text{SNTHR}[3:0] \) .

When \( \text{SNTHR}[3:0] = 6 \text{ dB} \) for example, this formula becomes:

So \( \text{ANMIN} = \text{THRH}/2 = 66/2 = 33 \text{ LSB} \) .

In Figure 281 , the trigger value (THRH in red) is fixed to 66 LSB. The input signal is at \( -65 \text{ dBFS} \) during 256 samples, then its value goes to \( -55 \text{ dB} \) for 256 samples, and finally it is reduced to \( -60 \text{ dBFS} \) .

The blue curve is showing the sound level estimation (SDLVL) versus time. Fluctuation on the estimated value can be observed due to windowing effect of FRSIZE samples.

The SAD DETECT state (when green signal is high) is maintained during four additional frames due to hangover function value.

In this example ANSLP = FRSIZE = 3 (64 samples), LFRNB = 0 (2 frames), HGOVR = 0 (4 frames), SNTHR = 1 (6 dB) and ANMIN = 33.

Figure 282. SAD example working with SADMOD = 01

Threshold programming with SADMOD = 1x

Consider the case of a sound capture where the application wants to wake up the system when the captured sound is bigger than 57 dB SPL.

The sound capture can be performed with a digital microphone such as the MP45DT02. The sensitivity of this microphone is typically - 26 dBFS for an input signal of 94 dB SPL.

An acoustic signal at 57 dB SPL produces a digital signal of about:

• • Adjust SCALE value

For this example, the filter configuration is the following:

• – CIC4 with a decimation by 48
• – RSFLT bypassed
• – HPF enabled

A SCALE value of 3.5 dB is recommended for this configuration. The samples provided by DFTL0 are only used for a sound detection, without providing the samples to the application, a bigger gain value can be provided: it increases the SAD accuracy and a saturation does not affect the SAD behavior (for example, a SCALE value of 24 dB).

• • Input signal amplitude

The input signal is - 63 dBFS, corresponding to an amplitude:

• • Signal level at SAD input

The total filter gain for the SAD is:

The signal amplitude received by the SAD is:

The gain can be increased if the expected amplitude is too small.

If the input signal is expected to be a sine, the sound level for a signal amplitude of 232 LSB is:

where 0.9 is the correction factor to apply with respect to the RMS value.

Note: ANLVL converges to average of SDLVL values, with a long constant time.
So \( \text{SDLVL} \sim \text{ANLVL} = 148 \text{ LSB} \) for a constant input signal at 57 dB SPL.

• • Programming trigger value

For \( \text{SADMOD} = 1' \) , the SAD compares the estimated ambient noise multiplied by the gain selected by \( \text{SNTHR}[3:0] \) to \( \text{ANMIN}[12:0] * 4 \) .

For simplification, \( \text{SNTHR}[3:0] \) is set to 1 (6 dB), meaning that ANLVL is multiplied by two.

The SAD triggers if \( 2 * \text{ANLVL} > \text{THRH} \) .

In this mode:

So the SAD triggers if:

So \( \text{ANMIN} = 148 / 2 = 74 \text{ LSB} \)

In Figure 282, the trigger value (THRH in red) is fixed to 148 LSB. The input signal is at - 75 dBFS during 512 samples, then its value goes to - 62 dB for 11000 samples, and finally it is reduced to - 70 dBFS.

The blue curve shows the sound level estimation (SDLVL) versus time. The black curve shows the ambient noise estimation versus time, increasing or decreasing logarithmically. During the learning phase, it reaches the SDLVL value.

In this example \( \text{ANS LP} = 6 \) , \( \text{FRSIZE} = 3 \) (64 samples), \( \text{LFRNB} = 0 \) (2 frames), \( \text{HGOVR} = 0 \) (4 frames), \( \text{SNTHR} = 1 \) (6 dB) and \( \text{ANMIN} = 74 \) .

Figure 283. SAD example working with \( \text{SADMOD} = 1x \)

28.8 ADF registers

All the ADF registers must be accessed either in word (32-bit) or half-word (16-bit) formats.

28.8.1 ADF global control register (ADF_GCR)

Address offset: 0x000

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TRGO : Trigger output control

This bit is set by software and reset by hardware. It is used to start the acquisition of several filters synchronously. It is also used to synchronize several ADF together by controlling the adf_trgo signal.

0: Write 0 has no effect. Read 0 means that the trigger can be set again to 1.

1: Write 1 generates a positive pulse on the adf_trgo signal and triggers the acquisition on enabled filter having their ACQMOD[2:0] = 01x and selecting TRGO as trigger. Read 1 means that the trigger pulse is still active.

28.8.2 ADF clock generator control register (ADF_CKGCR)

Address offset: 0x004

Reset value: 0x0000 0000

This register is used to control the clock generator. The clock adf_proc_ck must be enabled before enabling other ADF parts.

Bit 31 CKGACTIVE : Clock generator active flag

This bit is set and cleared by hardware. It is used by the application to check if the clock generator is effectively enabled (active) or not. The protected fields of this function can only be updated when CKGACTIVE = 0 (see Section 28.4.13: Register protection for details).

The delay between a transition on CKGDEN and a transition on CKGACTIVE is two periods of AHB clock and two 2 periods of adf_proc_ck.

0: The clock generator is not active and can be configured if needed.

1: The clock generator is active and protected fields cannot be configured.

Bits 30:24 PROCDIV[6:0] : Divider to control the serial interface clock

This bitfield is set and reset by software. It is used to adjust the frequency of the clock provided to the SITF.

This bitfield must not be changed if the filter is enabled (DFTEN = 1).

0: adf_ker_ck provided to the SITF

1: adf_ker_ck / 2 provided to the SITF

2: adf_ker_ck / 3 provided to the SITF

...

127: adf_ker_ck / 128 provided to the SITF

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bits 23:20 Reserved, must be kept at reset value.

Bits 19:16 CCKDIV[3:0] : Divider to control the ADF_CCK clock

This bitfield is set and reset by software. It is used to adjust the frequency of the ADF_CCK clock. The input clock of this divider is the clock provided to the SITF. More globally, the frequency of the ADF_CCK is given by the following formula:

This bitfield must not be changed if the filter is enabled (DFTEN = 1).

0000: The ADF_CCK clock is adf_proc_ck.

0001: The ADF_CCK clock is adf_proc_ck / 2.

0010: The ADF_CCK clock is adf_proc_ck / 3.

...

1111: The ADF_CCK clock is adf_proc_ck / 16.

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bits 15:12 TRGSRC[3:0] : Digital filter trigger signal selection

This bitfield is set and cleared by software. It is used to select which external signals trigger the corresponding filter. This bitfield is not significant if the CKGMOD = 0.

000x: TRGO selected

0010: adf_trg1 selected

Others: Reserved

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 TRGSENS : CKGEN trigger sensitivity selection

This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0.

0: A rising edge event triggers the activation of CKGEN dividers.

1: A falling edge even triggers the activation of CKGEN dividers.

Note: When the trigger source is TRGO, the sensitivity is forced to falling edge, thus TRGSENS value is not taken into account. This bit can be write-protected (see Section 28.4.13: Register protection for details).

Bit 7 Reserved, must be kept at reset value.

Bit 6 CCK1DIR : ADF_CCK1 direction

This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin.

0: The ADF_CCK1 pin direction is in input.

1: The ADF_CCK1 pin direction is in output.

Note: This bit can be write-protected (see Section 28.4.13: Register protection for details).

Bit 5 CCK0DIR : ADF_CCK0 direction

This bit is set and reset by software. It is used to control the direction of the ADF_CCK0 pin.

0: The ADF_CCK0 pin direction is in input.

1: The ADF_CCK0 pin direction is in output.

Note: This bit can be write-protected (see Section 28.4.13: Register protection for details).

Bit 4 CKGMOD : Clock generator mode

This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1).

0: The kernel clock is provided to the dividers as soon as CKGDEN is set to 1.

1: The kernel clock is provided to the dividers when CKGDEN is set to 1 and the trigger condition met.

Note: This bit can be write-protected (see Section 28.4.13: Register protection for details).

Bit 3 Reserved, must be kept at reset value.

Bit 2 CCK1EN : ADF_CCK1 clock enable

This bit is set and reset by software. It is used to control the generation of the bitstream clock on the ADF_CCK1 pin.

0: Bitstream clock not generated

1: Bitstream clock generated on the ADF_CCK1 pin.

Bit 1 CCK0EN : ADF_CCK0 clock enable

This bit is set and reset by software. It is used to control the generation of the bitstream clock on the ADF_CCK0 pin.

0: Bitstream clock not generated

1: Bitstream clock generated on the ADF_CCK0 pin

Bit 0 CKGDEN : CKGEN dividers enable

This bit is set and reset by software. It is used to enable/disable the clock dividers of the CKGEN: PROCDIV and CCKDIV.

0: CKGEN dividers disabled

1: CKGEN dividers enabled

28.8.3 ADF trigger input selection register (ADF_TRGISEL)

Address offset: 0x020

Reset value: 0x0000 0000

This register is used to select the trigger signal.

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 TRGISEL[2:0] : Input selection for adf_trgi

This bitfield is used to select the signal connected to adf_trgi input. The filter(s) must be disabled (DFTEN=0) before changing this field.

000: adf_trgi0 is selected (default after reset)

001: adf_trgi1 is selected

010: adf_trgi2 is selected

011: adf_trgi3 is selected

100: adf_trgi4 is selected

Others: Reserved

Refer to Table 253 to find signals connected to each input.

28.8.4 ADF serial interface control register 0 (ADF_SITF0CR)

Address offset: 0x080

Reset value: 0x0000 1F00

This register is used to control the serial interface SITF0.

Bit 31 SITFACTIVE : Serial interface active flag

This bit is set and cleared by hardware. It is used by the application to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when SITFACTIVE is set to 0 (see Section 28.4.13: Register protection for details).

The delay between a transition on SITFEN and a transition on SITFACTIVE is two periods of AHB clock and two periods of adf_proc_ck.

0: The serial interface is not active, and can be configured if needed.

1: The serial interface is active and protected fields cannot be configured.

Bits 30:13 Reserved, must be kept at reset value.

Bits 12:8 STH[4:0] : Manchester symbol threshold/SPI threshold

This bitfield is set and cleared by software. It is used for Manchester mode to define the expected symbol threshold levels (see Manchester mode for details on computation).

In addition this bitfield is used to define the timeout value for the clock absence detection in Normal SPI mode. STH[4:0] values lower than four are invalid.

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bits 7:6 Reserved, must be kept at reset value.

Bits 5:4 SITFMOD[1:0] : Serial interface type

This bitfield is set and cleared by software. It is used to define the serial interface type.

00: LF_MASTER SPI mode

01: Normal SPI mode

10: Manchester mode: rising edge = logic 0, falling edge = logic 1

11: Manchester mode: rising edge = logic 1, falling edge = logic 0

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bit 3 Reserved, must be kept at reset value.

Bits 2:1 SCKSRC[1:0] : Serial clock source

This bitfield is set and cleared by software. It is used to select the clock source of the serial interface.

00: Serial clock source is ADF_CCK0.

01: Serial clock source is ADF_CCK1.

others: reserved

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bit 0 SITFEN : Serial interface enable

This bit is set and cleared by software. It is used to enable/disable the serial interface.

0: Serial interface disabled

1: Serial interface enabled

28.8.5 ADF bitstream matrix control register 0 (ADF_BSMX0CR)

Address offset: 0x084

Reset value: 0x0000 0000

This register is used to select the bitstream to be provided to DFLT0.

Bit 31 BSMXACTIVE : BSMX active flag

This bit is set and cleared by hardware. It is used by the application to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when BSMXACTIVE is set to 0. This BSMXACTIVE flag cannot go to 0 if DFLT0 is enabled.

0: BSMX is not active and can be configured if needed.

1: BSMX is active and protected fields cannot be configured.

Bits 30:5 Reserved, must be kept at reset value.

Bits 4:0 BSSEL[4:0] : Bitstream selection

This bitfield is set and cleared by software. It is used to select the bitstream to be processed for DFLT0.

00000: bs0_r provided to DFLT0

00001: bs0_f provided to DFLT0

others: reserved

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

28.8.6 ADF digital filter control register 0 (ADF_DFLT0CR)

Address offset: 0x088

Reset value: 0x0000 0000

Bit 31 DFLTACTIVE: DFLT0 active flag

This bit is set and cleared by hardware. It indicates if DFLT0 is active: can be running or waiting for events.

0: DFLT0 not active (can be re-enabled again, via DFLTEN bit, if needed)

1: DFLT0 active

Bit 30 DFLTRUN: DFLT0 run status flag

This bit is set and cleared by hardware. It indicates if DFLT0 is running or not.

0: DFLT0 not running and ready to accept a new trigger event

1: DFLT0 running

Bits 29:28 Reserved, must be kept at reset value.

Bits 27:20 NBDIS[7:0]: Number of samples to be discarded

This bitfield is set and cleared by software. It is used to define the number of samples to be discarded every time DFLT0 is re-started.

0: No sample discarded

1: 1 sample discarded

2: 2 samples discarded

...

255: 255 samples discarded

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bits 19:16 Reserved, must be kept at reset value.

Bits 15:12 TRGSRC[3:0]: DFLT0 trigger signal selection

This bitfield is set and cleared by software. It is used to select which external signals trigger DFLT0.

0000: TRGO selected

0010: adf_trgi selected

Others: Reserved

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bits 11:9 Reserved, must be kept at reset value.

This bitfield is set and cleared by software. It is used to select the trigger sensitivity of the external signals

0: A rising edge event triggers the acquisition.

1: A falling edge even triggers the acquisition.

Note: When the trigger source is TRGO, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge.

This bit can be write-protected (see Section 28.4.13: Register protection for details).

Bit 7 Reserved, must be kept at reset value.

This bitfield is set and cleared by software. It is used to select the filter trigger mode.

000: Asynchronous continuous acquisition mode

001: Asynchronous single-shot acquisition mode

010: Synchronous continuous acquisition mode

011: Synchronous single-shot acquisition mode

100: Window continuous acquisition mode

Others: Same as 000

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bit 3 Reserved, must be kept at reset value.

This bit is set and cleared by software. It is used to select the RXFIFO threshold.

0: RXFIFO threshold event generated when the RXFIFO is not empty

1: RXFIFO threshold event generated when the RXFIFO is half-full

Note: This bit can be write-protected (see Section 28.4.13: Register protection for details).

This bit is set and cleared by software. It is used to control the generation of DMA request to transfer the processed samples into the memory.

0: DMA interface for the corresponding digital filter disabled

1: DMA interface for the corresponding digital filter enabled

Note: This bit can be write-protected (see Section 28.4.13: Register protection for details).

This bit is set and cleared by software. It is used to control the start of acquisition of the DFLT0 path. This bit behavior depends on ACQMOD[2:0] and external events. The serial or parallel interface delivering the samples must be enabled as well.

0: Acquisition immediately stopped

1: Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x.

28.8.7 ADF digital filter configuration register 0 (ADF_DFLT0CICR)

Address offset: 0x08C

Reset value: 0x0000 0000

This register is used to control the main CIC filter.

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:20 SCALE[5:0] : Scaling factor selection

This bitfield is set and cleared by software. It is used to select the gain to be applied at CIC output (see Table 258 for details). If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back this bitfield informs the application on the current gain value.

000000: 0 dB

000001: + 3.5 dB

000010: + 6 dB or shift left by 1 bit

...

011000: + 72 dB or shift left by 12 bits

100000: - 48.2 dB or shift right by 8 bits (default value)

100001: - 44.6 dB

100010: - 42.1 dB or shift right by 7 bits

100011: - 38.6 dB

...

101110: -6 dB or shift right by 1 bit

101111: -2.5 dB

Others: Reserved

Bits 19:17 Reserved, must be kept at reset value.

Bits 16:8 MCICD[8:0] : CIC decimation ratio selection

This bitfield is set and cleared by software. It is used to select the CIC decimation ratio. A decimation ratio smaller than two is not allowed. The decimation ratio is given by (CICDEC+1).

0: Decimation ratio is 2.

1: Decimation ratio is 2.

2: Decimation ratio is 3.

3: Decimation ratio is 4.

...

511: Decimation ratio is 512.

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 CICMOD[2:0] : Select the CIC order

This bitfield is set and cleared by software. It is used to select the order of the MCIC.

100: MCIC configured in single Sinc ⁴ filter

101: MCIC configured in single Sinc ⁵ filter

Others: Reserved

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bits 3:2 Reserved, must be kept at reset value.

Bits 1:0 DATSRC[1:0] : Source data for the digital filter

This bitfield is set and cleared by software.

0x: Stream coming from the BSMX selected

10: Stream coming from the ADCITF1 selected

11: Stream coming from the ADCITF2 selected

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

28.8.8 ADF reshape filter configuration register 0 (ADF_DFLT0RSFR)

Address offset: 0x090

Reset value: 0x0000 0000

This register is used to control the reshape and HPF filter.

Bits 31:10 Reserved, must be kept at reset value.

Bits 9:8 HPFC[1:0] : High-pass filter cut-off frequency

This bitfield is set and cleared by software. it is used to select the cut-off frequency of the high-pass filter. F _PCM represents the sampling frequency at HPF input.

00: Cut-off frequency = 0.000625 x F _PCM

01: Cut-off frequency = 0.00125 x F _PCM

10: Cut-off frequency = 0.00250 x F _PCM

11: Cut-off frequency = 0.00950 x F _PCM

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bit 7 HPFBYP : High-pass filter bypass

This bit is set and cleared by software. It is used to bypass the high-pass filter.

0: HPF not bypassed (default value)

1: HPF bypassed

Note: This bit can be write-protected (see Section 28.4.13: Register protection for details).

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 RSFLTD : Reshaper filter decimation ratio

This bit is set and cleared by software. It is used to select the decimation ratio for the reshape filter

0: Decimation ratio is 4 (default value).

1: Decimation ratio is 1.

Note: This bit can be write-protected (see Section 28.4.13: Register protection for details).

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 RSFLTBY : Reshaper filter bypass

This bit is set and cleared by software. It is used to bypass the reshape filter and its decimation block.

0: Reshape filter not bypassed (default value)

1: Reshape filter bypassed

Note: This bit can be write-protected (see Section 28.4.13: Register protection for details).

28.8.9 ADF delay control register 0 (ADF_DLY0CR)

Address offset: 0x0A4

Reset value: 0x0000 0000

This register is used for the adjustment stream delays.

Bit 31 SKPBF : Skip busy flag

This bit is set and cleared by hardware. It is used to control if the delay sequence is completed.

0: ADF ready to accept a new value into SKPDLY[6:0]

1: Last valid SKPDLY[6:0] still under precessing

Bits 30:7 Reserved, must be kept at reset value.

Bits 6:0 SKPDLY[6:0] : Delay to apply to a bitstream

This bitfield is set and cleared by software. It defines the number of input samples that are skipped. Skipping is applied immediately after writing to this bitfield, if SKPBF = 0 and DFLTEN = 1. If SKPBF = 1, the value written into the register is ignored by the delay state machine.

0: No input sample skipped

1: 1 input sample skipped

...

127: 127 input samples skipped

28.8.10 ADF DFLT0 interrupt enable register (ADF_DFLT0IER)

Address offset: 0x0AC

Reset value: 0x0000 0000

This register is used for allowing or not the events to generate an interrupt.

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 SDLVLIE : SAD sound-level value ready enable

This bit is set and cleared by software.

0: Sound-level-ready interrupt disabled

1: Sound-level-ready interrupt enabled

Bit 12 SDDETIE : Sound activity detection interrupt enable

This bit is set and cleared by software.

0: Sound-trigger interrupt disabled

1: Sound-trigger interrupt enabled

Bit 11 RFOVRIE : Reshape filter overrun interrupt enable

This bit is set and cleared by software.

0: Reshape filter overrun interrupt disabled

1: Reshape filter overrun interrupt enabled

Bit 10 CKABIE : Clock absence detection interrupt enable

This bit is set and cleared by software.

0: Clock absence interrupt disabled

1: Clock absence interrupt enabled

Bit 9 SATIE : Saturation detection interrupt enable

This bit is set and cleared by software.

0: Saturation interrupt disabled

1: Saturation interrupt enabled

Bits 8:2 Reserved, must be kept at reset value.

Bit 1 DOVRIE : Data overflow interrupt enable

This bit is set and cleared by software.

0: Data overflow interrupt disabled

1: Data overflow interrupt enabled

Bit 0 FTHIE : RXFIFO threshold interrupt enable

This bit is set and cleared by software.

0: RXFIFO threshold interrupt disabled

1: RXFIFO threshold interrupt enabled

28.8.11 ADF DFLT0 interrupt status register 0 (ADF_DFLT0ISR)

Address offset: 0x0B0

Reset value: 0x0000 0000

This register contains the status flags for the digital filter path.

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 SDLVLF : Sound level value ready flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that new sound level value is not ready. Write 0 has no effect.

1: Read 1 means that new sound level value is ready. Write 1 clears this flag.

Bit 12 SDDETF : Sound activity detection flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no sound activity is detected. Write 0 has no effect.

1: Read 1 means that sound activity is detected. Write 1 clears this flag.

Bit 11 RFOVRF : Reshape filter overrun detection flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no reshape filter overrun is detected. Write 0 has no effect.

1: Read 1 means that reshape filter overrun is detected. Write 1 clears this flag.

Bit 10 CKABF : Clock absence detection flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no clock absence is detected. Write 0 has no effect.

1: Read 1 means that a clock absence is detected. Write 1 clears this flag.

Bit 9 SATF : Saturation detection flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no saturation is detected. Write 0 has no effect.

1: Read 1 means that a saturation is detected. Write 1 clears this flag.

Bits 8:4 Reserved, must be kept at reset value.

Bit 3 RXNEF : RXFIFO not empty flag

This bit is set and cleared by hardware according to the RXFIFO level.

0: RXFIFO empty

1: RXFIFO not empty

Bit 2 Reserved, must be kept at reset value.

Bit 1 DOVRF : Data overflow flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no overflow is detected. Write 0 has no effect.

1: Read 1 means that an overflow is detected; Write 1 clears this flag.

Bit 0 FTHF : RXFIFO threshold flag

This bit is set by hardware, and cleared by the hardware when the RXFIFO level is lower than the threshold.

0: RXFIFO threshold not reached

1: RXFIFO threshold reached

28.8.12 ADF SAD control register (ADF_SADCR)

Address offset: 0x0B8

Reset value: 0x0000 0000

This register is used for the configuration and the control of the sound activity detection.

Bit 31 SADACTIVE : SAD Active flag

This bit is set and cleared by hardware. It is used to check if the SAD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the SADACTIVE is set to 0 (see Section 28.4.13: Register protection for details).

The delay between a transition on SADEN and a transition on SADACTIVE is two periods of AHB clock and two periods of adf_proc_ck.

0: SAD not active and can be configured if needed

1: SAD active and protected fields cannot be configured.

Bits 30:14 Reserved, must be kept at reset value.

Bits 13:12 SADMOD[1:0] : SAD working mode

This bitfield is set and cleared by software. It is used to define the way the SAD works.

00: Threshold value computed according to the estimated ambient noise

The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a voice activity detector.

01: Threshold value equal to ANMIN[12:0], multiplied by the gain selected by SNTHR[3:0]

The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a sound detector.

1x: Threshold value given by 4 x ANMIN[12:0]

The SAD triggers when the estimated ambient noise (ANLVL), multiplied by the gain selected by SNTHR[3:0] is bigger than the defined threshold. In this mode, the SAD is working like an ambient noise estimator. Hysteresis function cannot be used in this mode.

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bit 11 Reserved, must be kept at reset value.

This bitfield is set and cleared by software. It is used to define the size of one frame and also to define how many samples are taken into account to compute the short-term signal level.

000: 8 PCM samples used to compute the short-term signal level

001: 16 PCM samples used to compute the short-term signal level

010: 32 PCM samples used to compute the short-term signal level

011: 64 PCM samples used to compute the short-term signal level

100: 128 PCM samples used to compute the short-term signal level

101: 256 PCM samples used to compute the short-term signal level

11x: 512 PCM samples used to compute the short-term signal level

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

This bit is set and cleared by software. It is used to enable/disable the hysteresis function (see Table 258 for details). This bit must be kept to 0 when SADMOD[1:0] = 1x.

0: Hysteresis function disabled. THR _H is always used.

1: Hysteresis function enabled. THR _H is used for MONITOR to DETECT transition and THR _L is used for DETECT to MONITOR transition.

Note: This bit can be write-protected (see Section 28.4.13: Register protection for details).

Bit 6 Reserved, must be kept at reset value.

This bitfield is set and cleared by hardware. It indicates the SAD state and is meaningful only when SADEN = 1. The SAD state can be:

- LEARN when the SAD is in learning phase or in SDLVL computation mode

- MONITOR when the SAD is in monitoring phase

- DETECT when the SAD detects a sound

00: SAD in LEARN state

01: SAD in MONITOR state

11: SAD in DETECT state

This bit is set and cleared by software. It is used to define if the sddet_evt event is generated only when the SAD enters to MONITOR state or when the SAD enters or exits the DETECT state.

0: sddet_evt generated when SAD enters the MONITOR state

1: sddet_evt generated when SAD enters or exits the DETECT state

Note: This bit can be write-protected (see Section 28.4.13: Register protection for details).

This bitfield is set and cleared by software. It is used to define in which conditions, the samples provided by DFLT0 are stored into the memory.

00: Samples from DFLT0 not transferred into the memory

01: Samples from DFLT0 transferred into the memory when SAD is in DETECT state

1x: Samples from DFLT0 transferred into memory when SAD and DFLT0 are enabled

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

This bit is set and cleared by software. It is used to enable/disable the SAD.

0: SAD disabled and SAD state reset

1: SAD enabled

28.8.13 ADF SAD configuration register (ADF_SADCFGR)

Address offset: 0x0BC

Reset value: 0x0000 0000

This register is used for the configuration of the sound activity detection.

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:16 ANMIN[12:0] : Minimum noise level

This bitfield is set and cleared by software. It is used to define the minimum noise level and then the sensitivity. It represents a positive number.

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bit 15 Reserved, must be kept at reset value.

Bits 14:12 HGOVR[2:0] : Hangover time window

This bitfield is set and cleared by software. Once the SAD state is DETECT, this parameter is used to define the amount of time the sound is allowed to remain below the threshold, before switching the SAD to MONITOR state (see FRSIZE bitfield for the description of a frame).

000: SAD back to MONITOR state if sound is below threshold for 4 frames

001: SAD back to MONITOR state if sound is below threshold for 8 frames

010: SAD back to MONITOR state if sound is below threshold for 16 frames

011: SAD back to MONITOR state if sound is below threshold for 32 frames

100: SAD back to MONITOR state if sound is below threshold for 64 frames

101: SAD back to MONITOR state if sound is below threshold for 128 frames

110: SAD back to MONITOR state if sound is below threshold for 256 frames

111: SAD back to MONITOR state if sound is below threshold for 512 frames

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 LFRNB[2:0] : Number of learning frames

This bitfield is set and cleared by software. It is used to define the number of learning frames to perform the first estimate of the noise level.

000: 2 frames used to compute the initial noise level

001: 4 frames used to compute the initial noise level

010: 8 frames used to compute the initial noise level

011: 16 frames used to compute the initial noise level

1xx: 32 frames used to compute the initial noise level

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 ANSLP[2:0] : Ambient noise slope control

This bitfield is set and cleared by software. It is used to define the positive and negative slope of the noise estimator, in charge of updating the ANLVL (see Ambient noise estimation (ANLVL) for information about programming this bitfield).

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

Bits 3:0 SNTHR[3:0] : Signal to noise threshold

This bitfield is set and cleared by software. It is used to define \( THR_H \) (and \( THR_L \) if hysteresis is enabled). See Table 258 for details.

0000: \( THR_H \) is 3.5 dB higher than ANLVL

0001: \( THR_H \) is 6.0 dB higher than ANLVL

0010: \( THR_H \) is 9.5 dB higher than ANLVL

0011: \( THR_H \) is 12 dB higher than ANLVL

0100: \( THR_H \) is 15.6 dB higher than ANLVL

0101: \( THR_H \) is 18 dB higher than ANLVL

0110: \( THR_H \) is 21.6 dB higher than ANLVL

0111: \( THR_H \) is 24.1 dB higher than ANLVL

1000: \( THR_H \) is 27.6 dB higher than ANLVL

1001: \( THR_H \) is 30.1 dB higher than ANLVL

others: Reserved

Note: This bitfield can be write-protected (see Section 28.4.13: Register protection for details).

28.8.14 ADF SAD sound level register (ADF_SADSDLVR)

Address offset: 0x0C0

Reset value: 0x0000 0000

This register contains the short-term sound-level computed by the SAD.

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:0 SDLVL[14:0] : Short term sound level

This bitfield is set by hardware. It contains the latest sound level computed by the SAD. To refresh this value, SDLVLF must be cleared.

28.8.15 ADF SAD ambient noise level register (ADF_SADANLVR)

Address offset: 0x0C4

Reset value: 0x0000 0000

This register contains the ambient noise level computed by the SAD.

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:0 ANLVL[14:0] : Ambient noise level estimation

This bitfield is set by hardware. It contains the latest ambient noise level computed by the SAD. To refresh this bitfield, the SDLVLF flag must be cleared.

28.8.16 ADF digital filter data register 0 (ADF_DFLT0DR)

Address offset: 0x0F0

Reset value: 0x0000 0000

This register is used to read the data processed by the digital filter.

Bits 31:8 DR[23:0] : Data processed by DFT0

Bits 7:0 Reserved, must be kept at reset value.

28.8.17 ADF register map

Table 271. ADF register map and reset values

Table 271. ADF register map and reset values (continued)

Table 271. ADF register map and reset values (continued)

Refer to Section 2.3: Memory organization for the register boundary addresses.