26. Comparator (COMP)

26.1 Introduction

The device embeds two ultra-low-power comparators COMP1 and COMP2.

These comparators can be used for a variety of functions including:

• Wake-up from low-power mode triggered by an analog signal
• Analog signal conditioning
• Cycle-by-cycle current control loop when combined with a PWM output from a timer

26.2 COMP main features

• Each comparator has configurable plus and minus inputs used for flexible voltage selection:
- – Multiplexed I/O pins
- – Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by a scaler (buffered voltage divider)
• Programmable hysteresis
• Programmable speed/consumption
• Outputs that can be redirected to an I/O or to timer inputs for triggering break events for fast PWM shutdowns
• Comparator outputs with blanking source
• Comparators that can be combined as a window comparator
• Interrupt generation capability for each comparator with wake-up from Sleep and Stop modes (through the EXTI controller)

26.3 COMP functional description

26.3.1 COMP block diagram

Figure 244. Comparator block diagrams

Figure 244. Comparator block diagram. The diagram shows the internal architecture of a comparator (COMPx). It includes two multiplexers for input selection: COMPx_INPSEL for the non-inverting input (COMPx_INP) and COMPx_INMSEL for the inverting input (COMPx_INM). The non-inverting input can be selected from COMPx_INP I/Os, COMPx_INP, or a reference voltage (VREFINT, 3/4 VREFINT, 1/2 VREFINT, 1/4 VREFINT). The inverting input can be selected from COMPx_INM I/Os, COMPx_INM, or a reference voltage. The comparator core (COMPx) compares these inputs. The output is controlled by COMPx_POLARITY and can be connected to a GPIO alternate function (COMPx_OUT) or internally redirected (compx_out (internal)). The output is also controlled by COMPx_VALUE and COMPx_WINOUT. A blank source is also shown.

26.3.2 COMP pins and internal signals

The I/Os used as comparators inputs must be configured in analog mode in the GPIOs registers.

The comparator output can be connected to the I/Os using the alternate function channel given in “Alternate function mapping” table in the datasheet.

The output can also be internally redirected to a variety of timer input for the following purposes:

• Emergency shut-down of PWM signals, using BKIN and BKIN2 inputs
• Cycle-by-cycle current control, using OCREF_CLR inputs
• Input capture for timing measures

The comparator output can be simultaneously redirected internally and externally.

Table 237. COMP1 noninverting input assignment

COMP1_INP	COMP1_INPSEL[1:0]
COMP1_INP1	00
COMP1_INP2	01
COMP1_INP3	10
COMP1_INP4	11

Table 238. COMP1 inverting input assignment

COMP1_INM	COMP1_INMSEL[3:0]
$\frac{1}{4} V_{REFINT}$	0000
$\frac{1}{2} V_{REFINT}$	0001
$\frac{3}{4} V_{REFINT}$	0010
$V_{REFINT}$	0011
DAC channel1	0100
DAC channel2	0101
COMP1_INM1	0110
COMP1_INM2	0111
Reserved	$\geq 1000$

Table 239. COMP2 noninverting input assignment

COMP2_INP	COMP2_INPSEL[1:0]
COMP2_INP1	00
COMP2_INP2	01
Reserved	10
Reserved	11

Table 240. COMP2 inverting input assignment

COMP2_INM	COMP2_INMSEL[3:0]
$\frac{1}{4} V_{REFINT}$	0000
$\frac{1}{2} V_{REFINT}$	0001
$\frac{3}{4} V_{REFINT}$	0010
$V_{REFINT}$	0011
DAC channel1	0100
DAC channel2	0101
COMP2_INM1	0110
COMP2_INM2	0111
Reserved	$\geq 1000$

Table 241. COMP1 output-blanking PWM assignment

PWM output	COMP1_BLANKSEL[4:0]
None (no blanking)	00000
tim1_oc5	xxxx1
tim2_oc3	xxx1x

Table 241. COMP1 output-blanking PWM assignment (continued)

PWM output	COMP1_BLANKSEL[4:0]
tim3_oc3	xx1xx
Reserved	Others

Table 242. COMP2 output-blanking PWM assignment

PWM output	COMP2_BLANKSEL[4:0]
None (no blanking)	00000
tim3_oc4	xxxx1
tim8_oc5 ⁽¹⁾	xxx1x
tim15_oc1	xx1xx
Reserved	Others

1. This internal connection is only available on STM32U3B5/U3C5 devices

26.3.3 Comparator LOCK mechanism

The comparators can be used for safety purposes, such as over-current or thermal protection. For applications having specific functional safety requirements, the comparator programming must not be altered in case of spurious register access or program counter corruption. For this purpose, the comparator control and status registers can be write-protected (read-only).

Once the programming is completed, the COMPxLOCK bit can be set to 1. This causes the whole COMPx_CSR register to become read-only, including the COMPxLOCK bit.

The write protection can be reset only by an MCU reset.

26.3.4 Window comparator

The purpose of the window comparator is to monitor the analog voltage if it is within the voltage range defined by the lower and upper thresholds.

The two embedded comparators can be used to create a window comparator. The monitored analog voltage is connected to the noninverting (plus) inputs of the two comparators connected together. The upper and lower threshold voltages are connected to the inverting (minus) inputs of the comparators.

Two noninverting inputs can be connected internally by enabling the WINMODE bit to save one I/O for other purposes.

Figure 245. Window mode

Schematic diagram of window mode using two comparators, COMPx and COMPy. COMPx has WINMODE = 0 and its output (COMPx_OUT) is the OR of its internal value (COMPx_VALUE) and the inverted output of COMPy (COMPy_OUT). COMPy has WINMODE = 1 and its output (COMPy_OUT) is the AND of its internal value (COMPy_VALUE) and the output of COMPx (COMPx_OUT). The input is connected to the non-inverting inputs (COMPx_INP, COMPy_INP). The upper threshold is connected to the inverting input of COMPx (COMPx_INM). The lower threshold is connected to the inverting input of COMPy (COMPy_INM).

26.3.5 Hysteresis

The comparator includes a programmable hysteresis to avoid spurious output transitions in case of noisy signals. The hysteresis can be disabled if it is not needed (for instance when exiting a low-power mode) to be able to force the hysteresis value using external components.

Figure 246. Comparator hysteresis

Timing diagram showing the effect of hysteresis on a comparator. The top graph shows the input signal (INP) as a sine wave and the inverting input (INM) as a constant reference voltage. The hysteresis is indicated by the difference between the rising and falling threshold levels (INM and INM-V_hyst). The bottom graph shows the output signal (COMP_OUT) as a square wave that toggles based on the input signal crossing these hysteresis thresholds.

26.3.6 Comparator output-blanking function

The blanking function prevents the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches anti parallel diodes). This blanking function consists of a selection of a blanking window that is a timer output compare signal. The selection is done by the software (refer to the comparator register description for possible blanking signals).

The complementary of the blanking signal is AND-ed with the comparator output to provide the wanted comparator output (see the example in Figure 247).

Figure 247. Comparator output blanking

The figure illustrates the comparator output blanking mechanism. It consists of two parts: a timing diagram and a logic schematic.

Timing Diagram:

PWM: A periodic square wave signal.
Inverting input (represents current limit): A dashed line representing a constant voltage threshold.
Noninverting input (represents current): A solid line representing a sawtooth-like current waveform that ramps up and then drops abruptly.
cmp_out (before blanking gate): The raw output signal, which shows narrow pulses when the noninverting input exceeds the inverting input. Two "spurious spikes" are circled on this signal, corresponding to the abrupt drops in the current waveform.
cmp_blk (blanking window): A signal that goes high for a short duration immediately following each drop in the current waveform.
comp_out (COMP output): The final output signal, which is the AND of the raw output and the blanking window. The spurious spikes are filtered out because they occur outside the blanking window.

Logic Schematic:

The cmp_out signal and the cmp_blk signal (inverted) are inputs to a 2-input AND gate labeled "Blanking gate".
The output of the gate is comp_out (to I/Os, TIM_BK ...) .

MSV30964V1

Timing diagram and logic schematic for comparator output blanking.

26.3.7 COMP power and speed modes

COMP1 and COMP2 power consumption versus propagation delay can be adjusted to have the optimum trade-off for a given application.

26.3.8 Scaler function

The scaler block provides the different voltage reference levels to the comparator inputs. This block is based on an amplifier driving a resistor bridge. The amplifier input is connected to the internal voltage reference. The amplifier and the resistor bridge are enabled by setting the INMSEL value in the COMP_CFGRx registers, to connect the corresponding inverting input to the scaler output.

When the divided voltage is not used, the resistor bridge and the amplifier are disabled to reduce the consumption. When the resistor bridge is disconnected, the 1/4 VREF_COMP, 1/2 VREF_COMP, and 3/4 VREF_COMP levels are equal to VREF_COMP.

Figure 248. Scaler

Circuit diagram of a comparator scaler. A comparator is shown with its non-inverting input (+) connected to VREFINT and its inverting input (-) connected to the output. The output is connected to a resistor ladder that produces four reference voltages: VREF_COMP, 3/4 VREF_COMP, 1/2 VREF_COMP, and 1/4 VREF_COMP. An INMSEL < 3 input controls a switch at the bottom of the ladder. The entire circuit is enclosed in a dashed box. MSV63603V1 is noted in the bottom right corner.

26.4 COMP in low-power modes

Table 243. Comparator behavior in the low-power modes

Mode	Description
Sleep	No effect on the comparators. Comparator interrupts cause the device to exit Sleep mode.
Stop	No effect on the comparators. Comparator interrupts cause the device to exit Stop mode.
Standby	COMP registers are powered down and must be reinitialized after exiting Standby mode.

26.5 COMP interrupts

The comparator outputs are internally connected to the extended interrupts and events controller (EXTI). Each comparator has its own EXTI line and can generate either interrupts or events. The same mechanism is used to exit the low-power modes.

Refer to Section 17: Extended interrupts and event controller (EXTI) for more details.

To enable the COMPx interrupt, follow this sequence:

1. Configure and enable the EXTI line corresponding to the COMPx output event in interrupt mode and select the rising, falling or both edges sensitivity.
2. Configure and enable the NVIC IRQ channel mapped to the corresponding EXTI lines.
3. Enable the COMPx.

Table 244. Interrupt control bits

Interrupt event	Event flag	Enable control bit	Exit Sleep mode	Exit Stop modes	Exit Standby mode
COMP1 output	In EXTI	Through EXTI	Yes	Yes	No
COMP2 output	In EXTI	Through EXTI	Yes	Yes	No

26.6 COMP registers

26.6.1 COMP1 control and status register (COMP1_CSR)

Address offset: 0x00

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK	VALUE	Res.	Res.	Res.	Res.	Res.	BLANKSEL[4:0]					PWRMODE[1:0]	HYST[1:0]
rs	r						rw	rw	rw	rw	rw	rw	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POLARITY	WINOUT	Res.	Res.	WINMODE	Res.	INPSEL[1:0]	INMSEL[3:0]				Res.	Res.	Res.	Res.	EN
rw	rw			rw		rw	rw	rw	rw	rw	rw				rw

Bit 31 LOCK : COMP1_CSR register lock

This bit is set by the software and cleared by reset. It locks the whole content of COMP1_CSR.

0: COMP1_CSR read/write bits can be written by software.

1: COMP1_CSR bits can be read but not written by software.

Bit 30 VALUE : COMP1 output status

This bit is read-only. It reflects the level of the COMP1 output after the polarity selector and blanking (see Figure 247: Comparator output blanking ).

Bits 29:25 Reserved, must be kept at reset value.

Bits 24:20 BLANKSEL[4:0] : COMP1 blanking source selector

This bitfield is controlled by software (if not locked), and selects the blanking source.

00000: None (no blanking)

00001: tim1_oc5

00010: tim2_oc3

Others: Reserved

Bits 19:18 PWRMODE[1:0] : COMP1 power mode selector

This bitfield is controlled by software (if not locked). It selects the power consumption and, as a consequence, the speed of the COMP1.

00: High speed

01: Intermediate speed and power

10: Medium speed and power

11: Ultra-low-power

Bits 17:16 HYST[1:0] : COMP1 hysteresis selector

This bitfield is controlled by software (if not locked). It selects the COMP1 hysteresis.

00: None

01: Low hysteresis

10: Medium hysteresis

11: High hysteresis

Bit 15 POLARITY : COMP1 polarity selector

This bit is controlled by software (if not locked). It selects the COMP1 output polarity.

0: Noninverted

1: Inverted

Bit 14 WINOUT : COMP1 output selector

This bit is controlled by the software (if not locked). It selects the COMP1 output.

0: COMP1_VALUE

1: COMP1_VALUE XOR COMP2_VALUE (required for window mode, see Figure 245: Window mode )

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WINMODE : COMP1 noninverting input selector for window mode

This bit is controlled by software (if not locked). It selects the signal for the COMP1_INP input of the COMP1.

0: Signal selected with INPSEL[1:0]

1: COMP2_INP signal of COMP2 (required for window mode, see Figure 245: Window mode )

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 INPSEL[1:0] : COMP1 signal selector for noninverting input

This bitfield is controlled by software (if not locked). It selects the signal for the noninverting input COMP1_INP (see Table 239: COMP2 noninverting input assignment for the assignment).

Bits 7:4 INMSEL[3:0] : COMP1 signal selector for inverting input INM

This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP1_INM (see Table 238: COMP1 inverting input assignment for the assignment).

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 EN : COMP1 enable

This bit is controlled by the software (if not locked). It enables COMP1.

0: COMP1 disabled

1: COMP1 enabled

26.6.2 COMP2 control and status register (COMP2_CSR)

Address offset: 0x04

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK	VALUE	Res.	Res.	Res.	Res.	Res.	BLANKSEL[4:0]					PWRMODE[1:0]	HYST[1:0]
rs	r						rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POLARITY	WINOUT	Res.	Res.	WINMODE	Res.	INPSEL[1:0]	INMSEL[3:0]				Res.	Res.	Res.	EN
rw	rw			rw		rw	rw	rw	rw	rw	rw				rw

Bit 31 LOCK : COMP2_CSR register lock

This bit is set by software and cleared by reset. It locks the whole content of COMP2_CSR.

0: COMP2_CSR read/write bits can be written by software.

1: COMP2_CSR bits can be read but not written by software.

Bit 30 VALUE : COMP2 output status

This bit is read-only. It reflects the level of the COMP2 output after the polarity selector and blanking (see Figure 247: Comparator output blanking ).

Bits 29:25 Reserved, must be kept at reset value.

Bits 24:20 BLANKSEL[4:0] : COMP2 blanking source selector

This bitfield is controlled by software (if not locked), and selects the blanking source.

00000: None (no blanking)

00001: tim3_oc4

Others: Reserved

Bits 19:18 PWRMODE[1:0] : COMP2 power mode selector

This bitfield is controlled by software (if not locked). It selects the power consumption and, as a consequence, the speed of the COMP2.

00: High speed

01: Intermediate speed and power

10: Medium speed and power

11: Ultra-low-power

Bits 17:16 HYST[1:0] : COMP2 hysteresis selector

This bitfield is controlled by software (if not locked). It selects the COMP2 hysteresis.

00: None

01: Low hysteresis

10: Medium hysteresis

11: High hysteresis

Bit 15 POLARITY : COMP2 polarity selector

This bit is controlled by software (if not locked). It selects the COMP2 output polarity.

0: Noninverted

1: Inverted

Bit 14 WINOUT : COMP2 output selector

This bit is controlled by software (if not locked). It selects the COMP2 output.

0: COMP2_VALUE

1: COMP1_VALUE XOR COMP2_VALUE (required for window mode, see Figure 245: Window mode )

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WINMODE : COMP2 noninverting input selector for window mode

This bit is controlled by software (if not locked). It selects the signal for the COMP2_INP input of the COMP2.

0: Signal selected with INPSEL[1:0]
1: COMP1_INP signal of COMP1 (required for window mode, see Figure 245: Window mode )

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 INPSEL[1:0] : COMP2 signal selector for noninverting input

This bitfield is controlled by software (if not locked). It selects the signal for the noninverting input COMP2_INP (see Figure 239: COMP2 noninverting input assignment for the assignment).

Bits 7:4 INMSEL[3:0] : COMP2 signal selector for inverting input INM

This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP2_INM (see Figure 238: COMP1 inverting input assignment for the assignment).

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 EN : COMP2 enable

This bit is controlled by software (if not locked). It enables COMP2.

0: COMP2 disabled
1: COMP2 enabled

26.6.3 COMP register map

Table 245. COMP register map and reset values

Offset	Register name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	COMP1_CSR	LOCK	VALUE	Res.	Res.	Res.	Res.	Res.	BLANKSEL[4:0]					PWRMODE[1:0]		HYST[1:0]		POLARITY	WINOUT	Res.	Res.	WINMODE	Res.	INPSEL[1:0]		INPSEL[3:0]				Res.	Res.	EN
0x00	Reset value	0	0						0	0	0	0	0	0	0	0	0	0	0			0		0	0	0	0	0	0				0
0x04	COMP2_CSR	LOCK	VALUE	Res.	Res.	Res.	Res.	Res.	BLANKSEL[4:0]					PWRMODE[1:0]		HYST[1:0]		POLARITY	WINOUT	Res.	Res.	WINMODE	Res.	INPSEL[1:0]		INPSEL[3:0]				Res.	Res.	EN
0x04	Reset value	0	0						0	0	0	0	0	0	0	0	0	0	0			0		0	0	0	0	0	0				0

Refer to Section 2.3 for the register boundary addresses.