17. Extended interrupts and event controller (EXTI)

17.1 EXTI introduction

The extended interrupts and event controller (EXTI) manages the individual CPU and system wake-up through configurable event inputs. It provides wake-up requests to the power control and generates an interrupt request to the CPU NVIC and events to the CPU event input. For the CPU, an additional event generation block (EVG) is needed to generate the CPU event signal.

The EXTI wake-up requests allow the system to be woken up from Stop modes.

The interrupt request and event request generation can be used also in Run modes. The EXTI also includes the EXTI mux I/O port selection.

17.2 EXTI main features

The EXTI main features are the following:

• Up to 23 input events supported
• All event inputs allow the possibility to wake up the system
• Events that do not have an associated wake-up flag in the peripheral, have a flag in the EXTI and generate an interrupt to the CPU from the EXTI
• Events can be used to generate a CPU wake-up event
• Secure events: The access to control and configuration bits of secure input events can be made secure
• EXTI I/O port selection

The configurable events have the following features:

• Selectable active trigger edge
• Interrupt pending status register bits independent for the rising and falling edge
• Individual interrupt and event generation mask, used for conditioning the CPU wake-up, interrupt and event generation
• Software trigger possibility

17.3 EXTI functional description

17.3.1 EXTI block diagram

The EXTI consists of a register block accessed via an AHB interface, the event input trigger block, the masking block and EXTI mux as shown in Figure 63 .

The register block contains all the EXTI registers.

The event input trigger block provides event input edge trigger logic.

The masking block provides the event input distribution to the different wake-up, interrupt and event outputs, and their masking.

The EXTI mux provides the I/O port selection of the EXTI event signal.

Figure 63. EXTI block diagram

Figure 63. EXTI block diagram. The diagram shows the internal architecture of the EXTI block. It includes an AHB interface connected to Registers, which are also connected to an EXTI multiplexer (EXTI mux). The EXTI mux receives inputs from GPIO IOPort and Peripherals (Configurable event(15:0) and Wake-up). The EXTI mux output goes to an Event trigger, which then connects to a Masking block. The Masking block output goes to a Pulse block, which is part of the EVG (Event Generator). The EVG output (c_event) goes to the CPU (specifically rxev and nvic(x)). The EVG also receives inputs from the CPU (c_evt_exti and c_evt_rst) and a CPU clock (c_fclk). The EXTI block also has output signals: exti_ilac, exti[15:0] (To interconnect), sys_wake-up, c_wake-up (to PWR), and it_exti_per(y) (to CPU).

Table 135. EXTI signals

Name	I/O	Description
AHB interface	I/O	EXTI register bus interface. When one event is configured to enable security, the AHB interface supports secure accesses.
hclk	I	AHB bus clock and EXTI system clock
Configurable event(y)	I	Asynchronous wake-up events from peripherals that do not have an associated interrupt and flag in the peripheral
exti_ilac	O	Illegal access event
IOPort(n)	I	GPIOs block I/O ports[15:0]
exti[15:0]	O	EXTI GPIO output port to trigger other peripherals
it_exti_per (y)	O	Interrupts to the CPU associated with configurable event (y)
c_evt_exti	O	High-level sensitive event output for CPU, synchronous to hclk
c_evt_rst	I	Asynchronous reset input to clear c_evt_exti
sys_wakeup	O	Asynchronous system wake-up request to PWR for ck_sys and hclk
c_wakeup	O	Wake-up request to PWR for CPU, synchronous to hclk

Table 136. EVG signals

Name	I/O	Description
c_fclk	I	CPU free running clock
c_evt_in	I	High-level sensitive events input from EXTI, asynchronous to CPU clock
c_event	O	Event pulse, synchronous to CPU clock
c_evt_rst	O	Event reset signal, synchronous to CPU clock

EXTI connections between peripherals and CPU

Some peripherals able to generate wake-up or interrupt events when the system is in Stop mode, are connected to the EXTI.

• Peripheral wake-up signals that generate a pulse or do not have an interrupt status bits in the peripheral, are connected to an EXTI configurable event input. For these events, the EXTI provides a status pending bit that requires to be cleared. It is the EXTI interrupt, associated with the status bit, that interrupts the CPU.
• All GPIO ports input to the EXTI multiplexer allow the selection of a port pin to wake up the system via a configurable event.

The EXTI configurable event interrupts are connected to the NVIC.

The dedicated EXTI/EVG CPU event is connected to the CPU rxeiv input.

The EXTI CPU wake-up signals are connected to the PWR and are used to wake up the system and the CPU sub- system bus clocks.

EXTI interrupt/event mapping

The EXTI lines are connected as shown in the table below.

Table 137. EXTI line connections

EXTI line	Line source	Line type
0-15	GPIO	Configurable
16	PVD output	Configurable
17	COMP1 output	Configurable
18	COMP2 output	Configurable
19	V _DDUSBvoltage monitor	Configurable
20	V _DDIO2voltage monitor ⁽¹⁾	Configurable
21	V _DDAvoltage monitor 1	Configurable
22	V _DDAvoltage monitor 2	Configurable

1. VDDIO2 is not available on STM32U356/366

17.3.2 Event features control

The events features are controlled from register bits as follows:

• Active trigger edge enable by
- – rising edge selection in the EXTI rising trigger selection register (EXTI_RTSR1)
- – falling edge selection in the EXTI falling trigger selection register (EXTI_FTSR1)

• Software trigger in the EXTI software interrupt event register (EXTI_SWIER1)
• Interrupt pending flag in the
- – EXTI rising edge pending register (EXTI_RPR1)
- – EXTI falling edge pending register (EXTI_FPR1)
• CPU wake-up and interrupt enable in the
- – EXTI CPU wake-up with interrupt mask register (EXTI_IMR1)
• CPU wake-up and event enable
- – EXTI CPU wake-up with event mask register (EXTI_EMR1)

17.3.3 EXTI configurable event input wake-up

The figure below is a detailed representation of the logic associated with configurable event inputs that wake up the CPU sub-system bus clocks and generate an EXTI pending flag and interrupt to the CPU, and/or a CPU wake-up event.

Figure 64. Configurable event trigger logic CPU wake-up

Figure 64: Configurable event trigger logic CPU wake-up. This block diagram shows the internal logic of the EXTI peripheral. On the left, an 'AHB interface' and 'hclk' clock are connected to a 'Peripheral interface' block. This block contains several registers: 'Falling trigger selection register', 'Rising trigger selection register', 'Software interrupt event register', 'CPU event mask register', 'CPU interrupt mask register', and 'Pending request register'. Below these registers, a 'Configurable event input(y)' is connected to an 'Asynchronous edge detection circuit rst'. This circuit's output goes to a 'Rising edge detect pulse generator' (which also takes 'hclk' and 'rst' as inputs) and to an AND gate. The AND gate also takes inputs from the 'Rising trigger selection register' and the 'CPU interrupt mask register'. The output of this AND gate is labeled 'CPU event(y) (1)'. This signal is ORed with 'Other CPU events(x,y)' to produce a signal that goes to a 'Rising edge detect rst' block (taking 'hclk' and 'rst' inputs). The output of this block is labeled 'c_evt_rst'. Another signal, 'c_evt_exti', is also input to this block. The outputs of the 'Rising edge detect rst' block go to an 'EVG' (Event Generator) block, which also takes 'ck_folk_c' as input. The EVG block produces a 'c_event' output. Below the AND gate, another AND gate takes inputs from the 'Software interrupt event register' and the 'CPU interrupt mask register'. Its output is ORed with 'Other CPU wake-ups' to produce 'CPU wake-up(y)'. This signal is then passed through a 'Synch' (synchronizer) block taking 'hclk' to produce 'c_wake-up'. Below this, another OR gate combines 'Other wake-ups' and 'wake-up(y)' to produce 'sys_wake-up'. The 'Pending request register' is connected to the 'CPU event(y) (1)' signal and the 'it_exti_per(y)' output. The diagram is labeled 'EXTI' at the bottom left and 'MSv62643V1' at the bottom right.

1. Only for the input events that support CPU rxeu generation c_event .

The software interrupt event register allows configurable events to be triggered by software, writing the corresponding register bit, whatever the edge selection setting.

The configurable event active trigger edge (or both edges) is selected and enabled in the rising/falling edge selection registers.

The CPU has its dedicated wake-up (interrupt) mask register and a dedicated event mask registers. When the event is enabled, it is generated to the CPU. All events for the CPU are ORed together into a single CPU event signal. The event pending registers (EXTI_RPR1 and EXTI_FPR1) are not set for an unmasked CPU event.

The configurable events have unique interrupt pending request registers. The pending register is only set for an unmasked interrupt. Each configurable event provides a common interrupt to the CPU. The configurable event interrupts must be acknowledged by software in the EXTI_RPR1 and/or EXTI_FPR1 registers.

When a CPU wake-up (interrupt) or CPU event is enabled, the asynchronous edge detection circuit is reset by the clocked delay and rising edge detect pulse generator. This guarantees that the EXTI hclk clock is woken up before the asynchronous edge detection circuit is reset.

Note: A detected configurable event interrupt pending request can be cleared by the CPU with the correct access permission. The system is not able to enter into low-power modes as long as an interrupt pending request is active.

17.3.4 EXTI mux selection

The EXTI mux allows the selection of GPIOs as interrupts and wake-up. GPIOs are connected via 16 EXTI mux lines to the first 16 EXTI events as configurable event.

The selection of GPIO port as EXTI mux output is controlled in the EXTI_EXTICRx.

Figure 65. EXTI mux GPIO selection

Diagram of EXTI mux GPIO selection showing three multiplexers. The first multiplexer (EXTI_EXTICR1.EXTI0) selects between PA0, PB0, PC0, and Px0 to output EXTI0. The second multiplexer (EXTI_EXTICR1.EXTI1) selects between PA1, PB1, PC1, and Px1 to output EXTI1. The third multiplexer (EXTI_EXTICR4.EXTI15) selects between PA15, PB15, PC15, and Px15 to output EXTI15. A dashed line connects EXTI1 to EXTI15. The diagram is labeled MSv44726V1.

The EXTI mux outputs are available as output signals from the EXTI to trigger other peripherals, whatever the masking in EXTI_IMR1 and EXTI_EM1 registers.

17.3.5 EXTI functional behavior

The configurable events are enabled by enabling at least one of the trigger edges.

Once an event input is enabled, the CPU wake-up generation is conditioned by the CPU interrupt mask and CPU event mask.

Table 138. Masking functionality

CPU interrupt enable (in EXTI_IMR.IMn)	CPU event enable (in EXTI_EM1.EMn)	Configurable event inputs (in EXTI_RPR.RPIFn and EXTI_FPR.FPIFn)	Exti(n) interrupt ⁽¹⁾	CPU event	CPU wake-up
0	0	No	Masked	Masked	Masked
0	1	No	Masked	Yes	Yes
1	0	Status latched	Yes	Masked	Yes ⁽²⁾
1	1	Status latched	Yes	Yes	Yes

1. The single exti(n) interrupt goes to the CPU. If no interrupt is required for CPU(m), the exti(n) interrupt must be masked in the CPU NVIC.

2. Only if CPU interrupt is enabled in EXTI_IMR1.IMn.

For configurable event inputs, when the enabled edges occur on the event input, an event request is generated. When the associated CPU interrupt is unmasked, the corresponding pending bits EXTI_RPR1.RPIFn and/or EXTI_FPR1.FPIFn is/are set: the CPU sub-system

is woken up and the CPU interrupt signal is activated. The EXTI_RPR1.RPIFn and/or EXTI_FPR1.FPIFn pending bits must be cleared by software writing it to 1. This action clears the CPU interrupt.

For the configurable event inputs, an event request can be generated by software when writing a 1 in the software interrupt/event register EXTI_SWIER1, allowing the generation of a rising edge on the event. The rising edge event pending bit is set in EXTI_RPR1, whatever the setting in EXTI_RTSR1.

17.3.6 EXTI event protection

The EXTI is able to protect event register bits from being modified by nonsecure and unprivileged accesses. The protection is individually activated per input event via the register bits in EXTI_SECCFGR1 and EXTI_PRIVCFGR1. At EXTI level, the protection consists in preventing the following unauthorized write access:

• Change the settings of the secure and/or privileged configurable events.
• Change the masking of the secure and/or privileged input events.
• Clear pending status of the secure and/or privileged input events.

Table 139. Register protection overview

Register name	Access type	Protection ⁽¹⁾⁽²⁾
EXTI_RTSR1	RW	Security and privilege can be bit-wise enabled in EXTI_SECCFGR1 and EXTI_PRIVCFGR1.
EXTI_FTSR1	RW
EXTI_SWIER1	RW
EXTI_RPR1	RW
EXTI_FPR1	RW
EXTI_SECCFGR1	RW	Always secure. Privilege can be bit-wise enabled in EXTI_PRIVCFGR1.
EXTI_PRIVCFGR1	RW	Always privilege. Security can be bit-wise enabled in EXTI_SECCFGR1.
EXTI_EXTICRx	RW	Security and privilege can be bit-wise enabled in EXTI_SECCFGR1 and EXTI_PRIVCFGR1.
EXTI_LOCKR	RW	Always secure.
EXTI_IMR1	RW	Security and privilege can be bit-wise enabled in EXTI_SECCFGR1 and EXTI_PRIVCFGR1.
EXTI_EMR1	RW

1. Privilege is enabled with the individual Input event (EXTI_PRIVCFGR1 register).

2. Security is enabled with the individual input event (EXTI_SECCFGR1 register).

EXTI security protection

When security is enabled for an input event, the associated input event configuration and control bits can only be modified and read by a secure access. A nonsecure write access is discarded and a read returns 0.

When input events are nonsecure, the security is disabled. The associated input event configuration and control bits can be modified and read by a secure access and nonsecure access.

The security configuration in EXTI_SECCFGR1 can be globally locked after reset by EXTI_LOCKR.LOCK.

EXTI privilege protection

When privilege is enabled for an input event, the associated input event configuration and control bits can only be modified and read by a privileged access. An unprivileged write access is discarded and a read returns 0.

When input events are unprivileged, the privilege is disabled. The associated input event configuration and control bits can be modified and read by a privileged access and unprivileged access.

The privileged configuration in EXTI_PRIVCFGR1 can be globally locked after reset by EXTI_LOCKR.LOCK.

17.4 EXTI registers

All registers can be accessed with word (32-bit), half-word (16-bit), and byte (8-bit) access.

17.4.1 EXTI rising trigger selection register (EXTI_RTSR1)

Address offset: 0x000

Reset value: 0x0000 0000

This register contains only bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RT22	RT21	RT20	RT19	RT18	RT17	RT16
									rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RT15	RT14	RT13	RT12	RT11	RT10	RT9	RT8	RT7	RT6	RT5	RT4	RT3	RT2	RT1	RT0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 RTi : Rising trigger event configuration bit of configurable event input $i^{(1)}$ ( $$ i = 22 $$ to 0)

When EXTI_SECCFGR.SECi is disabled, RTi can be accessed with nonsecure and secure access.

When EXTI_SECCFGR.SECi is enabled, RTi can only be accessed with secure access. Nonsecure write to this bit $$ i $$ is discarded and nonsecure read returns 0.

When EXTI_PRIVCFGR.PRIVi is disabled, RTi can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVi is enabled, RTi can only be accessed with privileged access. Unprivileged write to this bit $$ i $$ is discarded. Unprivileged read returns 0.

0: Rising trigger disabled (for event and interrupt) for input line

1: Rising trigger enabled (for event and interrupt) for input line

1. The configurable event inputs are edge triggered. No glitch must be generated on these inputs. If a rising edge on the configurable event input occurs during writing of the register, the associated pending bit is not set. Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

17.4.2 EXTI falling trigger selection register (EXTI_FTSR1)

Address offset: 0x004

Reset value: 0x0000 0000

This register contains only bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	FT22	FT21	FT20	FT19	FT18	FT17	FT16
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FT15	FT14	FT13	FT12	FT11	FT10	FT9	FT8	FT7	FT6	FT5	FT4	FT3	FT2	FT1	FT0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 FTi : Falling trigger event configuration bit of configurable event input i ⁽¹⁾(i = 22 to 0)

When EXTI_SECCFGR.SECi is disabled, FTi can be accessed with nonsecure and secure access.

When EXTI_SECCFGR.SECi is enabled, FTi can only be accessed with secure access.

Nonsecure write to this FTi is discarded. Nonsecure read returns 0.

When EXTI_PRIVCFGR.PRIVi is disabled, FTi can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVi is enabled, FTi can only be accessed with privileged access.

Unprivileged write to this FTi is discarded, unprivileged read returns 0.

0: Falling trigger disabled (for event and interrupt) for input line

1: Falling trigger enabled (for event and interrupt) for input line.

1. The configurable event inputs are edge triggered. No glitch must be generated on these inputs. If a falling edge on the configurable event input occurs during writing of the register, the associated pending bit is not set. Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

17.4.3 EXTI software interrupt event register (EXTI_SWIER1)

Address offset: 0x008

Reset value: 0x0000 0000

This register contains only bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SWI22	SWI21	SWI20	SWI19	SWI18	SWI17	SWI16
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWI15	SWI14	SWI13	SWI12	SWI11	SWI10	SWI9	SWI8	SWI7	SWI6	SWI5	SWI4	SWI3	SWI2	SWI1	SWI0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 SWIi : Software interrupt on event i (i = 22 to 0)

When EXTI_SECCFGR.SECi is disabled, SWIi can be accessed with nonsecure and secure access.

When EXTI_SECCFGR.SECi is enabled, SWIi can only be accessed with secure access.

Nonsecure write to this SWIi is discarded. Nonsecure read returns 0.

When EXTI_PRIVCFGR.PRIVI is disabled, SWIi can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVI is enabled, SWIi can only be accessed with privileged access. Unprivileged write to this SWIi is discarded, unprivileged read returns 0.

A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read.

0: Writing 0 has no effect.

1: Writing 1 triggers a rising edge event on event i. This bit is auto cleared by hardware.

17.4.4 EXTI rising edge pending register (EXTI_RPR1)

Address offset: 0x00C

Reset value: 0x0000 0000

This register contains only bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RPIF22	RPIF21	RPIF20	RPIF19	RPIF18	RPIF17	RPIF16
									rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RPIF15	RPIF14	RPIF13	RPIF12	RPIF11	RPIF10	RPIF9	RPIF8	RPIF7	RPIF6	RPIF5	RPIF4	RPIF3	RPIF2	RPIF1	RPIF0
rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 RPIFi : Configurable event input i rising edge pending bit (i = 22 to 0)

When EXTI_SECCFGR.SECi is disabled, RPIFi can be accessed with nonsecure and secure access.

When EXTI_SECCFGR.SECi is enabled, RPIFi can only be accessed with secure access.

Nonsecure write to this RPIFi is discarded. Nonsecure read returns 0.

When EXTI_PRIVCFGR.PRIVI is disabled, RPIFi can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVI is enabled, RPIFi can only be accessed with privileged access. Unprivileged write to this RPIFi is discarded, unprivileged read returns 0.

This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it.

0: No rising edge trigger request occurred.

1: Rising edge trigger request occurred.

17.4.5 EXTI falling edge pending register (EXTI_FPR1)

Address offset: 0x010

Reset value: 0x0000 0000

This register contains only bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	FPIF22	FPIF21	FPIF20	FPIF19	FPIF18	FPIF17	FPIF16
									rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FPIF15	FPIF14	FPIF13	FPIF12	FPIF11	FPIF10	FPIF9	FPIF8	FPIF7	FPIF6	FPIF5	FPIF4	FPIF3	FPIF2	FPIF1	FPIF0
rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 FPIFi : configurable event inputs i falling edge pending bit (i = 22 to 0)

When EXTI_SECCFGR.SECi is disabled, FPIFi can be accessed with nonsecure and secure access.

When EXTI_SECCFGR.SECi is enabled, FPIFi can only be accessed with secure access.

Nonsecure write to this FPIFi is discarded, nonsecure read returns 0.

When EXTI_PRIVCFGR.PRIVi is disabled, FPIFi can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVi is enabled, FPIFi can only be accessed with privileged access. Unprivileged write to this FPIFi is discarded, unprivileged read returns 0.

This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it.

0: No falling edge trigger request occurred

1: Falling edge trigger request occurred

17.4.6 EXTI security configuration register (EXTI_SECCFGR1)

Address offset: 0x014

Reset value: 0x0000 0000

This register provides write access security. A nonsecure write access is ignored and causes the generation of an illegal access event. A nonsecure read returns the register data. This register contains only bits for security capable input events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16
									rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 SECi : Security enable on event input i (i = 22 to 0)

When EXTI_PRIVCFG.PRIVi is disabled, SECi can be accessed with privileged and unprivileged access.
When EXTI_PRIVCFG.PRIVi is enabled, SECi can only be written with privileged access. Unprivileged write to this SECi is discarded.

0: Event security disabled (nonsecure)

1: Event security enabled (secure)

17.4.7 EXTI privilege configuration register (EXTI_PRIVCFG1)

Address offset: 0x018

Reset value: 0x0000 0000

This register provides privileged write access protection. An unprivileged read returns the register data. This register contains only bits for security capable input events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16
									rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 PRIVi : Security enable on event input i ( i = 22 to 0)

When EXTI_SECCFG.SECi is disabled, PRIVi can be accessed with secure and nonsecure access.

When EXTI_SECCFG.SECi is enabled, PRIVi can only be written with secure access.

Nonsecure write to this PRIVi is discarded.

0: Event privilege disabled (unprivileged)

1: Event privilege enabled (privileged)

17.4.8 EXTI external interrupt selection register (EXTI_EXTICRx)

Address offset: 0x060 + 0x4 * ( x - 1) ( x = 1 to 4)

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EXTI{4*(x-1)+3}[7:0]								EXTI{4*(x-1)+2}[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI{4*(x-1)+1}[7:0]								EXTI{4*(x-1)}[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:24 EXTI{4 * (x - 1) + 3}[7:0]: EXTI{4 * (x - 1) + 3} GPIO port selection

These bits are written by software to select the source input for EXTI{4 * (x - 1) + 3} external interrupt.

When EXTI_SECCFGR.SEC{4 * (x - 1) + 3} is disabled, this bitfield can be accessed with nonsecure and secure access.

When EXTI_SECCFGR.SEC{4 * (x - 1) + 3} is enabled, this bitfield can only be accessed with secure access. Nonsecure write is discarded. Nonsecure read returns 0.

When EXTI_PRIVCFGR.PRIV{4 * (x - 1) + 3} is disabled, this bitfield can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR.PRIV{4 * (x - 1) + 3} is enabled, this bitfield can only be accessed with privileged access. Unprivileged write to this bit is discarded.

0x00: PA[{4 * (x - 1) + 3}] pin

0x01: PB[{4 * (x - 1) + 3}] pin

0x02: PC[{4 * (x - 1) + 3}] pin

0x03: PD[{4 * (x - 1) + 3}] pin

0x04: PE[{4 * (x - 1) + 3}] pin

0x05: PF[{4 * (x - 1) + 3}] pin

0x06: PG[{4 * (x - 1) + 3}] pin

0x07: PH[{4 * (x - 1) + 3}] pin

Others: Reserved

Note: Port F is only available on STM32U3B5/3C5.

Port G is not available on STM32U356/366.

Bits 23:16 EXTI{4 * (x - 1) + 2}[7:0]: EXTI{4 * (x - 1) + 2} GPIO port selection

These bits are written by software to select the source input for EXTI{4 * (x - 1) + 2} external interrupt.

When EXTI_SECCFGR.SEC{4 * (x - 1) + 2} is disabled, this bitfield can be accessed with nonsecure and secure access.

When EXTI_SECCFGR.SEC{4 * (x - 1) + 2} is enabled, this bitfield can only be accessed with secure access. Nonsecure write is discarded. Nonsecure read returns 0.

When EXTI_PRIVCFGR.PRIV{4 * (x - 1) + 2} is disabled, this bitfield can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR.PRIV{4 * (x - 1) + 2} is enabled, this bitfield can only be accessed with privileged access. Unprivileged write to this bit is discarded.

0x00: PA[{4 * (x - 1) + 2}] pin

0x01: PB[{4 * (x - 1) + 2}] pin

0x02: PC[{4 * (x - 1) + 2}] pin

0x03: PD[{4 * (x - 1) + 2}] pin

0x04: PE[{4 * (x - 1) + 2}] pin

0x05: PF[{4 * (x - 1) + 2}] pin

0x06: PG[{4 * (x - 1) + 2}] pin

0x07: PH[{4 * (x - 1) + 2}] pin

Others: Reserved

Note: Port F is only available on STM32U3B5/3C5.

Port G is not available on STM32U356/366.

Bits 15:8 EXTI{4 * (x - 1) + 1}[7:0]: EXTI{4 * (x - 1) + 1} GPIO port selection

These bits are written by software to select the source input for EXTI{4 * (x - 1) + 1} external interrupt.

When EXTI_SECCFGR.SEC{4 * (x - 1) + 1} is disabled, this bitfield can be accessed with nonsecure and secure access.

When EXTI_SECCFGR.SEC{4 * (x - 1) + 1} is enabled, this bitfield can only be accessed with secure access. Nonsecure write is discarded. Nonsecure read returns 0.

When EXTI_PRIVCFGR.PRIV{4 * (x - 1) + 1} is disabled, this bitfield can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR.PRIV{4 * (x - 1) + 1} is enabled, this bitfield can only be accessed with privileged access. Unprivileged write to this bit is discarded.

0x00: PA[{4 * (x - 1) + 1}] pin

0x01: PB[{4 * (x - 1) + 1}] pin

0x02: PC[{4 * (x - 1) + 1}] pin

0x03: PD[{4 * (x - 1) + 1}] pin

0x04: PE[{4 * (x - 1) + 1}] pin

0x05: PF[{4 * (x - 1) + 1}] pin

0x06: PG[{4 * (x - 1) + 1}] pin

0x07: PH[{4 * (x - 1) + 1}] pin

Others: Reserved

Note: Port F is only available on STM32U3B5/3C5.

Port G is not available on STM32U356/366.

Bits 7:0 EXTI{4 * (x - 1)}[7:0]: EXTI{4 * (x - 1)} GPIO port selection

These bits are written by software to select the source input for EXTI{4 * (x - 1)} external interrupt.

When EXTI_SECCFGR.SEC{4 * (x - 1)} is disabled, this bitfield can be accessed with nonsecure and secure access.

When EXTI_SECCFGR.SEC{4 * (x - 1)} is enabled, this bitfield can only be accessed with secure access. Nonsecure write is discarded. Nonsecure read returns 0.

When EXTI_PRIVCFGR.PRIV{4 * (x - 1)} is disabled, this bitfield can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR.PRIV{4 * (x - 1)} is enabled, this bitfield can only be accessed with privileged access. Unprivileged write to this bit is discarded.

0x00: PA[{4 * (x - 1)}] pin

0x01: PB[{4 * (x - 1)}] pin

0x02: PC[{4 * (x - 1)}] pin

0x03: PD[{4 * (x - 1)}] pin

0x04: PE[{4 * (x - 1)}] pin

0x05: PF[{4 * (x - 1)}] pin

0x06: PG[{4 * (x - 1)}] pin

0x07: PH[{4 * (x - 1)}] pin

Others: Reserved

Note: Port F is only available on STM32U3B5/3C5.

Port G is not available on STM32U356/366.

17.4.9 EXTI lock register (EXTI_LOCKR)

Address offset: 0x070

Reset value: 0x0000 0000

This register provides write access security: a nonsecure write access is ignored, a read access returns zero data, and both generates an illegal access event.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	LOCK
															rs

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 LOCK : Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock

This bit is written once after reset.

0: Security and privilege configuration open, can be modified.

1: Security and privilege configuration locked, can no longer be modified.

17.4.10 EXTI CPU wake-up with interrupt mask register (EXTI_IMR1)

Address offset: 0x080

Reset value: 0x0000 0000

This register contains bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	IM22	IM21	IM20	IM19	IM18	IM17	IM16
									rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM15	IM14	IM13	IM12	IM11	IM10	IM9	IM8	IM7	IM6	IM5	IM4	IM3	IM2	IM1	IM0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 IMi : CPU wake-up with interrupt mask on event input i ⁽¹⁾(i = 22 to 0)

When EXTI_SECCFGR.SECi is disabled, IMi can be accessed with nonsecure and secure access.

When EXTI_SECCFGR.SECi is enabled, IMi can only be accessed with secure access.

Nonsecure write to this bit is discarded. Nonsecure read returns 0.

When EXTI_PRIVCFGR.PRIVI is disabled, IMi can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR.PRIVI is enabled, IMi can only be accessed with privileged access.

Unprivileged write to this bit is discarded.

0: Wake-up with interrupt request from input event i is masked.

1: Wake-up with interrupt request from input event i is unmasked.

1. The reset value for configurable event inputs is set to 0 in order to disable the interrupt by default.

17.4.11 EXTI CPU wake-up with event mask register (EXTI_EMR1)

Address offset: 0x084

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	EM22	EM21	EM20	EM19	EM18	EM17	EM16
									rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EM15	EM14	EM13	EM12	EM11	EM10	EM9	EM8	EM7	EM6	EM5	EM4	EM3	EM2	EM1	EM0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 EMi : CPU wake-up with event generation mask on event input i (i = 22 to 0)

When EXTI_SECCFGR.SECi is disabled, EMi can be accessed with nonsecure and secure access.

When EXTI_SECCFGR.SECi is enabled, EMi can only be accessed with secure access.

Nonsecure write to this EMi is discarded. Nonsecure read returns 0.

When EXTI_PRIVCFGR.PRIVi is disabled, EMi can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR.PRIVi is enabled, EMi can only be accessed with privileged access. Unprivileged write to this bit is discarded.

0: Wake-up with event generation from line i is masked.

1: Wake-up with event generation from line i is unmasked.

17.4.12 EXTI register map

Table 140. EXTI register map and reset values

Offset	Register name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x000	EXTI_RTSR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RT22	RT21	RT20	RT19	RT18	RT17	RT16	RT15	RT14	RT13	RT12	RT11	RT10	RT9	RT8	RT7	RT6	RT5	RT4	RT3	RT2	RT1	RT0
0x000	Reset value										0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x004	EXTI_FTSR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	FT22	FT21	FT20	FT19	FT18	FT17	FT16	FT15	FT14	FT13	FT12	FT11	FT10	FT9	FT8	FT7	FT6	FT5	FT4	FT3	FT2	FT1	FT0
0x004	Reset value										0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x008	EXTI_SWIER1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SWI22	SWI21	SWI20	SWI19	SWI18	SWI17	SWI16	SWI15	SWI14	SWI13	SWI12	SWI11	SWI10	SWI9	SWI8	SWI7	SWI6	SWI5	SWI4	SWI3	SWI2	SWI1	SWI0
0x008	Reset value										0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x00C	EXTI_RPR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RPIF22	RPIF21	RPIF20	RPIF19	RPIF18	RPIF17	RPIF16	RPIF15	RPIF14	RPIF13	RPIF12	RPIF11	RPIF10	RPIF9	RPIF8	RPIF7	RPIF6	RPIF5	RPIF4	RPIF3	RPIF2	RPIF1	RPIF0
0x00C	Reset value										0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x010	EXTI_FPR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	FPIF22	FPIF21	FPIF20	FPIF19	FPIF18	FPIF17	FPIF16	FPIF15	FPIF14	FPIF13	FPIF12	FPIF11	FPIF10	FPIF9	FPIF8	FPIF7	FPIF6	FPIF5	FPIF4	FPIF3	FPIF2	FPIF1	FPIF0
0x010	Reset value										0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x014	EXTI_SECCFGR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x014	Reset value										0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x018	EXTI_PRIVCFGR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x018	Reset value										0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x020-0x05C	Reserved	Reserved

Table 140. EXTI register map and reset values (continued)

Offset	Register name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x060	EXTI_EXTICR1	EXTI3[7:0]							EXTI2[7:0]							EXTI1[7:0]							EXTI0[7:0]
0x060	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x064	EXTI_EXTICR2	EXTI7[7:0]							EXTI6[7:0]							EXTI5[7:0]							EXTI4[7:0]
0x064	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x068	EXTI_EXTICR3	EXTI11[7:0]							EXTI10[7:0]							EXTI9[7:0]							EXTI8[7:0]
0x068	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x06C	EXTI_EXTICR4	EXTI15[7:0]							EXTI14[7:0]							EXTI13[7:0]							EXTI12[7:0]
0x06C	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x070	EXTI_LOCKR	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	LOCK
0x070	Reset value																																0
0x074- 0x07C	Reserved	Reserved
0x080	EXTI_IMR1	Res	Res	Res	Res	Res	Res	Res	Res	Res	IM22	IM21	IM20	IM19	IM18	IM17	IM16	IM15	IM14	IM13	IM12	IM11	IM10	IM9	IM8	IM7	IM6	IM5	IM4	IM3	IM2	IM1	IM0
0x080	Reset value										0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x084	EXTI_EMR1	Res	Res	Res	Res	Res	Res	Res	Res	Res	EM22	EM21	EM20	EM19	EM18	EM17	EM16	EM15	EM14	EM13	EM12	EM11	EM10	EM9	EM8	EM7	EM6	EM5	EM4	EM3	EM2	EM1	EM0
0x084	Reset value										0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Refer to Section 2.3 for the register boundary addresses.