16. Nested vectored interrupt controller (NVIC)

16.1 NVIC main features

• • 108 maskable interrupt channels (not including the 16 Cortex-M33 with FPU interrupt lines)
• • 16 programmable priority levels (4 bits of interrupt priority used)
• • Low-latency exception and interrupt handling
• • Power management control
• • Implementation of system control registers

The NVIC and the processor core interface are closely coupled, enabling low-latency interrupt processing and efficient processing of late arriving interrupts.

The NVIC registers are banked across secure and nonsecure states. All interrupts including the core exceptions are managed by the NVIC. For more information about NVIC and its registers, refer to the programming manual for Cortex-M33 core (PM0264).

16.2 SysTick calibration value register

The Cortex-M33 with TrustZone mainline security extension embeds two SysTick timers. When TrustZone is activated, the following SysTick timers are available:

• • SysTick, secure instance
• • SysTick, nonsecure instance

When TrustZone is disabled, only one SysTick timer is available.

The SysTick timer calibration value (STCALIB) is 0x3E8. It gives a reference time base of 1 ms based on a SysTick clock frequency of 1 MHz. In order to match the 1 ms time base for an application running at a given frequency, the SysTick reload value must be programmed as follows in the SYST_RVR register:

• • When SysTick clock source is CPU clock HCLK reload value = \( (HCLK \times STCALIB) - 1 \)
• • When SysTick clock source is external clock (HCLK/8) reload value = \( ((HCLK/8) \times STCALIB) - 1 \)

The HCLK refers to the AHB frequency value in MHz.

Example: SysTick clock source is CPU clock HCLK of 100 MHz, to match a time base of 1 ms: SysTick reload value = \( (100 \times STCALIB) - 1 = 0x1869F \)

For more information about SysTick and its registers, refer to the programming manual for Cortex-M33 core (PM0264).

16.3 Interrupt and exception vectors

The grey rows in the table below indicate core exceptions.

Table 134. STM32U3 series vector table ⁽¹⁾

1. 1. Some interrupt lines are only available on some STM32U3 series devices. Refer to the device datasheet for availability of associated peripheral. If not present, consider this interrupt line as reserved.
2. 2. If multiple pending interrupts have the same programmed priority level, the pending interrupt with the lowest IRQ number takes precedence. For example, if both interrupt[n] and interrupt[n+1] are pending and have the same priority, then interrupt[n] is processed before interrupt[n+1]. For further information, refer to the Arm Cortex-M33 technical documentation.