14. Peripheral interconnect matrix

14.1 Interconnect matrix introduction

Several peripherals have direct connections between them. This allows autonomous communication and or synchronization between peripherals, saving CPU resources, thus power supply consumption.

In addition, these hardware connections remove software latency and allow design of predictable system.

Depending on peripherals, these interconnections can operate in various power modes: Run, Sleep, Stop 0, Stop 1, Stop 2, and Stop 3 modes.

Some peripherals are available only on specific STM32U3 series devices. Refer to the device datasheet to check the availability of the associated peripheral. If a peripheral is not present, consider the interconnect unavailable.

14.2 Connection summary

Table 121. Peripheral interconnect matrix

Table 121. Peripheral interconnect matrix (continued)

Table 121. Peripheral interconnect matrix (continued)

14.3 Interconnection details

14.3.1 Master to slave interconnection for timers

From timer (TIM1/2/3/4/8/12/15/16/17) to timer (TIM1/2/3/4/8/12/15).

Purpose

Some of the TIMx timers are linked together internally for timer synchronization or chaining.

When one timer is configured in master mode, it can reset, start, stop, or clock the counter of another timer configured in slave mode.

A description of the feature is provided in Section 37.3.32: ADC synchronization .

The synchronization modes are detailed in:

• • Section 37.3.32: ADC synchronization
• • Section 38.4.22: Timers and external trigger synchronization
• • Section 41.4.23: External trigger synchronization (TIM15 only)

Triggering signals

The output (from master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1/8) following a configurable timer event. It can be also from signals tim16_oc1 and tim17_oc1 in case of TIM16/17. The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.

The possible master/slave connections are given in:

• • Table 384: Internal trigger connection
• • Table 408: TIMx internal trigger connection
• • Table 440: TIMx internal trigger connection

Active power mode

Timers are optionally active in Run and Sleep modes. The effects of low-power modes on TIMx are given in:

• • Table 397: Effect of low-power modes on TIM1/TIM8
• • Table 416: Effect of low-power modes on TIM2/TIM3/TIM4
• • Table 432: Effect of low-power modes on TIM12
• • Table 447: Effect of low-power modes on TIM15/TIM16/TIM17

14.3.2 Triggers to ADCs

From EXTI, timers (TIM1/2/3/4/6/8/15) and LP timers (LPTIM1/2/3/4) to ADC1/2

Purpose

A conversion, or a sequence of conversions, can be triggered either by software or by an external event (such as timer capture or input pins). For ADC1/2, if the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then external events can trigger a conversion with the selected polarity.

More details in:

• • Section 23.4.19: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN)

• • EXTEN[1:0] defined in ADC configuration register (ADC_CFGR1)
• • JEXTEN[1:0] defined in ADC injected sequence register (ADC_JSQR)

General-purpose timers (TIM2/3/4), basic timer (TIM6), advanced-control timers (TIM1/8), and general-purpose timer (TIM15) can be used to generate the ADC triggering event through the timer outputs tim_oc and tim_trgo.

Low-power timers (LPTIM1/ 2/3/4) can be used to generate the ADC triggering event through the LPTIM channels (TIMx synchronization described in Section 37.3.32: ADC synchronization ) in addition to the EXTI on channels 11 and 15.

Triggering signals

For ADC1/2, the input triggering signals and the description of the interconnection between ADC1/2, and timers, are given in:

• • adc_ext_trgi: Table 206: ADC1/2 interconnection
• • adc_jext_trgi: Table 206: ADC1/2 interconnection
• • Section 23.4.19: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN)
• • Section 23.4.25: Timing diagram examples (single/continuous modes, hardware/software triggers)

Active power mode

This interconnection is active in Run and Sleep modes for all ADCs. The timers are active in Run and Sleep modes only. The effects of low-power modes are given in:

• • Table 397: Effect of low-power modes on TIM1/TIM8
• • Table 447: Effect of low-power modes on TIM15/TIM16/TIM17
• • Table 453: STM32U3 series LPTIM features
• • Table 469: Effect of low-power modes on the LPTIM

14.3.3 ADC analog watchdogs as triggers to timers

From ADC1/2 to TIM1/3/8

Purpose

The internal analog watchdog output signals coming from ADC1/2, are connected to on-chip timers. ADC1/2 can provide trigger event through analog watchdog signals to timers (TIM1/3/8) in order to reset, start, stop, or clock the counter.

Settings description of the ADC analog watchdog and timer trigger, are provided in:

• • Section 37.3.6: External trigger input for TIM1/8
• • Table 385: Interconnect to the tim_etr input multiplexer for the internal ADC1/2 sources connected to TIM1/8 (tim_etr) input multiplexer
• • Table 409: Interconnect to the tim_etr input multiplexer for the internal ADC1/2 sources connected to TIM3 (tim_etr) input multiplexer
• • Section 23.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWDCH of ADC_AWD2CR and ADC_AWD3CR, HTR, LTR, AWDFILT) for the ADCn/ADC_AWDy_OUT signal output generation

Triggering signals

The output (from ADC) is on signals ADCn_AWDx_OUT, with n being the ADC instance and x = 1, 2, 3 (three watchdogs per ADC). The input (to timer) is on signal TIMx_ETR (external trigger).

Active power mode

ADC1/2 are active in Run and Sleep modes.

14.3.4 Triggers to DAC

From timer (TIM1/2/4/6/7/8/12/15), LP timers (LPTIM1/3) and EXTI to DAC (DAC1)

Purpose

General-purpose timers (TIM2/4/12/15), basic timers (TIM6/7), advanced control timers (TIM1/8), LP timers (LPTIM1/3) outputs channels (lptim1_ch1 and lptim3_ch1), and EXTI can be used as triggering event to start a DAC conversion.

Triggering signals

The output (from timer) on the TIMx_TRGO signal and from LP timers are directly connected to corresponding DAC inputs.

The selection of input triggers on DAC is provided in:

• • Table 226: DAC interconnection
• • Section 24.4.8: DAC trigger selection

Active power mode

This interconnect is active in Run, Sleep, Stop 0, Stop 1, and Stop 2 modes.

14.3.5 Triggers to ADF1

ADF1 can be triggered by EXTI15, tim1_trgo, tim3_trgo, tim6_trgo and tim8_trgo.

Purpose

EXTI15, tim1_trgo, tim3_trgo, tim6_trgo and tim8_trgo can trigger ADF1.

Triggering signals

ADF trigger inputs connections are detailed in:

• • Table 253: ADF trigger connections

Active power mode

This interconnection remains active down Stop 0, Stop 1, and Stop 2 modes for ADF1, assuming the trigger source remains active.

14.3.6 Data input to ADF1

ADF1 peripheral can directly use data input from ADC1/2.

Purpose

ADC1/2 data stream can be routed to ADF1 for direct post-processing.

Triggering signals

ADF trigger inputs connections are detailed in:

• • Table 253: ADF trigger connections

Active power mode

This interconnection is active in Run and Sleep modes.

14.3.7 Clock sources to timers

From HSE, LSE, LSI, MSI, HSI and MCO to timers (TIM1/2/3/4/15/16/17) and LP timers (LPTIM1/2/3)

Purpose

A timer input or timer counter can receive different clock sources and can be used to calibrate internal oscillator on a reference clock for example.

External clocks (HSE, LSE), internal clocks (LSI, MSI, HSI), and microcontroller output clock (MCO) can be used as input to timers:

• • MSI/HSI are assigned to advanced-control timer TIM1/8 as external trigger signals inputs (tim_etr3/ tim_etr4). MSI/HSI can be selected as counter clock provided by an external clock source in mode2: external trigger input (tim_etr_in). Inputs assignment and clock selection description are detailed in:
  • – Section 37.3.7: Clock selection for TIM1/8
  • – Table 385: Interconnect to the tim_etr input multiplexer for TIM1/8
• • MSI, HSI, and LSE are assigned to general purpose timers TIM2/3/4 as external inputs signals. MSI/HSI/LSE can be selected as counter clock provided by an external clock source in mode1 (tim_ti1_in) and mode2 (external trigger input tim_etr_in). Inputs assignment and clock selection description are detailed in:
  • – Section 38.4.5: Clock selection for TIM2/3/4
  • – External clock mode2: Table 385: Interconnect to the tim_etr input multiplexer , tim_etr3 (MSI), tim_etr4 (HSI) for TIM2/3/4, tim_etr5 (MSIS) for TIM4 and tim_etr11 (LSE) for TIM2.
• • LSE, LSI, MSI, and HSI are assigned to general purpose timers TIM12/15/16/17 as external inputs signals. LSE/LSI/MSI/HSI can be selected as counter clock provided by an external clock source in mode1 (tim_ti1 or tim_ti2 signals). Inputs assignment and clock selection description are detailed in:
  • – Table 41.4.6: Clock selection for TIM12/15/16/17. External clock mode1: external input pin (tim_ti1 or tim_ti2, if available)
  • – Table 438: Interconnect to the tim_ti1 input multiplexer , tim_ti1_in1 (LSE-TIM12/15), tim_ti1_in5(LSE-TIM16/17), tim_ti1_in6 (LSI- TIM16/17), tim_ti1_in7/_8 (MSI-TIM16/17), and tim_ti1_in9 (HSI-TIM16/17)
• • Microcontroller output clock (MCO) is connected as external input to general-purpose timers TIM16/17. This allows the calibration of the HSI16/MSI system clocks (with TIM12/15/16 and LSE) or LSI (with TIM16 and HSE). This is also used to precisely measure LSI (with TIM16 and HSI16) or MSI (with TIM17 and HSI16) oscillator

frequency. When the low-speed external (LSE) oscillator is used, no additional hardware connections are required. This feature is given in:

• – Section : Internal/external clock measurement with TIM15/TIM16/TIM17
• – Table 380: Interconnect to the tim_ti1 input multiplexer for TIM15/TIM16/TIM17
• • LSI and LSE can be selected as input capture 2 to LPTIM1 as described in Table 463: LPTIM1 input capture 2 connections .
• • HSI/256, MSI/1024, and MSI/4 can be selected as input capture 2 to LPTIM2 as described in Table 464: LPTIM2 input capture 2 connections .

Triggering signals

lptim_ic2_mux1 LPTIM input capture selection can be set in the LPTIM configuration register 2 (LPTIM_CFGR2). For timers, the internal clock signal can be selected as counter clock provided by an external clock source in mode1 (tim_ti1_in) and mode2 (external trigger input tim_etr_in).

Active power mode

This feature is available under Run and Sleep modes.

14.3.8 Triggers to low-power timers

From comparators (COMP1/2), EXTI, TAMP and RTC alarm to LP timers (LPTIM1/2/3/4)

Purpose

LPTIM1/2/3/4 counters can be started either by software or after the detection of an active edge on one of the eight trigger inputs (see Section 42.4.7: Trigger multiplexer ).

GPIO can also be selected as LPTIM input capture selection or LPTIM input selection, according to the LPTIM configuration register 2 (LPTIM_CFGR2).

Triggering signals

This trigger feature is described in Section 42.4.7: Trigger multiplexer and the following sections. The input selection is described in Section 42.4.3: LPTIM input and trigger mapping .

Active power mode

This interconnection remains active down to Stop 2 mode.

14.3.9 Blanking sources to comparators

From timers (TIM1/8/2/3/4/15/16/17) to comparators (COMP1/2)

Purpose

Advanced-control timers (TIM1/8) and general-purpose timers (TIM2/3/4/15/16/17) can be used as blanking window input to COMP1/2.

The blanking function is described in Section 26.3.6: Comparator output-blanking function .

The blanking sources are given in:

• • Table 241: COMP1 output-blanking PWM assignment , BLANKSEL[4:0]

• • Table 242: COMP2 output-blanking PWM assignment , BLANKSEL[4:0]

Triggering signals

Timer output signal TIMx_Ocx are the inputs to blanking source of COMP1/2.

Active power mode

This feature is available under Run and Sleep modes.

14.3.10 RTC wake-up as inputs to timers

From RTC to timers (TIM16/17)

Purpose

RTC wake-up interrupt can be used as input to general-purpose timers (TIM16/17) channel 1.

Triggering signals

RTC wake-up signal is connected to tim_ti1_in4 signal as described in Table 438: Interconnect to the tim_ti1 input multiplexer for TIM16/17.

Active power mode

This interconnection is active down to Stop 3 mode. Timers are not active but the count is performed at wake-up.

14.3.11 USB SOF as trigger to timers

From USB SOF to TIM2

Purpose

USB SOF (start-of-frame) can generate a trigger to the general-purpose timer TIM2. The USB connection to TIM2 is described in Table 409: Interconnect to the tim_etr input multiplexer .

Triggering signals

The tim_etr13 internal signal is generated by USB SOF.

Active power mode

This interconnection is active in Run and Sleep modes.

14.3.12 Comparators as inputs, trigger or break signals to timers

From comparators to timers (TIM1/2/3/4/8/12/15/16/17)

Purpose

The comparators (COMP1/2) output values can be connected to timers (TIM1/2/3/4/8/12/15/16/17) input captures, TIMx_ETR or timer break signals. The connection to ETR is described in Section 37.3.6: External trigger input .

Comparators (COMP1/2) output values can also generate break input signals for timers (such as TIM1/8). The sources for break (tim_brk) channel are one of the following:

• • external: connected to one of the TIMx_BKIN pin (as per selection done in the AFIO controller) with polarity selection and optional digital filtering
• • internal: coming from comparators, tim_brk_cmpx input (refer to Table 379: TIM internal input/output signals for product specific implementation).

Triggering signals

The tim_etr and tim_brk signals connected TIM1/8 (coming from COMP1/2) are given in:

• • tim_etr ( Table 385: Interconnect to the tim_etr input multiplexer ): external trigger internal input bus

These inputs can be used as trigger, external clock or for hardware cycle-by-cycle pulse width control.

• • tim_brk ( Table 386: Timer break interconnect and Table 387: Timer break2 interconnect )
• • Section 37.3.6: External trigger input
• • Section 37.3.18: Using the break function

For TIM2/3/4, the sources connected to the tim_ti[1:4] input multiplexers coming from comparators and some other peripherals, are given in:

• • Table 404: Interconnect to the tim_ti1 input multiplexer
• • Table 405: Interconnect to the tim_ti2 input multiplexer
• • Table 407: Interconnect to the tim_ti4 input multiplexer
• • Table 409: Interconnect to the tim_etr input multiplexer
• • Table 410: Interconnect to the tim_ocref_clr input multiplexer
• • Section 38.4.22: Timers and external trigger synchronization
• • TIMx_TISEL

For TIM12/15/16/17, the sources connected to timers coming from comparators and other peripherals are given in:

• • Table 439: Interconnect to the tim_ti2 input multiplexer
• • Table 441: Timer break interconnect
• • Table 443: Interconnect to the ocref_clr input multiplexer
• • Section 41.4.15: Using the break function
• • Section 41.4.23: External trigger synchronization (TIM15 only)

Active power mode

Run, Sleep, and wake-up capability in Stop 0, Stop 1, and Stop 2 modes for trigger sources. Input and break remain active in same low-power modes as timers activity, on Run and Sleep modes.

14.3.13 System errors as break signals to timers

From system errors to timers (TIM1/8/15/16/17)

Purpose

CSS, CPU lockup, SRAM2 parity errors, ECC double errors, FLASH ECC double-error detection, HSP1 break, and PVD can generate system errors in the form of timer break toward timers (TIM1/8/15/16/17).

The purpose of the break function is to protect power switches driven by PWM signals generated by the timers.

Triggering signals

The possible sources of break are described in:

• • Section 37.3.18: Using the break function for TIM1/8
• • Section 41.4.15: Using the break function for TIM15/16/17
• • Table 388: System break interconnect for TIM1/8
• • Table 442: System break interconnect for TIM15/16/17

Active power mode

Timers are optionally active in Run and Sleep modes. The effects of low-power modes on TIMx are given in:

• • Table 397: Effect of low-power modes on TIM1/TIM8
• • Table 416: Effect of low-power modes on TIM2/TIM3/TIM4
• • Table 447: Effect of low-power modes on TIM15/TIM16/TIM17

14.3.14 Timers generating IRTIM signal

From timers (TIM16/17) to IRTIM

The general-purpose timer (TIM16/TIM17) output channels TIMx_OC1 and USART1/UART4 TX output, are used to generate the waveform of the infrared signal output.

This functionality is described in Section 43: Infrared interface (IRTIM) .

14.3.15 Triggers for communication peripherals

From LP timers (LPTIM1/2/3), comparators (COMP1/2), GPDMA1 transfer complete, EXTI, RTC alarm and RTC wake-up to USART1/2/3, UART4/UART5, LPUART1, I2C1/2, I3C1/2, and SPI1/2

Purpose

LP timer (LPTIM1/2/3) output channels (lptim1_ch1, lptim1_ch2 and lptim3_ch1), timers (tim15_trgo_cktim, tim16_oc1), comparator (COMP1/2) output channels (comp1_out and comp2_out),

EXTI, RTC alarm and RTC wakeup, can be used as trigger to start a communication on the selected USART, UART, LPUART, I2C, I3C, or SPI peripherals.

A GPDMA1 transfer complete can trigger both the GPDMA1 regular or linked-list new transfers and communication on selected communication peripheral.

Triggering signals

The outputs from triggers are directly connected to peripheral trigger inputs.

The selection of input triggers is detailed in:

• • Table 558: USART interconnection (USART1/2/3 and UART4/5)
• • Table 570: LPUART interconnections (LPUART1)
• • Table 504: Trigger interconnections for I2C peripherals
• • Table 524: I3C triggers, when I3C as controller for I3C peripherals

The outputs (from timer) are directly connected to SPI1/2 inputs on signals spi_itrx (x = 6, 7). The selection of input triggers on SPI is provided in:

• • Section : Description of SPI interconnections

Active power mode

These interconnections remain active in Run, Sleep, and Stop modes if both source and communication line are autonomous under the mode. Refer to:

• • Section 51.6: USART in low-power modes
• • Section 48.5: I2C in low-power modes
• • Section 53.6: SPI in low-power modes
• • Section 49.14: I3C in low-power modes

14.3.16 Triggers to GPDMA

From EXTI, RTC (alarm/wakeup), TAMP (TAMP1/2/3), timers (TIM2/8/12/15), LP timers (LPTIM1/3/4), comparators (COMP1/2), GPDMA1 transfer complete (gpdma1_chx_tc), ADC1/2, HSP1 and analog watchdog to GPDMA1

Purpose

A GPDMA trigger can be assigned to a GPDMA channel x. A programmed GPDMA transfer can be triggered by a rising/falling edge of a selected input trigger event. The trigger mode can also be programmed to condition the LLI link transfer. More details are given in the sections below:

• • Section 15.3.6: GPDMA triggers
• • Section 15.4.12: GPDMA triggered transfer
• • GPDMA_CxTR2 for more details on:
  • – Trigger selection TRIGSEL[5:0] field
  • – Trigger mode (LLI) defined by TRIGM[1:0].
  • – Trigger polarity as defined by TRIGPOL[1:0]

Triggering signals

GPDMA trigger mapping is specified in Table 128: Programmed GPDMA1 trigger , according to GPDMA_CxTR2.TRIGSEL[5:0].

Active power mode

Assuming sources are active down to Stop modes, this interconnection remains functional in Stop 0 and Stop 1 modes for GPDMA.

Refer to:

• • Section 15.6: GPDMA in low-power modes

14.3.17 Internal analog signals to analog peripherals

From internal analog source to ADC (ADC1/2), comparators (COMP1/2) and OPAMP (OPAMP1/2)

Purpose

The internal reference voltage ( \( V_{REFINT} \) ), the internal temperature sensor ( \( V_{TS} \) ), and \( V_{BAT} \) monitoring channel are connected to ADC (ADC1/2) input channels. In addition, the internal digital core voltage ( \( V_{CORE} \) ) is connected to ADC1/2 input channels.

DAC channels (DAC1_OUT1/DAC2_OUT2) and \( V_{REFINT} \) are connected to comparators (COMP1/2).

OPAMP1/2 outputs can be connected to ADC1/2 input channels through the GPIO. DAC1_OUT1 can be connected to OPAMP1_VINP. DAC1_OUT2 can be connected to OPAMP2_VINP.

Refer to Section 24.4.2: DAC pins and internal signals for:

• • dac_out1 analog output DAC channel1, output, for on-chip peripherals
• • dac_out2 analog output DAC channel2, output, for on-chip peripherals

This is according to:

• • Section 23.2: ADC main features , Figure 119. ADC1 connectivity, Figure 120. ADC2 connectivity
• • Section 27.3.3: Signal routing
• • Section 26.3.2: COMP pins and internal signals

Active power mode

These interconnections remain in Stop modes if the selected peripheral is kept active.

Refer to:

• • Section 23.5: ADC in low-power modes
• • Section 27.4: OPAMP low-power modes
• • Section 26.4: COMP in low-power modes

14.3.18 Clock source for the DAC sample and hold mode

From LSI/LSE to DAC1/2

Purpose

DAC1 can run in Stop mode. The sample and hold block and its associated registers use the LSI or LSE clock source (dac_hold_ck) in Stop mode.

Refer to Section 24.4.2: DAC pins and internal signals :

dac_hold_ck (input) - DAC low-power clock used in sample and hold mode

Active power mode

This feature remains available down to Stop 2 mode.

14.3.19 Internal tamper sources

From internal peripherals, clocks to tamper.

Purpose

In order to detect any abnormal activity or tentative to corrupt the device, tampers are introduced and alert the system of such undesired event. Different actions can be taken in consequences.

List of tamper sources can be found in Table 493: TAMP interconnection .

Active power mode

This interconnection is active in all power modes if the tamper source is activated.

14.3.20 Output from tamper to RTC

From TAMP to RTC

Purpose

The RTC can timestamp a tamper event in order to retrieve history in time of such detection. The RTC can also control GPIOs and set a signal based on tamp or alarm status outside the MCU.

Refer to Section 46.3.3: GPIOs controlled by the RTC for more details.

Active power mode

This interconnection remains active in all power modes.

14.3.21 Encryption keys to AES/SAES

From TAMP backup registers, system flash memory to and in between SAES and AES

Purpose

The encryption mechanism requires an hardware key that must be stored in a protected non-volatile memory. Different approaches are implemented in order to load them in a non-readable way. Tamper backup registers or system flash memory can be used to store respectively BHK or RHUK, and to implement a dedicated bus to pass it to the SAES.

Refer to Section 34.4.14: SAES operation with wrapped keys for more details.

The AES encryption mechanism (faster than the SAES) can benefit from the sharing key of the SAES. Refer to Section 34.4.15: SAES operation with shared keys for more details.

Active power mode

AES and SAES are operating under Run and Sleep modes.

14.3.22 I3C IBI acknowledge to timers from I3C1/2 to TIM12/15/16/17 and LPTIM1/2/3

Purpose

The I3C peripherals generate an IBI acknowledge event when peripheral acts as controller, for timing control with asynchronous mode 0. This enables to timestamp the moment at which the target(s) acquired sampled data and to time-correlate them.

Refer to Section 49.9.13: I3C IBI transfer, as controller/target for more details.

Active power mode

Timers are functional in Run and Sleep modes. I3C is functional in Run, Sleep, Stop 0, and Stop 1 modes, and so are functional LP timers.

14.3.23 Triggers to HSP1

Purpose

The HSP1 peripheral can be triggered by some peripheral to start automatically HSP processing.

Refer to Section 19.4.9: Trigger input interface (TRGITF) for more details.

Active power mode

HSP1 is functional in Run and Sleep modes.