2. Memory and bus architecture

2.1 System architecture

The STM32U3 series architecture relies on an Arm Cortex-M33 core optimized for execution thanks to an instruction cache having a direct access to the embedded flash memory.

This architecture also features a 32-bit multilayer AHB bus matrix that interconnects:

• • up to 9 masters:
  • – Fast C-bus, connecting Cortex-M33 with Arm TrustZone mainline and FPU core to the internal SRAMs and flash memory through the instruction cache
  • – Slow C-bus, connecting Cortex-M33 with Arm TrustZone mainline and FPU core to the OCTOSPI1 external memory through the instruction cache
  • – Cortex-M33 with Arm TrustZone mainline and FPU core S-bus (up to four masters connected to two internal SRAMs without latency), and to peripherals and OCTOSPI1 external memory
  • – GPDMA1 (general purpose DMA featuring two master ports)
  • – SDMMC1
• • up to 8 slaves:
  • – internal flash memory
  • – internal SRAM1
  • – internal SRAM2
  • – internal SRAM3
  • – internal SRAM4
  • – AHB1 peripherals including AHB to APB bridges and APB peripherals (connected to APB1 and APB2)
  • – AHB2 peripherals
  • – OCTOSPI1

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. This architecture is shown in the figure below.

Figure 1. System architecture

2.1.1 Fast C-bus

This bus connects the C-bus of the Cortex-M33 core to the internal flash memory and to the bus matrix via the instruction cache. This bus is used for instruction fetch and data access to the internal memories mapped in the code region. This bus targets the internal flash memory and the internal SRAMs (SRAM1, SRAM2, and SRAM3).

SRAM1, SRAM2, and SRAM3 are accessible on this bus with a continuous mapping.

2.1.2 Slow C-bus

This bus connects the C-bus of the Cortex-M33 core to the bus matrix via the instruction cache. This bus is used for instruction fetch and data access to the external memories mapped in the code region. This bus targets the external memories (OCTOSPI).

2.1.3 S-bus

This bus connects the system bus of the Cortex-M33 core to the bus matrix. This bus is used by the core to access data located in a peripheral or SRAM area. This bus targets the internal SRAMs (SRAM1, SRAM2, SRAM3, and SRAM4), the AHB1 peripherals including the APB1 and APB2 peripherals, and the AHB2 peripherals.

SRAM1, SRAM2, SRAM3, and SRAM4 are accessible on this bus with a continuous mapping.

Note: The bus matrix has a zero latency when accessing SRAM1, SRAM2, SRAM3, and SRAM4.

2.1.4 GPDMA-bus

These buses connect the two AHB master interfaces of the GPDMA to the bus matrix. These buses target the internal flash memory, the internal SRAMs (SRAM1, SRAM2, SRAM3, and SRAM4), the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals, the APB3 peripherals and the external memories through OCTOSPI.

2.1.5 SDMMC1 controller DMA bus

This bus connects the SDMMC1 DMA master interface to the bus matrix. This bus is used only by the SDMMC1 DMA to load/store data from/to the memory. This bus targets the data memories: internal flash memory, internal SRAMs (SRAM1, SRAM2, SRAM3, and SRAM4) and external memories through OCTOSPI.

2.1.6 Bus matrix

The bus matrix manages the access arbitration between masters. The arbitration uses a round-robin algorithm. This bus matrix features a fast bus multiplexer used to connect each master to a given slave without latency (see Figure 1 ). For the same master, other slaves undergo a latency of at least one cycle at each new access.

2.1.7 AHB/APB bridges

The three AHB/APB bridges provide full synchronous connections between the AHB and the APB buses, allowing flexible selection of the peripheral frequency.

Refer to Memory and bus architecture for the address mapping of the peripherals connected to these bridges.

After each device reset, all peripheral clocks are disabled (except for the internal SRAMs and flash memory interfaces). Before using a peripheral, its clock must be enabled in the RCC_AHBxENR and RCC_APBxENR registers.

Note: When an 8- or 16-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 8- or 16-bit data to feed the 32-bit vector.

2.2 Arm TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M mainline extension.

The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.

When the TrustZone is enabled, the SAU (security-attribution unit) and IDAU (implementation-defined-attribution unit) defines the access permissions based on secure and nonsecure states.

• • SAU: Up to eight SAU configurable regions are available for security attribution.
• • IDAU: provides a first memory partition as nonsecure or nonsecure callable attributes. The IDAU memory map partition is not configurable and fixed by hardware implementation (refer to Figure 1 and to Table 4 in Section 2.3.2: Memory map and

register boundary addresses ). It is then combined with the results from the SAU security attribution and the higher security state is selected.

Based on IDAU security attribution, the flash memory, system SRAMs, and peripherals memory space are aliased twice for secure and nonsecure states. The external memories space is not aliased.

The table below shows an example of typical eight SAU regions mapping based on IDAU regions. The user can split and choose the secure, nonsecure or NSC regions for external memories as needed.

Table 1. Example of memory map security attribution versus SAU configuration regions

1. NSC = nonsecure callable

2.2.1 Default Arm TrustZone security state

When the TrustZone security is activated by the TZEN option bit in the FLASH_OPTR, the default system security state is detailed below:

• • CPU:
  • – Cortex-M33 is in secure state after reset. The boot address must be at a secure address.
• • Memory map:
  • – SAU is fully secure after reset. Consequently, all memory map is fully secure. Up to height SAU configurable regions are available for security attribution.
• • Flash memory:
  • – The flash memory security area is defined by watermark user options.
  • – Flash block-based security attributions are nonsecure after reset.
• • SRAMs:
  • – All SRAMs are secure after reset. MPCBBx (block-based memory protection controller) are secure.

• – On STM32U3B5/3C5 devices, SRAM4 is secure after reset but can be accessed directly by nonsecure HSP1.
• • External memories:
  • – OCTOSPI does not support any TrustZone protection.
• • Peripherals (see Table 2 and Table 3 for a list of securable and TrustZone-aware peripherals)
  • – Securables peripherals are nonsecure after reset.
  • – TrustZone-aware peripherals are nonsecure after reset. Their secure configuration registers are secure.
• • All GPIOs secure after reset
• • Interrupts:
  • – NVIC: All interrupts are secure after reset. NVIC is banked for secure and nonsecure state.
  • – TZIC: All illegal access interrupts are disabled after reset (see Section 2.2: Arm TrustZone security architecture ).

2.2.2 Arm TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either securable or TrustZone-aware type as follows:

• • Securables: peripheral protected by an AHB/APB firewall gate that is controlled from TZSC controller to define security properties
• • TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing a specific TrustZone behavior such as a subset of registers being secure.

Refer to Section 2.2: Arm TrustZone security architecture for more details.

The tables below list the securable and TrustZone-aware peripherals within the system.

Table 2. Securables peripherals by TZSC

Table 2. Securable peripherals by TZSC (continued)

Table 2. Securable peripherals by TZSC (continued)

Table 3. TrustZone aware peripherals

2.3 Memory organization

2.3.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

2.3.2 Memory map and register boundary addresses

Figure 2. Memory map based on IDAU mapping for STM32U356/366

Figure 4. Memory map based on IDAU mapping for STM323B5/3C5

All memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. The following table gives the boundary addresses of the peripherals available in the devices.

Table 4. Memory map and peripheral register boundary addresses

Table 4. Memory map and peripheral register boundary addresses (continued)

Table 4. Memory map and peripheral register boundary addresses (continued)

Table 4. Memory map and peripheral register boundary addresses (continued)

2.3.3 Embedded SRAMs

The devices feature following SRAMs configuration:

Table 5. SRAM sizes

These SRAMs can be accessed as bytes, half-words (16 bits), or full words (32 bits). These memories can be addressed both by CPU and DMAs.

The CPU can access the SRAM1 and SRAM2 through the system bus or through the C-bus depending on the selected address.

On STM32U3B5/3C5 devices, the last 32 Kbytes of SRAM4 can be accessed as dual port RAM on the next 16 Kbytes address range: from 0x200A 0000 to 0x200A 3FFF or from 0x300A 0000 to 0x300A 3FFF).

When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM can be programmed as nonsecure with a block granularity. For more details, refer to Section 5: Global TrustZone controller (GTZC) .

SRAM features are detailed in Section 6.3.1: Internal SRAMs features .

2.3.4 Flash memory overview

The flash memory is composed of two distinct physical areas:

• • the main flash memory block, that contains the application program and user data
• • the information block, that is composed of the following parts:
  • – option bytes for hardware and memory protection user configuration
  • – system memory that contains ST proprietary code
  • – OTP (one-time programmable) area

The flash memory interface implements instruction access and data access based on the AHB protocol. It also implements the logic necessary to carry out the flash memory operations (program/erase) controlled through the flash memory registers plus security access control features. Refer to Section 7: Embedded flash memory (FLASH) for more details.