RM0487-STM32U3

This reference manual complements the datasheets of the STM32U3 series microcontrollers, providing information required for application and in particular for software development. It pertains to the superset of feature sets available on STM32U3 series microcontrollers.

For feature set, ordering information, and mechanical and electrical characteristics of a particular STM32U3 series device, refer to its corresponding datasheet.

For information on the Arm ® Cortex-M33 core, refer to the Cortex-M33 technical reference manual .

The STM32U3 series microcontrollers include ST state-of-the-art patented technology.

a. Available on STMicroelectronics website www.st.com

Contents

5.4GTZC1 MPCBB1 registers . . . . .202
5.4.1GTZC1 SRAM1 MPCBB control register (GTZC1_MPCBB1_CR) . . .202
5.4.2GTZC1 SRAM1 MPCBB configuration lock register 1
(GTZC1_MPCBB1_CFGLOCKR1) . . . . .		203
5.4.3GTZC1 SRAM1 MPCBB security configuration for super-block x
register (GTZC1_MPCBB1_SECCFGGRx) . . . . .		203
5.4.4GTZC1 SRAM1 MPCBB privileged configuration for super-block x
register (GTZC1_MPCBB1_PRIVCFGGRx) . . . . .		204
5.4.5GTZC1 MPCBB1 register map . . . . .204
5.5GTZC1 MPCBB2 registers . . . . .205
5.5.1GTZC1 SRAM2 MPCBB control register (GTZC1_MPCBB2_CR) . . .205
5.5.2GTZC1 SRAM2 MPCBB configuration lock register 1
(GTZC1_MPCBB2_CFGLOCKR1) . . . . .		206
5.5.3GTZC1 SRAM2 MPCBB security configuration for super-block x
register (GTZC1_MPCBB2_SECCFGGRx) . . . . .		206
5.5.4GTZC1 SRAM2 MPCBB privileged configuration for super-block x
register (GTZC1_MPCBB2_PRIVCFGGRx) . . . . .		207
5.5.5GTZC1 MPCBB2 register map . . . . .207
5.6GTZC1 MPCBB3 registers . . . . .208
5.6.1GTZC1 SRAM3 MPCBB control register (GTZC1_MPCBB3_CR) . . .208
5.6.2GTZC1 SRAM3 MPCBB configuration lock register 1
(GTZC1_MPCBB3_CFGLOCKR1) . . . . .		209
5.6.3GTZC1 SRAM3 MPCBB security configuration for super-block x
register (GTZC1_MPCBB3_SECCFGGRx) . . . . .		209
5.6.4GTZC1 SRAM3 MPCBB privileged configuration for super-block x
register (GTZC1_MPCBB3_PRIVCFGGRx) . . . . .		210
5.6.5GTZC1 MPCBB3 register map . . . . .210
5.7GTZC1 MPCBB4 registers . . . . .211
5.7.1GTZC1 SRAM4 MPCBB control register (GTZC1_MPCBB4_CR) . . .211
5.7.2GTZC1 SRAM4 MPCBB configuration lock register 1
(GTZC1_MPCBB4_CFGLOCKR1) . . . . .		212
5.7.3GTZC1 SRAM4 MPCBB security configuration for super-block x
register (GTZC1_MPCBB4_SECCFGGRx) . . . . .		212
5.7.4GTZC1 SRAM4 MPCBB privileged configuration for super-block x
register (GTZC1_MPCBB4_PRIVCFGGRx) . . . . .		213
5.7.5GTZC1 MPCBB4 register map . . . . .213
6RAM configuration controller (RAMCFG) . . . . .214
6.1RAMCFG introduction . . . . .214
6.2RAMCFG main features . . . . .214
6.3RAMCFG functional description . . . . .214
6.3.1Internal SRAMs features . . . . .214
6.3.2Parity error detection (SRAM2/3) . . . . .215
6.3.3Write protection (SRAM2) . . . . .215
6.3.4Software erase . . . . .216
6.4RAMCFG in low-power modes . . . . .216
6.5RAMCFG interrupts . . . . .216
6.6RAMCFG registers . . . . .217
6.6.1RAMCFG memory x control register (RAMCFG_MxCR) . . . . .217
6.6.2RAMCFG memory x interrupt enable register (RAMCFG_MxIER) . . . . .218
6.6.3RAMCFG memory x interrupt status register (RAMCFG_MxISR) . . . . .218
6.6.4RAMCFG memory x parity error address register
(RAMCFG_MxPEAR) . . . . .		219
6.6.5RAMCFG memory x interrupt clear register (RAMCFG_MxICR) . . . . .219
6.6.6RAMCFG memory 2 write protection register 1
(RAMCFG_M2WPR1) . . . . .		219
6.6.7RAMCFG memory 2 write protection register 2
(RAMCFG_M2WPR2) . . . . .		220
6.6.8RAMCFG memory x parity key register (RAMCFG_MxPARKEYR) . . . . .220
6.6.9RAMCFG memory x erase key register (RAMCFG_MxERKEYR) . . . . .221
6.6.10RAMCFG register map . . . . .221
7Embedded flash memory (FLASH) . . . . .223
7.1FLASH introduction . . . . .223
7.2FLASH main features . . . . .223
7.3FLASH functional description . . . . .224
7.3.1Flash memory organization . . . . .224
7.3.2Error code correction (ECC) . . . . .226
7.3.3Read access latency . . . . .227
7.3.4Bank power-down mode . . . . .229
7.3.5Flash memory program and erase operations . . . . .229
7.3.6Flash main memory erase sequences . . . . .231
7.3.7Flash memory programming sequences . . . . .232
7.3.8Flash memory errors flags . . . . .234
7.3.9Read-while-write (RWW) . . . . .236
7.3.10Power-down during flash programming or erase operation . . . . .236
7.3.11Reset during flash programming or erase operation . . . . .236
7.4FLASH option bytes . . . . .237
7.4.1Option-byte description . . . . .237
7.4.2Option-byte programming . . . . .239
7.5FLASH TrustZone security and privilege protections . . . . .241
7.5.1TrustZone security protection . . . . .241
7.5.2Watermark-based secure flash memory area protection . . . . .242
7.5.3Secure hide protection (HDP) . . . . .242
7.5.4Secure hide protection extension (HDP extension) . . . . .244
7.5.5Block-based secure flash memory area protection . . . . .246
7.5.6Flash security attribute state . . . . .247
7.5.7Block-based privileged flash memory area protection . . . . .247
7.5.8Flash memory register privileged and unprivileged modes . . . . .248
7.5.9Flash memory bank attributes in case of bank swap . . . . .248
7.6FLASH memory protection . . . . .250
7.6.1Write protection (WRP) . . . . .250
7.6.2Readout protection (RDP) . . . . .251
7.7System memory . . . . .260
7.7.1RSS user functions . . . . .260
7.8Summary of flash memory and flash memory registers access control . . . . .262
7.9FLASH interrupts . . . . .266
7.10FLASH registers . . . . .266
7.10.1FLASH access control register (FLASH_ACR) . . . . .266
7.10.2FLASH nonsecure key register (FLASH_KEYR) . . . . .268
7.10.3FLASH secure key register (FLASH_SKEYR) . . . . .268
7.10.4FLASH option key register (FLASH_OPTKEYR) . . . . .269
7.10.5FLASH bank 1 power-down key register (FLASH_PDKEY1R) . . . . .269
7.10.6FLASH bank 2 power-down key register (FLASH_PDKEY2R) . . . . .270
7.10.7FLASH nonsecure status register (FLASH_SR) . . . . .270
7.10.8FLASH secure status register (FLASH_SSR) . . . . .272
7.10.9FLASH nonsecure control register (FLASH_CR) . . . . .273
7.10.10FLASH secure control register (FLASH_SCR) . . . . .275
7.10.11FLASH ECC register (FLASH_ECCCORR) . . . . .277
7.10.12FLASH ECC detection register (FLASH_ECCDETR) . . . . .278
7.10.13FLASH operation status register (FLASH_OPSR) . . . . .279
7.10.14FLASH option register (FLASH_OPTR) . . . . .280
7.10.15FLASH option register [alternate] (FLASH_OPTR) . . . . .282

7.10.16 FLASH nonsecure boot address 0 register (FLASH_BOOT0R) . . . . . 285

7.10.17 FLASH nonsecure boot address 1 register (FLASH_BOOT1R) . . . . . 286

7.10.18 FLASH secure boot address 0 register (FLASH_SBOOT0R) . . . . . 287

7.10.19 FLASH secure watermark1 register 1 (FLASH_SECWM1R1) . . . . . 288

7.10.20 FLASH secure watermark1 register 2 (FLASH_SECWM1R2) . . . . . 289

7.10.21 FLASH WRP1 area A address register (FLASH_WRP1AR) . . . . . 289

7.10.22 FLASH WRP1 area B address register (FLASH_WRP1BR) . . . . . 290

7.10.23 FLASH secure watermark2 register 1 (FLASH_SECWM2R1) . . . . . 291

7.10.24 FLASH secure watermark2 register 2 (FLASH_SECWM2R2) . . . . . 292

7.10.25 FLASH WRP2 area A address register (FLASH_WRP2AR) . . . . . 293

7.10.26 FLASH WRP2 area B address register (FLASH_WRP2BR) . . . . . 294

7.10.27 FLASH secure block based bank 1 register x (FLASH_SECB1Rx) . . . . . 295

7.10.28 FLASH secure block based bank 2 register x (FLASH_SECB2Rx) . . . . . 295

7.10.29 FLASH secure HDP control register (FLASH_SECHDPCR) . . . . . 296

7.10.30 FLASH privilege configuration register (FLASH_PRIVCFGR) . . . . . 297

7.10.31 FLASH HDP extension register (FLASH_SECHDPEXTR) . . . . . 298

7.10.32 FLASH privilege block based bank 1 register x (FLASH_PRIVBB1Rx) . . . . . 298

7.10.33 FLASH privilege block based bank 2 register x (FLASH_PRIVBB2Rx) . . . . . 300

7.10.34 FLASH OEM1 key register 1 (FLASH_OEM1KEYR1) . . . . . 300

7.10.35 FLASH OEM1 key register 2 (FLASH_OEM1KEYR2) . . . . . 301

7.10.36 FLASH OEM1 key register 3 (FLASH_OEM1KEYR3) . . . . . 301

7.10.37 FLASH OEM1 key register 4 (FLASH_OEM1KEYR4) . . . . . 302

7.10.38 FLASH OEM2 key register 1 (FLASH_OEM2KEYR1) . . . . . 302

7.10.39 FLASH OEM2 key register 2 (FLASH_OEM2KEYR2) . . . . . 303

7.10.40 FLASH OEM2 key register 3 (FLASH_OEM2KEYR3) . . . . . 303

7.10.41 FLASH OEM2 key register 4 (FLASH_OEM2KEYR4) . . . . . 304

7.10.42 FLASH OEM key status register (FLASH_OEMKEYSR) . . . . . 304

7.10.43 FLASH register map . . . . . 305

8 Instruction cache (ICACHE) . . . . . 309

8.1 ICACHE introduction . . . . . 309

8.2 ICACHE main features . . . . . 309

8.3 ICACHE implementation . . . . . 310

8.4 ICACHE functional description . . . . . 310

8.4.1ICACHE block diagram . . . . .311
8.4.2ICACHE reset and clocks . . . . .311
8.4.3ICACHE TAG memory . . . . .312
8.4.4Direct-mapped ICACHE (1-way cache) . . . . .313
8.4.5ICACHE enable . . . . .314
8.4.6Cacheable and noncacheable traffic . . . . .314
8.4.7Address remapping . . . . .315
8.4.8Cacheable accesses . . . . .317
8.4.9Dual-master cache . . . . .318
8.4.10ICACHE security . . . . .318
8.4.11ICACHE maintenance . . . . .318
8.4.12ICACHE performance monitoring . . . . .319
8.4.13ICACHE boot . . . . .319
8.5ICACHE low-power modes . . . . .319
8.6ICACHE error management and interrupts . . . . .320
8.7ICACHE registers . . . . .320
8.7.1ICACHE control register (ICACHE_CR) . . . . .320
8.7.2ICACHE status register (ICACHE_SR) . . . . .321
8.7.3ICACHE interrupt enable register (ICACHE_IER) . . . . .322
8.7.4ICACHE flag clear register (ICACHE_FCR) . . . . .322
8.7.5ICACHE hit monitor register (ICACHE_HMONR) . . . . .323
8.7.6ICACHE miss monitor register (ICACHE_MMONR) . . . . .323
8.7.7ICACHE region x configuration register (ICACHE_CRRx) . . . . .323
8.7.8ICACHE register map . . . . .324
9Power control (PWR) . . . . .326
9.1PWR introduction . . . . .326
9.2PWR main features . . . . .326
9.3PWR functional description . . . . .326
9.3.1PWR pins and internal signals . . . . .326
9.3.2PWR power supplies and supply domains . . . . .328
9.3.3PWR system supply voltage regulation . . . . .332
9.3.4PWR power supply supervision . . . . .334
9.3.5PWR power management . . . . .337
9.3.6PWR security and privileged protection . . . . .360
9.4PWR interrupts . . . . .362
9.5PWR registers . . . . .363
9.5.1PWR control register 1 (PWR_CR1) . . . . .363
9.5.2PWR control register 2 (PWR_CR2) . . . . .365
9.5.3PWR control register 3 (PWR_CR3) . . . . .367
9.5.4PWR voltage scaling register (PWR_VOSR) . . . . .368
9.5.5PWR supply voltage monitoring control register (PWR_SVMCR) . . . . .369
9.5.6PWR wake-up control register 1 (PWR_WUCR1) . . . . .371
9.5.7PWR wake-up control register 2 (PWR_WUCR2) . . . . .371
9.5.8PWR wake-up control register 3 (PWR_WUCR3) . . . . .372
9.5.9PWR backup domain control register (PWR_BDCR) . . . . .373
9.5.10PWR disable backup domain register (PWR_DBPR) . . . . .373
9.5.11PWR security configuration register (PWR_SECCFGR) . . . . .374
9.5.12PWR privilege control register (PWR_PRIVCFGR) . . . . .375
9.5.13PWR status register (PWR_SR) . . . . .375
9.5.14PWR supply voltage monitoring status register (PWR_SVMSR) . . . . .376
9.5.15PWR wake-up status register (PWR_WUSR) . . . . .377
9.5.16PWR wake-up status clear register (PWR_WUSCR) . . . . .377
9.5.17PWR apply pull configuration register (PWR_APCR) . . . . .378
9.5.18PWR port A pull-up control register (PWR_PUCRA) . . . . .378
9.5.19PWR port A pull-down control register (PWR_PDCRA) . . . . .379
9.5.20PWR port B pull-up control register (PWR_PUCRB) . . . . .380
9.5.21PWR port B pull-down control register (PWR_PDCRB) . . . . .380
9.5.22PWR port C pull-up control register (PWR_PUCRC) . . . . .381
9.5.23PWR port C pull-down control register (PWR_PDCRC) . . . . .382
9.5.24PWR port D pull-up control register (PWR_PUCRD) . . . . .382
9.5.25PWR port D pull-down control register (PWR_PDCRD) . . . . .383
9.5.26PWR port E pull-up control register (PWR_PUCRE) . . . . .384
9.5.27PWR port E pull-down control register (PWR_PDCRE) . . . . .384
9.5.28PWR port F pull-up control register (PWR_PUCRF) . . . . .385
9.5.29PWR port F pull-down control register (PWR_PDCRF) . . . . .386
9.5.30PWR port G pull-up control register (PWR_PUCRG) . . . . .386
9.5.31PWR port G pull-down control register (PWR_PDCRG) . . . . .387
9.5.32PWR port H pull-up control register (PWR_PUCRH) . . . . .388
9.5.33PWR port H pull-down control register (PWR_PDCRH) . . . . .388
9.5.34PWR I3C pull-up control register 1 (PWR_I3CPUCR1) . . . . .389
9.5.35PWR I3C pull-up control register 2 (PWR_I3CPUCR2) . . . . .390
9.5.36PWR register map . . . . .391
10Reset and clock control (RCC) . . . . .394
10.1RCC introduction . . . . .394
10.2RCC functional description . . . . .394
10.2.1RCC pins and internal signals . . . . .394
10.2.2RCC reset functional description . . . . .394
10.2.3RCC clock functional description . . . . .396
10.2.4RCC security and privilege functional description . . . . .411
10.3RCC in low-power modes . . . . .414
10.4RCC interrupts . . . . .415
10.5RCC registers . . . . .417
10.5.1RCC clock control register (RCC_CR) . . . . .417
10.5.2RCC internal clock source calibration register 1 (RCC_ICSCR1) . . . . .420
10.5.3RCC internal clock source calibration register 2 (RCC_ICSCR2) . . . . .423
10.5.4RCC internal clock source calibration register 3 (RCC_ICSCR3) . . . . .424
10.5.5RCC clock recovery RC register (RCC_CRRRCR) . . . . .424
10.5.6RCC clock configuration register 1 (RCC_CFGR1) . . . . .425
10.5.7RCC clock configuration register 2 (RCC_CFGR2) . . . . .427
10.5.8RCC clock configuration register 3 (RCC_CFGR3) . . . . .428
10.5.9RCC clock configuration register 4 (RCC_CFGR4) . . . . .429
10.5.10RCC clock interrupt enable register (RCC_CIER) . . . . .430
10.5.11RCC clock interrupt flag register (RCC_CIFR) . . . . .431
10.5.12RCC clock interrupt clear register (RCC_CICR) . . . . .433
10.5.13RCC AHB1 peripheral reset register 1 (RCC_AHB1RSTR1) . . . . .434
10.5.14RCC AHB2 peripheral reset register 1 (RCC_AHB2RSTR1) . . . . .435
10.5.15RCC AHB2 peripheral reset register 2 (RCC_AHB2RSTR2) . . . . .436
10.5.16RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . .437
10.5.17RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . .438
10.5.18RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .439
10.5.19RCC APB3 peripheral reset register (RCC_APB3RSTR) . . . . .440
10.5.20RCC AHB1 peripheral clock enable register 1 (RCC_AHB1ENR1) . . . . .441
10.5.21RCC AHB2 peripheral clock enable register 1 (RCC_AHB2ENR1) . . . . .442
10.5.22RCC AHB2 peripheral clock enable register 2 (RCC_AHB2ENR2) . . . . .444
10.5.23RCC AHB1 peripheral clock enable register 2 (RCC_AHB1ENR2) . . . . .444
10.5.24RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . .445
10.5.25RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . .447
10.5.26RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .447

10.5.27 RCC APB3 peripheral clock enable register (RCC_APB3ENR) . . . . 449

10.5.28 RCC AHB1 peripheral clock enable in Sleep mode register
(RCC_AHB1SLPENR1) . . . . . 450

10.5.29 RCC AHB2 peripheral clock enable in Sleep mode register 1
(RCC_AHB2SLPENR1) . . . . . 451

10.5.30 RCC AHB2 peripheral clock enable in Sleep mode register 2
(RCC_AHB2SLPENR2) . . . . . 453

10.5.31 RCC AHB1 peripheral clock enable in Sleep mode register 2
(RCC_AHB1SLPENR2) . . . . . 453

10.5.32 RCC APB1 peripheral clock enable in Sleep mode register 1
(RCC_APB1SLPENR1) . . . . . 454

10.5.33 RCC APB1 peripheral clock enable in Sleep mode register 2
(RCC_APB1SLPENR2) . . . . . 456

10.5.34 RCC APB2 peripheral clock enable in Sleep mode register
(RCC_APB2SLPENR) . . . . . 457

10.5.35 RCC APB3 peripheral clock enable in Sleep mode register
(RCC_APB3SLPENR) . . . . . 458

10.5.36 RCC AHB1 peripheral clock enable in Stop mode register
(RCC_AHB1STPENR1) . . . . . 459

10.5.37 RCC AHB2 peripheral clock enable in Stop mode register 1
(RCC_AHB2STPENR1) . . . . . 460

10.5.38 RCC APB1 peripheral clock enable in Stop mode register 1
(RCC_APB1STPENR1) . . . . . 461

10.5.39 RCC APB1 peripheral clock enable in Stop mode register 2
(RCC_APB1STPENR2) . . . . . 463

10.5.40 RCC APB2 peripheral clock enable in Stop mode register
(RCC_APB2STPENR) . . . . . 464

10.5.41 RCC APB3 peripheral clock enable in Stop mode register
(RCC_APB3STPENR) . . . . . 465

10.5.42 RCC peripheral independent clock configuration register 1
(RCC_CCIPR1) . . . . . 466

10.5.43 RCC peripheral independent clock configuration register 2
(RCC_CCIPR2) . . . . . 468

10.5.44 RCC peripheral independent clock configuration register 3
(RCC_CCIPR3) . . . . . 470

10.5.45 RCC backup domain control register (RCC_BDCR) . . . . . 471

10.5.46 RCC control/status register (RCC_CSR) . . . . . 474

10.5.47 RCC secure configuration register (RCC_SECCFGR) . . . . . 476

10.5.48 RCC privilege configuration register (RCC_PRIVCFGR) . . . . . 477

10.5.49 RCC register map . . . . . 478

11 Clock recovery system (CRS) . . . . . 484

ST logo
ST logo
11.1CRS introduction . . . . .484
11.2CRS main features . . . . .484
11.3CRS implementation . . . . .484
11.4CRS functional description . . . . .485
11.4.1CRS block diagram . . . . .485
11.4.2CRS internal signals . . . . .485
11.4.3Synchronization input . . . . .486
11.4.4Frequency error measurement . . . . .486
11.4.5Frequency error evaluation and automatic trimming . . . . .487
11.4.6CRS initialization and configuration . . . . .488
11.5CRS in low-power modes . . . . .489
11.6CRS interrupts . . . . .489
11.7CRS registers . . . . .489
11.7.1CRS control register (CRS_CR) . . . . .489
11.7.2CRS configuration register (CRS_CFGR) . . . . .491
11.7.3CRS interrupt and status register (CRS_ISR) . . . . .492
11.7.4CRS interrupt flag clear register (CRS_ICR) . . . . .494
11.7.5CRS register map . . . . .494
12General-purpose I/Os (GPIO) . . . . .496
12.1Introduction . . . . .496
12.2GPIO main features . . . . .496
12.3GPIO functional description . . . . .496
12.3.1General-purpose I/O (GPIO) . . . . .498
12.3.2I/O pin alternate function multiplexer and mapping . . . . .499
12.3.3I/O port control registers . . . . .499
12.3.4I/O port state in low-power modes . . . . .500
12.3.5I/O port data registers . . . . .500
12.3.6I/O data bitwise handling . . . . .500
12.3.7GPIO locking mechanism . . . . .500
12.3.8I/O alternate function input/output . . . . .501
12.3.9Input configuration . . . . .501
12.3.10Output configuration . . . . .502
12.3.11Alternate function configuration . . . . .502
12.3.12Analog configuration . . . . .503
12.3.13Using HSE or LSE oscillator pins as GPIOs . . . . .503
12.3.14Using the GPIO pins in the RTC supply domain . . . . .504
12.3.15Using BOOT0 pin as GPIO . . . . .504
12.3.16TrustZone security . . . . .504
12.3.17Privileged and unprivileged modes . . . . .505
12.3.18High-speed low-voltage mode (HSLV) . . . . .505
12.3.19I/O compensation cell . . . . .506
12.4GPIO in low-power modes . . . . .506
12.5GPIO interrupts . . . . .506
12.6GPIO registers . . . . .507
12.6.1GPIO port mode register (GPIOx_MODER) (x = A to H) . . . . .507
12.6.2GPIO port output type register (GPIOx_OTYPER) (x = A to H) . . . . .507
12.6.3GPIO port output speed register (GPIOx_OSPEEDR) (x = A to H) . . . . .508
12.6.4GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to H) . . . . .509
12.6.5GPIO port input data register (GPIOx_IDR) (x = A to H) . . . . .509
12.6.6GPIO port output data register (GPIOx_ODR) (x = A to H) . . . . .510
12.6.7GPIO port bit set/reset register (GPIOx_BRR) (x = A to H) . . . . .510
12.6.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to H) . . . . .		511
12.6.9GPIO alternate function low register
(GPIOx_AFRL) (x = A to H) . . . . .		512
12.6.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to H) . . . . .		513
12.6.11GPIO port bit reset register (GPIOx_BRR) (x = A to H) . . . . .514
12.6.12GPIO high-speed low-voltage register (GPIOx_HSLVR) (x = A to H) . . . . .515
12.6.13GPIO secure configuration register (GPIOx_SECCFGR) (x = A to H) . . . . .515
12.6.14GPIO register map . . . . .516
13System configuration controller (SYSCFG) . . . . .518
13.1SYSCFG main features . . . . .518
13.2SYSCFG functional description . . . . .518
13.2.1I/O compensation cell management . . . . .518
13.2.2SYSCFG TrustZone security and privilege . . . . .519
13.2.3GPIO analog switches supply selection . . . . .520
13.3SYSCFG registers . . . . .521
13.3.1SYSCFG secure configuration register (SYSCFG_SECCFGR) . . . . .521
13.3.2SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .522
13.3.3SYSCFG FPU interrupt mask register (SYSCFG_FPUIMR) . . . . .524
13.3.4SYSCFG CPU nonsecure lock register (SYSCFG_CNSLCKR) . . . . .525
13.3.5SYSCFG CPU secure lock register (SYSCFG_CSLCKR) . . . . .525
13.3.6SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .526
13.3.7SYSCFG compensation cell control/status register
(SYSCFG_CCCSR) . . . . .		527
13.3.8SYSCFG compensation cell value register (SYSCFG_CCVR) . . . . .529
13.3.9SYSCFG compensation cell code register (SYSCFG_CCCR) . . . . .530
13.3.10SYSCFG RSS command register (SYSCFG_RSSCMDR) . . . . .531
13.3.11SYSCFG register map . . . . .531
14Peripheral interconnect matrix . . . . .533
14.1Interconnect matrix introduction . . . . .533
14.2Connection summary . . . . .533
14.3Interconnection details . . . . .536
14.3.1Master to slave interconnection for timers . . . . .536
14.3.2Triggers to ADCs . . . . .536
14.3.3ADC analog watchdogs as triggers to timers . . . . .537
14.3.4Triggers to DAC . . . . .538
14.3.5Triggers to ADF1 . . . . .538
14.3.6Data input to ADF1 . . . . .538
14.3.7Clock sources to timers . . . . .539
14.3.8Triggers to low-power timers . . . . .540
14.3.9Blanking sources to comparators . . . . .540
14.3.10RTC wake-up as inputs to timers . . . . .541
14.3.11USB SOF as trigger to timers . . . . .541
14.3.12Comparators as inputs, trigger or break signals to timers . . . . .541
14.3.13System errors as break signals to timers . . . . .542
14.3.14Timers generating IRTIM signal . . . . .543
14.3.15Triggers for communication peripherals . . . . .543
14.3.16Triggers to GPDMA . . . . .544
14.3.17Internal analog signals to analog peripherals . . . . .545
14.3.18Clock source for the DAC sample and hold mode . . . . .545
14.3.19Internal tamper sources . . . . .546
14.3.20Output from tamper to RTC . . . . .546
14.3.21Encryption keys to AES/SAES . . . . .546
14.3.22I3C IBI acknowledge to timers from I3C1/2 to TIM12/15/16/17 and
LPTIM1/2/3 . . . . .		547
14.3.23Triggers to HSP1 . . . . .547
15General purpose direct memory access controller (GPDMA) . . . . .548
15.1GPDMA introduction . . . . .548
15.2GPDMA main features . . . . .548
15.3GPDMA implementation . . . . .549
15.3.1GPDMA channels . . . . .549
15.3.2GPDMA in low-power modes . . . . .550
15.3.3GPDMA requests . . . . .550
15.3.4GPDMA block requests . . . . .554
15.3.5GPDMA channels with peripheral early termination . . . . .554
15.3.6GPDMA triggers . . . . .554
15.4GPDMA functional description . . . . .557
15.4.1GPDMA block diagram . . . . .557
15.4.2GPDMA channel state and direct programming without any linked-list . . . . .557
15.4.3GPDMA channel suspend and resume . . . . .558
15.4.4GPDMA channel abort and restart . . . . .559
15.4.5GPDMA linked-list data structure . . . . .560
15.4.6Linked-list item transfer execution . . . . .563
15.4.7GPDMA channel state and linked-list programming
in run-to-completion mode . . . . .		563
15.4.8GPDMA channel state and linked-list programming in link step mode . . . . .567
15.4.9GPDMA channel state and linked-list programming . . . . .574
15.4.10GPDMA FIFO-based transfers . . . . .576
15.4.11GPDMA transfer request and arbitration . . . . .583
15.4.12GPDMA triggered transfer . . . . .587
15.4.13GPDMA circular buffering with linked-list programming . . . . .588
15.4.14GPDMA transfer in peripheral flow-control mode . . . . .590
15.4.15GPDMA secure/nonsecure channel . . . . .591
15.4.16GPDMA privileged/unprivileged channel . . . . .592
15.4.17GPDMA error management . . . . .592
15.5GPDMA in debug mode . . . . .594
15.6GPDMA in low-power modes . . . . .594
15.7GPDMA interrupts . . . . .595
15.8GPDMA registers . . . . .596
15.8.1GPDMA secure configuration register (GPDMA_SECCFGR) . . . . .596
15.8.2GPDMA privileged configuration register (GPDMA_PRIVCFGR) . . . .597
15.8.3GPDMA configuration lock register (GPDMA_RCFGLOCKR) . . . . .597
15.8.4GPDMA nonsecure masked interrupt status register
(GPDMA_MISR) . . . . .		598
15.8.5GPDMA secure masked interrupt status register (GPDMA_SMISR) . .599
15.8.6GPDMA channel x linked-list base address register
(GPDMA_CxLBAR) . . . . .		599
15.8.7GPDMA channel x flag clear register (GPDMA_CxFCR) . . . . .600
15.8.8GPDMA channel x status register (GPDMA_CxSR) . . . . .601
15.8.9GPDMA channel x control register (GPDMA_CxCR) . . . . .602
15.8.10GPDMA channel x transfer register 1 (GPDMA_CxTR1) . . . . .604
15.8.11GPDMA channel x transfer register 2 (GPDMA_CxTR2) . . . . .608
15.8.12GPDMA channel x block register 1 (GPDMA_CxBR1) . . . . .612
15.8.13GPDMA channel x alternate block register 1 (GPDMA_CxBR1) . . . .613
15.8.14GPDMA channel x source address register (GPDMA_CxSAR) . . . . .616
15.8.15GPDMA channel x destination address register (GPDMA_CxDAR) . .617
15.8.16GPDMA channel x transfer register 3 (GPDMA_CxTR3) . . . . .618
15.8.17GPDMA channel x block register 2 (GPDMA_CxBR2) . . . . .619
15.8.18GPDMA channel x linked-list address register (GPDMA_CxLLR) . . . .620
15.8.19GPDMA channel x alternate linked-list address register
(GPDMA_CxLLR) . . . . .		622
15.8.20GPDMA register map . . . . .623
16Nested vectored interrupt controller (NVIC) . . . . .626
16.1NVIC main features . . . . .626
16.2SysTick calibration value register . . . . .626
16.3Interrupt and exception vectors . . . . .627
17Extended interrupts and event controller (EXTI) . . . . .633
17.1EXTI introduction . . . . .633
17.2EXTI main features . . . . .633
17.3EXTI functional description . . . . .633
17.3.1EXTI block diagram . . . . .633
17.3.2Event features control . . . . .635
17.3.3EXTI configurable event input wake-up . . . . .636
17.3.4EXTI mux selection . . . . .637
17.3.5EXTI functional behavior . . . . .637
17.3.6EXTI event protection .....638
17.4EXTI registers .....639
17.4.1EXTI rising trigger selection register (EXTI_RTSR1) .....639
17.4.2EXTI falling trigger selection register (EXTI_FTSR1) .....640
17.4.3EXTI software interrupt event register (EXTI_SWIER1) .....640
17.4.4EXTI rising edge pending register (EXTI_RPR1) .....641
17.4.5EXTI falling edge pending register (EXTI_FPR1) .....642
17.4.6EXTI security configuration register (EXTI_SECCFGR1) .....642
17.4.7EXTI privilege configuration register (EXTI_PRIVCFGR1) .....643
17.4.8EXTI external interrupt selection register (EXTI_EXTICRx) .....643
17.4.9EXTI lock register (EXTI_LOCKR) .....646
17.4.10EXTI CPU wake-up with interrupt mask register (EXTI_IMR1) .....646
17.4.11EXTI CPU wake-up with event mask register (EXTI_EM1R1) .....647
17.4.12EXTI register map .....647
18Cyclic redundancy check calculation unit (CRC) .....649
18.1CRC introduction .....649
18.2CRC main features .....649
18.3CRC functional description .....650
18.3.1CRC block diagram .....650
18.3.2CRC internal signals .....650
18.3.3CRC operation .....650
18.4CRC registers .....652
18.4.1CRC data register (CRC_DR) .....652
18.4.2CRC independent data register (CRC_IDR) .....652
18.4.3CRC control register (CRC_CR) .....653
18.4.4CRC initial value (CRC_INIT) .....654
18.4.5CRC polynomial (CRC_POL) .....654
18.4.6CRC register map .....655
19Hardware signal processor (HSP) .....656
19.1HSP introduction .....656
19.2HSP main features .....658
19.3HSP implementation .....659
19.4HSP functional description .....660
19.4.1HSP block diagram .....660
19.4.2HSP pins and internal signals . . . . .660
19.4.3Floating-point format . . . . .663
19.4.4Memory management . . . . .664
19.4.5HSP boot . . . . .667
19.4.6Message box (MSGB) . . . . .671
19.4.7Direct command interface (DCMD) . . . . .673
19.4.8STREAM interface . . . . .677
19.4.9Trigger input interface (TRGITF) . . . . .681
19.4.10Software events generator (SEG) . . . . .684
19.4.11Event controller (EVTC) . . . . .687
19.4.12HSP interrupt controller (HITC) . . . . .695
19.4.13HSP reset and clocking . . . . .703
19.4.14Task comparator unit (TCU) . . . . .705
19.4.15Trigger outputs (TRGO) . . . . .707
19.4.16Time-stamp capture (TSC) . . . . .708
19.4.17BRAM conflict counter . . . . .715
19.4.18Snoop function (SNOOP) . . . . .715
19.4.19Break interface (BKITF) . . . . .716
19.5Debug . . . . .719
19.5.1Register protection . . . . .721
19.6HSP firmware description . . . . .723
19.6.1Processing list mapping . . . . .723
19.6.2Sending commands to the HSP . . . . .724
19.6.3Recording processing lists . . . . .727
19.6.4Executing direct commands (accelerator mode) . . . . .728
19.6.5Data buffer handling . . . . .730
19.6.6Performance monitoring . . . . .730
19.6.7Processing functions summary . . . . .730
19.7HSP registers . . . . .736
19.7.1HSP control register (HSP_CR) . . . . .736
19.7.2HSP CPU-to-HSP semaphore register (HSP_C2HSEMR) . . . . .738
19.7.3HSP CPU-to-HSP message data register (HSP_C2HMSGDR) . . . . .738
19.7.4HSP HSP-to-CPU semaphore register (HSP_H2CSEMR) . . . . .739
19.7.5HSP HSP-to-CPU message data register (HSP_H2CMSGDR) . . . . .739
19.7.6HSP DCMD command status register (HSP_DCMDDSR) . . . . .740
19.7.7HSP DCMD pointer status register (HSP_DCMDPTSR) . . . . .740
19.7.8HSP DCMD command ID register (HSP_DCMDIDR) . . . . .741
19.7.9HSP DCMD address pointer register x (HSP_DCMDPTRx) . . . . .742
19.7.10HSP event enable register (HSP_EVTENR) . . . . .742
19.7.11HSP event synchronization enable register (HSP_ESYNCENR) . . . . .743
19.7.12HSP event synchronization source register 0 (HSP_ESYNC0SRCR) . . . . .743
19.7.13HSP event synchronization source register 1 (HSP_ESYNC1SRCR) . . . . .745
19.7.14HSP event synchronization source register 2 (HSP_ESYNC2SRCR) . . . . .747
19.7.15HSP pending event level register (HSP_PEVTLR) . . . . .749
19.7.16HSP interface enable register (HSP_ITFENR) . . . . .749
19.7.17HSP event source register 0 (HSP_EVTSRC0R) . . . . .751
19.7.18HSP event source register 1 (HSP_EVTSRC1R) . . . . .753
19.7.19HSP event source register 2 (HSP_EVTSRC2R) . . . . .756
19.7.20HSP BUFF configuration register (HSP_BUFFCFGR) . . . . .758
19.7.21HSP BUFFx data register x (HSP_BUFFxDR) . . . . .759
19.7.22HSP TRGIN configuration register (HSP_TRGINCFGR) . . . . .759
19.7.23HSP TRGO configuration register (HSP_TRGOCFGR) . . . . .760
19.7.24HSP TRGIN input selection register 0 (HSP_TRGINSEL0) . . . . .760
19.7.25HSP TRGIN input selection register 1 (HSP_TRGINSEL1) . . . . .761
19.7.26HSP TRGIN input selection register 2 (HSP_TRGINSEL2) . . . . .762
19.7.27HSP CPU shared event generator register (HSP_CSEGR) . . . . .763
19.7.28HSP CPU dedicated event generation register (HSP_CDEGR) . . . . .764
19.7.29HSP task comparator unit register (HSP_TCUCFGR) . . . . .764
19.7.30HSP task overlap control register (HSP_TOVLPCTR) . . . . .766
19.7.31HSP SNOOP register (HSP_SNPR) . . . . .766
19.7.32HSP conflict counter register (HSP_CCNTR) . . . . .767
19.7.33HSP data capture register (HSP_CAPDR) . . . . .768
19.7.34HSP data capture register [alternate] (HSP_CAPDR) . . . . .768
19.7.35HSP capture control register (HSP_CAPCR) . . . . .769
19.7.36HSP break output configuration register x (HSP_BKOxCFGR) . . . . .770
19.7.37HSP break input configuration register (HSP_BKICFGR) . . . . .771
19.7.38HSP SPE interrupt enable register (HSP_SPE_IER) . . . . .773
19.7.39HSP SPE interrupt status register (HSP_SPE_ISR) . . . . .773
19.7.40HSP error interrupt enable register (HSP_ERR_IER) . . . . .774
19.7.41HSP events interrupt enable register (HSP_EVT_IER) . . . . .776
19.7.42HSP processing event interrupt enable register
(HSP_PFCTEVT_IER) . . . . .		777
19.7.43HSP error interrupt status register (HSP_ERR_ISR) . . . . .778
19.7.44HSP events interrupt status register (HSP_EVT_ISR) . . . . .779
19.7.45HSP processing event interrupt status register (HSP_PFCTEVT_ISR) . . . . .781
19.7.46HSP error interrupt clear register (HSP_ERR_ICR) . . . . .781
19.7.47HSP events interrupt clear register (HSP_EVT_ICR) . . . . .783
19.7.48HSP processing event interrupt clear register (HSP_PFCTEVT_ICR) . . . . .784
19.7.49HSP error information register (HSP_ERRINFR) . . . . .784
19.7.50HSP firmware error register (HSP_FWERR) . . . . .786
19.7.51HSP parameter register x (HSP_PARAMRx) . . . . .786
19.7.52HSP firmware versions register (HSP_FWVERR) . . . . .787
19.7.53HSP SPE version register (HSP_SPEVERR) . . . . .787
19.7.54HSP register map . . . . .788
20Extended-SPI interface (OCTOSPI) . . . . .794
20.1OCTOSPI introduction . . . . .794
20.2OCTOSPI main features . . . . .794
20.3OCTOSPI implementation . . . . .795
20.4OCTOSPI functional description . . . . .796
20.4.1OCTOSPI block diagram . . . . .796
20.4.2OCTOSPI pins and internal signals . . . . .797
20.4.3OCTOSPI interface to memory modes . . . . .798
20.4.4OCTOSPI regular-command protocol . . . . .798
20.4.5OCTOSPI regular-command protocol signal interface . . . . .802
20.4.6HyperBus protocol . . . . .805
20.4.7Specific features . . . . .809
20.4.8OCTOSPI operating mode introduction . . . . .810
20.4.9OCTOSPI indirect mode . . . . .810
20.4.10OCTOSPI automatic status-polling mode . . . . .812
20.4.11OCTOSPI memory-mapped mode . . . . .813
20.4.12OCTOSPI configuration introduction . . . . .814
20.4.13OCTOSPI system configuration . . . . .814
20.4.14OCTOSPI device configuration . . . . .815
20.4.15OCTOSPI regular-command mode configuration . . . . .817
20.4.16OCTOSPI HyperBus protocol configuration . . . . .820
20.4.17OCTOSPI error management . . . . .821
20.4.18OCTOSPI BUSY and ABORT . . . . .821
20.4.19OCTOSPI reconfiguration or deactivation . . . . .822
20.4.20NCS behavior . . . . .822
20.5Address alignment and data number . . . . .823
20.6OCTOSPI interrupts . . . . .824
20.7OCTOSPI registers . . . . .825
20.7.1OCTOSPI control register (OCTOSPI_CR) . . . . .825
20.7.2OCTOSPI device configuration register 1 (OCTOSPI_DCR1) . . . . .828
20.7.3OCTOSPI device configuration register 2 (OCTOSPI_DCR2) . . . . .830
20.7.4OCTOSPI device configuration register 3 (OCTOSPI_DCR3) . . . . .831
20.7.5OCTOSPI device configuration register 4 (OCTOSPI_DCR4) . . . . .831
20.7.6OCTOSPI status register (OCTOSPI_SR) . . . . .832
20.7.7OCTOSPI flag clear register (OCTOSPI_FCR) . . . . .833
20.7.8OCTOSPI data length register (OCTOSPI_DLR) . . . . .834
20.7.9OCTOSPI address register (OCTOSPI_AR) . . . . .834
20.7.10OCTOSPI data register (OCTOSPI_DR) . . . . .835
20.7.11OCTOSPI polling status mask register (OCTOSPI_PSMKR) . . . . .835
20.7.12OCTOSPI polling status match register (OCTOSPI_PSMAR) . . . . .836
20.7.13OCTOSPI polling interval register (OCTOSPI_PIR) . . . . .836
20.7.14OCTOSPI communication configuration register (OCTOSPI_CCR) . . . . .836
20.7.15OCTOSPI timing configuration register (OCTOSPI_TCR) . . . . .839
20.7.16OCTOSPI instruction register (OCTOSPI_IR) . . . . .839
20.7.17OCTOSPI alternate bytes register (OCTOSPI_ABR) . . . . .840
20.7.18OCTOSPI low-power timeout register (OCTOSPI_LPTR) . . . . .840
20.7.19OCTOSPI wrap communication configuration register
(OCTOSPI_WPCCR) . . . . .		841
20.7.20OCTOSPI wrap timing configuration register (OCTOSPI_WPTCR) . . . . .843
20.7.21OCTOSPI wrap instruction register (OCTOSPI_WPIR) . . . . .843
20.7.22OCTOSPI wrap alternate bytes register (OCTOSPI_WPABR) . . . . .844
20.7.23OCTOSPI write communication configuration register
(OCTOSPI_WCCR) . . . . .		844
20.7.24OCTOSPI write timing configuration register (OCTOSPI_WTCR) . . . . .846
20.7.25OCTOSPI write instruction register (OCTOSPI_WIR) . . . . .847
20.7.26OCTOSPI write alternate bytes register (OCTOSPI_WABR) . . . . .847
20.7.27OCTOSPI HyperBus latency configuration register
(OCTOSPI_HLCR) . . . . .		848
20.7.28OCTOSPI register map . . . . .848
21Secure digital input/output MultiMediaCard interface (SDMMC) . . .852
21.1SDMMC main features . . . . .852
21.2SDMMC implementation . . . . .852
21.3SDMMC bus topology . . . . .853
21.4SDMMC operation modes . . . . .855
21.5SDMMC functional description . . . . .856
21.5.1SDMMC block diagram . . . . .856
21.5.2SDMMC pins and internal signals . . . . .856
21.5.3General description . . . . .857
21.5.4SDMMC adapter . . . . .859
21.5.5SDMMC AHB slave interface . . . . .881
21.5.6SDMMC AHB master interface . . . . .882
21.5.7AHB and SDMMC_CK clock relation . . . . .885
21.6Card functional description . . . . .885
21.6.1SD I/O mode . . . . .885
21.6.2CMD12 send timing . . . . .893
21.6.3Sleep (CMD5) . . . . .897
21.6.4Interrupt mode (Wait-IRQ) . . . . .898
21.6.5Boot operation . . . . .899
21.6.6Response R1b handling . . . . .902
21.6.7Reset and card cycle power . . . . .903
21.7Hardware flow control . . . . .904
21.8Ultra-high-speed phase I (UHS-I) voltage switch . . . . .904
21.9SDMMC interrupts . . . . .908
21.10SDMMC registers . . . . .909
21.10.1SDMMC power control register (SDMMC_POWER) . . . . .909
21.10.2SDMMC clock control register (SDMMC_CLKCR) . . . . .910
21.10.3SDMMC argument register (SDMMC_ARGR) . . . . .912
21.10.4SDMMC command register (SDMMC_CMDR) . . . . .912
21.10.5SDMMC command response register (SDMMC_RESPCMDR) . . . . .914
21.10.6SDMMC response x register (SDMMC_RESPxR) . . . . .915
21.10.7SDMMC data timer register (SDMMC_DTIMER) . . . . .915
21.10.8SDMMC data length register (SDMMC_DLENR) . . . . .916
21.10.9SDMMC data control register (SDMMC_DCTRL) . . . . .917
21.10.10SDMMC data counter register (SDMMC_DCNTR) . . . . .918
21.10.11SDMMC status register (SDMMC_STAR) . . . . .919
21.10.12SDMMC interrupt clear register (SDMMC_ICR) . . . . .922
21.10.13SDMMC mask register (SDMMC_MASKR) . . . . .924

21.10.14 SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . . 927

21.10.15 SDMMC DMA control register (SDMMC_IDMACTLRLR) . . . . . 927

21.10.16 SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . . 928

21.10.17 SDMMC IDMA buffer base address register
(SDMMC_IDMABASER) . . . . . 929

21.10.18 SDMMC IDMA linked list address register (SDMMC_IDMALAR) . . . 929

21.10.19 SDMMC IDMA linked list memory base register
(SDMMC_IDMABAR) . . . . . 930

21.10.20 SDMMC data FIFO registers x (SDMMC_FIFORx) . . . . . 931

21.10.21 SDMMC register map . . . . . 931

22 Delay block (DLYB) . . . . . 934

22.1 DLYB introduction . . . . . 934

22.2 DLYB main features . . . . . 934

22.3 DLYB implementation . . . . . 934

22.4 DLYB functional description . . . . . 934

22.4.1 DLYB diagram . . . . . 934

22.4.2 DLYB pins and internal signals . . . . . 935

22.4.3 General description . . . . . 935

22.4.4 Delay line length configuration procedure . . . . . 936

22.4.5 Output clock phase configuration procedure . . . . . 937

22.5 DLYB registers . . . . . 937

22.5.1 DLYB control register (DLYB_CR) . . . . . 937

22.5.2 DLYB configuration register (DLYB_CFGR) . . . . . 938

22.5.3 DLYB register map . . . . . 939

23 Analog-to-digital converters (ADC) . . . . . 940

23.1 ADC introduction . . . . . 940

23.2 ADC main features . . . . . 940

23.3 ADC implementation . . . . . 942

23.4 ADC functional description . . . . . 943

23.4.1 ADC block diagram . . . . . 943

23.4.2 ADC pins and internal signals . . . . . 944

23.4.3 ADC clocks . . . . . 947

23.4.4 ADC connectivity . . . . . 948

23.4.5 Slave AHB interface . . . . . 950

23.4.6ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . . . . .950
23.4.7Calibration (ADCAL) . . . . .950
23.4.8ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .952
23.4.9Constraints when writing the ADC control bits . . . . .953
23.4.10Channel selection (ADC_SQRY, ADC_JSQR) . . . . .954
23.4.11Channel preselection register (ADC_PCSEL) . . . . .955
23.4.12Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .955
23.4.13Single conversion mode . . . . .957
23.4.14Continuous conversion mode (CONT = 1) . . . . .958
23.4.15Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .958
23.4.16Starting conversions (ADSTART, JADSTART) . . . . .960
23.4.17Timing . . . . .961
23.4.18Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .961
23.4.19Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .963
23.4.20Injected channel management . . . . .964
23.4.21Queue of context for injected conversions . . . . .965
23.4.22Programmable resolution (RES) - fast conversion mode . . . . .973
23.4.23End of conversion and end of sampling phase (EOC, JEOC, EOSMP) . . . . .974
23.4.24End of conversion sequence (EOS, JEOS) . . . . .974
23.4.25Timing diagram examples (single/continuous modes, hardware/software triggers) . . . . .975
23.4.26Data management . . . . .977
23.4.27Managing conversions using the ADF . . . . .985
23.4.28Dynamic low-power features . . . . .986
23.4.29Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWDCH of ADC_AWD2CR and ADC_AWD3CR, HTR, LTR, AWDFILT) . . . . .989
23.4.30Oversampler . . . . .994
23.4.31Dual ADC modes . . . . .1000
23.4.32Temperature sensor . . . . .1016
23.4.33VBAT supply monitoring . . . . .1018
23.4.34Monitoring the internal voltage reference . . . . .1019
23.4.35Monitoring the DAC output voltage . . . . .1020
23.4.36Monitoring the supply voltage . . . . .1020
23.5ADC in low-power modes . . . . .1021
23.6ADC interrupts . . . . .1021
23.7ADC registers (for each ADC) . . . . .1022
23.7.1ADC interrupt and status register (ADC_ISR) . . . . .1022
23.7.2ADC interrupt enable register (ADC_IER) . . . . .1025
23.7.3ADC control register (ADC_CR) . . . . .1027
23.7.4ADC configuration register (ADC_CFGR1) . . . . .1030
23.7.5ADC configuration register 2 (ADC_CFGR2) . . . . .1033
23.7.6ADC sample time register 1 (ADC_SMPR1) . . . . .1036
23.7.7ADC sample time register 2 (ADC_SMPR2) . . . . .1037
23.7.8ADC channel preselection register (ADC_PCSEL) . . . . .1038
23.7.9ADC regular sequence register 1 (ADC_SQR1) . . . . .1038
23.7.10ADC regular sequence register 2 (ADC_SQR2) . . . . .1039
23.7.11ADC regular sequence register 3 (ADC_SQR3) . . . . .1040
23.7.12ADC regular sequence register 4 (ADC_SQR4) . . . . .1041
23.7.13ADC regular data register (ADC_DR) . . . . .1042
23.7.14ADC injected sequence register (ADC_JSQR) . . . . .1042
23.7.15ADC offset y configuration register (ADC_OFCFG Ry) . . . . .1044
23.7.16ADC offset y register (ADC_OF Ry) . . . . .1045
23.7.17ADC gain compensation register (ADC_GCOMP) . . . . .1046
23.7.18ADC injected channel y data register (ADC_JDRy) . . . . .1047
23.7.19ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .1047
23.7.20ADC analog watchdog 3 configuration register (ADC_AWD3CR) . . . . .1048
23.7.21ADC analog watchdog 1 lower threshold register (ADC_AWD1LTR) . . . . .1048
23.7.22ADC analog watchdog 1 higher threshold register
(ADC_AWD1HTR) . . . . .		1049
23.7.23ADC analog watchdog 2 lower threshold register (ADC_AWD2LTR) . . . . .1049
23.7.24ADC analog watchdog 2 higher threshold register
(ADC_AWD2HTR) . . . . .		1050
23.7.25ADC analog watchdog 3 lower threshold register (ADC_AWD3LTR) . . . . .1050
23.7.26ADC analog watchdog 3 higher threshold register
(ADC_AWD3HTR) . . . . .		1050
23.7.27ADC calibration factors (ADC_CALFACT) . . . . .1051
23.7.28ADC option register (ADC_OR) . . . . .1052
23.8ADC common registers . . . . .1052
23.8.1ADC common status register (ADCC_CSR) . . . . .1052
23.8.2ADC common control register (ADCC_CCR) . . . . .1054
23.8.3ADC common regular data register for dual mode
(ADCC_CDR) . . . . .		1055
23.8.4ADC common regular data register for dual mode (ADCC_CDR2) . . . . .1056
23.9ADC register map . . . . .1056
24Digital-to-analog converter (DAC) . . . . .1061
24.1DAC introduction . . . . .1061
24.2DAC main features . . . . .1061
24.3DAC implementation . . . . .1062
24.4DAC functional description . . . . .1063
24.4.1DAC block diagram . . . . .1063
24.4.2DAC pins and internal signals . . . . .1064
24.4.3DAC clocks . . . . .1065
24.4.4DAC channel enable . . . . .1065
24.4.5DAC data format . . . . .1066
24.4.6DAC conversion . . . . .1067
24.4.7DAC output voltage . . . . .1068
24.4.8DAC trigger selection . . . . .1069
24.4.9DMA requests . . . . .1069
24.4.10Noise generation . . . . .1070
24.4.11Triangle-wave generation . . . . .1071
24.4.12DAC channel modes . . . . .1072
24.4.13DAC channel buffer calibration . . . . .1075
24.4.14DAC channel conversion modes . . . . .1076
24.4.15Dual DAC channel conversion modes (if dual channels are available) . . . . .1077
24.4.16DAC autonomous mode . . . . .1081
24.5DAC in low-power modes . . . . .1082
24.6DAC interrupts . . . . .1082
24.7DAC registers . . . . .1083
24.7.1DAC control register (DAC_CR) . . . . .1083
24.7.2DAC software trigger register (DAC_SWTRGR) . . . . .1086
24.7.3DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . .1087
24.7.4DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . .1088
24.7.5DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . .1088
24.7.6DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . .1089
24.7.7DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . .1089
24.7.8DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .1090
24.7.9Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .1090
24.7.10Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . .1091
24.7.11Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . .1091
24.7.12DAC channel1 data output register (DAC_DOR1) . . . . .1092
24.7.13DAC channel2 data output register (DAC_DOR2) . . . . .1092
24.7.14DAC status register (DAC_SR) . . . . .1093
24.7.15DAC calibration control register (DAC_CCR) . . . . .1094
24.7.16DAC mode control register (DAC_MCR) . . . . .1095
24.7.17DAC channel1 sample and hold sample time register (DAC_SHSR1) . . . . .1096
24.7.18DAC channel2 sample and hold sample time register (DAC_SHSR2) . . . . .1097
24.7.19DAC sample and hold time register (DAC_SHHR) . . . . .1097
24.7.20DAC sample and hold refresh time register (DAC_SHRR) . . . . .1098
24.7.21DAC autonomous mode control register (DAC_AUTOCR) . . . . .1099
24.7.22DAC register map . . . . .1099
25Voltage reference buffer (VREFBUF) . . . . .1102
25.1VREFBUF introduction . . . . .1102
25.2VREFBUF implementation . . . . .1102
25.3VREFBUF functional description . . . . .1102
25.4VREFBUF trimming . . . . .1103
25.5VREFBUF registers . . . . .1104
25.5.1VREFBUF control and status register (VREFBUF_CSR) . . . . .1104
25.5.2VREFBUF calibration control register (VREFBUF_CCR) . . . . .1105
25.5.3VREFBUF register map . . . . .1105
26Comparator (COMP) . . . . .1106
26.1Introduction . . . . .1106
26.2COMP main features . . . . .1106
26.3COMP functional description . . . . .1107
26.3.1COMP block diagram . . . . .1107
26.3.2COMP pins and internal signals . . . . .1107
26.3.3Comparator LOCK mechanism . . . . .1109
26.3.4Window comparator . . . . .1109
26.3.5Hysteresis . . . . .1110
26.3.6Comparator output-blanking function . . . . .1110
26.3.7COMP power and speed modes . . . . .1111
26.3.8Scaler function . . . . .1111
26.4COMP in low-power modes . . . . .1112
26.5COMP interrupts . . . . .1112
26.6COMP registers . . . . .1113
26.6.1COMP1 control and status register (COMP1_CSR) . . . . .1113
26.6.2COMP2 control and status register (COMP2_CSR) . . . . .1115
26.6.3COMP register map . . . . .1116
27Operational amplifier (OPAMP) . . . . .1117
27.1OPAMP introduction . . . . .1117
27.2OPAMP main features . . . . .1117
27.3OPAMP functional description . . . . .1117
27.3.1OPAMP reset and clocks . . . . .1117
27.3.2Initial configuration . . . . .1118
27.3.3Signal routing . . . . .1118
27.3.4OPAMP modes . . . . .1119
27.3.5Calibration . . . . .1122
27.4OPAMP low-power modes . . . . .1124
27.5OPAMP registers . . . . .1124
27.5.1OPAMP1 control/status register (OPAMP1_CSR) . . . . .1124
27.5.2OPAMP1 offset trimming register in normal mode (OPAMP1_OTR) . . . . .1126
27.5.3OPAMP1 offset trimming register in low-power mode
(OPAMP1_LPOTR) . . . . .		1126
27.5.4OPAMP2 control/status register (OPAMP2_CSR) . . . . .1127
27.5.5OPAMP2 offset trimming register in normal mode
(OPAMP2_OTR) . . . . .		1128
27.5.6OPAMP2 offset trimming register in low-power mode
(OPAMP2_LPOTR) . . . . .		1128
27.5.7OPAMP register map . . . . .1129
28Audio digital filter (ADF) . . . . .1130
28.1ADF introduction . . . . .1130
28.2ADF main features . . . . .1130
28.3ADF implementation . . . . .1131
28.4ADF functional description . . . . .1132
28.4.1ADF block diagram . . . . .1132
28.4.2ADF pins and internal signals . . . . .1132
28.4.3Serial input interface (SITF) . . . . .1133
28.4.4ADC slave interface (ADCITF) . . . . .1138
28.4.5Clock generator (CKGEN) . . . . .1139
28.4.6Bitstream matrix (BSMX) . . . . .1141
28.4.7Digital filter processing (DFLT) . . . . .1142
28.4.8Digital filter acquisition modes . . . . .1151
28.4.9Start-up sequence examples . . . . .1159
28.4.10Sound activity detection (SAD) . . . . .1160
28.4.11Data transfer to memory . . . . .1168
28.4.12Autonomous mode . . . . .1171
28.4.13Register protection . . . . .1171
28.5ADF low-power modes . . . . .1172
28.6ADF interrupts . . . . .1172
28.7ADF application information . . . . .1174
28.7.1ADF configuration examples for audio capture . . . . .1174
28.7.2Programming examples . . . . .1175
28.7.3Connection examples . . . . .1177
28.7.4Global frequency response . . . . .1178
28.7.5Total ADF gain . . . . .1179
28.7.6How to compute SAD thresholds . . . . .1182
28.8ADF registers . . . . .1186
28.8.1ADF global control register (ADF_GCR) . . . . .1186
28.8.2ADF clock generator control register (ADF_CKGCR) . . . . .1186
28.8.3ADF trigger input selection register (ADF_TRGISEL) . . . . .1188
28.8.4ADF serial interface control register 0 (ADF_SITF0CR) . . . . .1189
28.8.5ADF bitstream matrix control register 0 (ADF_BSMX0CR) . . . . .1190
28.8.6ADF digital filter control register 0 (ADF_DFLT0CR) . . . . .1191
28.8.7ADF digital filter configuration register 0 (ADF_DFLT0CICR) . . . . .1193
28.8.8ADF reshape filter configuration register 0 (ADF_DFLT0RSFR) . . . . .1194
28.8.9ADF delay control register 0 (ADF_DLY0CR) . . . . .1195
28.8.10ADF DFLT0 interrupt enable register (ADF_DFLT0IER) . . . . .1196
28.8.11ADF DFLT0 interrupt status register 0 (ADF_DFLT0ISR) . . . . .1197
28.8.12ADF SAD control register (ADF_SADCR) . . . . .1198
28.8.13ADF SAD configuration register (ADF_SADCFGR) . . . . .1200
28.8.14ADF SAD sound level register (ADF_SADSDLVR) . . . . .1201
28.8.15ADF SAD ambient noise level register (ADF_SADANLVR) . . . . .1202
28.8.16ADF digital filter data register 0 (ADF_DFLT0DR) . . . . .1202
28.8.17ADF register map . . . . .1202
29Liquid crystal display controller (LCD) . . . . .1205
29.1LCD introduction . . . . .1205
29.2LCD main features . . . . .1205
29.3LCD functional description . . . . .1207
29.3.1General description . . . . .1207
29.3.2Frequency generator . . . . .1208
29.3.3Common driver . . . . .1209
29.3.4Segment driver . . . . .1212
29.3.5Voltage generator and contrast control . . . . .1216
29.3.6Double-buffer memory . . . . .1219
29.3.7COM and SEG multiplexing . . . . .1219
29.3.8Flowchart . . . . .1225
29.4LCD low-power modes . . . . .1226
29.5LCD interrupts . . . . .1226
29.6LCD registers . . . . .1227
29.6.1LCD control register (LCD_CR) . . . . .1227
29.6.2LCD frame control register (LCD_FCR) . . . . .1228
29.6.3LCD status register (LCD_SR) . . . . .1230
29.6.4LCD clear register (LCD_CLR) . . . . .1231
29.6.5LCD display memory (LCD_RAMx) . . . . .1232
29.6.6LCD display memory (LCD_RAMx) . . . . .1232
29.6.7LCD display memory (LCD_RAMx) . . . . .1233
29.6.8LCD register map . . . . .1233
30Touch sensing controller (TSC) . . . . .1236
30.1TSC introduction . . . . .1236
30.2TSC main features . . . . .1236
30.3TSC implementation . . . . .1237
30.4TSC functional description . . . . .1237
30.4.1TSC block diagram . . . . .1237
30.4.2Surface charge transfer acquisition overview . . . . .1238
30.4.3Reset and clocks . . . . .1240
30.4.4Charge transfer acquisition sequence . . . . .1240
30.4.5Spread spectrum feature . . . . .1241
30.4.6Max count error . . . . .1242
30.4.7Sampling capacitor I/O and channel I/O mode selection . . . . .1242
30.4.8Acquisition mode . . . . .1243
30.4.9I/O hysteresis and analog switch control . . . . .1244
30.5TSC low-power modes . . . . .1244
30.5.1Comparator usage overview . . . . .1244
30.6TSC interrupts . . . . .1247
30.7TSC registers . . . . .1247
30.7.1TSC control register (TSC_CR) . . . . .1247
30.7.2TSC interrupt enable register (TSC_IER) . . . . .1250
30.7.3TSC interrupt clear register (TSC_ICR) . . . . .1250
30.7.4TSC interrupt status register (TSC_ISR) . . . . .1251
30.7.5TSC I/O hysteresis control register (TSC_IOHCR) . . . . .1251
30.7.6TSC I/O analog switch control register
(TSC_IOASCR) . . . . .		1252
30.7.7TSC I/O sampling control register (TSC_IOSCR) . . . . .1252
30.7.8TSC I/O channel control register (TSC_IOCCR) . . . . .1253
30.7.9TSC I/O group control status register (TSC_IOGCSR) . . . . .1253
30.7.10TSC I/O group x counter register (TSC_IOGxCR) . . . . .1254
30.7.11TSC register map . . . . .1254
31Coupling and chaining bridge (CCB) . . . . .1256
31.1CCB introduction . . . . .1256
31.2CCB main features . . . . .1256
31.3CCB implementation . . . . .1257
31.4CCB functional description . . . . .1257
31.4.1CCB block diagram . . . . .1257
31.4.2CCB internal signals . . . . .1258
31.4.3CCB reset and clocks . . . . .1258
31.4.4CCB coupling and chaining . . . . .1258
31.4.5CCB error management . . . . .1261
31.5CCB coupling and chaining operations . . . . .1261
31.5.1Preliminary steps before any protected operation . . . . .1263
31.5.2ECDSA signature . . . . .1264
31.5.3ECC scalar multiplication . . . . .1271
31.5.4RSA modular exponentiation . . . . .1274
31.6CCB interrupts . . . . .1276
31.7CCB registers . . . . .1277
31.7.1CCB control register (CCB_CR) . . . . .1277
31.7.2CCB status register (CCB_SR) . . . . .1278
31.7.3CCB reference tag register (CCB_REFTAGRx) . . . . .1280
31.7.4CCB register map . . . . .1281
32True random number generator (RNG) . . . . .1282
32.1RNG introduction . . . . .1282
32.2RNG main features . . . . .1282
32.3RNG functional description . . . . .1283
32.3.1RNG block diagram . . . . .1283
32.3.2RNG internal signals . . . . .1283
32.3.3Random number generation . . . . .1284
32.3.4RNG initialization . . . . .1286
32.3.5RNG operation . . . . .1287
32.3.6RNG clocking . . . . .1289
32.3.7Error management . . . . .1289
32.3.8RNG low-power use . . . . .1291
32.4RNG interrupts . . . . .1291
32.5RNG processing time . . . . .1292
32.6RNG entropy source validation . . . . .1292
32.6.1Introduction . . . . .1292
32.6.2Validation conditions . . . . .1292
32.7RNG registers . . . . .1294
32.7.1RNG control register (RNG_CR) . . . . .1294
32.7.2RNG status register (RNG_SR) . . . . .1296
32.7.3RNG data register (RNG_DR) . . . . .1297

33 AES hardware accelerator (AES) . . . . . 1302

33.8.2AES status register (AES_SR) . . . . .1336
33.8.3AES data input register (AES_DINR) . . . . .1337
33.8.4AES data output register (AES_DOUTR) . . . . .1338
33.8.5AES key register 0 (AES_KEYR0) . . . . .1338
33.8.6AES key register 1 (AES_KEYR1) . . . . .1339
33.8.7AES key register 2 (AES_KEYR2) . . . . .1339
33.8.8AES key register 3 (AES_KEYR3) . . . . .1339
33.8.9AES initialization vector register 0 (AES_IVR0) . . . . .1340
33.8.10AES initialization vector register 1 (AES_IVR1) . . . . .1340
33.8.11AES initialization vector register 2 (AES_IVR2) . . . . .1340
33.8.12AES initialization vector register 3 (AES_IVR3) . . . . .1341
33.8.13AES key register 4 (AES_KEYR4) . . . . .1341
33.8.14AES key register 5 (AES_KEYR5) . . . . .1341
33.8.15AES key register 6 (AES_KEYR6) . . . . .1342
33.8.16AES key register 7 (AES_KEYR7) . . . . .1342
33.8.17AES suspend registers (AES_SUSPRx) . . . . .1342
33.8.18AES interrupt enable register (AES_IER) . . . . .1343
33.8.19AES interrupt status register (AES_ISR) . . . . .1344
33.8.20AES interrupt clear register (AES_ICR) . . . . .1345
33.8.21AES register map . . . . .1345
34Secure AES coprocessor (SAES) . . . . .1348
34.1SAES introduction . . . . .1348
34.2SAES main features . . . . .1348
34.3SAES implementation . . . . .1349
34.4SAES functional description . . . . .1349
34.4.1SAES block diagram . . . . .1349
34.4.2SAES internal signals . . . . .1350
34.4.3SAES reset and clocks . . . . .1351
34.4.4SAES symmetric cipher implementation . . . . .1351
34.4.5SAES encryption or decryption typical usage . . . . .1352
34.4.6SAES authenticated encryption, decryption, and cipher-based message authentication . . . . .1354
34.4.7SAES ciphertext stealing and data padding . . . . .1355
34.4.8SAES suspend and resume operations . . . . .1355
34.4.9SAES basic chaining modes (ECB, CBC) . . . . .1356
34.4.10SAES counter (CTR) mode . . . . .1360
35.2HASH main features . . . . .1403
35.3HASH implementation . . . . .1404
35.4HASH functional description . . . . .1404
35.4.1HASH block diagram . . . . .1404
35.4.2HASH internal signals . . . . .1404
35.4.3About secure hash algorithms . . . . .1405
35.4.4Message data feeding . . . . .1405
35.4.5Message digest computing . . . . .1406
35.4.6Message padding . . . . .1408
35.4.7HMAC operation . . . . .1410
35.4.8HASH suspend/resume operations . . . . .1411
35.4.9HASH DMA interface . . . . .1413
35.4.10HASH error management . . . . .1414
35.4.11HASH processing time . . . . .1414
35.5HASH interrupts . . . . .1415
35.6HASH registers . . . . .1415
35.6.1HASH control register (HASH_CR) . . . . .1415
35.6.2HASH data input register (HASH_DIN) . . . . .1417
35.6.3HASH start register (HASH_STR) . . . . .1418
35.6.4HASH digest registers . . . . .1419
35.6.5HASH interrupt enable register (HASH_IMR) . . . . .1421
35.6.6HASH status register (HASH_SR) . . . . .1421
35.6.7HASH context swap registers . . . . .1422
35.6.8HASH register map . . . . .1423
36Public key accelerator (PKA) . . . . .1425
36.1PKA introduction . . . . .1425
36.2PKA main features . . . . .1425
36.3PKA implementation . . . . .1425
36.4PKA functional description . . . . .1426
36.4.1PKA block diagram . . . . .1426
36.4.2PKA internal signals . . . . .1426
36.4.3PKA reset and clocks . . . . .1427
36.4.4PKA public key acceleration . . . . .1427
36.4.5Typical applications for PKA . . . . .1429
36.4.6PKA procedure to perform an operation . . . . .1431

37 Advanced-control timers (TIM1/TIM8) . . . . . 1464

37.2TIM1/TIM8 main features . . . . .1465
37.3TIM1/TIM8 functional description . . . . .1466
37.3.1Block diagram . . . . .1466
37.3.2TIM1/TIM8 pins and internal signals . . . . .1467
37.3.3Time-base unit . . . . .1471
37.3.4Counter modes . . . . .1473
37.3.5Repetition counter . . . . .1485
37.3.6External trigger input . . . . .1486
37.3.7Clock selection . . . . .1487
37.3.8Capture/compare channels . . . . .1491
37.3.9Input capture mode . . . . .1494
37.3.10PWM input mode . . . . .1495
37.3.11Forced output mode . . . . .1496
37.3.12Output compare mode . . . . .1496
37.3.13PWM mode . . . . .1498
37.3.14Asymmetric PWM mode . . . . .1506
37.3.15Combined PWM mode . . . . .1507
37.3.16Combined 3-phase PWM mode . . . . .1508
37.3.17Complementary outputs and dead-time insertion . . . . .1509
37.3.18Using the break function . . . . .1512
37.3.19Bidirectional break inputs . . . . .1518
37.3.20Clearing the tim_ocxref signal on an external event . . . . .1519
37.3.216-step PWM generation . . . . .1521
37.3.22One-pulse mode . . . . .1522
37.3.23Retriggerable One-pulse mode . . . . .1524
37.3.24Pulse on compare mode . . . . .1525
37.3.25Encoder interface mode . . . . .1527
37.3.26Direction bit output . . . . .1544
37.3.27UIF bit remapping . . . . .1545
37.3.28Timer input XOR function . . . . .1545
37.3.29Interfacing with Hall sensors . . . . .1545
37.3.30Timer synchronization . . . . .1547
37.3.31ADC triggers . . . . .1552
37.3.32ADC synchronization . . . . .1552
37.3.33DMA burst mode . . . . .1553
37.3.34TIM1/TIM8 DMA requests . . . . .1554
37.3.35Debug mode . . . . .1554
37.4TIM1/TIM8 low-power modes . . . . .1555
37.5TIM1/TIM8 interrupts . . . . .1555
37.6TIM1/TIM8 registers . . . . .1556
37.6.1TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . .1556
37.6.2TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . .1557
37.6.3TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) . . . . .1561
37.6.4TIMx DMA/interrupt enable register (TIMx_DIER)(x = 1, 8) . . . . .1565
37.6.5TIMx status register (TIMx_SR)(x = 1, 8) . . . . .1566
37.6.6TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . .1569
37.6.7TIMx capture/compare mode register 1 (TIMx_CCMR1)
(x = 1, 8) . . . . .		1570
37.6.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . .		1572
37.6.9TIMx capture/compare mode register 2 (TIMx_CCMR2)
(x = 1, 8) . . . . .		1575
37.6.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . .		1576
37.6.11TIMx capture/compare enable register (TIMx_CCER)(x = 1, 8) . . . . .1579
37.6.12TIMx counter (TIMx_CNT)(x = 1, 8) . . . . .1583
37.6.13TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . .1583
37.6.14TIMx autoreload register (TIMx_ARR)(x = 1, 8) . . . . .1584
37.6.15TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . .1584
37.6.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 1, 8) . . . . .1585
37.6.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 1, 8) . . . . .1585
37.6.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 1, 8) . . . . .1586
37.6.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 1, 8) . . . . .1587
37.6.20TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) . . . . .1588
37.6.21TIMx capture/compare register 5 (TIMx_CCR5)(x = 1, 8) . . . . .1592
37.6.22TIMx capture/compare register 6 (TIMx_CCR6)(x = 1, 8) . . . . .1593
37.6.23TIMx capture/compare mode register 3 (TIMx_CCMR3)
(x = 1, 8) . . . . .		1594
37.6.24TIMx timer deadtime register 2 (TIMx_DTR2)(x = 1, 8) . . . . .1595
37.6.25TIMx timer encoder control register (TIMx_ECR)(x = 1, 8) . . . . .1596
37.6.26TIMx timer input selection register (TIMx_TISEL)(x = 1, 8) . . . . .1597
37.6.27TIMx alternate function option register 1 (TIMx_AF1)(x = 1, 8) . . . . .1598
37.6.28TIMx alternate function register 2 (TIMx_AF2)(x = 1, 8) . . . . .1601
37.6.29TIMx DMA control register (TIMx_DCR)(x = 1, 8) . . . . .1603
37.6.30TIMx DMA address for full transfer (TIMx_DMAR)(x = 1, 8) . . . . .1605
37.6.31TIMx register map .....1605
38General-purpose timers (TIM2/TIM3/TIM4) .....1608
38.1TIM2/TIM3/TIM4 introduction .....1608
38.2TIM2/TIM3/TIM4 main features .....1608
38.3TIM2/TIM3/TIM4 implementation .....1609
38.4TIM2/TIM3/TIM4 functional description .....1610
38.4.1Block diagram .....1610
38.4.2TIM2/TIM3/TIM4 pins and internal signals .....1611
38.4.3Time-base unit .....1614
38.4.4Counter modes .....1616
38.4.5Clock selection .....1628
38.4.6Capture/compare channels .....1632
38.4.7Input capture mode .....1634
38.4.8PWM input mode .....1635
38.4.9Forced output mode .....1636
38.4.10Output compare mode .....1636
38.4.11PWM mode .....1638
38.4.12Asymmetric PWM mode .....1646
38.4.13Combined PWM mode .....1647
38.4.14Clearing the tim_ocxref signal on an external event .....1648
38.4.15One-pulse mode .....1650
38.4.16Retriggerable one-pulse mode .....1651
38.4.17Pulse on compare mode .....1652
38.4.18Encoder interface mode .....1654
38.4.19Direction bit output .....1672
38.4.20UIF bit remapping .....1673
38.4.21Timer input XOR function .....1673
38.4.22Timers and external trigger synchronization .....1673
38.4.23Timer synchronization .....1677
38.4.24ADC triggers .....1682
38.4.25ADC synchronization .....1683
38.4.26DMA burst mode .....1684
38.4.27TIM2/TIM3/TIM4 DMA requests .....1685
38.4.28Debug mode .....1685
38.4.29TIM2/TIM3/TIM4 low-power modes .....1685
38.4.30TIM2/TIM3/TIM4 interrupts .....1686
38.5TIM2/TIM3/TIM4 registers . . . . .1687
38.5.1TIMx control register 1 (TIMx_CR1)(x = 2 to 4) . . . . .1687
38.5.2TIMx control register 2 (TIMx_CR2)(x = 2 to 4) . . . . .1688
38.5.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 4) . . . . .1690
38.5.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 4) . . . . .1694
38.5.5TIMx status register (TIMx_SR)(x = 2 to 4) . . . . .1695
38.5.6TIMx event generation register (TIMx_EGR)(x = 2 to 4) . . . . .1697
38.5.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 4) . . . . .1698
38.5.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 2 to 4) . . . . .		1700
38.5.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 4) . . . . .1702
38.5.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 2 to 4) . . . . .		1703
38.5.11TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 4) . . . . .1706
38.5.12TIMx counter (TIMx_CNT)(x = 2 to 4) . . . . .1708
38.5.13TIMx prescaler (TIMx_PSC)(x = 2 to 4) . . . . .1708
38.5.14TIMx autoreload register (TIMx_ARR)(x = 2 to 4) . . . . .1709
38.5.15TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 4) . . . . .1709
38.5.16TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 4) . . . . .1710
38.5.17TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 4) . . . . .1711
38.5.18TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 4) . . . . .1712
38.5.19TIMx timer encoder control register (TIMx_ECR)(x = 2 to 4) . . . . .1713
38.5.20TIMx timer input selection register (TIMx_TISEL)(x = 2 to 4) . . . . .1714
38.5.21TIMx alternate function register 1 (TIMx_AF1)(x = 2 to 4) . . . . .1715
38.5.22TIMx alternate function register 2 (TIMx_AF2)(x = 2 to 4) . . . . .1716
38.5.23TIMx DMA control register (TIMx_DCR)(x = 2 to 4) . . . . .1717
38.5.24TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 4) . . . . .1718
38.5.25TIMx register map . . . . .1719
39Basic timers (TIM6/TIM7) . . . . .1722
39.1TIM6/TIM7 introduction . . . . .1722
39.2TIM6/TIM7 main features . . . . .1722
39.3TIM6/TIM7 functional description . . . . .1723
39.3.1TIM6/TIM7 block diagram . . . . .1723
39.3.2TIM6/TIM7 internal signals . . . . .1723
39.3.3TIM6/TIM7 clocks . . . . .1724
39.3.4Time-base unit . . . . .1724
39.3.5Counting mode .....1726
39.3.6UIF bit remapping .....1733
39.3.7ADC triggers .....1734
39.3.8ADC synchronization .....1734
39.3.9TIM6/TIM7 DMA requests .....1735
39.3.10Debug mode .....1735
39.3.11TIM6/TIM7 low-power modes .....1735
39.3.12TIM6/TIM7 interrupts .....1735
39.4TIM6/TIM7 registers .....1736
39.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) .....1736
39.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) .....1738
39.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) .....1738
39.4.4TIMx status register (TIMx_SR)(x = 6 to 7) .....1739
39.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) .....1739
39.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) .....1740
39.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) .....1740
39.4.8TIMx autoreload register (TIMx_ARR)(x = 6 to 7) .....1741
39.4.9TIMx register map .....1742
40General-purpose timers (TIM12) .....1743
40.1TIM12 introduction .....1743
40.2TIM12 main features .....1743
40.3TIM12 functional description .....1744
40.3.1Block diagram .....1744
40.3.2TIM12 pins and internal signals .....1744
40.3.3Time-base unit .....1746
40.3.4Counter modes .....1748
40.3.5Clock selection .....1751
40.3.6Capture/compare channels .....1753
40.3.7Input capture mode .....1755
40.3.8PWM input mode (TIM12 only) .....1756
40.3.9Forced output mode .....1757
40.3.10Output compare mode .....1757
40.3.11PWM mode .....1759
40.3.12Combined PWM mode (TIM12 only) .....1764
40.3.13One-pulse mode .....1765
40.3.14Retriggerable one pulse mode (TIM12 only) .....1767
40.3.15UIF bit remapping . . . . .1768
40.3.16Timer input XOR function . . . . .1768
40.3.17TIM12 external trigger synchronization . . . . .1768
40.3.18Slave mode – combined reset + trigger mode . . . . .1771
40.3.19Slave mode – combined reset + gated mode . . . . .1771
40.3.20Timer synchronization (TIM12 only) . . . . .1771
40.3.21Using timer output as trigger for other timers
(N/A only) . . . . .		1771
40.3.22ADC triggers (TIM12 only) . . . . .1771
40.3.23Debug mode . . . . .1771
40.4TIM12 low-power modes . . . . .1772
40.5TIM12 interrupts . . . . .1772
40.6TIM12 registers . . . . .1772
40.6.1TIM12 control register 1 (TIM12_CR1) . . . . .1772
40.6.2TIM12 control register 2 (TIM12_CR2) . . . . .1774
40.6.3TIM12 slave mode control register (TIM12_SMCR) . . . . .1774
40.6.4TIM12 interrupt enable register (TIM12_DIER) . . . . .1776
40.6.5TIM12 status register (TIM12_SR) . . . . .1777
40.6.6TIM12 event generation register (TIM12_EGR) . . . . .1778
40.6.7TIM12 capture/compare mode register 1 (TIM12_CCMR1) . . . . .1779
40.6.8TIM12 capture/compare mode register 1 [alternate]
(TIM12_CCMR1) . . . . .		1780
40.6.9TIM12 capture/compare enable register (TIM12_CCER) . . . . .1783
40.6.10TIM12 counter (TIM12_CNT) . . . . .1784
40.6.11TIM12 prescaler (TIM12_PSC) . . . . .1785
40.6.12TIM12 autoreload register (TIM12_ARR) . . . . .1785
40.6.13TIM12 capture/compare register 1 (TIM12_CCR1) . . . . .1786
40.6.14TIM12 capture/compare register 2 (TIM12_CCR2) . . . . .1786
40.6.15TIM12 timer input selection register (TIM12_TISEL) . . . . .1787
40.6.16TIM12 register map . . . . .1788
41General purpose timers (TIM15/TIM16/TIM17) . . . . .1790
41.1TIM15/TIM16/TIM17 introduction . . . . .1790
41.2TIM15 main features . . . . .1790
41.3TIM16/TIM17 main features . . . . .1791
41.4TIM15/TIM16/TIM17 functional description . . . . .1792
41.4.1Block diagram . . . . .1792
41.4.2TIM15/TIM16/TIM17 pins and internal signals . . . . .1793
41.4.3Time-base unit . . . . .1796
41.4.4Counter modes . . . . .1798
41.4.5Repetition counter . . . . .1802
41.4.6Clock selection . . . . .1803
41.4.7Capture/compare channels . . . . .1805
41.4.8Input capture mode . . . . .1807
41.4.9PWM input mode (only for TIM15) . . . . .1809
41.4.10Forced output mode . . . . .1810
41.4.11Output compare mode . . . . .1810
41.4.12PWM mode . . . . .1812
41.4.13Combined PWM mode (TIM15 only) . . . . .1817
41.4.14Complementary outputs and dead-time insertion . . . . .1818
41.4.15Using the break function . . . . .1821
41.4.16Bidirectional break input . . . . .1825
41.4.17Clearing the tim_ocxref signal on an external event . . . . .1826
41.4.186-step PWM generation . . . . .1827
41.4.19One-pulse mode . . . . .1829
41.4.20Retriggerable one pulse mode (TIM15 only) . . . . .1830
41.4.21UIF bit remapping . . . . .1831
41.4.22Timer input XOR function (TIM15 only) . . . . .1831
41.4.23External trigger synchronization (TIM15 only) . . . . .1831
41.4.24Slave mode – combined reset + trigger mode (TIM15 only) . . . . .1834
41.4.25Slave mode – combined reset + gated mode (TIM15 only) . . . . .1834
41.4.26Timer synchronization (TIM15 only) . . . . .1835
41.4.27Using timer output as trigger for other timers (TIM16/TIM17 only) . . . . .1835
41.4.28ADC triggers (TIM15 only) . . . . .1835
41.4.29ADC synchronization (TIM15 only) . . . . .1836
41.4.30DMA burst mode . . . . .1836
41.4.31TIM15/TIM16/TIM17 DMA requests . . . . .1837
41.4.32Debug mode . . . . .1838
41.5TIM15/TIM16/TIM17 low-power modes . . . . .1838
41.6TIM15/TIM16/TIM17 interrupts . . . . .1838
41.7TIM15 registers . . . . .1839
41.7.1TIM15 control register 1 (TIM15_CR1) . . . . .1839
41.7.2TIM15 control register 2 (TIM15_CR2) . . . . .1840
41.7.3TIM15 slave mode control register (TIM15_SMCR) . . . . .1842
41.7.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .1844
41.7.5TIM15 status register (TIM15_SR) . . . . .1845
41.7.6TIM15 event generation register (TIM15_EGR) . . . . .1847
41.7.7TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .1848
41.7.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		1849
41.7.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .1852
41.7.10TIM15 counter (TIM15_CNT) . . . . .1855
41.7.11TIM15 prescaler (TIM15_PSC) . . . . .1855
41.7.12TIM15 autoreload register (TIM15_ARR) . . . . .1856
41.7.13TIM15 repetition counter register (TIM15_RCR) . . . . .1856
41.7.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .1857
41.7.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .1858
41.7.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .1858
41.7.17TIM15 timer deadtime register 2 (TIM15_DTR2) . . . . .1861
41.7.18TIM15 input selection register (TIM15_TISEL) . . . . .1862
41.7.19TIM15 alternate function register 1 (TIM15_AF1) . . . . .1863
41.7.20TIM15 alternate function register 2 (TIM15_AF2) . . . . .1865
41.7.21TIM15 DMA control register (TIM15_DCR) . . . . .1866
41.7.22TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .1867
41.7.23TIM15 register map . . . . .1867
41.8TIM16/TIM17 registers . . . . .1870
41.8.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .1870
41.8.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .1871
41.8.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .1872
41.8.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .1873
41.8.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .1874
41.8.6TIMx capture/compare mode register 1 (TIMx_CCMR1)
(x = 16 to 17) . . . . .		1875
41.8.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1876
41.8.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .1878
41.8.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .1881
41.8.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .1881
41.8.11TIMx auto-reautoreload register (TIMx_ARR)(x = 16 to 17) . . . . .1882
41.8.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .1882
41.8.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .1883
41.8.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .1884
41.8.15TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16 to 17) . . . . .1887
41.8.16TIMx input selection register (TIMx_TISEL)(x = 16 to 17) . . . . .1888
41.8.17TIMx alternate function register 1 (TIMx_AF1)(x = 16 to 17) . . . . .1888
41.8.18TIMx alternate function register 2 (TIMx_AF2)(x = 16 to 17) . . . . .1891
41.8.19TIMx option register 1 (TIMx_OR1)(x = 16 to 17) . . . . .1891
41.8.20TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .1892
41.8.21TIM16/TIM17 DMA address for full transfer
(TIMx_DMAR)(x = 16 to 17) . . . . .		1893
41.8.22TIM16/TIM17 register map . . . . .1894
42Low-power timer (LPTIM) . . . . .1896
42.1LPTIM introduction . . . . .1896
42.2LPTIM main features . . . . .1896
42.3LPTIM implementation . . . . .1897
42.4LPTIM functional description . . . . .1898
42.4.1LPTIM block diagram . . . . .1898
42.4.2LPTIM pins and internal signals . . . . .1899
42.4.3LPTIM input and trigger mapping . . . . .1901
42.4.4LPTIM reset and clocks . . . . .1902
42.4.5Glitch filter . . . . .1903
42.4.6Prescaler . . . . .1904
42.4.7Trigger multiplexer . . . . .1904
42.4.8Operating mode . . . . .1905
42.4.9Timeout function . . . . .1907
42.4.10Waveform generation . . . . .1907
42.4.11Register update . . . . .1908
42.4.12Counter mode . . . . .1909
42.4.13Timer enable . . . . .1909
42.4.14Timer counter reset . . . . .1910
42.4.15Encoder mode . . . . .1910
42.4.16Repetition counter . . . . .1912
42.4.17Capture/compare channels . . . . .1913
42.4.18Input capture mode . . . . .1914
42.4.19PWM mode . . . . .1916
42.4.20Autonomous mode . . . . .1918
42.4.21DMA requests . . . . .1919
42.4.22Debug mode . . . . .1920
44.4.3Software and hardware watchdog modes . . . . .1952
44.4.4Window option . . . . .1953
44.4.5Debug . . . . .1956
44.4.6Register access protection . . . . .1956
44.5IWDG low power modes . . . . .1956
44.6IWDG interrupts . . . . .1957
44.7IWDG registers . . . . .1958
44.7.1IWDG key register (IWDG_KR) . . . . .1958
44.7.2IWDG prescaler register (IWDG_PR) . . . . .1959
44.7.3IWDG reload register (IWDG_RLR) . . . . .1960
44.7.4IWDG status register (IWDG_SR) . . . . .1960
44.7.5IWDG window register (IWDG_WINR) . . . . .1961
44.7.6IWDG early wake-up interrupt register (IWDG_EWCR) . . . . .1962
44.7.7IWDG register map . . . . .1964
45System window watchdog (WWDG) . . . . .1965
45.1WWDG introduction . . . . .1965
45.2WWDG main features . . . . .1965
45.3WWDG implementation . . . . .1965
45.4WWDG functional description . . . . .1966
45.4.1WWDG block diagram . . . . .1966
45.4.2WWDG internal signals . . . . .1966
45.4.3Enabling the watchdog . . . . .1967
45.4.4Controlling the down-counter . . . . .1967
45.4.5How to program the watchdog timeout . . . . .1967
45.4.6Debug mode . . . . .1968
45.5WWDG interrupts . . . . .1969
45.6WWDG registers . . . . .1969
45.6.1WWDG control register (WWDG_CR) . . . . .1969
45.6.2WWDG configuration register (WWDG_CFR) . . . . .1970
45.6.3WWDG status register (WWDG_SR) . . . . .1971
45.6.4WWDG register map . . . . .1971
46Real-time clock (RTC) . . . . .1972
46.1RTC introduction . . . . .1972
46.2RTC main features . . . . .1972
46.6.14RTC timestamp date register (RTC_TSDR) . . . . .2011
46.6.15RTC timestamp subsecond register (RTC_TSSSR) . . . . .2012
46.6.16RTC alarm A register (RTC_ALRMAR) . . . . .2012
46.6.17RTC alarm A subsecond register (RTC_ALRMASSR) . . . . .2014
46.6.18RTC alarm B register (RTC_ALRMBR) . . . . .2015
46.6.19RTC alarm B subsecond register (RTC_ALRMBSSR) . . . . .2016
46.6.20RTC status register (RTC_SR) . . . . .2017
46.6.21RTC nonsecure masked interrupt status register (RTC_MISR) . . . . .2018
46.6.22RTC secure masked interrupt status register (RTC_SMISR) . . . . .2019
46.6.23RTC status clear register (RTC_SCR) . . . . .2021
46.6.24RTC timestamp on tamper control register (RTC_TAMPTSCR) . . . . .2022
46.6.25RTC timestamp status register (RTC_TSIDR) . . . . .2023
46.6.26RTC alarm A binary mode register (RTC_ALRABINR) . . . . .2024
46.6.27RTC alarm B binary mode register (RTC_ALRBBINR) . . . . .2024
46.6.28RTC register map . . . . .2025
47Tamper and backup registers (TAMP) . . . . .2028
47.1Introduction . . . . .2028
47.2TAMP main features . . . . .2028
47.3TAMP functional description . . . . .2029
47.3.1TAMP block diagram . . . . .2029
47.3.2TAMP pins and internal signals . . . . .2030
47.3.3GPIOs controlled by the RTC and TAMP . . . . .2032
47.3.4TAMP register write protection . . . . .2034
47.3.5TAMP secure protection modes . . . . .2034
47.3.6Backup registers protection zones . . . . .2034
47.3.7TAMP privilege protection modes . . . . .2035
47.3.8Boot hardware key (BHK) . . . . .2035
47.3.9Tamper detection . . . . .2036
47.3.10TAMP backup registers and other device secrets erase . . . . .2036
47.3.11Tamper detection - confirmed mode . . . . .2036
47.3.12Tamper detection configuration and initialization . . . . .2038
47.4TAMP in low-power modes . . . . .2041
47.5TAMP interrupts . . . . .2041
47.6TAMP registers . . . . .2042
47.6.1TAMP control register 1 (TAMP_CR1) . . . . .2042
47.6.2TAMP control register 2 (TAMP_CR2) . . . . .2043
47.6.3TAMP control register 3 (TAMP_CR3) . . . . .2044
47.6.4TAMP filter control register (TAMP_FLTCR) . . . . .2045
47.6.5TAMP secure configuration register (TAMP_SECCFGR) . . . . .2046
47.6.6TAMP privileged configuration register (TAMP_PRIVCFGR) . . . . .2048
47.6.7TAMP interrupt enable register (TAMP_IER) . . . . .2049
47.6.8TAMP status register (TAMP_SR) . . . . .2050
47.6.9TAMP nonsecure masked interrupt status register (TAMP_MISR) . . . . .2051
47.6.10TAMP secure masked interrupt status register (TAMP_SMISR) . . . . .2052
47.6.11TAMP status clear register (TAMP_SCR) . . . . .2053
47.6.12TAMP monotonic counter 1 register (TAMP_COUNT1R) . . . . .2054
47.6.13TAMP resource protection register (TAMP_RPFCFGR) . . . . .2054
47.6.14TAMP backup x register (TAMP_BKPxR) . . . . .2055
47.6.15TAMP register map . . . . .2055
48Inter-integrated circuit interface (I2C) . . . . .2058
48.1I2C introduction . . . . .2058
48.2I2C main features . . . . .2058
48.3I2C implementation . . . . .2059
48.4I2C functional description . . . . .2059
48.4.1I2C block diagram . . . . .2060
48.4.2I2C pins and internal signals . . . . .2060
48.4.3I2C clock requirements . . . . .2061
48.4.4I2C mode selection . . . . .2062
48.4.5I2C initialization . . . . .2063
48.4.6I2C reset . . . . .2067
48.4.7I2C data transfer . . . . .2067
48.4.8I2C target mode . . . . .2069
48.4.9I2C controller mode . . . . .2078
48.4.10I2C_TIMINGR register configuration examples . . . . .2089
48.4.11SMBus specific features . . . . .2091
48.4.12SMBus initialization . . . . .2094
48.4.13SMBus I2C_TIMEOUTR register configuration examples . . . . .2096
48.4.14SMBus target mode . . . . .2096
48.4.15SMBus controller mode . . . . .2100
48.4.16Autonomous mode . . . . .2103
48.4.17Error conditions . . . . .2105
48.5I2C in low-power modes . . . . .2106
48.6I2C interrupts . . . . .2107
48.7I2C DMA requests . . . . .2107
48.7.1Transmission using DMA . . . . .2107
48.7.2Reception using DMA . . . . .2108
48.7.3Controller event control using DMA . . . . .2108
48.8I2C debug modes . . . . .2109
48.9I2C registers . . . . .2109
48.9.1I2C control register 1 (I2C_CR1) . . . . .2109
48.9.2I2C control register 2 (I2C_CR2) . . . . .2112
48.9.3I2C own address 1 register (I2C_OAR1) . . . . .2114
48.9.4I2C own address 2 register (I2C_OAR2) . . . . .2114
48.9.5I2C timing register (I2C_TIMINGR) . . . . .2115
48.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .2116
48.9.7I2C interrupt and status register (I2C_ISR) . . . . .2117
48.9.8I2C interrupt clear register (I2C_ICR) . . . . .2120
48.9.9I2C PEC register (I2C_PECR) . . . . .2121
48.9.10I2C receive data register (I2C_RXDR) . . . . .2121
48.9.11I2C transmit data register (I2C_TXDR) . . . . .2122
48.9.12I2C autonomous mode control register (I2C_AUTOCR) . . . . .2122
48.9.13I2C register map . . . . .2124
49Improved inter-integrated circuit (I3C) . . . . .2126
49.1I3C introduction . . . . .2126
49.2I3C main features . . . . .2126
49.3I3C implementation . . . . .2128
49.3.1I3C instantiation . . . . .2128
49.3.2I3C wake-up from low-power mode(s) . . . . .2128
49.3.3I3C autonomous mode with DMA in Stop mode(s) . . . . .2128
49.3.4I3C FIFOs . . . . .2128
49.3.5I3C triggers . . . . .2129
49.3.6I3C interrupt(s) . . . . .2129
49.3.7I3C MIPI ® support . . . . .2130
49.4I3C block diagram . . . . .2131
49.5I3C pins and internal signals . . . . .2131
49.6I3C reset and clocks . . . . .2132
49.12.1Controller error management . . . . .2182
49.12.2Target error management . . . . .2184
49.13I3C wake-up from low-power mode(s) . . . . .2185
49.13.1Wake-up from Stop . . . . .2185
49.13.2I3C wake-up from Standby . . . . .2188
49.14I3C in low-power modes . . . . .2188
49.15I3C interrupts . . . . .2189
49.16I3C registers . . . . .2189
49.16.1I3C message control register (I3C_CR) . . . . .2189
49.16.2I3C message control register [alternate] (I3C_CR) . . . . .2191
49.16.3I3C configuration register (I3C_CFGGR) . . . . .2193
49.16.4I3C receive data byte register (I3C_RDR) . . . . .2198
49.16.5I3C receive data word register (I3C_RDWR) . . . . .2199
49.16.6I3C transmit data byte register (I3C_TDR) . . . . .2200
49.16.7I3C transmit data word register (I3C_TDWR) . . . . .2201
49.16.8I3C IBI payload data register (I3C_IBIDR) . . . . .2203
49.16.9I3C target transmit configuration register (I3C_TGTTDR) . . . . .2204
49.16.10I3C status register (I3C_SR) . . . . .2205
49.16.11I3C status error register (I3C_SER) . . . . .2206
49.16.12I3C received message register (I3C_RMR) . . . . .2208
49.16.13I3C event register (I3C_EVR) . . . . .2209
49.16.14I3C interrupt enable register (I3C_IER) . . . . .2213
49.16.15I3C clear event register (I3C_CEVR) . . . . .2215
49.16.16I3C masked interrupt status register (I3C_MISR) . . . . .2217
49.16.17I3C own device characteristics register (I3C_DEVR0) . . . . .2218
49.16.18I3C device x characteristics register (I3C_DEVRx) . . . . .2220
49.16.19I3C maximum read length register (I3C_MAXRLR) . . . . .2222
49.16.20I3C maximum write length register (I3C_MAXWLR) . . . . .2223
49.16.21I3C timing register 0 (I3C_TIMINGR0) . . . . .2224
49.16.22I3C timing register 1 (I3C_TIMINGR1) . . . . .2225
49.16.23I3C timing register 2 (I3C_TIMINGR2) . . . . .2227
49.16.24I3C bus characteristics register (I3C_BCR) . . . . .2228
49.16.25I3C device characteristics register (I3C_DCR) . . . . .2229
49.16.26I3C get capability register (I3C_GETCAPR) . . . . .2230
49.16.27I3C controller-role capability register (I3C_CRCAPR) . . . . .2231
49.16.28I3C get max data speed register (I3C_GETMXDSR) . . . . .2232
49.16.29I3C extended provisioned ID register (I3C_EPIDR) . . . . .2234
49.16.30 I3C register map .....2235
50 Improved inter-integrated circuit (I3C) .....2238
50.1 I3C introduction .....2238
50.2 I3C main features .....2238
50.3 I3C implementation .....2240
50.3.1 I3C instantiation .....2240
50.3.2 I3C wake-up from low-power mode(s) .....2240
50.3.3 I3C autonomous mode with DMA in Stop mode(s) .....2240
50.3.4 I3C FIFOs .....2241
50.3.5 I3C triggers .....2241
50.3.6 I3C interrupt(s) .....2242
50.3.7 I3C MIPI ® support .....2243
50.4 I3C block diagram .....2244
50.5 I3C pins and internal signals .....2244
50.6 I3C reset and clocks .....2245
50.6.1 I3C reset .....2245
50.6.2 I3C clocks and requirements .....2245
50.7 I3C peripheral state and programming .....2247
50.7.1 I3C peripheral state .....2247
50.7.2 I3C controller state and programming sequence .....2248
50.7.3 I3C target state and programming sequence .....2253
50.8 I3C registers and programming .....2260
50.8.1 I3C register set, as controller/target .....2260
50.8.2 I3C registers and fields use versus peripheral state, as controller ..2261
50.8.3 I3C registers and fields usage versus peripheral state, as target ..2263
50.9 I3C bus transfers and programming .....2265
50.9.1 I3C command set (CCC), as controller/target .....2265
50.9.2 I3C broadcast/direct CCC transfer (except ENTDAA, RSTACT),
as controller .....		2269
50.9.3 I3C broadcast ENTDAA CCC transfer, as controller .....2271
50.9.4 I3C broadcast/direct RSTACT CCC transfer, as controller .....2271
50.9.5 I3C broadcast/direct CCC transfer
(except ENTDAA, DEFTGTS, DEFGRPA), as target .....		2273
50.9.6 I3C broadcast ENTDAA CCC transfer, as target .....2275
50.9.7 I3C broadcast DEFTGTS CCC transfer, as target .....2276
50.9.8 I3C broadcast DEFGRPA CCC transfer, as target .....2277
50.9.9I3C direct GETSTATUS CCC response, as target . . . . .2278
50.9.10I3C private read/write transfer, as controller . . . . .2279
50.9.11I3C private read/write transfer, as target . . . . .2280
50.9.12Legacy I2C read/write transfer, as controller . . . . .2281
50.9.13Legacy I2C read/write transfer, as target . . . . .2282
50.9.14I3C IBI transfer, as controller/target . . . . .2282
50.9.15I3C hot-join request transfer, as controller/target . . . . .2284
50.9.16I3C controller-role request transfer, as controller/target . . . . .2285
50.10I3C FIFOs management, as controller . . . . .2286
50.10.1C-FIFO management, as controller . . . . .2286
50.10.2TX-FIFO management, as controller . . . . .2287
50.10.3RX-FIFO management, as controller . . . . .2290
50.10.4S-FIFO management, as controller . . . . .2292
50.11I3C FIFOs management, as target . . . . .2294
50.11.1RX-FIFO management, as target . . . . .2294
50.11.2TX-FIFO management, as target . . . . .2297
50.12I3C error management . . . . .2301
50.12.1Controller error management . . . . .2301
50.12.2Target error management . . . . .2303
50.13I3C wake-up from low-power mode(s) . . . . .2304
50.13.1Wake-up from Stop . . . . .2304
50.13.2I3C wake-up from Standby . . . . .2307
50.14I3C in low-power modes . . . . .2307
50.15I3C interrupts . . . . .2308
50.16I3C registers . . . . .2308
50.16.1I3C message control register (I3C_CR) . . . . .2308
50.16.2I3C message control register [alternate] (I3C_CR) . . . . .2310
50.16.3I3C configuration register (I3C_CFGGR) . . . . .2312
50.16.4I3C receive data byte register (I3C_RDR) . . . . .2317
50.16.5I3C receive data word register (I3C_RDWR) . . . . .2318
50.16.6I3C transmit data byte register (I3C_TDR) . . . . .2319
50.16.7I3C transmit data word register (I3C_TDWR) . . . . .2320
50.16.8I3C IBI payload data register (I3C_IBIDR) . . . . .2322
50.16.9I3C target transmit configuration register (I3C_TGTTDR) . . . . .2323
50.16.10I3C status register (I3C_SR) . . . . .2324
50.16.11I3C status error register (I3C_SER) . . . . .2325
50.16.12I3C received message register (I3C_RMR) . . . . .2327
50.16.13I3C event register (I3C_EVR) . . . . .2328
50.16.14I3C interrupt enable register (I3C_IER) . . . . .2332
50.16.15I3C clear event register (I3C_CEVR) . . . . .2334
50.16.16I3C masked interrupt status register (I3C_MISR) . . . . .2336
50.16.17I3C own device characteristics register (I3C_DEVR0) . . . . .2337
50.16.18I3C device x characteristics register (I3C_DEVRx) . . . . .2339
50.16.19I3C maximum read length register (I3C_MAXRLR) . . . . .2341
50.16.20I3C maximum write length register (I3C_MAXWLR) . . . . .2342
50.16.21I3C I2C target configuration register (I3C_I2CCFGR) . . . . .2343
50.16.22I3C timing register 0 (I3C_TIMINGR0) . . . . .2344
50.16.23I3C timing register 1 (I3C_TIMINGR1) . . . . .2345
50.16.24I3C timing register 2 (I3C_TIMINGR2) . . . . .2347
50.16.25I3C bus characteristics register (I3C_BCR) . . . . .2349
50.16.26I3C device characteristics register (I3C_DCR) . . . . .2350
50.16.27I3C get capability register (I3C_GETCAPR) . . . . .2351
50.16.28I3C controller-role capability register (I3C_CRCAPR) . . . . .2352
50.16.29I3C get max data speed register (I3C_GETMXDSR) . . . . .2353
50.16.30I3C extended provisioned ID register (I3C_EPIDR) . . . . .2355
50.16.31I3C register map . . . . .2356
51Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .2359
51.1USART introduction . . . . .2359
51.2USART main features . . . . .2359
51.3USART extended features . . . . .2360
51.4USART implementation . . . . .2360
51.5USART functional description . . . . .2362
51.5.1USART block diagram . . . . .2362
51.5.2USART pins and internal signals . . . . .2362
51.5.3USART clocks . . . . .2365
51.5.4USART character description . . . . .2365
51.5.5USART FIFOs and thresholds . . . . .2367
51.5.6USART transmitter . . . . .2367
51.5.7USART receiver . . . . .2370
51.5.8USART baud rate generation . . . . .2377
51.5.9Tolerance of the USART receiver to clock deviation . . . . .2379
51.5.10USART auto baud rate detection . . . . .2380
51.5.11USART multiprocessor communication . . . . .2382
51.5.12USART Modbus communication . . . . .2384
51.5.13USART parity control . . . . .2385
51.5.14USART LIN (local interconnection network) mode . . . . .2386
51.5.15USART synchronous mode . . . . .2388
51.5.16USART single-wire half-duplex communication . . . . .2392
51.5.17USART receiver timeout . . . . .2392
51.5.18USART smartcard mode . . . . .2393
51.5.19USART IrDA SIR ENDEC block . . . . .2397
51.5.20Continuous communication using USART and DMA . . . . .2400
51.5.21RS232 hardware flow control and RS485 driver enable . . . . .2402
51.5.22USART autonomous mode . . . . .2404
51.6USART in low-power modes . . . . .2406
51.7USART interrupts . . . . .2407
51.8USART registers . . . . .2409
51.8.1USART control register 1 (USART_CR1) . . . . .2409
51.8.2USART control register 1 [alternate] (USART_CR1) . . . . .2413
51.8.3USART control register 2 (USART_CR2) . . . . .2416
51.8.4USART control register 3 (USART_CR3) . . . . .2420
51.8.5USART control register 3 [alternate] (USART_CR3) . . . . .2424
51.8.6USART baud rate register (USART_BRR) . . . . .2427
51.8.7USART guard time and prescaler register (USART_GTPR) . . . . .2428
51.8.8USART receiver timeout register (USART_RTOR) . . . . .2429
51.8.9USART request register (USART_RQR) . . . . .2430
51.8.10USART interrupt and status register (USART_ISR) . . . . .2431
51.8.11USART interrupt and status register [alternate] (USART_ISR) . . . . .2437
51.8.12USART interrupt flag clear register (USART_ICR) . . . . .2442
51.8.13USART receive data register (USART_RDR) . . . . .2443
51.8.14USART transmit data register (USART_TDR) . . . . .2444
51.8.15USART prescaler register (USART_PRESC) . . . . .2444
51.8.16USART autonomous mode control register (USART_AUTOCR) . . . . .2445
51.8.17USART register map . . . . .2446
52Low-power universal asynchronous receiver
transmitter (LPUART) . . . . .		2448
52.1LPUART introduction . . . . .2448
52.2LPUART main features . . . . .2448
52.3LPUART implementation . . . . .2449
52.4LPUART functional description . . . . .2451
52.4.1LPUART block diagram . . . . .2451
52.4.2LPUART pins and internal signals . . . . .2452
52.4.3LPUART clocks . . . . .2454
52.4.4LPUART character description . . . . .2454
52.4.5LPUART FIFOs and thresholds . . . . .2456
52.4.6LPUART transmitter . . . . .2456
52.4.7LPUART receiver . . . . .2460
52.4.8LPUART baud rate generation . . . . .2464
52.4.9Tolerance of the LPUART receiver to clock deviation . . . . .2465
52.4.10LPUART multiprocessor communication . . . . .2466
52.4.11LPUART parity control . . . . .2468
52.4.12LPUART single-wire half-duplex communication . . . . .2469
52.4.13Continuous communication using DMA and LPUART . . . . .2469
52.4.14RS232 hardware flow control and RS485 driver enable . . . . .2472
52.4.15LPUART autonomous mode . . . . .2474
52.5LPUART in low-power modes . . . . .2476
52.6LPUART interrupts . . . . .2477
52.7LPUART registers . . . . .2478
52.7.1LPUART control register 1 (LPUART_CR1) . . . . .2478
52.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .2481
52.7.3LPUART control register 2 (LPUART_CR2) . . . . .2484
52.7.4LPUART control register 3 (LPUART_CR3) . . . . .2486
52.7.5LPUART control register 3 [alternate] (LPUART_CR3) . . . . .2488
52.7.6LPUART baud rate register (LPUART_BRR) . . . . .2490
52.7.7LPUART request register (LPUART_RQR) . . . . .2490
52.7.8LPUART interrupt and status register (LPUART_ISR) . . . . .2491
52.7.9LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .2496
52.7.10LPUART interrupt flag clear register (LPUART_ICR) . . . . .2499
52.7.11LPUART receive data register (LPUART_RDR) . . . . .2500
52.7.12LPUART transmit data register (LPUART_TDR) . . . . .2500
52.7.13LPUART prescaler register (LPUART_PRESC) . . . . .2501
52.7.14LPUART autonomous mode control register (LPUART_AUTOCR) . . . . .2502
52.7.15LPUART register map . . . . .2502
53Serial peripheral interface (SPI) . . . . .2505
53.1SPI introduction . . . . .2505
53.2SPI main features . . . . .2505
53.3SPI implementation . . . . .2506
53.4SPI functional description . . . . .2507
53.4.1SPI block diagram . . . . .2507
53.4.2SPI pins and internal signals . . . . .2508
53.4.3SPI communication general aspects . . . . .2510
53.4.4Communications between one master and one slave . . . . .2510
53.4.5Standard multislave communication . . . . .2513
53.4.6Multimaster communication . . . . .2514
53.4.7Slave select (NSS pin) management . . . . .2515
53.4.8Ready pin (RDY) management . . . . .2519
53.4.9Communication formats . . . . .2519
53.4.10Configuring the SPI . . . . .2521
53.4.11Enabling the SPI . . . . .2522
53.4.12SPI data transmission and reception procedures . . . . .2523
53.4.13Disabling the SPI . . . . .2527
53.4.14Communication using DMA (direct memory addressing) . . . . .2528
53.4.15Autonomous mode . . . . .2529
53.5SPI specific modes and control . . . . .2531
53.5.1TI mode . . . . .2531
53.5.2SPI error flags . . . . .2532
53.5.3CRC computation . . . . .2535
53.6SPI in low-power modes . . . . .2536
53.7SPI interrupts . . . . .2536
53.8SPI registers . . . . .2538
53.8.1SPI control register 1 (SPI_CR1) . . . . .2538
53.8.2SPI control register 2 (SPI_CR2) . . . . .2540
53.8.3SPI configuration register 1 (SPI_CFG1) . . . . .2540
53.8.4SPI configuration register 2 (SPI_CFG2) . . . . .2543
53.8.5SPI interrupt enable register (SPI_IER) . . . . .2545
53.8.6SPI status register (SPI_SR) . . . . .2546
53.8.7SPI interrupt/status flags clear register (SPI_IFCR) . . . . .2549
53.8.8SPI autonomous mode control register (SPI_AUTOCR) . . . . .2550
53.8.9SPI transmit data register (SPI_TXDR) . . . . .2550
53.8.10SPI receive data register (SPI_RXDR) . . . . .2551
53.8.11SPI polynomial register (SPI_CRCPOLY) . . . . .2551
53.8.12SPI transmitter CRC register (SPI_TXCRC) . . . . .2552
53.8.13SPI receiver CRC register (SPI_RXCRC) . . . . .2553
53.8.14SPI underrun data register (SPI_UDRDR) . . . . .2553
53.8.15SPI register map . . . . .2554
54Serial audio interface (SAI) . . . . .2555
54.1SAI introduction . . . . .2555
54.2SAI main features . . . . .2555
54.3SAI implementation . . . . .2556
54.4SAI functional description . . . . .2557
54.4.1SAI block diagram . . . . .2557
54.4.2SAI pins and internal signals . . . . .2558
54.4.3Main SAI modes . . . . .2559
54.4.4SAI synchronization mode . . . . .2560
54.4.5Audio data size . . . . .2560
54.4.6Frame synchronization . . . . .2560
54.4.7Slot configuration . . . . .2564
54.4.8SAI clock generator . . . . .2566
54.4.9Internal FIFOs . . . . .2569
54.4.10PDM interface . . . . .2571
54.4.11AC'97 link controller . . . . .2579
54.4.12SPDIF output . . . . .2580
54.4.13Specific features . . . . .2583
54.4.14Error flags . . . . .2587
54.4.15Disabling the SAI . . . . .2590
54.4.16SAI DMA interface . . . . .2590
54.5SAI interrupts . . . . .2591
54.6SAI registers . . . . .2593
54.6.1SAI configuration register 1 (SAI_ACR1) . . . . .2593
54.6.2SAI configuration register 2 (SAI_ACR2) . . . . .2595
54.6.3SAI frame configuration register (SAI_AFRCR) . . . . .2597
54.6.4SAI slot register (SAI_ASLOTR) . . . . .2598
54.6.5SAI interrupt mask register (SAI_AIM) . . . . .2599
54.6.6SAI status register (SAI_AS) . . . . .2601
54.6.7SAI clear flag register (SAI_ACLRFR) . . . . .2603
54.6.8SAI data register (SAI_ADR) . . . . .2604
54.6.9SAI configuration register 1 (SAI_BCR1) . . . . .2604
54.6.10SAI configuration register 2 (SAI_BCR2) . . . . .2607
54.6.11SAI frame configuration register (SAI_BFRCR) . . . . .2609
54.6.12SAI slot register (SAI_BSLOTR) . . . . .2610
54.6.13SAI interrupt mask register (SAI_BIM) . . . . .2611
54.6.14SAI status register (SAI_BSR) . . . . .2612
54.6.15SAI clear flag register (SAI_BCLRFR) . . . . .2614
54.6.16SAI data register (SAI_BDR) . . . . .2615
54.6.17SAI PDM control register (SAI_PDMCR) . . . . .2616
54.6.18SAI PDM delay register (SAI_PDMDLY) . . . . .2617
54.6.19SAI register map . . . . .2619
55FD controller area network (FDCAN) . . . . .2621
55.1FDCAN introduction . . . . .2621
55.2FDCAN main features . . . . .2623
55.3FDCAN implementation . . . . .2623
55.4FDCAN functional description . . . . .2624
55.4.1FDCAN block diagram . . . . .2624
55.4.2FDCAN pins and internal signals . . . . .2625
55.4.3Bit timing . . . . .2626
55.4.4Operating modes . . . . .2627
55.4.5Error management . . . . .2636
55.4.6Message RAM . . . . .2637
55.4.7FIFO acknowledge handling . . . . .2646
55.4.8FDCAN Rx FIFO element . . . . .2646
55.4.9FDCAN Tx buffer element . . . . .2648
55.4.10FDCAN Tx event FIFO element . . . . .2650
55.4.11FDCAN standard message ID filter element . . . . .2651
55.4.12FDCAN extended message ID filter element . . . . .2652
55.5FDCAN registers . . . . .2654
55.5.1FDCAN core release register (FDCAN_CREL) . . . . .2654
55.5.2FDCAN endian register (FDCAN_ENDN) . . . . .2654
55.5.3FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . . .2654
55.5.4FDCAN test register (FDCAN_TEST) . . . . .2655
55.5.5FDCAN RAM watchdog register (FDCAN_RWD) . . . . .2656
55.5.6FDCAN CC control register (FDCAN_CCCR) . . . . .2657
55.5.7FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . . . . .2658
55.5.8FDCAN timestamp counter configuration register (FDCAN_TSCC) . . . . .2660
55.5.9FDCAN timestamp counter value register (FDCAN_TSCV) . . . . .2660
55.5.10FDCAN timeout counter configuration register (FDCAN_TOCC) . . . . .2661
55.5.11FDCAN timeout counter value register (FDCAN_TOCV) . . . . .2662
55.5.12FDCAN error counter register (FDCAN_ECR) . . . . .2662
55.5.13FDCAN protocol status register (FDCAN_PSR) . . . . .2663
55.5.14FDCAN transmitter delay compensation register (FDCAN_TDCR) . . . . .2665
55.5.15FDCAN interrupt register (FDCAN_IR) . . . . .2665
55.5.16FDCAN interrupt enable register (FDCAN_IE) . . . . .2668
55.5.17FDCAN interrupt line select register (FDCAN_ILS) . . . . .2670
55.5.18FDCAN interrupt line enable register (FDCAN_ILE) . . . . .2671
55.5.19FDCAN global filter configuration register (FDCAN_RXGFC) . . . . .2671
55.5.20FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . .2673
55.5.21FDCAN high-priority message status register (FDCAN_HPMS) . . . . .2673
55.5.22FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . .2674
55.5.23CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . .2675
55.5.24FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . .2675
55.5.25FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . .2676
55.5.26FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . .2676
55.5.27FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . .2677
55.5.28FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . .2677
55.5.29FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . .2678
55.5.30FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . . . . .2679
55.5.31FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) . . . . .2679
55.5.32FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . . . . .2680
55.5.33FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . .		2680
55.5.34FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_TXBCIE) . . . . .		2681
55.5.35FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . .2681
55.5.36FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . . . .2682
55.5.37FDCAN CFG clock divider register (FDCAN_CKDIV) . . . . .2682
55.5.38FDCAN register map . . . . .2683
56Universal serial bus full-speed host/device interface (USB) . . . . .2687
56.1USB introduction . . . . .2687
56.2USB main features . . . . .2687
56.3USB implementation . . . . .2687
56.4USB functional description . . . . .2688
56.4.1USB block diagram . . . . .2688
56.4.2USB pins and internal signals . . . . .2688
56.4.3USB reset and clocks . . . . .2689
56.4.4General description and Device mode functionality . . . . .2689
56.4.5Description of USB blocks used in both Device and Host modes . . . . .2690
56.4.6Description of host frame scheduler (HFS) specific to Host mode . . . . .2691
56.5Programming considerations for Device and Host modes . . . . .2692
56.5.1Generic USB Device programming . . . . .2692
56.5.2System and power-on reset . . . . .2692
56.5.3Double-buffered endpoints and usage in Device mode . . . . .2699
56.5.4Double buffered channels: usage in Host mode . . . . .2701
56.5.5Isochronous transfers in Device mode . . . . .2702
56.5.6Isochronous transfers in Host mode . . . . .2703
56.5.7Suspend/resume events . . . . .2704
56.6USB registers . . . . .2707
56.6.1USB control register (USB_CNTR) . . . . .2708
56.6.2USB interrupt status register (USB_ISTR) . . . . .2711
56.6.3USB frame number register (USB_FNR) . . . . .2715
56.6.4USB Device address (USB_DADDR) . . . . .2715
56.6.5USB LPM control and status register (USB_LPMCSR) . . . . .2716
56.6.6USB battery charging detector (USB_BCDR) . . . . .2717
56.6.7USB endpoint/channel n register (USB_CHEPnR) . . . . .2718
56.7USB SRAM registers . . . . .2727
56.7.1Channel/endpoint transmit buffer descriptor n
(USB_CHEP_TXRXBD_n) . . . . .		2728
56.7.2Channel/endpoint receive buffer descriptor n [alternate]
(USB_CHEP_TXRXBD_n) . . . . .		2728
56.7.3Channel/endpoint receive buffer descriptor n
(USB_CHEP_RXTXBD_n) . . . . .		2730
56.7.4Channel/endpoint transmit buffer descriptor n [alternate]
(USB_CHEP_RXTXBD_n) . . . . .		2731
56.7.5USB SRAM register map . . . . .2732
57Debug support (DBG) . . . . .2733
57.1Introduction . . . . .2733
57.2DBG functional description . . . . .2734
57.2.1DBG block diagram . . . . .2734
57.2.2DBG pins and internal signals . . . . .2734
57.2.3DBG reset and clocks . . . . .2735
57.2.4DBG power domains . . . . .2735
57.2.5Debug and low-power modes . . . . .2735
57.2.6Security . . . . .2736
57.3Serial-wire and JTAG debug port (SWJ-DP) . . . . .2737
57.3.1JTAG debug port . . . . .2738
57.3.2Serial-wire debug port . . . . .2740
57.3.3Debug port registers . . . . .2741
57.3.4Debug port register map . . . . .2747
57.4Access ports . . . . .2748
57.4.1Access port registers . . . . .2748
57.4.2Access port register map . . . . .2753
57.5ROM tables . . . . .2753
57.5.1MCU ROM table registers . . . . .2756
57.5.2MCU ROM table register map . . . . .2759
57.5.3Processor ROM table registers . . . . .2760
57.5.4Processor ROM table register map . . . . .2764
57.6Data watchpoint and trace unit (DWT) . . . . .2766
57.6.1DWT registers . . . . .2766
57.6.2DWT register map . . . . .2778
57.7Instrumentation trace macrocell (ITM) . . . . .2781
57.7.1ITM registers . . . . .2781
57.7.2ITM register map . . . . .2788
57.8Breakpoint unit (BPU) . . . . .2789
57.8.1BPU registers . . . . .2789
57.8.2BPU register map . . . . .2794
57.9Embedded Trace Macrocell (ETM) . . . . .2796
57.9.1ETM registers . . . . .2796
57.9.2ETM register map . . . . .2818
57.10Trace port interface unit (TPIU) . . . . .2822
57.10.1TPIU registers . . . . .2822
57.10.2TPIU register map . . . . .2831
57.11Cross-trigger interface (CTI) . . . . .2833

List of tables

Table 1.Example of memory map security attribution versus SAU configuration regions . . . . .103
Table 2.Securable peripherals by TZSC . . . . .104
Table 3.TrustZone aware peripherals . . . . .106
Table 4.Memory map and peripheral register boundary addresses . . . . .112
Table 5.SRAM sizes . . . . .116
Table 6.Configuring security attributes with IDAU and SAU . . . . .123
Table 7.DMA channel use (security) . . . . .128
Table 8.Secure alternate function between peripherals and allocated I/Os . . . . .131
Table 9.Nonsecure peripherals not connectable to secure I/Os . . . . .131
Table 10.Nonsecure peripherals connectable to secure I/Os . . . . .132
Table 11.TrustZone-aware DBGMCU access management . . . . .133
Table 12.DMA channel use (privilege). . . . .137
Table 13.Accelerated-cryptographic operations . . . . .143
Table 14.Main product life-cycle transitions. . . . .145
Table 15.Typical product life-cycle phases . . . . .146
Table 16.OEM1/2 RDP unlocking methods . . . . .148
Table 17.Debug protection with RDP . . . . .149
Table 18.Software intellectual property protection with RDP. . . . .150
Table 19.Boot modes when TrustZone is disabled (TZEN = 0). . . . .152
Table 20.Boot modes when TrustZone is enabled (TZEN = 1) . . . . .153
Table 21.Boot space versus RDP protection. . . . .153
Table 22.GTZC features . . . . .157
Table 23.GTZC1 subblocks address offset for STM32U356/366
and STM32U375/385 . . . . .		158
Table 24.GTZC1 subblocks address offset for STM32U3B5/3C5. . . . .158
Table 25.MPCBB resource assignment for STM32U356/366 . . . . .158
Table 26.MPCBB resource assignment for STM32U375/385 . . . . .158
Table 27.MPCBB resource assignment for STM32U3B5/3C5 . . . . .159
Table 28.GTZC interrupt request. . . . .162
Table 29.GTZC1 TZSC register map and reset values . . . . .176
Table 30.GTZC1 TZIC register map and reset values. . . . .200
Table 31.GTZC1 MPCBB1 register map and reset values . . . . .204
Table 32.GTZC1 MPCBB2 register map and reset values . . . . .207
Table 33.GTZC1 MPCBB3 register map and reset values . . . . .210
Table 34.GTZC1 MPCBB4 register map and reset values . . . . .213
Table 35.SRAM structure . . . . .214
Table 36.Internal SRAM features . . . . .215
Table 37.Effect of low-power modes on RAMCFG . . . . .216
Table 38.RAMCFG interrupt requests . . . . .216
Table 39.RAMCFG register map and reset values . . . . .221
Table 40.Flash module 512-Kbyte dual-bank organization for STM32U356/366 . . . . .224
Table 41.Flash module 1-Mbyte dual-bank organization for STM32U375/385 . . . . .225
Table 42.Flash module 2-Mbyte dual-bank organization for STM32U3B5/3C5. . . . .226
Table 43.Number of wait states according to CPU clock (HCLK) frequency (LPM = 0) . . . . .227
Table 44.Number of wait states according to CPU clock (HCLK) frequency (LPM = 1) . . . . .227
Table 45.Flash operation interrupted by a system reset . . . . .237
Table 46.User option-byte organization mapping . . . . .238
Table 47.Default secure option bytes after TZEN activation . . . . .241
Table 48.Secure watermark-based area . . . . .242
Table 49.Secure hide protection . . . . .243
Table 50.Secure and HDP protections . . . . .244
Table 51.Write access register to HDPx_EXT and HDPxEXT_ACCDIS . . . . .245
Table 52.HDP extension protections . . . . .245
Table 53.Flash security state . . . . .247
Table 54.WRP protection . . . . .251
Table 55.Flash memory readout protection status (TZEN = 0) . . . . .252
Table 56.Access status versus protection level and execution mode when TZEN = 0 . . . . .253
Table 57.Flash memory readout protection status (TZEN = 1) . . . . .253
Table 58.Access status versus protection level and execution modes
when TZEN = 1 . . . . .		255
Table 59.Macros for RSS services . . . . .260
Table 60.RSS lib interface functions . . . . .261
Table 61.Flash memory access versus RDP level when TrustZone is active (TZEN = 1) . . . . .262
Table 62.Flash memory access versus HDPx and HDPx extended (x = 1 or 2) . . . . .262
Table 63.Flash memory access versus RDP level when TrustZone is disabled (TZEN = 0) . . . . .263
Table 64.Flash memory mass erase versus RDP level when TrustZone is active (TZEN = 1) . . . . .263
Table 65.Flash system memory, OTP and RSS accesses (valid for all RDP levels) . . . . .264
Table 66.FLASH registers access . . . . .264
Table 67.FLASH page access versus privilege mode . . . . .264
Table 68.FLASH mass erase versus privilege mode . . . . .265
Table 69.FLASH_SECBByRx registers access when TrustZone is active (TZEN = 1) . . . . .265
Table 70.FLASH_PRIVBByRx registers access when TrustZone is active (TZEN = 1) . . . . .265
Table 71.FLASH_PRIVBByRx registers access when TrustZone is disabled (TZEN = 0) . . . . .265
Table 72.Flash interrupt requests . . . . .266
Table 73.FLASH register map and reset values . . . . .305
Table 74.ICACHE features . . . . .310
Table 75.TAG memory dimensioning parameters
for n-way set associative operating mode (default) . . . . .		312
Table 76.TAG memory dimensioning parameters for direct-mapped cache mode . . . . .313
Table 77.ICACHE cacheability for AHB transaction . . . . .315
Table 78.Memory configurations . . . . .315
Table 79.ICACHE remap region size, base address, and remap address . . . . .316
Table 80.ICACHE interrupts . . . . .320
Table 81.ICACHE register map and reset values . . . . .324
Table 82.PWR input/output pins . . . . .326
Table 83.PWR internal input/output signals . . . . .327
Table 84.PWR wake-up source selection . . . . .327
Table 85.PVM features . . . . .336
Table 86.Low-power mode summary . . . . .340
Table 87.Functionalities depending on the working mode . . . . .341
Table 88.Sleep mode . . . . .346
Table 89.Stop 0 mode . . . . .348
Table 90.Stop 1 mode . . . . .349
Table 91.Stop 2 mode . . . . .351
Table 92.Stop 3 mode . . . . .354
Table 93.Standby mode . . . . .357
Table 94.Shutdown mode . . . . .359
Table 95.Power modes output states versus MCU power modes . . . . .360
Table 96.PWR Security configuration summary . . . . .361
Table 97.PWR interrupt requests . . . . .362
Table 98.PWR register map and reset values . . . . .391
Table 99.RCC input/output signals connected to package pins or balls . . . . .394
Table 100.HSE/LSE clock sources . . . . .399
Table 101.MSIS and MSIK ranges per internal MSIRCs (PLL mode disabled). . . . .401
Table 102.MSIS and MSIK frequencies of MSIRC1 in PLL mode. . . . .403
Table 103.Bus maximum frequency . . . . .406
Table 104.Clock source maximum frequency . . . . .406
Table 105.RCC security configuration summary . . . . .412
Table 106.Interrupt sources and control . . . . .415
Table 107.RCC register map and reset values . . . . .478
Table 108.CRS features . . . . .484
Table 109.CRS internal input/output signals . . . . .485
Table 110.CRS interconnection . . . . .486
Table 111.Effect of low-power modes on CRS . . . . .489
Table 112.Interrupt control bits . . . . .489
Table 113.CRS register map and reset values . . . . .494
Table 114.Port bit configuration. . . . .497
Table 115.GPIO secured bits . . . . .505
Table 116.Effect of low-power modes on the GPIO . . . . .506
Table 117.GPIO register map and reset values . . . . .516
Table 118.TrustZone security and privilege register accesses . . . . .520
Table 119.BOOSTEN and ANASWVDD set/reset. . . . .521
Table 120.SYSCFG register map and reset values. . . . .531
Table 121.Peripheral interconnect matrix . . . . .533
Table 122.GPDMA1 channel implementation . . . . .550
Table 123.GPDMA1 wake-up in low-power modes . . . . .550
Table 124.Programmed GPDMA1 request . . . . .550
Table 125.Programmed GPDMA1 request as a block request . . . . .554
Table 126.GPDMA1 channel with peripheral early termination . . . . .554
Table 127.Programmed GPDMA1 request with peripheral early termination . . . . .554
Table 128.Programmed GPDMA1 trigger . . . . .555
Table 129.Programmed GPDMA source/destination burst . . . . .576
Table 130.Programmed data handling . . . . .581
Table 131.Effect of low-power modes on GPDMA . . . . .594
Table 132.GPDMA interrupt requests . . . . .595
Table 133.GPDMA register map and reset values . . . . .623
Table 134.STM32U3 series vector table . . . . .627
Table 135.EXTI signals . . . . .634
Table 136.EVG signals . . . . .634
Table 137.EXTI line connections . . . . .635
Table 138.Masking functionality . . . . .637
Table 139.Register protection overview . . . . .638
Table 140.EXTI register map and reset values . . . . .647
Table 141.CRC internal input/output signals . . . . .650
Table 142.CRC register map and reset values . . . . .655
Table 143.HSP features . . . . .659
Table 144.HSP memory mapping . . . . .659
Table 145.HSP external pins . . . . .660
Table 146.HSP internal signals . . . . .660
Table 147.HSP trigger input connections . . . . .661
Table 148.HSP trigger output connections for STM32U3B5/3C5 . . . . .662
Table 149.HSP break connections . . . . .662
Table 150.Memory mapping seen from MMC AHB slave . . . . .665
Table 151.BSTAT possible values. . . . .671
Table 152.BUFFCMB programming examples . . . . .678
Table 153.Trigger sources versus priority and task number . . . . .690
Table 154.Trigger sources versus priority and task number . . . . .691
Table 155.Firmware error number . . . . .698
Table 156.HSP interrupt requests . . . . .702
Table 157.List of trigger sources . . . . .707
Table 158.Snoop signal selection . . . . .716
Table 159.Flags and signal sources for break function . . . . .717
Table 160.Flags and signal sources for break input and debug functions. . . . .718
Table 161.List of locked fields . . . . .721
Table 162.Processing list mapping . . . . .724
Table 163.List of processing functions . . . . .731
Table 164.HSP register map and reset values . . . . .788
Table 165.OCTOSPI implementation . . . . .795
Table 166.OCTOSPI input/output pins . . . . .797
Table 167.OCTOSPI internal signals. . . . .797
Table 168.Command/address phase description . . . . .806
Table 169.OctaRAM command address bit assignment
(based on 64-Mbyte OctaRAM) . . . . .		817
Table 170.Address alignment cases . . . . .823
Table 171.OCTOSPI interrupt requests. . . . .825
Table 172.OCTOSPI register map and reset values . . . . .848
Table 173.SDMMC features . . . . .852
Table 174.SDMMC operation modes SD and SDIO . . . . .855
Table 175.SDMMC operation modes e•MMC . . . . .855
Table 176.SDMMC internal input/output signals . . . . .856
Table 177.SDMMC pins. . . . .857
Table 178.SDMMC Command and data phase selection . . . . .858
Table 179.Command token format . . . . .864
Table 180.Short response with CRC token format . . . . .865
Table 181.Short response without CRC token format . . . . .865
Table 182.Long response with CRC token format. . . . .865
Table 183.Specific Commands overview. . . . .866
Table 184.Command path status flags . . . . .867
Table 185.Command path error handling . . . . .867
Table 186.Data token format . . . . .875
Table 187.Data path status flags and clear bits. . . . .875
Table 188.Data path error handling. . . . .877
Table 189.Data FIFO access. . . . .878
Table 190.Transmit FIFO status flags . . . . .879
Table 191.Receive FIFO status flags . . . . .880
Table 192.AHB and SDMMC_CK clock frequency relation. . . . .885
Table 193.SDIO special operation control. . . . .885
Table 194.4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . .889
Table 195.CMD12 use cases . . . . .894
Table 196.SDMMC interrupts . . . . .908
Table 197.Response type and SDMMC_RESPxR registers . . . . .915
Table 198.SDMMC register map . . . . .931
Table 199.STM32U3 series features . . . . .934
Table 200.DLYB internal input/output signals . . . . .935
Table 201.Delay block control . . . . .936
Table 202.DLYB register map and reset values . . . . .939
Table 203.ADC features . . . . .942
Table 204.ADC input/output pins . . . . .944
Table 205.ADC internal input/output signals . . . . .944
Table 206.ADC1/2 interconnection . . . . .944
Table 207.Configuring the trigger polarity for regular external triggers . . . . .963
Table 208.Configuring the trigger polarity for injected external triggers . . . . .963
Table 209.TSAR timings depending on resolution . . . . .974
Table 210.Offset computation versus data resolution . . . . .978
Table 211.12-bit data formats . . . . .980
Table 212.Numerical examples for 32-bit or 16-bit format (POSSPFF = 0) . . . . .981
Table 213.Analog window watchdog features . . . . .989
Table 214.Analog watchdog 1 channel selection . . . . .990
Table 215.Analog watchdog 1, 2, 3 comparison . . . . .991
Table 216.Maximum output results versus N and M . . . . .996
Table 217.Oversampler operating mode summary . . . . .1000
Table 218.DELAY bits versus ADC resolution. . . . .1006
Table 219.Effect of low-power modes on the ADC . . . . .1021
Table 220.ADC interrupts . . . . .1022
Table 221.ADC register map and reset values for each ADC . . . . .1056
Table 222.ADC register map and reset values (master and slave ADC common registers) . . . . .1059
Table 223.DAC features . . . . .1062
Table 224.DAC input/output pins . . . . .1064
Table 225.DAC internal input/output signals . . . . .1064
Table 226.DAC interconnection . . . . .1065
Table 227.Data format (case of 12-bit data) . . . . .1067
Table 228.HFSEL description . . . . .1068
Table 229.Sample and refresh timings . . . . .1073
Table 230.Channel output modes summary . . . . .1075
Table 231.Effect of low-power modes on DAC . . . . .1082
Table 232.DAC interrupts . . . . .1082
Table 233.DAC register map and reset values . . . . .1099
Table 234.VREFBUF typical values . . . . .1102
Table 235.VREF buffer modes . . . . .1103
Table 236.VREFBUF register map and reset values . . . . .1105
Table 237.COMP1 noninverting input assignment . . . . .1107
Table 238.COMP1 inverting input assignment . . . . .1108
Table 239.COMP2 noninverting input assignment . . . . .1108
Table 240.COMP2 inverting input assignment . . . . .1108
Table 241.COMP1 output-blanking PWM assignment . . . . .1108
Table 242.COMP2 output-blanking PWM assignment . . . . .1109
Table 243.Comparator behavior in the low-power modes . . . . .1112
Table 244.Interrupt control bits . . . . .1113
Table 245.COMP register map and reset values . . . . .1116
Table 246.Operational amplifier possible connections . . . . .1118
Table 247.Operating modes and calibration . . . . .1123
Table 248.Effect of low-power modes on the OPAMP . . . . .1124
Table 249.OPAMP register map and reset values . . . . .1129
Table 250.ADF features . . . . .1131
Table 251.ADF external pins . . . . .1132
Table 252.ADF internal signals . . . . .1132
Table 253.ADF trigger connections . . . . .1133
Table 254.MDF ADC data connections . . . . .1133
Table 255.Control of the common clock generation . . . . .1140
Table 256.Clock constraints with respect to the incoming stream. . . . .1141
Table 257.Data size according to CIC order and CIC decimation values . . . . .1146
Table 258.Possible gain values . . . . .1147
Table 259.Recommended maximum gain values
versus CIC decimation ratios . . . . .		1149
Table 260.Most common microphone settings . . . . .1149
Table 261.HPF 3 dB cut-off frequency examples . . . . .1151
Table 262.ANSLP values versus FRSIZE and sampling rates . . . . .1164
Table 263.Threshold values according SNTHR . . . . .1165
Table 264.Register protection summary . . . . .1171
Table 265.Effect of low-power modes on ADF . . . . .1172
Table 266.ADF interrupt requests . . . . .1173
Table 267.Examples of ADF settings for microphone capture . . . . .1174
Table 268.Programming sequence (CIC4) . . . . .1175
Table 269.Programming sequence (CIC5) . . . . .1176
Table 270.Output signal levels . . . . .1181
Table 271.ADF register map and reset values . . . . .1202
Table 272.Example of frame rate calculation . . . . .1208
Table 273.Blink frequency . . . . .1216
Table 274.Remapping capability . . . . .1220
Table 275.LCD behavior in low-power modes. . . . .1226
Table 276.LCD interrupt requests . . . . .1226
Table 277.LCD register map and reset values . . . . .1233
Table 278.TSC implementation . . . . .1237
Table 279.Acquisition sequence summary . . . . .1239
Table 280.Spread spectrum deviation versus AHB clock frequency. . . . .1242
Table 281.I/O state depending on its mode and IODEF bit value . . . . .1243
Table 282.Effect of low-power modes on TSC . . . . .1244
Table 283.Interrupt control bits . . . . .1247
Table 284.TSC register map and reset values . . . . .1254
Table 285.Peripherals connected by CCB interconnect . . . . .1257
Table 286.CCB internal input/output signals . . . . .1258
Table 287.Blob creation steps for ECDSA signature (CCOP = 0b110000 i >0) . . . . .1265
Table 288.Blob use steps for ECDSA signature (CCOP = 0b11000011) . . . . .1268
Table 289.Blob use steps for signing public key computation (CCOP = 0b10000001) . . . . .1270
Table 290.Blob creation steps for scalar multiplication (CCOP = 0b100000 i >0) . . . . .1272
Table 291.Blob use steps for scalar multiplication (CCOP = 0b10000001) . . . . .1273
Table 292.Blob creation steps for modular exponentiation (CCOP = 0b01000100) . . . . .1274
Table 293.Blob use steps for modular exponentiation (CCOP = 0b01000101) . . . . .1275
Table 294.CCB register map and reset values . . . . .1281
Table 295.RNG internal input/output signals . . . . .1283
Table 296.RNG interrupt requests. . . . .1292
Table 297.RNG configurations . . . . .1293
Table 298.Additional health test configurations. . . . .1293
Table 299.Configuration selection . . . . .1293
Table 300.RNG register map and reset map. . . . .1301
Table 301.AES versus SAES features . . . . .1303
Table 302.AES internal input/output signals . . . . .1304
Table 303.AES approved symmetric key functions . . . . .1305
Table 304.Counter mode initialization vector definition . . . . .1314
Table 305.Initialization of IV registers in GCM mode. . . . .1317
Table 306.GCM last block definition . . . . .1317
Table 307.Initialization of IV registers in CCM mode. . . . .1324
Table 308.AES data swapping example . . . . .1327
Table 309.Key endianness in AES_KEYRx registers (128/256-bit keys) . . . . .1329
Table 310.IVI bitfield spread over AES_IVRx registers . . . . .1330
Table 311.AES interrupt requests . . . . .1331
Table 312.Processing latency for ECB, CBC and CTR. . . . .1332
Table 313.Processing latency for GCM and CCM (in clock cycles). . . . .1333
Table 314.AES register map and reset values . . . . .1345
Table 315.AES versus SAES features . . . . .1349
Table 316.SAES internal input/output signals . . . . .1350
Table 317.SAES approved symmetric key functions. . . . .1351
Table 318.Counter mode initialization vector definition . . . . .1361
Table 319.Initialization of IV registers in GCM mode. . . . .1364
Table 320.GCM last block definition . . . . .1364
Table 321.Initialization of IV registers in CCM mode. . . . .1370
Table 322.AES data swapping example . . . . .1379
Table 323.Key endianness in SAES_KEYRx registers (128/256-bit keys) . . . . .1381
Table 324.IVI bitfield spread over SAES_IVRx registers. . . . .1383
Table 325.SAES interrupt requests . . . . .1385
Table 326.Processing latency for ECB, CBC and CTR. . . . .1386
Table 327.Processing latency for GCM and CCM (in SAES kernel clock cycles) . . . . .1386
Table 328.SAES register map and reset values . . . . .1401
Table 329.HASH internal input/output signals. . . . .1404
Table 330.Information on supported hash algorithms . . . . .1405
Table 331.Hash processor outputs . . . . .1408
Table 332.Processing time (in clock cycle) . . . . .1414
Table 333.HASH interrupt requests. . . . .1415
Table 334.HASH1 register map and reset values . . . . .1423
Table 335.Internal input/output signals . . . . .1426
Table 336.PKA integer arithmetic functions list . . . . .1427
Table 337.PKA prime field (Fp) elliptic curve functions list . . . . .1428
Table 338.Chaining mode to/from PKA . . . . .1433
Table 339.Integrity protected parameters list . . . . .1435
Table 340.Confidentiality protected parameter list . . . . .1435
Table 341.Example of 'a' curve coefficient for ECC Fp scalar. . . . .1437
Table 342.Montgomery parameter computation . . . . .1438
Table 343.Modular addition . . . . .1438
Table 344.Modular subtraction . . . . .1439
Table 345.Montgomery multiplication . . . . .1440
Table 346.Modular exponentiation (normal mode) . . . . .1441
Table 347.Modular exponentiation (fast mode) . . . . .1441
Table 348.Modular exponentiation (protected mode) . . . . .1442
Table 349.Modular inversion . . . . .1442
Table 350.Modular reduction . . . . .1443
Table 351.Arithmetic addition . . . . .1443
Table 352.Arithmetic subtraction . . . . .1443
Table 353.Arithmetic multiplication . . . . .1444
Table 354.Arithmetic comparison . . . . .1444
Table 355.CRT exponentiation . . . . .1445
Table 356.Point on elliptic curve Fp check . . . . .1446
Table 357.ECC Fp scalar multiplication. . . . .1446
Table 358.ECDSA sign - Inputs . . . . .1448
Table 359.ECDSA sign - Outputs . . . . .1448
Table 360.Extended ECDSA sign - additional outputs . . . . .1449
Table 361.ECDSA verification - inputs . . . . .1449
Table 362.ECDSA verification - outputs . . . . .1450
Table 363.ECC complete addition . . . . .1450
Table 364.ECC double base ladder. . . . .1451
Table 365.ECC projective to affine . . . . .1452
Table 366.Family of supported curves for ECC operations . . . . .1453
Table 367.Modular exponentiation . . . . .1454
Table 368.ECC scalar multiplication . . . . .1454
Table 369.ECDSA signature average computation time . . . . .1455
Table 370.ECDSA verification average computation times . . . . .1455
Table 371.ECC double base ladder average computation times . . . . .1455
Table 372.ECC projective to affine average computation times . . . . .1455
Table 373.ECC complete addition average computation times . . . . .1455
Table 374.Point on elliptic curve Fp check average computation times . . . . .1455
Table 375.Montgomery parameters average computation times. . . . .1456
Table 376.PKA interrupt requests . . . . .1456
Table 377.PKA register map and reset values . . . . .1463
Table 378.TIM input/output pins . . . . .1467
Table 379.TIM internal input/output signals . . . . .1467
Table 380.Interconnect to the tim_ti1 input multiplexer . . . . .1468
Table 381.Interconnect to the tim_ti2 input multiplexer . . . . .1469
Table 382.Interconnect to the tim_ti3 input multiplexer . . . . .1469
Table 383.Interconnect to the tim_ti4 input multiplexer . . . . .1469
Table 384.Internal trigger connection . . . . .1469
Table 385.Interconnect to the tim_etr input multiplexer. . . . .1470
Table 386.Timer break interconnect . . . . .1470
Table 387.Timer break2 interconnect . . . . .1470
Table 388.System break interconnect . . . . .1471
Table 389.Interconnect to the ocref_clr input multiplexer . . . . .1471
Table 390.CCR and ARR register change dithering pattern . . . . .1504
Table 391.CCR register change dithering pattern in center-aligned PWM mode . . . . .1505
Table 392.Behavior of timer outputs versus tim_brk/tim_brk2 inputs . . . . .1517
Table 393.Break protection disarming conditions . . . . .1519
Table 394.Counting direction versus encoder signals (CC1P = CC2P = 0) . . . . .1528
Table 395.Counting direction versus encoder signals and polarity settings . . . . .1532
Table 396.DMA request. . . . .1554
Table 397.Effect of low-power modes on TIM1/TIM8 . . . . .1555
Table 398.Interrupt requests . . . . .1555
Table 399.Output control bits for complementary tim_ocx and tim_ocxn channels
with break feature . . . . .		1582
Table 400.TIMx register map and reset values . . . . .1605
Table 401.STM32U3 series general purpose timers . . . . .1609
Table 402.TIM input/output pins . . . . .1611
Table 403.TIM internal input/output signals . . . . .1611
Table 404.Interconnect to the tim_ti1 input multiplexer . . . . .1612
Table 405.Interconnect to the tim_ti2 input multiplexer . . . . .1612
Table 406.Interconnect to the tim_ti3 input multiplexer . . . . .1612
Table 407.Interconnect to the tim_ti4 input multiplexer . . . . .1613
Table 408.TIMx internal trigger connection . . . . .1613
Table 409.Interconnect to the tim_etr input multiplexer . . . . .1613
Table 410.Interconnect to the tim_ocref_clr input multiplexer . . . . .1614
Table 411.CCR and ARR register change dithering pattern . . . . .1645
Table 412.CCR register change dithering pattern in center-aligned PWM mode . . . . .1646
Table 413.Counting direction versus encoder signals(CC1P = CC2P = 0) . . . . .1655
Table 414.Counting direction versus encoder signals and polarity settings . . . . .1660
Table 415.DMA request . . . . .1685
Table 416.Effect of low-power modes on TIM2/TIM3/TIM4 . . . . .1685
Table 417.Interrupt requests . . . . .1686
Table 418.Output control bit for standard tim_ocx channels . . . . .1707
Table 419.TIM2/TIM3/TIM4 register map and reset values . . . . .1719
Table 420.TIM internal input/output signals . . . . .1723
Table 421.TIMx_ARR register change dithering pattern . . . . .1733
Table 422.DMA request . . . . .1735
Table 423.Effect of low-power modes on TIM6/TIM7 . . . . .1735
Table 424.Interrupt request . . . . .1735
Table 425.TIMx register map and reset values . . . . .1742
Table 426.TIM input/output pins . . . . .1744
Table 427.TIM internal input/output signals . . . . .1745
Table 428.Interconnect to the tim_ti1 input multiplexer . . . . .1745
Table 429.Interconnect to the tim_ti2 input multiplexer . . . . .1745
Table 430.TIMx internal trigger connection . . . . .1746
Table 431.CCR and ARR register change dithering pattern . . . . .1763
Table 432.Effect of low-power modes on TIM12 . . . . .1772
Table 433.Interrupt requests . . . . .1772
Table 434.Output control bit for standard tim_ocx channels . . . . .1784
Table 435.TIM12 register map and reset values . . . . .1788
Table 436.TIM input/output pins . . . . .1793
Table 437.TIM internal input/output signals . . . . .1794
Table 438.Interconnect to the tim_ti1 input multiplexer . . . . .1794
Table 439.Interconnect to the tim_ti2 input multiplexer . . . . .1795
Table 440.TIMx internal trigger connection . . . . .1795
Table 441.Timer break interconnect . . . . .1796
Table 442.System break interconnect . . . . .1796
Table 443.Interconnect to the ocref_clr input multiplexer . . . . .1796
Table 444.CCR and ARR register change dithering pattern . . . . .1816
Table 445.Break protection disarming conditions . . . . .1825
Table 446.DMA request . . . . .1838
Table 447.Effect of low-power modes on TIM15/TIM16/TIM17 . . . . .1838
Table 448.Interrupt requests . . . . .1839
Table 449.Output control bits for complementary tim_ocx and tim_ocxn channels with break feature (TIM15) . . . . .1854
Table 450.TIM15 register map and reset values . . . . .1867
Table 451.Output control bits for complementary tim_oc1 and tim_oc1n channels with break feature (TIM16/TIM17) . . . . .1880
Table 452.TIM16/TIM17 register map and reset values . . . . .1894
Table 453.STM32U3 series LPTIM features . . . . .1897
Table 454.LPTIM1/2/3 input/output pins . . . . .1899
Table 455.LPTIM4 input/output pins . . . . .1899
Table 456.LPTIM1/2/3 internal signals . . . . .1900
Table 457.LPTIM4 internal signals . . . . .1900
Table 458.LPTIM1/2/3/4 external trigger connections . . . . .1901
Table 459.LPTIM1/2/3/4 input 1 connections . . . . .1901
Table 460.LPTIM1/2 input 2 connections . . . . .1901
Table 461.LPTIM1 input capture 1 connections . . . . .1901
Table 462.LPTIM2/3 input capture 1 connections . . . . .1902
Table 463.LPTIM1 input capture 2 connections . . . . .1902
Table 464.LPTIM2 input capture 2 connections . . . . .1902
Table 465.LPTIM3 input capture 2 connections . . . . .1902
Table 466.Prescaler division ratios . . . . .1904
Table 467.Encoder counting scenarios . . . . .1911
Table 468.Input capture Glitch filter latency (in counter step unit). . . . .1915
Table 469.Effect of low-power modes on the LPTIM . . . . .1920
Table 470.Interrupt events . . . . .1921
Table 471.LPTIM register map and reset values . . . . .1945
Table 472.STM32U3 series IWDG features . . . . .1950
Table 473.IWDG delays versus actions . . . . .1951
Table 474.IWDG internal input/output signals . . . . .1951
Table 475.Effect of low power modes on IWDG . . . . .1956
Table 476.IWDG interrupt request . . . . .1958
Table 477.IWDG register map and reset values . . . . .1964
Table 478.WWDG features . . . . .1965
Table 479.WWDG internal input/output signals . . . . .1966
Table 480.WWDG interrupt requests . . . . .1969
Table 481.WWDG register map and reset values . . . . .1971
Table 482.RTC input/output pins . . . . .1975
Table 483.RTC internal input/output signals . . . . .1975
Table 484.RTC interconnection . . . . .1976
Table 485.RTC_OUT mapping . . . . .1976
Table 486.Effect of low-power modes on RTC . . . . .1992
Table 487.RTC pins functionality over modes . . . . .1992
Table 488.Nonsecure interrupt requests . . . . .1993
Table 489.Secure interrupt requests . . . . .1993
Table 490.RTC register map and reset values . . . . .2025
Table 491.TAMP input/output pins . . . . .2030
Table 492.TAMP internal input/output signals . . . . .2030
Table 493.TAMP interconnection . . . . .2031
Table 494.PC13 pin configuration . . . . .2033
Table 495.Backup registers and BHK tamper protection . . . . .2038
Table 496.Other device resource x tamper protection . . . . .2038
Table 497.Effect of low-power modes on TAMP . . . . .2041
Table 498.TAMP pins functionality over modes . . . . .2041
Table 499.Interrupt requests . . . . .2041
Table 500.TAMP register map and reset values . . . . .2055
Table 501.I2C implementation . . . . .2059
Table 502.I2C input/output pins . . . . .2060
Table 503.I2C internal input/output signals . . . . .2061
Table 504.Trigger interconnections . . . . .2061
Table 505.Comparison of analog and digital filters . . . . .2063
Table 506.I 2 C-bus and SMBus specification data setup and hold times . . . . .2065
Table 507.I2C configuration . . . . .2069
Table 508.I 2 C-bus and SMBus specification clock timings . . . . .2080
Table 509.Timing settings for f I2CCLK of 8 MHz. . . . .2090
Table 510.Timing settings for f I2CCLK of 16 MHz. . . . .2090
Table 511.Timing settings for f I2CCLK of 48 MHz. . . . .2091
Table 512.SMBus timeout specifications . . . . .2093
Table 513.SMBus with PEC configuration . . . . .2095
Table 514.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms. . . . .2096
Table 515.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .2096
Table 516.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .2096
Table 517.Effect of low-power modes to I2C. . . . .2106
Table 518.I2C interrupt requests . . . . .2107
Table 519.I2C register map and reset values . . . . .2124
Table 520.I3C instantiation . . . . .2128
Table 521.I3C wake-up . . . . .2128
Table 522.I3C autonomous mode with DMA in Stop mode(s). . . . .2128
Table 523.I3C FIFOs implementation . . . . .2129
Table 524.I3C triggers, when I3C as controller . . . . .2129
Table 525.I3C interrupt(s) . . . . .2130
Table 526.I3C peripheral controller/target features versus MIPI v1.1 . . . . .2130
Table 527.I3C input/output pins. . . . .2131
Table 528.I3C internal input/output signals . . . . .2131
Table 529.I3C register usage . . . . .2144
Table 530.I3C registers/fields usage versus controller state . . . . .2145
Table 531.I3C registers/fields usage versus target state. . . . .2148
Table 532.List of supported I3C CCCs, as controller/target . . . . .2151
Table 533.I3C controller error management . . . . .2182
Table 534.I3C target error management . . . . .2184
Table 535.Effect of low-power modes . . . . .2188
Table 536.I3C register map and reset values . . . . .2235
Table 537.I3C instantiation . . . . .2240
Table 538.I3C wake-up . . . . .2240
Table 539.I3C autonomous mode with DMA in Stop mode(s). . . . .2241
Table 540.I3C FIFOs implementation . . . . .2241
Table 541.I3C triggers, when I3C as controller . . . . .2241
Table 542.I3C interrupt(s) . . . . .2242
Table 543.I3C peripheral controller/target features versus MIPI v1.1 . . . . .2243
Table 544.I3C input/output pins. . . . .2244
Table 545.I3C internal input/output signals . . . . .2244
Table 546.I3C register usage . . . . .2260
Table 547.I3C registers/fields usage versus controller state . . . . .2261
Table 548.I3C registers/fields usage versus target state. . . . .2263
Table 549.List of supported I3C CCCs, as controller/target . . . . .2266
Table 550.I3C controller error management . . . . .2301
Table 551.I3C target error management . . . . .2303
Table 552.Effect of low-power modes . . . . .2307
Table 553.I3C register map and reset values . . . . .2356
Table 554.Instance implementation on STM32U3 series . . . . .2360
Table 555.USART/LPUART features . . . . .2360
Table 556.USART/UART input/output pins . . . . .2363
Table 557.USART internal input/output signals. . . . .2364
Table 558.USART interconnection (USART1/2/3 and UART4/5) . . . . .2364
Table 559.Noise detection from sampled data . . . . .2376
Table 560.Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .2380
Table 561.Tolerance of the USART receiver when BRR[3:0] is different from 0000. . . . .2380
Table 562.USART frame formats . . . . .2385
Table 563.Effect of low-power modes on the USART . . . . .2406
Table 564.USART interrupt requests. . . . .2407
Table 565.USART register map and reset values . . . . .2446
Table 566.Instance implementation on STM32U3 series . . . . .2449
Table 567.USART/LPUART features . . . . .2449
Table 568.LPUART input/output pins . . . . .2452
Table 569.LPUART internal input/output signals. . . . .2452
Table 570.LPUART interconnections (LPUART1). . . . .2453
Table 571.Error calculation for programmed baud rates at lpuart_ker_ck_pres= 32.768 kHz . . . . .2464
Table 572.Tolerance of the LPUART receiver. . . . .2465
Table 574.Effect of low-power modes on the LPUART . . . . .2476
Table 575.LPUART interrupt requests. . . . .2477
Table 576.LPUART register map and reset values . . . . .2502
Table 577.SPI features . . . . .2506
Table 578.SPI input/output pins. . . . .2508
Table 579.SPI internal input/output signals . . . . .2509
Table 580.SPI interconnection (SPI1 and SPI2) . . . . .2509
Table 581.SPI interconnection (SPI3 and SPI4) . . . . .2510
Table 582.Effect of low-power modes on the SPI . . . . .2536
Table 583.SPI wake-up and interrupt requests . . . . .2537
Table 584.SPI register map and reset values . . . . .2554
Table 585.SAI features . . . . .2556
Table 586.SAI internal input/output signals . . . . .2558
Table 587.SAI input/output pins. . . . .2558
Table 588.MCLK_x activation conditions. . . . .2566
Table 589.Clock generator programming examples . . . . .2569
Table 590.SAI_A configuration for TDM mode . . . . .2576
Table 591.TDM frame configuration examples . . . . .2578
Table 592.SOPD pattern . . . . .2581
Table 593.Parity bit calculation . . . . .2581
Table 594.Audio sampling frequency versus symbol rates . . . . .2582
Table 595.SAI interrupt sources . . . . .2591
Table 596.SAI register map and reset values . . . . .2619
Table 597.FDCAN features . . . . .2623
Table 598.CAN subsystem I/O signals . . . . .2625
Table 599.CAN subsystem I/O pins. . . . .2625
Table 600.DLC coding in FDCAN . . . . .2629
Table 601.Possible configurations for frame transmission . . . . .2643
Table 602.Rx FIFO element . . . . .2646
Table 603.Rx FIFO element description . . . . .2646
Table 604.Tx buffer and FIFO element . . . . .2648
Table 605.Tx buffer element description . . . . .2648
Table 606.Tx event FIFO element. . . . .2650
Table 607.Tx event FIFO element description. . . . .2650
Table 608.Standard message ID filter element . . . . .2651
Table 609.Standard message ID filter element field description . . . . .2652
Table 610.Extended message ID filter element. . . . .2652
Table 611.Extended message ID filter element field description. . . . .2653
Table 612.FDCAN register map and reset values . . . . .2683
Table 613.STM32U3 series USB implementation . . . . .2687
Table 614.USB input/output pins . . . . .2688
Table 615.Double-buffering buffer flag definition . . . . .2700
Table 616.Bulk double-buffering memory buffers usage (Device mode) . . . . .2700
Table 617.Bulk double-buffering memory buffers usage (Host mode) . . . . .2702
Table 618.Isochronous memory buffers usage . . . . .2703
Table 619.Isochronous memory buffers usage . . . . .2704
Table 620.Resume event detection . . . . .2706
Table 621.Resume event detection for host . . . . .2707
Table 622.Reception status encoding . . . . .2725
Table 623.Endpoint/channel type encoding . . . . .2725
Table 624.Endpoint/channel kind meaning . . . . .2725
Table 625.Transmission status encoding . . . . .2725
Table 626.USB register map and reset values . . . . .2726
Table 627.Definition of allocated buffer memory . . . . .2729
Table 628.USB SRAM register map and reset values . . . . .2732
Table 629.JTAG/Serial-wire debug port pins . . . . .2734
Table 630.Trace port pins . . . . .2734
Table 631.Single-wire trace port pins . . . . .2735
Table 632.Authentication signal states . . . . .2736
Table 633.JTAG-DP data registers . . . . .2739
Table 634.Packet request . . . . .2740
Table 635.ACK response . . . . .2741
Table 636.Data transfer . . . . .2741
Table 637.Debug port register map and reset values . . . . .2747
Table 638.Access port register map and reset values . . . . .2753
Table 639.MCU ROM table . . . . .2754
Table 640.Processor ROM table . . . . .2754
Table 641.MCU ROM table register map and reset values . . . . .2759
Table 642.CPU ROM table register map and reset values . . . . .2764
Table 643.DWT register map and reset values . . . . .2778
Table 644.ITM register map and reset values . . . . .2788
Table 645.BPU register map and reset values . . . . .2794
Table 646.ETM register map and reset values . . . . .2818
Table 647.TPIU register map and reset values . . . . .2831
Table 648.CTI register map and reset values . . . . .2843
Table 649.Peripheral clock freeze control bits . . . . .2845
Table 650.Peripheral behavior in debug mode . . . . .2847
Table 651.Debugger access to freeze register bits . . . . .2847
Table 652.DBGMCU register map and reset values . . . . .2858
Table 653.Document revision history . . . . .2865

List of figures

Figure 1.System architecture . . . . .101
Figure 2.Memory map based on IDAU mapping for STM32U356/366 . . . . .109
Figure 3.Memory map based on IDAU mapping for STM32U375/385 . . . . .110
Figure 4.Memory map based on IDAU mapping for STM323B5/3C5 . . . . .111
Figure 5.Secure/nonsecure partitioning using TrustZone technology . . . . .120
Figure 6.Sharing memory map between CPU in secure and nonsecure state . . . . .122
Figure 7.Secure world transition and memory partitioning . . . . .122
Figure 8.Global TrustZone framework and TrustZone awareness . . . . .124
Figure 9.Flash memory TrustZone protections . . . . .127
Figure 10.Flash memory secure HDP area . . . . .135
Figure 11.Key management principle . . . . .142
Figure 12.Device life-cycle security . . . . .145
Figure 13.RDP level transition scheme . . . . .147
Figure 14.Collaborative development principle . . . . .150
Figure 15.GTZC in Armv8-M subsystem block diagram . . . . .157
Figure 16.GTZC block diagram . . . . .160
Figure 17.MPCBB block diagram . . . . .161
Figure 18.Secure, HDP, and HDP extension areas . . . . .246
Figure 19.Flash memory security attributes and protections
in case of no bank swap (SWAP_BANK = 0) . . . . .		249
Figure 20.Flash memory security attributes and protections
in case of bank swap (SWAP_BANK = 1) . . . . .		249
Figure 21.RDP level transition scheme when TrustZone is disabled (TZEN = 0) . . . . .257
Figure 22.RDP level transition scheme when TrustZone is enabled (TZEN = 1) . . . . .257
Figure 23.ICACHE block diagram . . . . .311
Figure 24.ICACHE TAG and data memories functional view . . . . .313
Figure 25.ICACHE remapping address mechanism . . . . .316
Figure 26.Power supply overview . . . . .328
Figure 27.Brownout reset waveform . . . . .335
Figure 28.PVD thresholds . . . . .335
Figure 29.I/O states in Stop 3 mode . . . . .354
Figure 30.I/O states in Standby mode . . . . .357
Figure 31.Simplified diagram of the reset circuit . . . . .395
Figure 32.Clock tree (1) . . . . .398
Figure 33.MSI block diagram . . . . .401
Figure 34.CRS block diagram . . . . .485
Figure 35.CRS counter behavior . . . . .487
Figure 36.Structure of three-volt or five-volt tolerant GPIO (TT or FT) . . . . .497
Figure 37.Input floating/pull-up/pull-down configurations . . . . .501
Figure 38.Output configuration . . . . .502
Figure 39.Alternate function configuration . . . . .503
Figure 40.High-impedance analog configuration . . . . .503
Figure 41.I/O compensation cell block diagram . . . . .519
Figure 42.GPDMA block diagram . . . . .557
Figure 43.GPDMA channel direct programming without linked-list (GPDMA_CxLLR = 0) . . . . .558
Figure 44.GPDMA channel suspend and resume sequence . . . . .559
Figure 45.GPDMA channel abort and restart sequence . . . . .560
Figure 46.Static linked-list data structure (all Uxx = 1)

of a linear addressing channel x . . . . . 561

Figure 47. Static linked-list data structure (all Uxx = 1)
of a 2D addressing channel x . . . . . 562

Figure 48. GPDMA dynamic linked-list data structure
of a linear addressing channel x . . . . . 563

Figure 49. GPDMA dynamic linked-list data structure
of a 2D addressing channel x . . . . . 563

Figure 50. GPDMA channel execution and linked-list programming
in run-to-completion mode (GPDMA_CxCR.LSM = 0) . . . . . 565

Figure 51. Inserting a LLn with an auxiliary GPDMA channel y . . . . . 567

Figure 52. GPDMA channel execution and linked-list programming
in link step mode (GPDMA_CxCR.LSM = 1) . . . . . 569

Figure 53. Building LLn+1: GPDMA dynamic linked-lists in link step mode . . . . . 570

Figure 54. Replace with a new LLn' in register file in link step mode . . . . . 571

Figure 55. Replace with a new LLn' and LLn+1' in memory in link step mode (option 1) . . . . . 572

Figure 56. Replace with a new LLn' and LLn+1' in memory in link step mode (option 2) . . . . . 573

Figure 57. GPDMA channel execution and linked-list programming . . . . . 575

Figure 58. Programmed 2D addressing . . . . . 578

Figure 59. GPDMA arbitration policy . . . . . 585

Figure 60. Trigger hit, memorization, and overrun waveform . . . . . 588

Figure 61. GPDMA circular buffer programming: update of the memory start address
with a linear addressing channel . . . . . 589

Figure 62. Shared GPDMA channel with circular buffering: update of the memory
start address with a linear addressing channel. . . . . 590

Figure 63. EXTI block diagram . . . . . 634

Figure 64. Configurable event trigger logic CPU wake-up. . . . . 636

Figure 65. EXTI mux GPIO selection. . . . . 637

Figure 66. CRC calculation unit block diagram . . . . . 650

Figure 67. HSP functional view . . . . . 657

Figure 68. HSP block diagram . . . . . 660

Figure 69. Single-precision floating-point format . . . . . 663

Figure 70. MMC overview . . . . . 664

Figure 71. Memory mapping seen from the AHB slave port SP1 . . . . . 666

Figure 72. BRAM arbitration . . . . . 667

Figure 73. HSP code loading . . . . . 668

Figure 74. HSP start-up . . . . . 670

Figure 75. MSGB block diagram . . . . . 671

Figure 76. DCMD block diagram . . . . . 674

Figure 77. Direct command programming example. . . . . 676

Figure 78. STREAM block diagram . . . . . 677

Figure 79. BUF CMB details . . . . . 678

Figure 80. Buffer usage generation example. . . . . 680

Figure 81. TRGITF block diagram . . . . . 682

Figure 82. TRGIN overrun detection . . . . . 684

Figure 83. SEG block diagram. . . . . 685

Figure 84. Example of dedicated event generation . . . . . 687

Figure 85. EVTC block diagram. . . . . 688

Figure 86. Processing request control . . . . . 689

Figure 87. Example of synchronization mechanism . . . . . 690

Figure 88. Task controller details. . . . . 693

Figure 89. Priority encoder example . . . . . 694

Figure 90. HSP interrupt controller . . . . . 695

Figure 91.HSP error interrupt controller. . . . .696
Figure 92.HSP event interrupt controller. . . . .700
Figure 93.Saturation flag. . . . .701
Figure 94.HCC block diagram. . . . .704
Figure 95.TRGITF wake-up capabilities . . . . .705
Figure 96.TCU block diagram. . . . .706
Figure 97.Task overlap . . . . .706
Figure 98.TRGO block diagram . . . . .707
Figure 99.TSC block diagram. . . . .708
Figure 100.Trace controller block diagram . . . . .710
Figure 101.TSC capture example 1 . . . . .712
Figure 102.TSC capture example 2 . . . . .713
Figure 103.SNOOP function . . . . .715
Figure 104.Break interface . . . . .717
Figure 105.Break input timing example . . . . .719
Figure 106.Step-by-step timing example . . . . .721
Figure 107.PLSUP simplified algorithm . . . . .726
Figure 108.Processing list programming algorithm. . . . .728
Figure 109.Direct command processing list simplified algorithm . . . . .729
Figure 110.Data sharing models. . . . .730
Figure 111.OCTOSPI block diagram in octal configuration . . . . .796
Figure 112.OCTOSPI block diagram in quad configuration . . . . .796
Figure 113.OCTOSPI block diagram in dual-quad configuration . . . . .797
Figure 114.SDR read command in octal configuration. . . . .798
Figure 115.DTR read in octal-SPI mode with DQS (Macronix mode) example . . . . .801
Figure 116.SDR write command in octo-SPI mode example . . . . .803
Figure 117.DTR write in octal-SPI mode (Macronix mode) example . . . . .804
Figure 118.Example of HyperBus read operation. . . . .806
Figure 119.HyperBus write operation with initial latency . . . . .807
Figure 120.HyperBus read operation with additional latency . . . . .807
Figure 121.HyperBus write operation with additional latency . . . . .808
Figure 122.HyperBus write operation with no latency (register write). . . . .808
Figure 123.HyperBus read operation page crossing with latency. . . . .809
Figure 124.D0/D1 data ordering in octal-SPI DTR mode (Micron) - Read access . . . . .816
Figure 125.OctaRAM read operation with reverse data ordering D1/D0 . . . . .816
Figure 126.NCS when CKMODE = 0 (T = CLK period) . . . . .822
Figure 127.NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .822
Figure 128.NCS when CKMODE = 1 in DTR mode (T = CLK period) . . . . .823
Figure 129.NCS when CKMODE = 1 with an abort (T = CLK period). . . . .823
Figure 130.SDMMC “no response” and “no data” operations. . . . .853
Figure 131.SDMMC (multiple) block read operation. . . . .853
Figure 132.SDMMC (multiple) block write operation. . . . .854
Figure 133.SDMMC (sequential) stream read operation . . . . .854
Figure 134.SDMMC (sequential) stream write operation . . . . .854
Figure 135.SDMMC block diagram. . . . .856
Figure 136.SDMMC Command and data phase relation . . . . .858
Figure 137.Control unit . . . . .860
Figure 138.Command/response path . . . . .861
Figure 139.Command path state machine (CPSM) . . . . .862
Figure 140.Data path . . . . .868
Figure 141.DDR mode data packet clocking . . . . .869
Figure 142.DDR mode CRC status / boot acknowledgment clocking. . . . .869
Figure 143. Data path state machine (DPSM) . . . . .870
Figure 144. CLKMUX unit . . . . .881
Figure 145. Linked list structures . . . . .883
Figure 146. Asynchronous interrupt generation . . . . .886
Figure 147. Synchronous interrupt period data read . . . . .887
Figure 148. Synchronous interrupt period data write . . . . .887
Figure 149. Asynchronous interrupt period data read . . . . .888
Figure 150. Asynchronous interrupt period data write . . . . .889
Figure 151. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25. . . . .892
Figure 152. Clock stop with SDMMC_CK for DDR50, SDR50, SDR104. . . . .892
Figure 153. Read Wait with SDMMC_CK < 50 MHz . . . . .893
Figure 154. Read Wait with SDMMC_CK > 50 MHz . . . . .893
Figure 155. CMD12 stream timing . . . . .896
Figure 156. CMD5 Sleep Awake procedure . . . . .898
Figure 157. Normal boot mode operation . . . . .900
Figure 158. Alternative boot mode operation . . . . .901
Figure 159. Command response R1b busy signaling . . . . .902
Figure 160. SDMMC state control . . . . .903
Figure 161. Card cycle power / power up diagram . . . . .904
Figure 162. CMD11 signal voltage switch sequence . . . . .905
Figure 163. Voltage switch transceiver typical application. . . . .907
Figure 164. DLYB block diagram . . . . .935
Figure 165. ADC block diagram . . . . .943
Figure 166. ADC clock scheme . . . . .947
Figure 167. ADC1 connectivity . . . . .948
Figure 168. ADC2 connectivity . . . . .949
Figure 169. ADC calibration. . . . .951
Figure 170. Calibration factor forcing. . . . .952
Figure 171. Enabling/disabling the ADC . . . . .953
Figure 172. Bulb mode timing diagram . . . . .956
Figure 173. Analog-to-digital conversion time . . . . .961
Figure 174. Stopping ongoing regular conversions . . . . .962
Figure 175. Stopping ongoing regular and injected conversions . . . . .962
Figure 176. Triggers shared between ADC master and slave . . . . .964
Figure 177. Injected conversion latency during ongoing regular conversion . . . . .965
Figure 178. Example of ADC_JSQR queue of context (sequence change) . . . . .967
Figure 179. Example of ADC_JSQR queue of context (trigger change) . . . . .967
Figure 180. Example of ADC_JSQR queue of context with overflow before conversion. . . . .968
Figure 181. Example of ADC_JSQR queue of context with overflow during conversion . . . . .968
Figure 182. Example of ADC_JSQR queue of context with empty queue (case JQM = 0). . . . .969
Figure 183. Example of ADC_JSQR queue of context with empty queue (JQM = 1) . . . . .970
Figure 184. Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0) -
JADSTP occurs during an ongoing conversion. . . . .		970
Figure 185. Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0) -
JADSTP occurs during an ongoing conversion and a new
trigger occurs . . . . .		971
Figure 186. Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0) -
JADSTP occurs outside an ongoing conversion. . . . .		971
Figure 187. Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 1) . . . . .972
Figure 188. Flushing ADC_JSQR queue of context by setting ADDIS = 1 (JQM = 0). . . . .972
Figure 189. Flushing ADC_JSQR queue of context by setting ADDIS = 1 (JQM = 1). . . . .973
Figure 190. Single conversions of a sequence, software trigger . . . . .975
Figure 191. Continuous conversion of a sequence, software trigger . . . . .975
Figure 192. Single conversions of a sequence, hardware trigger . . . . .976
Figure 193. Continuous conversions of a sequence, hardware trigger . . . . .976
Figure 194. Right alignment (offset disabled, unsigned value) . . . . .978
Figure 195. Right alignment (offset enabled, signed value). . . . .979
Figure 196. Left alignment (offset disabled, unsigned value) . . . . .979
Figure 197. Left alignment (offset enabled, signed value). . . . .980
Figure 198. Example of overrun (OVRMOD = 0). . . . .983
Figure 199. Example of overrun (OVRMOD = 1). . . . .983
Figure 200. AUTDLY = 1, regular conversion in continuous mode, software trigger . . . . .987
Figure 201. AUTDLY = 1, regular hardware conversions interrupted by injected conversions
(DISCEN = 0; JDISCEN = 0) . . . . .		987
Figure 202. AUTDLY = 1, regular hardware conversions interrupted by injected conversions
(DISCEN = 1, JDISCEN = 1) . . . . .		988
Figure 203. AUTDLY = 1, regular continuous conversions interrupted by injected conversions . . . . .988
Figure 204. AUTDLY = 1 in autoinjection mode (JAUTO = 1) . . . . .989
Figure 205. Analog watchdog guarded area . . . . .990
Figure 206. ADC_AWDy_OUT signal generation (on all regular channels). . . . .992
Figure 207. ADC_AWDy_OUT signal generation (AWDy flag not cleared by software) . . . . .993
Figure 208. ADC_AWDy_OUT signal generation (on a single regular channel) . . . . .993
Figure 209. ADC_AWDy_OUT signal generation (on all injected channels) . . . . .994
Figure 210. 12-bit result oversampling with 10-bit right shift and rounding . . . . .995
Figure 211. Triggered regular oversampling mode (TROVS bit = 1). . . . .997
Figure 212. Regular oversampling modes (4x ratio) . . . . .998
Figure 213. Regular and injected oversampling modes used simultaneously . . . . .999
Figure 214. Triggered regular oversampling with injection . . . . .999
Figure 215. Oversampling in autoinjection mode. . . . .1000
Figure 216. Dual ADC block diagram . . . . .1002
Figure 217. Injected simultaneous mode on four channels: Dual ADC mode . . . . .1003
Figure 218. Regular simultaneous mode on 16 channels: dual ADC mode . . . . .1005
Figure 219. Interleaved mode on 1 channel in continuous conversion mode:
Dual ADC mode . . . . .		1007
Figure 220. Interleaved mode on 1 channel in single conversion mode:
Dual ADC mode . . . . .		1007
Figure 221. Interleaved conversion with injection . . . . .1008
Figure 222. Alternate trigger: injected group of each ADC . . . . .1009
Figure 223. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode. . . . .1010
Figure 224. Alternate + regular simultaneous . . . . .1010
Figure 225. Case of trigger occurring during injected conversion . . . . .1011
Figure 226. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . .1011
Figure 227. Two interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first. . . . .		1012
Figure 228. Two interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first. . . . .		1012
Figure 229. DMA requests in regular simultaneous mode when DAMDF[1:0] = 0b00 . . . . .1013
Figure 230. DMA requests in interleaved mode when DAMDF = 0b10 . . . . .1014
Figure 231. Temperature sensor channel block diagram . . . . .1017
Figure 232. VBAT channel block diagram . . . . .1018
Figure 233. VREFINT channel block diagram . . . . .1019
Figure 234. Dual-channel DAC block diagram . . . . .1063
Figure 235. Data registers in single DAC channel mode. . . . .1066
Figure 236. Data registers in dual DAC channel mode . . . . .1067
Figure 237. Timing diagram for conversion with trigger disabled TEN = 0 . . . . .1068
Figure 238. DAC LFSR register calculation algorithm . . . . .1070
Figure 239. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . .1071
Figure 240. DAC triangle wave generation . . . . .1071
Figure 241. DAC conversion (SW trigger enabled) with triangle wave generation . . . . .1072
Figure 242. DAC sample and hold mode phase diagram . . . . .1074
Figure 243. VREFBUF block diagram . . . . .1102
Figure 244. Comparator block diagrams . . . . .1107
Figure 245. Window mode . . . . .1110
Figure 246. Comparator hysteresis . . . . .1110
Figure 247. Comparator output blanking . . . . .1111
Figure 248. Scaler . . . . .1112
Figure 249. Standalone mode: external gain setting mode . . . . .1119
Figure 250. Follower configuration. . . . .1120
Figure 251. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . .1121
Figure 252. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering . . . . .1122
Figure 253. ADF block diagram . . . . .1132
Figure 254. SITF overview. . . . .1134
Figure 255. SPI timing example . . . . .1135
Figure 256. Manchester timing example (SITFMOD = 11) . . . . .1137
Figure 257. CKGEN overview . . . . .1139
Figure 258. BSMX overview . . . . .1141
Figure 259. DFLT overview . . . . .1142
Figure 260. Programmable delay. . . . .1143
Figure 261. CIC4 and CIC5 frequency response with decimation ratio = 32 or 16 . . . . .1145
Figure 262. Reshape filter frequency response normalized (FRS / 2 = 1). . . . .1150
Figure 263. Trigger logic for DFLT and CKGEN . . . . .1152
Figure 264. Asynchronous continuous mode (ACQMOD[2:0] = 0) . . . . .1153
Figure 265. Asynchronous single-shot mode (ACQMOD[2:0] = 001) . . . . .1154
Figure 266. Synchronous continuous mode (ACQMOD[2:0] = 010) . . . . .1155
Figure 267. Synchronous single-shot mode (ACQMOD[2:0] = 011) . . . . .1156
Figure 268. Window continuous mode (ACQMOD[2:0] = 100) . . . . .1157
Figure 269. Discard function example . . . . .1159
Figure 270. Start sequence with DFLTEN, in continuous mode, audio configuration . . . . .1159
Figure 271. SAD block diagram . . . . .1160
Figure 272. SAD flow diagram . . . . .1162
Figure 273. SAD timing diagram example . . . . .1168
Figure 274. ADF_DFLTxDATA format . . . . .1168
Figure 275. Data resynchronization . . . . .1169
Figure 276. Example of overflow and transfer to memory . . . . .1170
Figure 277. ADF interrupt interface . . . . .1173
Figure 278. Sensor connection examples . . . . .1178
Figure 279. Global frequency response. . . . .1178
Figure 280. Detailed frequency response . . . . .1179
Figure 281. Simplified DFLT view with gain information . . . . .1181
Figure 282. SAD example working with SADMOD = 01 . . . . .1184
Figure 283. SAD example working with SADMOD = 1x . . . . .1185
Figure 284. LCD controller block diagram . . . . .1207
Figure 285. 1/3 bias, 1/4 duty . . . . .1209
Figure 286. Static duty case 1 . . . . .1210
Figure 287. Static duty case 2 . . . . .1211
Figure 288. 1/2 duty, 1/2 bias .....1212
Figure 289. 1/3 duty, 1/3 bias .....1213
Figure 290. 1/4 duty, 1/3 bias .....1214
Figure 291. 1/8 duty, 1/4 bias .....1215
Figure 292. LCD voltage control .....1218
Figure 293. Dead time .....1219
Figure 294. SEG/COM mux feature example .....1224
Figure 295. Flowchart example .....1225
Figure 296. TSC block diagram .....1237
Figure 297. Surface charge transfer analog I/O group structure .....1238
Figure 298. Sampling capacitor voltage variation .....1240
Figure 299. Charge transfer acquisition sequence .....1241
Figure 300. Spread spectrum variation principle .....1242
Figure 301. Surface charge transfer with comparator analog I/O group structure .....1245
Figure 302. Sensor voltage variation for both normal and comparator mode .....1246
Figure 303. CCB block diagram .....1257
Figure 304. CCB operation CPU → PKA + SAES (write) .....1259
Figure 305. CCB operation PKA → SAES .....1259
Figure 306. CCB operation SAES → PKA .....1259
Figure 307. CCB operation SAES → CCB .....1260
Figure 308. CCB operation RNG → PKA (write) .....1260
Figure 309. CCB operation RNG → SAES (write) .....1261
Figure 310. Blob creation scenarios .....1262
Figure 311. RNG block diagram .....1283
Figure 312. NIST SP800-90B entropy source model .....1284
Figure 313. RNG initialization overview .....1287
Figure 314. AES block diagram .....1304
Figure 315. Encryption/ decryption typical usage .....1305
Figure 316. Typical operation with authentication .....1308
Figure 317. Example of suspend mode management .....1309
Figure 318. ECB encryption .....1310
Figure 319. ECB decryption .....1310
Figure 320. CBC encryption .....1310
Figure 321. CBC decryption .....1311
Figure 322. Message construction in CTR mode .....1313
Figure 323. CTR encryption .....1314
Figure 324. Message construction in GCM .....1315
Figure 325. GCM authenticated encryption .....1317
Figure 326. Message construction in GMAC mode .....1320
Figure 327. GMAC authentication mode .....1321
Figure 328. Message construction in CCM mode .....1322
Figure 329. CCM mode authenticated encryption .....1323
Figure 330. 128-bit block construction according to the data type .....1328
Figure 331. SAES block diagram .....1350
Figure 332. Encryption/ decryption typical usage .....1352
Figure 333. Typical operation with authentication .....1354
Figure 334. Example of suspend mode management .....1355
Figure 335. ECB encryption .....1356
Figure 336. ECB decryption .....1356
Figure 337. CBC encryption .....1357
Figure 338. CBC decryption .....1357
Figure 339. Message construction in CTR mode .....1360
Figure 340. CTR encryption . . . . .1361
Figure 341. Message construction in GCM . . . . .1362
Figure 342. GCM authenticated encryption . . . . .1364
Figure 343. Message construction in GMAC mode . . . . .1367
Figure 344. GMAC authentication mode . . . . .1367
Figure 345. Message construction in CCM mode . . . . .1368
Figure 346. CCM mode authenticated encryption . . . . .1370
Figure 347. Operation with wrapped keys for SAES in ECB and CBC modes . . . . .1373
Figure 348. Operation with wrapped keys for SAES in CTR mode . . . . .1376
Figure 349. Usage of Shared-key mode . . . . .1377
Figure 350. 128-bit block construction according to the data type. . . . .1380
Figure 351. Key protection mechanisms . . . . .1382
Figure 352. HASH block diagram . . . . .1404
Figure 353. Message data swapping feature . . . . .1406
Figure 354. HASH suspend/resume mechanism . . . . .1412
Figure 355. PKA block diagram . . . . .1426
Figure 356. Chaining of PKA with SAES or RNG . . . . .1433
Figure 357. Advanced-control timer block diagram . . . . .1466
Figure 358. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1472
Figure 359. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1473
Figure 360. Counter timing diagram, internal clock divided by 1 . . . . .1474
Figure 361. Counter timing diagram, internal clock divided by 2 . . . . .1475
Figure 362. Counter timing diagram, internal clock divided by 4 . . . . .1475
Figure 363. Counter timing diagram, internal clock divided by N . . . . .1476
Figure 364. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded). . . . .		1476
Figure 365. Counter timing diagram, update event when ARPE = 1
(TIMx_ARR preloaded). . . . .		1477
Figure 366. Counter timing diagram, internal clock divided by 1 . . . . .1478
Figure 367. Counter timing diagram, internal clock divided by 2 . . . . .1479
Figure 368. Counter timing diagram, internal clock divided by 4 . . . . .1479
Figure 369. Counter timing diagram, internal clock divided by N . . . . .1480
Figure 370. Counter timing diagram, update event when repetition counter is not used. . . . .1480
Figure 371. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1482
Figure 372. Counter timing diagram, internal clock divided by 2 . . . . .1482
Figure 373. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .1483
Figure 374. Counter timing diagram, internal clock divided by N . . . . .1483
Figure 375. Counter timing diagram, update event with ARPE = 1 (counter underflow) . . . . .1484
Figure 376. Counter timing diagram, Update event with ARPE = 1 (counter overflow) . . . . .1485
Figure 377. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1486
Figure 379. Control circuit in normal mode, internal clock divided by 1 . . . . .1488
Figure 380. tim_ti2 external clock connection example . . . . .1488
Figure 381. Control circuit in external clock mode 1 . . . . .1489
Figure 382. External trigger input block . . . . .1490
Figure 383. Control circuit in external clock mode 2 . . . . .1491
Figure 384. Capture/compare channel (example: channel 1 input stage) . . . . .1491
Figure 385. Capture/compare channel 1 main circuit . . . . .1492
Figure 386. Output stage of capture/compare channel (channel 1, idem ch. 2, 3 and 4) . . . . .1493
Figure 387. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .1493
Figure 388. PWM input mode timing . . . . .1496
Figure 389. Output compare mode, toggle on tim_oc1 . . . . .1498
Figure 390. Edge-aligned PWM waveforms (ARR = 8) . . . . .1499
Figure 391. Center-aligned PWM waveforms (ARR = 8) . . . . .1500
Figure 392. Dithering principle . . . . .1501
Figure 393. Data format and register coding in dithering mode . . . . .1502
Figure 394. PWM resolution vs frequency . . . . .1503
Figure 395. PWM dithering pattern . . . . .1504
Figure 396. Dithering effect on duty cycle in center-aligned PWM mode . . . . .1505
Figure 397. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1507
Figure 398. Combined PWM mode on channel 1 and 3 . . . . .1508
Figure 399. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .1509
Figure 400. Complementary output with symmetrical dead-time insertion . . . . .1510
Figure 401. Asymmetrical deadtime . . . . .1511
Figure 402. Dead-time waveforms with delay greater than the negative pulse . . . . .1511
Figure 403. Dead-time waveforms with delay greater than the positive pulse . . . . .1511
Figure 404. Break and Break2 circuitry overview . . . . .1514
Figure 405. Various output behavior in response to a break event on tim_brk (OSSI = 1) . . . . .1516
Figure 406. PWM output state following tim_brk and tim_brk2 assertion (OSSI = 1) . . . . .1517
Figure 407. PWM output state following tim_brk assertion (OSSI = 0) . . . . .1518
Figure 408. Output redirection (tim_brk2 request not represented) . . . . .1519
Figure 409. tim_ocref_clr input selection multiplexer . . . . .1520
Figure 410. Clearing TIMx tim_ocxref . . . . .1521
Figure 411. 6-step generation, COM example (OSSR = 1) . . . . .1522
Figure 412. Example of one pulse mode . . . . .1523
Figure 413. Retriggerable one-pulse mode . . . . .1524
Figure 414. Pulse generator circuitry . . . . .1525
Figure 415. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .1526
Figure 416. Extended pulsewidth in case of concurrent triggers . . . . .1527
Figure 417. Example of counter operation in encoder interface mode . . . . .1529
Figure 418. Example of encoder interface mode with tim_ti1fp1 polarity inverted . . . . .1529
Figure 419. Quadrature encoder counting modes . . . . .1530
Figure 420. Direction plus clock encoder mode . . . . .1531
Figure 421. Directional clock encoder mode (CC1P = CC2P = 0) . . . . .1531
Figure 422. Directional clock encoder mode (CC1P = CC2P = 1) . . . . .1532
Figure 423. Index gating options . . . . .1533
Figure 424. Jittered Index signals . . . . .1533
Figure 425. Index generation for IPOS[1:0] = 11 . . . . .1534
Figure 426. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .1534
Figure 427. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .1535
Figure 428. Counter reading with index gated on channel A and B . . . . .1535
Figure 429. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11) . . . . .1536
Figure 430. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .1537
Figure 431. Index behavior in x1 and x2 mode (IPOS[1:0] = 01) . . . . .1538
Figure 432. Directional index sensitivity . . . . .1538
Figure 433. Counter reset as function of FIDX bit setting . . . . .1539
Figure 434. Index blanking . . . . .1539
Figure 435. Index behavior in clock + direction mode, IPOS[0] = 1 . . . . .1540
Figure 436. Index behavior in directional clock mode, IPOS[0] = 1 . . . . .1540
Figure 437. State diagram for quadrature encoded signals . . . . .1541
Figure 438. Up-counting encoder error detection . . . . .1542
Figure 439. Down-counting encode error detection . . . . .1543
Figure 440. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .1544
Figure 441. Measuring time interval between edges on three signals . . . . .1545
Figure 442. Example of Hall sensor interface . . . . .1547
Figure 443.Control circuit in reset mode . . . . .1548
Figure 444.Control circuit in Gated mode . . . . .1549
Figure 445.Control circuit in trigger mode . . . . .1550
Figure 446.Control circuit in external clock mode 2 + trigger mode . . . . .1551
Figure 447.General-purpose timer block diagram . . . . .1610
Figure 448.Counter timing diagram with prescaler division change from 1 to 2 . . . . .1615
Figure 449.Counter timing diagram with prescaler division change from 1 to 4 . . . . .1616
Figure 450.Counter timing diagram, internal clock divided by 1 . . . . .1617
Figure 451.Counter timing diagram, internal clock divided by 2 . . . . .1617
Figure 452.Counter timing diagram, internal clock divided by 4 . . . . .1618
Figure 453.Counter timing diagram, internal clock divided by N . . . . .1618
Figure 454.Counter timing diagram, Update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .1619
Figure 455.Counter timing diagram, Update event when ARPE = 1 (TIMx_ARR preloaded). . . . .1620
Figure 456.Counter timing diagram, internal clock divided by 1 . . . . .1621
Figure 457.Counter timing diagram, internal clock divided by 2 . . . . .1622
Figure 458.Counter timing diagram, internal clock divided by 4 . . . . .1622
Figure 459.Counter timing diagram, internal clock divided by N . . . . .1623
Figure 460.Counter timing diagram, Update event . . . . .1623
Figure 461.Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1625
Figure 462.Counter timing diagram, internal clock divided by 2 . . . . .1625
Figure 463.Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .1626
Figure 464.Counter timing diagram, internal clock divided by N . . . . .1626
Figure 465.Counter timing diagram, Update event with ARPE = 1 (counter underflow). . . . .1627
Figure 466.Counter timing diagram, Update event with ARPE = 1 (counter overflow). . . . .1628
Figure 467.Control circuit in normal mode, internal clock divided by 1 . . . . .1629
Figure 468.tim_ti2 external clock connection example . . . . .1629
Figure 469.Control circuit in external clock mode 1 . . . . .1630
Figure 470.External trigger input block . . . . .1631
Figure 471.Control circuit in external clock mode 2 . . . . .1632
Figure 472.Capture/compare channel (example: channel 1 input stage). . . . .1632
Figure 473.Capture/compare channel 1 main circuit . . . . .1633
Figure 474.Output stage of capture/compare channel (channel 1, idem ch.2, 3 and 4). . . . .1633
Figure 475.PWM input mode timing . . . . .1636
Figure 476.Output compare mode, toggle on tim_oc1 . . . . .1638
Figure 477.Edge-aligned PWM waveforms (ARR = 8). . . . .1639
Figure 478.Center-aligned PWM waveforms (ARR = 8). . . . .1640
Figure 479.Dithering principle . . . . .1641
Figure 480.Data format and register coding in dithering mode . . . . .1642
Figure 481.PWM resolution vs frequency (16-bit mode). . . . .1643
Figure 482.PWM resolution vs frequency (32-bit mode). . . . .1643
Figure 483.PWM dithering pattern . . . . .1644
Figure 484.Dithering effect on duty cycle in center-aligned PWM mode . . . . .1645
Figure 485.Generation of two phase-shifted PWM signals with 50% duty cycle . . . . .1647
Figure 486.Combined PWM mode on channels 1 and 3 . . . . .1648
Figure 487.OCREF_CLR input selection multiplexer . . . . .1649
Figure 488.Clearing TIMx tim_ocxref . . . . .1649
Figure 489.Example of One-pulse mode . . . . .1650
Figure 490.Retriggerable one-pulse mode . . . . .1652
Figure 491.Pulse generator circuitry . . . . .1653
Figure 492.Pulse generation on compare event, for edge-aligned and encoder modes . . . . .1653
Figure 493.Extended pulse width in case of concurrent triggers . . . . .1654
Figure 494.Example of counter operation in encoder interface mode . . . . .1656
Figure 495.Example of encoder interface mode with tim_ti1fp1 polarity inverted . . . . .1656
Figure 496.Quadrature encoder counting modes . . . . .1657
Figure 497.Direction plus clock encoder mode . . . . .1658
Figure 498.Directional clock encoder mode (CC1P = CC2P = 0) . . . . .1659
Figure 499.Directional clock encoder mode (CC1P = CC2P = 1) . . . . .1659
Figure 500.Index gating options . . . . .1661
Figure 501.Jittered Index signals . . . . .1661
Figure 502.Index generation for IPOS[1:0] = 11 . . . . .1662
Figure 503.Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .1662
Figure 504.Counter reading with index ungated (IPOS[1:0] = 00) . . . . .1663
Figure 505.Counter reading with index gated on channel A and B . . . . .1663
Figure 506.Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11) . . . . .1664
Figure 507.Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .1665
Figure 508.Index behavior in x1 and x2 mode (IPOS[1:0] = 01) . . . . .1666
Figure 509.Directional index sensitivity . . . . .1666
Figure 510.Counter reset as function of FIDX bit setting . . . . .1667
Figure 511.Index blanking . . . . .1667
Figure 512.Index behavior in clock + direction mode, IPOS[0] = 1 . . . . .1668
Figure 513.Index behavior in directional clock mode, IPOS[0] = 1 . . . . .1668
Figure 514.State diagram for quadrature encoded signals . . . . .1669
Figure 515.Up-counting encoder error detection . . . . .1670
Figure 516.Down-counting encode error detection . . . . .1671
Figure 517.Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .1672
Figure 518.Control circuit in reset mode . . . . .1674
Figure 519.Control circuit in gated mode . . . . .1675
Figure 520.Control circuit in trigger mode . . . . .1675
Figure 521.Control circuit in external clock mode 2 + trigger mode . . . . .1677
Figure 522.Master/Slave timer example . . . . .1677
Figure 523.Master/slave connection example with 1 channel only timers . . . . .1678
Figure 524.Gating TIM_slv with tim_oc1ref of TIM_mstr . . . . .1679
Figure 525.Gating TIM_slv with Enable of TIM_mstr . . . . .1680
Figure 526.Triggering TIM_slv with update of TIM_mstr . . . . .1681
Figure 527.Triggering TIM_slv with Enable of TIM_mstr . . . . .1681
Figure 528.Triggering TIM_mstr and TIM_slv with TIM_mstr tim_ti1 input . . . . .1682
Figure 529.Basic timer block diagram . . . . .1723
Figure 530.Control circuit in normal mode, internal clock divided by 1 . . . . .1724
Figure 531.Counter timing diagram with prescaler division change from 1 to 2 . . . . .1725
Figure 532.Counter timing diagram with prescaler division change from 1 to 4 . . . . .1726
Figure 533.Counter timing diagram, internal clock divided by 1 . . . . .1727
Figure 534.Counter timing diagram, internal clock divided by 2 . . . . .1727
Figure 535.Counter timing diagram, internal clock divided by 4 . . . . .1728
Figure 536.Counter timing diagram, internal clock divided by N . . . . .1728
Figure 537.Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded) . . . . .		1729
Figure 538.Counter timing diagram, update event when ARPE = 1 (TIMx_ARR
preloaded) . . . . .		1730
Figure 539.Dithering principle . . . . .1731
Figure 540.Data format and register coding in dithering mode . . . . .1731
Figure 541.FCnt resolution vs frequency . . . . .1732
Figure 542.PWM dithering pattern . . . . .1732
Figure 543.General-purpose timer block diagram (TIM12) . . . . .1744
Figure 544.Counter timing diagram with prescaler division change from 1 to 2 . . . . .1747
Figure 545.Counter timing diagram with prescaler division change from 1 to 4 . . . . .1747
Figure 546.Counter timing diagram, internal clock divided by 1 . . . . .1748
Figure 547.Counter timing diagram, internal clock divided by 2 . . . . .1749
Figure 548.Counter timing diagram, internal clock divided by 4 . . . . .1749
Figure 549.Counter timing diagram, internal clock divided by N . . . . .1750
Figure 550.Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .1750
Figure 551.Counter timing diagram, update event when ARPE = 1 (TIMx_ARR preloaded). . . . .1751
Figure 552.Control circuit in normal mode, internal clock divided by 1 . . . . .1752
Figure 553.tim_ti2 external clock connection example . . . . .1752
Figure 554.Control circuit in external clock mode 1 . . . . .1753
Figure 555.Capture/compare channel 1 input stage (TIM12) . . . . .1754
Figure 556.Capture/compare channel 1 main circuit . . . . .1754
Figure 557.Output stage of capture/compare channel 1 . . . . .1755
Figure 558.PWM input mode timing . . . . .1757
Figure 559.Output compare mode, toggle on tim_oc1. . . . .1759
Figure 560.Edge-aligned PWM waveforms (ARR = 8) . . . . .1760
Figure 561.Dithering principle . . . . .1761
Figure 562.Data format and register coding in dithering mode . . . . .1761
Figure 563.PWM resolution vs frequency . . . . .1762
Figure 564.PWM dithering pattern . . . . .1763
Figure 565.Combined PWM mode on channel 1 and 2 . . . . .1765
Figure 566.Example of one pulse mode . . . . .1766
Figure 567.Retriggerable one pulse mode . . . . .1767
Figure 568.Measuring time interval between edges on 2 signals . . . . .1768
Figure 569.Control circuit in reset mode . . . . .1769
Figure 570.Control circuit in gated mode . . . . .1770
Figure 571.Control circuit in trigger mode . . . . .1770
Figure 572.TIM15 block diagram . . . . .1792
Figure 573.TIM16/TIM17 block diagram . . . . .1793
Figure 574.Counter timing diagram with prescaler division change from 1 to 2 . . . . .1797
Figure 575.Counter timing diagram with prescaler division change from 1 to 4 . . . . .1798
Figure 576.Counter timing diagram, internal clock divided by 1 . . . . .1799
Figure 577.Counter timing diagram, internal clock divided by 2 . . . . .1800
Figure 578.Counter timing diagram, internal clock divided by 4 . . . . .1800
Figure 579.Counter timing diagram, internal clock divided by N . . . . .1801
Figure 580.Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .1801
Figure 581.Counter timing diagram, update event when ARPE = 1 (TIMx_ARR preloaded). . . . .1802
Figure 582.Update rate examples depending on mode and TIMx_RCR register settings . . . . .1803
Figure 583.Control circuit in normal mode, internal clock divided by 1 . . . . .1804
Figure 584.tim_ti2 external clock connection example . . . . .1804
Figure 585.Control circuit in external clock mode 1 . . . . .1805
Figure 586.Capture/compare channel (example: channel 1 input stage) . . . . .1806
Figure 587.Capture/compare channel 1 main circuit . . . . .1806
Figure 588.Output stage of capture/compare channel (channel 1). . . . .1807
Figure 589.Output stage of capture/compare channel (channel 2 for TIM15) . . . . .1807
Figure 590.PWM input mode timing . . . . .1810
Figure 591.Output compare mode, toggle on tim_oc1 . . . . .1812
Figure 592.Edge-aligned PWM waveforms (ARR = 8) . . . . .1813
Figure 593. Dithering principle . . . . .1814
Figure 594. Data format and register coding in dithering mode . . . . .1814
Figure 595. PWM resolution vs frequency . . . . .1815
Figure 596. PWM dithering pattern . . . . .1816
Figure 597. Combined PWM mode on channel 1 and 2 . . . . .1818
Figure 598. Complementary output with symmetrical dead-time insertion. . . . .1819
Figure 599. Asymmetrical deadtime . . . . .1820
Figure 600. Dead-time waveforms with delay greater than the negative pulse. . . . .1820
Figure 601. Dead-time waveforms with delay greater than the positive pulse. . . . .1820
Figure 602. Break circuitry overview . . . . .1822
Figure 603. Output behavior in response to a break event on tim_brk . . . . .1824
Figure 604. Output redirection . . . . .1826
Figure 605. tim_ocref_clr input selection multiplexer. . . . .1827
Figure 606. 6-step generation, COM example (OSSR = 1) . . . . .1828
Figure 607. Example of one pulse mode. . . . .1829
Figure 608. Retriggerable one pulse mode . . . . .1831
Figure 609. Measuring time interval between edges on 2 signals . . . . .1831
Figure 610. Control circuit in reset mode . . . . .1832
Figure 611. Control circuit in gated mode . . . . .1833
Figure 612. Control circuit in trigger mode. . . . .1834
Figure 613. LPTIM1/2/3 block diagram (1) . . . . .1898
Figure 614. LPTIM4 block diagram(1) . . . . .1899
Figure 615. Glitch filter timing diagram . . . . .1904
Figure 616. LPTIM output waveform, single-counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . .		1905
Figure 617. LPTIM output waveform, single-counting mode configuration
and Set-once mode activated (WAVE bit is set). . . . .		1906
Figure 618. LPTIM output waveform, Continuous counting mode configuration . . . . .1906
Figure 619. Waveform generation . . . . .1908
Figure 620. Encoder mode counting sequence . . . . .1912
Figure 621. Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . .		1913
Figure 622. Capture/compare input stage (channel 1) . . . . .1914
Figure 623. Capture/compare output stage (channel 1) . . . . .1914
Figure 624. Edge-aligned PWM mode (PRELOAD = 1) . . . . .1916
Figure 625. Edge-aligned PWM waveforms (ARR=8 and CCxP = 0) . . . . .1917
Figure 626. PWM mode with immediate update versus preloaded update . . . . .1918
Figure 627. IRTIM internal hardware connections . . . . .1948
Figure 628. Independent watchdog block diagram . . . . .1951
Figure 629. Reset timing due to timeout . . . . .1953
Figure 630. Reset timing due to refresh in the not allowed area . . . . .1954
Figure 631. Changing PR, RL, and performing a refresh (1) . . . . .1955
Figure 632. Independent watchdog interrupt timing diagram. . . . .1957
Figure 633. Watchdog block diagram . . . . .1966
Figure 634. Window watchdog timing diagram . . . . .1968
Figure 635. RTC block diagram . . . . .1974
Figure 636. TAMP block diagram . . . . .2029
Figure 637. Backup registers protection zones . . . . .2035
Figure 638. Tamper sampling with precharge pulse . . . . .2040
Figure 639. Low level detection with precharge and filtering . . . . .2040
Figure 640. Block diagram . . . . .2060
Figure 641. I 2 C-bus protocol . . . . .2062
Figure 642. Setup and hold timings . . . . .2064
Figure 643. I2C initialization flow . . . . .2067
Figure 644. Data reception . . . . .2068
Figure 645. Data transmission . . . . .2068
Figure 646. Target initialization flow . . . . .2072
Figure 647. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .2073
Figure 648. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .2074
Figure 649. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .2075
Figure 650. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .2076
Figure 651. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .2077
Figure 652. Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . .		2077
Figure 653. Controller clock generation . . . . .2079
Figure 654. Controller initialization flow . . . . .2081
Figure 655. 10-bit address read access with HEAD10R = 0 . . . . .2081
Figure 656. 10-bit address read access with HEAD10R = 1 . . . . .2082
Figure 657. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .2083
Figure 658. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .2084
Figure 659. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		2085
Figure 660. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .2087
Figure 661. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .2088
Figure 662. Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		2089
Figure 663. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .2093
Figure 664. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .2097
Figure 665. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .2097
Figure 666. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .2099
Figure 667. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .2100
Figure 668. Bus transfer diagrams for SMBus controller transmitter . . . . .2101
Figure 669. Bus transfer diagrams for SMBus controller receiver . . . . .2103
Figure 670. I3C block diagram. . . . .2131
Figure 671. I3C (primary) controller state and programming sequence diagram. . . . .2136
Figure 672. I3C target state and programming sequence diagram . . . . .2141
Figure 673. I3C CCC messages, as controller . . . . .2155
Figure 674. I3C broadcast ENTDAA CCC, as controller . . . . .2156
Figure 675. I3C broadcast, direct read and direct write RSTACT CCC, as controller . . . . .2157
Figure 676. I3C CCC messages, as target . . . . .2159
Figure 677. I3C broadcast ENTDAA CCC, as target. . . . .2160
Figure 678. I3C broadcast DEFTGTS CCC, as target. . . . .2161
Figure 679. I3C broadcast DEFGSPA CCC, as target . . . . .2162
Figure 680. I3C private read/write messages, as controller. . . . .2164
Figure 681. I3C private read/write messages, as target . . . . .2165
Figure 682. Legacy I2C read/write messages, as controller . . . . .2166
Figure 683. IBI transfer, as controller/target . . . . .2167
Figure 684. Hot-join request transfer, as controller/target . . . . .2168
Figure 685. Controller-role request transfer, as controller/target . . . . .2169
Figure 686. C-FIFO management, as controller . . . . .2170
Figure 687. TX-FIFO management, as controller . . . . .2172
Figure 688. RX-FIFO management, as controller . . . . .2174
Figure 689. S-FIFO management, as controller . . . . .2177
Figure 690. RX-FIFO management, as target on the I3C bus . . . . .2178
Figure 691.TX-FIFO management with I3C_TGTTDR, as target on the I3C bus . . . . .2180
Figure 692.TX-FIFO management by software without I3C_TGTTDR
if reading less bytes than TX-FIFO size, as target. . . . .		2182
Figure 693.I3C block diagram. . . . .2244
Figure 694.I3C (primary) controller state and programming sequence diagram. . . . .2249
Figure 695.I3C target state and programming sequence diagram, when initialized on an I3C bus
without a static address . . . . .		2254
Figure 696.I3C target state and programming sequence diagram when initialized on an I3C bus
with a static address, . . . . .		2255
Figure 697.I3C target state and programming sequence diagram, when initialized on an I2C bus
with a static address . . . . .		2256
Figure 698.I3C CCC messages, as controller . . . . .2270
Figure 699.I3C broadcast ENTDAA CCC, as controller . . . . .2271
Figure 700.I3C broadcast, direct read and direct write RSTACT CCC, as controller . . . . .2272
Figure 701.I3C CCC messages, as target . . . . .2274
Figure 702.I3C broadcast ENTDAA CCC, as target. . . . .2275
Figure 703.I3C broadcast DEFTGTS CCC, as target. . . . .2276
Figure 704.I3C broadcast DEFGRPA CCC, as target . . . . .2277
Figure 705.I3C private read/write messages, as controller. . . . .2279
Figure 706.I3C private read/write messages, as target . . . . .2280
Figure 707.Legacy I2C read/write messages, as controller . . . . .2281
Figure 708.Legacy I 2 C read/write messages, as target . . . . .2282
Figure 709.IBI transfer, as controller/target . . . . .2283
Figure 710.Hot-join request transfer, as controller/target . . . . .2284
Figure 711.Controller-role request transfer, as controller/target . . . . .2285
Figure 712.C-FIFO management, as controller . . . . .2286
Figure 713.TX-FIFO management, as controller . . . . .2288
Figure 714.RX-FIFO management, as controller . . . . .2290
Figure 715.S-FIFO management, as controller . . . . .2293
Figure 716.RX-FIFO management, as target on the I3C bus. . . . .2295
Figure 717.RX-FIFO management, as target on the I2C bus. . . . .2296
Figure 718.TX-FIFO management with I3C_TGTTDR, as target on the I3C bus. . . . .2298
Figure 719.TX-FIFO management with I3C_TGTTDR, as target on the I2C bus. . . . .2299
Figure 720.TX-FIFO management by software without I3C_TGTTDR
if reading less bytes than TX-FIFO size, as target. . . . .		2301
Figure 721.USART block diagram . . . . .2362
Figure 722.Word length programming . . . . .2366
Figure 723.Configurable stop bits . . . . .2368
Figure 724.TC/TXE behavior when transmitting . . . . .2370
Figure 725.Start bit detection when oversampling by 16 or 8. . . . .2371
Figure 726.usart_ker_ck clock divider block diagram. . . . .2374
Figure 727.Data sampling when oversampling by 16. . . . .2375
Figure 728.Data sampling when oversampling by 8. . . . .2376
Figure 729.Mute mode using Idle line detection . . . . .2383
Figure 730.Mute mode using address mark detection . . . . .2384
Figure 731.Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .2387
Figure 732.Break detection in LIN mode vs. Framing error detection. . . . .2388
Figure 733.USART example of synchronous master transmission. . . . .2389
Figure 734.USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		2389
Figure 735.USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		2390
Figure 736. USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		2391
Figure 737. ISO 7816-3 asynchronous protocol . . . . .2393
Figure 738. Parity error detection using the 1.5 stop bits . . . . .2395
Figure 739. IrDA SIR ENDEC block diagram. . . . .2399
Figure 740. IrDA data modulation (3/16) - normal mode . . . . .2399
Figure 741. Transmission using DMA . . . . .2401
Figure 742. Reception using DMA . . . . .2402
Figure 743. Hardware flow control between two USARTs. . . . .2402
Figure 744. RS232 RTS flow control . . . . .2403
Figure 745. RS232 CTS flow control . . . . .2404
Figure 746. LPUART block diagram . . . . .2451
Figure 747. LPUART word length programming . . . . .2455
Figure 748. Configurable stop bits . . . . .2457
Figure 749. TC/TXE behavior when transmitting . . . . .2459
Figure 750. lpuart_ker_ck clock divider block diagram . . . . .2463
Figure 751. Mute mode using Idle line detection . . . . .2467
Figure 752. Mute mode using address mark detection . . . . .2468
Figure 753. Transmission using DMA . . . . .2470
Figure 754. Reception using DMA . . . . .2471
Figure 755. Hardware flow control between two LPUARTs. . . . .2472
Figure 756. RS232 RTS flow control . . . . .2472
Figure 757. RS232 CTS flow control . . . . .2473
Figure 758. SPI block diagram . . . . .2507
Figure 759. Full-duplex single master/ single slave application. . . . .2511
Figure 760. Half-duplex single master/ single slave application . . . . .2512
Figure 761. Simplex single master / single slave application
(master in transmit-only / slave in receive-only mode) . . . . .		2513
Figure 762. Master and three independent slaves connected in star topology . . . . .2514
Figure 763. Multimaster application . . . . .2515
Figure 764. Scheme of NSS control logic . . . . .2517
Figure 765. Data flow timing control (SSOE = 1, SSOM = 0, SSM = 0) . . . . .2517
Figure 766. NSS interleaving pulses between data (SSOE = 1, SSOM = 1, SSM = 0). . . . .2518
Figure 767. Data clock timing diagram . . . . .2520
Figure 768. Data alignment when data size is not equal to 8, 16 or 32 bits . . . . .2521
Figure 769. TI mode transfer . . . . .2531
Figure 770. Optional configurations of the slave behavior when an underrun condition is detected . . . . .2533
Figure 771. SAI functional block diagram . . . . .2557
Figure 772. Audio frame . . . . .2560
Figure 773. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .2563
Figure 774. FS role is start of frame (FSDEF = 0). . . . .2564
Figure 775. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .2565
Figure 776. First bit offset . . . . .2565
Figure 777. Audio block clock generator overview . . . . .2567
Figure 778. PDM typical connection and timing. . . . .2571
Figure 779. Detailed PDM interface block diagram . . . . .2572
Figure 780. Start-up sequence . . . . .2573
Figure 781. SAI_ADR format in TDM mode, 32-bit slot width . . . . .2574
Figure 782. SAI_ADR format in TDM mode, 16-bit slot width . . . . .2575
Figure 783. SAI_ADR format in TDM mode, 8-bit slot width . . . . .2576
Figure 784. AC'97 audio frame . . . . .2579
Figure 785. SPDIF format . . . . .2580
Figure 786. SAI_xDR register ordering . . . . .2581
Figure 787. Data companding hardware in an audio block in the SAI . . . . .2584
Figure 788. Tristate strategy on SD output line on an inactive slot . . . . .2586
Figure 789. Tristate on output data line in a protocol like I2S . . . . .2587
Figure 790. Overrun detection error . . . . .2588
Figure 791. FIFO underrun event . . . . .2588
Figure 792. CAN subsystem . . . . .2622
Figure 793. FDCAN block diagram . . . . .2624
Figure 794. Bit timing . . . . .2626
Figure 795. Transceiver delay measurement . . . . .2631
Figure 796. Pin control in bus monitoring mode . . . . .2632
Figure 797. Pin control in loop-back mode . . . . .2635
Figure 798. CAN error state diagram . . . . .2636
Figure 799. Message RAM configuration . . . . .2637
Figure 800. Standard message ID filter path . . . . .2640
Figure 801. Extended message ID filter path . . . . .2641
Figure 802. USB peripheral block diagram . . . . .2688
Figure 803. Packet buffer areas with examples of buffer description table locations . . . . .2694
Figure 804. Block diagram of debug support infrastructure . . . . .2734
Figure 805. JTAG TAP state machine . . . . .2738
Figure 806. CoreSight topology . . . . .2755

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