81. Revision history

Chapter 87.1.0
Table 903. Document revision history

DateRevisionChanges
28-Nov-20241Initial release.
27-Jan-20252Updated Table 3: Peripheral register boundary addresses , Table 28: Peripheral indexes in IAC , Table 55: Functionalities depending on system operating mode , Table 63: PWR register map and reset values , Table 762: Ethernet peripheral pins , and Table 852: Ethernet MAC register map and reset values .
Updated Section 3.1: Key security features , Section 13.2: PWR main features , Section 13.5: Power supply supervision , Section 13.5.8: Battery voltage thresholds , Section 13.9.6: PWR backup domain control register 1 (PWR_BDCR1) , Section 14.6.9: General clock concept overview , Section 20: Neural-ART accelerator™ (NPU) and its subsections, Section 57.7.19: TIM15 alternate function register 1 (TIM15_AF1) , and Section 57.8.17: TIMx alternate function register 1 (TIMx_AF1)(x = 16 to 17) .
Updated Figure 15: Power control block diagram and Figure 28: V 08CAP thresholds .
Minor text edits across the whole document.

Table 903. Document revision history

DateRevisionChanges
15-Dec-20253

Document scope extended to STM32N645/655xx devices.

Updated Section 2.1.2: Bus architecture , Section 2.2.2: NPU_NIC network interconnect , Section 7.3: RISAF implementation , Configuring base regions in RISAF , Section 10.3.1: Internal SRAM features , Section 10.3.2: FLEXRAM control , Section 12.3: CACHEAXI implementation , Section 12.4.8: AXI traffic to slave SRAM port , Section 12.7.1: CACHEAXI control register 1 (CACHEAXI_CR1) , Section 13.5.5: V DDCORE monitoring , Section 14.5.3: NRST reset , Section 26.3.3: CRC operation , Section 29.5.8: A single XSPI drives two external memories , Section 32.6.5: ADC configuration register 2 (ADC_CFGR2) , Section 37.5.3: High-resolution CSI2 camera and DCMIPP , Section 39.4.1: DCMIPP common configuration , Section 39.14.15: DCMIPP common frame counter register (DCMIPP_CMFRCR) , Section 39.14.18: DCMIPP common status register 2 (DCMIPP_CMSR2) , Section 39.14.19: DCMIPP common interrupt clear register (DCMIPP_CMFCR) , Section 39.14.98: DCMIPP Pipe1 status register (DCMIPP_P1SR) , Section 39.14.99: DCMIPP Pipe1 interrupt clear register (DCMIPP_P1FCR) , Section 45.1: VENC introduction , Section 47.7.1: RNG control register (RNG_CR) , Section 51.6.5: MCE illegal access interrupt enable register (MCE_IAIER) , Section 52.3.7: PKA error management , Section 52.4.1: Introduction , Section 62.2: TAMP main features , Section 68.6.5: SAI slot register (SAI_ASLOTR) , and Section 68.6.13: SAI slot register (SAI_BSLOTR) .

Register SYSCFG_VDDIOxCCCR replaced by registers SYSCFG_VDDIO2CCCR, SYSCFG_VDDIO3CCCR, SYSCFG_VDDIO4CCCR, and SYSCFG_VDDIO5CCCR. Register SYSCFG_VDDIOxCCSR replaced by registers SYSCFG_VDDIO2CCSR, SYSCFG_VDDIO3CCSR, SYSCFG_VDDIO4CCSR, and SYSCFG_VDDIO5CCSR. Replaced timx_tgo_cktim and timx_tgo2_cktim, respectively, by timx_trgo_cktim and timx_trgo2_cktim in Section 32: Analog-to-digital converters (ADC) .

Internal signals gpu2d_irq and gpu2d_irqsys renamed, respectively, gpu2d_it and gpu2d_sys_it in Section 44: Neo-Chrom graphic processor (GPU2D) .

Updated text, tables and figures in Section 64: Improved inter-integrated circuit (I3C) and Section 76: Ethernet (ETH): gigabit media access control (GMAC) with DMA controller .

Updated Table 1: Memory map based on IDAU mapping , Table 2: Memory map and peripheral register boundary addresses , Table 3: Peripheral register boundary addresses , Table 18: OTP fuse description (lower OTP region) , Table 20: RISUP indexes , Table 24: RISAF resource assignment , Table 28: Peripheral indexes in IAC , Table 33: Internal SRAM features , Table 50: PWR input/output signals connected to package pins or balls , Table 64: RCC input/output signals connected to package pins or balls , Table 72: Peripheral clock distribution summary , Table 82: SYSCFG register map and reset values , Table 83: Connectivity matrix , Table 130: GFXTIM internal signals , Table 132: Graphic timer interrupt requests , Table 134: STM32N6x5/x7xx vector table , Table 204: Use cases , Table 241: ADC1/2 interconnection , Table 364: DCMIPP interrupts , and Table 398: RNG configurations .

Updated Figure 10: FLEXMEM versus retention , Figure 17: System supply configurations , Figure 58: Clock distribution for XSPIs and MCE1/2/3 , Figure 131: Neural-ART 14 integration , Figure 140: GFXTIM block diagram , Figure 177: Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) , Figure 178: Synchronous multiplexed write mode waveforms - PSRAM (CRAM) , figures 220 to 224, Figure 263: ADC1 connectivity , Figure 264: ADC2 connectivity , Figure 387: Camera subsystem clock diagram , Figure 541: Combined PWM mode on channel 1 and 3 , Figure 736: Edge-aligned PWM waveforms (ARR = 8) , and Figure 985: SOF connectivity (SOF trigger output to TIM and ITR1 connection) .

Minor text edits across the whole document.

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