77. Hardware debug port (HDP)

77.1 HDP introduction

The hardware debug port (HDP) is used to observe internal signals, thanks to some multiplexers: up to 16 signals for each of 8-bit output.

77.2 HDP functional description

HDP main features:

• • 8 output signals
• • 15 input signals for each output signal
• • 8 software programmable signals for pinout agnostic code debugging (one for each output signal)
• • output disabling by security signal

The HDP is mainly composed of eight multiplexers under software control through HDP_CTRL. Each multiplexer can output an observed signal on an output pin. The observed signal is selected among a pool of 15 interesting signals for each multiplexer. For each multiplexer, a software programmable signal can be observed.

Table 853 presents for each of the muxes which signal can be selected.

The HDP value at the main multiplexer output can be read by software thanks to HDP_VAL. During the debug, it is often useful to output some signals that are controlled by the software: they can be used to precisely observe a code sequence, or to indicate the current executed task. The debug set #15 is reserved for this purpose: it provides on HDP outputs, the HDP_GPOVAL value. This register is associated with HDP_GPOSET and HDP_GPOCLR, used to toggle signals without a read-modify-write sequence.

Some debug sets expose internal data that require to be protected: HDPEN signal, when low, forces low all HDP block outputs.

Note: Internal signals may toggle at a rate higher than pins can support: their observability may then be compromised.

Table 853. Muxing of HDP signals

Table 853. Muxing of HDP signals (continued)

77.3 HDP block diagram

Figure 1074. HDP block diagram

77.4 HDP register description

77.4.1 HDP control register (HDP_CTRL)

Address offset: 0x000

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 EN: Enable HDP, valid if enabled in BSEC

77.4.2 HDP multiplexer control register (HDP_MUX)

Address offset: 0x004

Reset value: 0x0000 0000

Bits 31:0 MUXy[3:0] : Select the HDPy output among the 16 available signals (y = 7 to 0)

77.4.3 HDP read back value register (HDP_VAL)

Address offset: 0x010

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 HDPVAL[7:0] : Value of the HDP signals

77.4.4 HDP general-purpose output set register (HDP_GPOSET)

Address offset: 0x014

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 HDPGPOSET[7:0] : When a bit is written to 1, the corresponding HDP GPO is set
Writing a bit to 0 has no effect.

77.4.5 HDP general purpose output clear register (HDP_GPOCLR)

Address offset: 0x018

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 HDPGPOCLR[7:0] : When a bit is written to 1, the corresponding HDP GPO is cleared. Writing a bit to 0 has no effect.

77.4.6 HDP general purpose output value register (HDP_GPOVAL)

Address offset: 0x01C

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 HDPGPOVAL[7:0] : When written, define the value of the HDP GPO. When read, provide the current GPO value.

77.4.7 HDP register map

Table 854. HDP register map and reset values

Table 854. HDP register map and reset values

Refer to Section 2.3 for the register boundary addresses.