74. USB HS PHY controller (USBPHYC)

There are two near-identical instances of USBPHYC

• • USBPHYC1 (associated with OTG1)
• • USBPHYC2 (associated with OTG2)
  • – includes one additional control bit concerning hardware debug (HDP)

For a more complete system view of the USB controllers and PHYs, refer to the block diagram of the main OTG controller.

74.1 Introduction

This controller handles general and miscellaneous control of the OTG PHYs.

Note that the main UTMI+ interface for protocol including battery charging features are all controlled by the OTG.

74.2 USBPHYC main features

The USBPHYC allows

• • PLL configuration
• • Trimming of the electrical parameters (should this be required)

74.3 USBPHYC implementation

Table 748. USBPHYC implementation

1. This bit is reserved in USBPHYC1.

74.4 USBPHYC functional description

74.4.1 USBPHYC block diagram

USBPHYC is a small satellite controller allowing full control of a HS PHY block. Refer to the block diagram of the main OTG controller.

74.4.2 USBPHYC reset and clocks

USBPHYC instances can be reset from the RCC using bits

• • OTGPHY1RST
• • OTGPHY2RST

USBPHYC uses a single AHB clock.

74.4.3 USBPHYC programmable parameters

In addition to the selection of the OTGPHY reference clock frequency, some register bits are used to control the trimming of the electrical parameters of the OTGPHY.

74.4.4 USBPHYC trimming of electrical parameters

Some parameters inside the OTGPHYC can be adjusted by control bits in USBPHYC_TRIM1CR and USBPHYC_TRIM2CR registers. Those adjustments must be programmed while the OTGPHY is under reset.

The adjustable parameters are: the internal PLL, the disconnect threshold, the squelch threshold, the data detection threshold, the transmitter high-speed crossover point, the FS/LS source impedance, the HS DC voltage level, the HS transmitter rise/fall times, the driver source impedance, the HS transmitter pre-emphasis current, the HS transmitter pre-emphasis duration.

The default values in USBPHYC_TRIM1CR and USBPHYC_TRIM2CR registers correspond to the recommended values.

74.5 USBPHYC registers

74.5.1 USBPHYC control register (USBPHYC_CR)

Address offset: 0x0

Reset value: 0x0001 0015

Bit 31 SELOTGDBG : Select OTG debug

Selects the set of USB signals that are routed to the hardware debug port (HDP)

0: Debug signals from OTGPHY1 are routed to the HDP (default)

1: Debug signals from OTGPHY2 are routed to the HDP

Note: This bit is only available in USBPHYC2.

Bits 30:18 Reserved, must be kept at reset value.

Bit 17 DRVVBUS0 : Drive \( V_{BUS} \) 0

Control bit for the \( V_{BUS} \) valid comparator

0: The \( V_{BUS} \) valid comparator is OFF in Suspend and Sleep modes (default)

1: The \( V_{BUS} \) valid comparator is ON in Suspend and Sleep modes

Bit 16 OTGDISABLE0 : OTG disable 0

Disable control bit for the \( V_{BUS} \) valid comparator

0: The \( V_{BUS} \) valid comparator is ON in normal mode. The state of the \( V_{BUS} \) valid comparator in Suspend and Sleep modes depends on DRVVBUS0 setting. The session valid comparator is ON.

1: The \( V_{BUS} \) valid comparator is powered down. The session valid comparator is ON (default)

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 FSEL[2:0] : Frequency selection

PHY refclk speed setting:

000: 19.2 MHz

001: 20 MHz (default)

010: 24 MHz

Others: reserved

Bit 3 Reserved, must be kept at reset value.

Bit 2 CMN : Controls the power down of analog blocks during Suspend and Sleep.

0: PHY clocks are kept active during Suspend and Sleep mode (with the exception of PHYCLK). PLL is on. Requires to keep the PHY reference clock on.

1: PHY clocks are off during Suspend and Sleep mode. PLL is off. (default)

Bit 1 AUTORSMENB1 : Auto-resume mode enable

Enables auto-resume logic in so that the PHY automatically responds to a remote wake-up without initial involvement of the Host controller.

0: Auto-resume disabled (default)

1: A pulse on this bit prior to enabling the retention mode enables the auto-resume mode.

Bit 0 RETENABLEN1 : Retention mode enable (active low)

0: Retention mode enabled

1: Retention mode disabled (default)

74.5.2 USBPHYC trimming 1 register (USBPHYC_TRIM1CR)

Address offset: 0x4

Reset value: 0x299E D6F0

Bit 31 Reserved, must be kept at reset value.

Bits 30:29 TXRESTUNE[1:0]: USB source impedance adjustment

In some applications there can be significant serial resistance on the DP and DM paths between the transceiver and the cable. This bitfield adjusts the driver source impedance to compensate for added serial resistance on the USB.

Note: Any setting other than the default one can result in source impedance variations across process, voltage and temperature that do not meet USB2.0 specification limits.

11: Source impedance is decreased by approximately 5.6 Ω

10: Source impedance is decreased by approximately 3.6 Ω

01: Nominal

00: Source impedance is increased by approximately 1.3 Ω

This is a strapping option that must be set prior to USBPHYC reset. It must remain static during normal operation.

Bits 28:27 TXRISETUNE[1:0]: HS transmitter rise/fall time adjustment

It adjusts the rise/fall times of the high-speed waveform.

11: -8.1%

10: -7.2%

01: Nominal

00: +5.4%

This is a strapping option that must be set prior to USBPHYC reset. It must remain static during normal operation.

It adjusts the high speed DC level voltage.

1111: +24%

1110: +22%

1101: +20%

1100: +18%

1011: +16%

1010: +14%

1001: +12%

1000: +10%

0111: +8%

0110: +6%

0101: +4%

0100: +2%

0011: Nominal

0010: -2%

0001: -4%

0000: -6%

When the PHY is in a Host role, any adjustment of the HS transmit voltage level tune bits (TXVREF tune[3:0]) might also necessitate a change to the HS disconnect detection threshold (COMPDISTUNE[2:0]).

This is a strapping option that must be set prior to USBPHYC reset. It must remain static during normal operation.

It adjusts the low- and full-speed single-ended source impedance while driving high. The following adjustment values are based on nominal process, voltage and temperature.

1111: -10.7%

1110: Reserved

1101: Reserved

1100: Reserved

1011: Reserved

1010: Reserved

1001: Reserved

1000: Reserved

0111: -5.6%

0110: Reserved

0101: Reserved

0100: Reserved

0011: Nominal

0010: Reserved

0001: +6.5%

0000: +14%

This is a strapping option that must be set prior to USBPHYC reset. It must remain static during normal operation.

It adjusts the voltage at which DP and DM signals crossover while transmitting in high-speed mode.

11: Nominal

10: +15 mV

01: -15 mV

00: Reserved

This is a strapping option that must be set prior to USBPHYC reset. It must remain static during normal operation.

It adjusts the voltage level for the V _BUS valid threshold.

111: +12%

110: +9%

101: +6%

100: +3%

011: Nominal

010: -3%

001: -6%

000: -9%

This is a strapping option that must be set prior to USBPHYC reset. It must remain static during normal operation.

It adjusts the threshold voltage level (V _{DAT_REF} ) used to detect data during charger type detection.

11: -20%

10: -10%

01: Nominal

00: +10%

This is a strapping option that must be set prior to USBPHYC reset. It must remain static during normal operation.

It adjusts the voltage level for the threshold used to detect valid high speed data.

111: -20%

110: -15%

101: -10%

100: -5%

011: Nominal

010: +5%

001: +10%

000: +15%

This is a strapping option that must be set prior to USBPHYC reset. It must remain static during normal operation.

It adjusts the voltage level for the threshold used to detect a disconnect event at the Host.

111: +12%

110: +10%

101: +7%

100: +3%

011: Nominal

010: -4%

001: -6%

000: -9%

When the PHY is in a Host role, any adjustment of the HS transmit voltage level tune bits (TXVREFTUNE[3:0]) might also necessitate a change to the HS disconnect detection threshold (COMPDISTUNE[2:0]).

This is a strapping option that must be set prior to USBPHYC reset. It must remain static during normal operation.

1111: 5.5×

1110: 5×

1101: 4.5×

1100: 4×

1011: 4.5×

1010: 4×

1001: 3.5×

1000: 3×

0111: 3.5×

0110: 3×

0101: 2.5×

0100: 2×

0011: 2.5×

0010: 2×

0001: 1.5×

0000: 1×

This is a strapping option that must be set prior to USBPHYC reset. It must remain static during normal operation.

11: 2.0×

10: 1.5×

01: 1.0×

00: 0.5×

This is a strapping option that must be set prior to USBPHYC reset. It must remain static during normal operation.

74.5.3 USBPHYC trimming 2 register (USBPHYC_TRIM2CR)

Address offset: 0x8

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 TXPREEMPULSE TUNE: HS transmitter pre-emphasis duration control

This bit controls the duration for which the HS pre-emphasis current is sourced onto DM or DP. The HS transmitter pre-emphasis duration is defined in terms of unit amounts. One unit of pre-emphasis duration is approximately 580 ps and is defined as 1× pre-emphasis duration. This bit is valid only if TXPREEMPAMPTUNE[0] or TXPREEMPAMPTUNE[1] is set to 1.

1: 1×, short pre-emphasis current duration

0: 2×, long pre-emphasis current duration

This is a strapping option that must be set prior to USBPHYC reset. It must remain static during normal operation.

Bits 1:0 TXPREEMPAMPTUNE[1:0]: HS transmitter pre-emphasis current control

This bitfield controls the amount of current sourced to DP and DM after a J-to-K or K-to-J transition. The HS transmitter pre-emphasis current is defined in terms of unit amounts. One unit amount is approximately 600 µA and is defined as 1× pre-emphasis current.

11: HS transmitter pre-emphasis circuit sources 3× pre-emphasis current

10: HS transmitter pre-emphasis circuit sources 2× pre-emphasis current

01: HS transmitter pre-emphasis circuit sources 1× pre-emphasis current

00: HS transmitter pre-emphasis is disabled

This is a strapping option that must be set prior to USBPHYC reset. It must remain static during normal operation.

74.5.4 USBPHYC register map

Table 749. USBPHYC register map and reset values

Refer to Section 2.3 for the register boundary addresses.