29. XSPI I/O manager (XSPIM)

29.1 XSPIM introduction

The XSPI I/O manager is a low-level interface, enabling an efficient XSPI pin assignment with a full I/O matrix (before alternate function map), and multiplex of single/dual/quad/octal/16-bit SPI interfaces over the same bus.

29.2 XSPIM main features

• • Supports up to two single/dual/quad/octal/16-bit SPI interfaces
• • Supports up to two ports for pin assignment
• • Supports high-speed interfaces
• • Manages up to three XSPIs

29.3 XSPIM implementation

Table 202 describes the XSPIM implementation.

Table 202. XSPIM implementation

29.4 XSPIM functional description

29.4.1 XSPIM block diagram

The block diagram of the XSPI I/O manager is shown in Figure 216 .

Figure 216. XSPIM block diagram

29.4.2 XSPIM input/output pins

Table 203. XSPIM input/output pins

1. x = 1 to 2.

29.4.3 XSPIM matrix

The XSPI I/O manager matrix allows the user to set a premapping of functions:

• • XSPI1 mapped to Port 1, with XSPI2 mapped to Port 2 (direct mode)
• • XSPI1 mapped to Port 2, with XSPI2 mapped to Port 1 (swapped mode)
• • XSPI1 and XSPI2 both mapped to Port 1, with arbitration (multiplexed mode), and XSPI3 mapped to Port 2
• • XSPI1 and XSPI2 both mapped to Port 2, with arbitration (multiplexed mode), and XSPI3 mapped to Port 1

Note: There is no possibility to use mixed combinations of signals (like NCS of XSPI1 with data of XSPI2).

When several I/O pins have the same configuration and are enabled at the same time, the result can be unpredictable.

In the default out-of-reset configuration, all the XSPI1 and XSPI2 signals are mapped, respectively, on Port 1 and on Port 2.

The configuration can be changed only when all XSPIs are disabled.

29.4.4 XSPIM multiplexed mode

When this mode is set, the XSPIs are time-multiplexed over the same bus. They get the ownership of the bus (in turn) through a request/acknowledge protocol with REQ/ACK signals.

The time-multiplexing is enabled by setting the MUXEN bit in the configuration register XSPIM_CR.

The fairness counter (MAXTRAN) of each XSPI can be used to manage the maximum duration for which a given XSPI takes the bus: this feature ensures the maximum bus access latency for the other XSPI(s). When one XSPI releases the bus, a round-robin arbitration phase occurs: when another XSPI requests the bus, it gets it.

When the multiplexed mode is enabled, either the fairness counter or the refresh timeout counter of both XSPI interfaces must be activated.

Each XSPI delivers two NCS signals (NCS1, NCS2). In multiplexed modes, the active NCS signal is the one of the XSPI owning the bus. Only XSPI_n_IOs, XSPI_n_DQS and XSPI_n_CLK / XSPI_n_NCLK are multiplexed.

When the multiplexed mode is used, only clock mode 0 is supported on the XSPIs.

Due to arbitration and bus sharing, the auto polling interval time of the XSPI, when used, can be increased.

Minimum switching duration

The minimum number of cycles needed to switch from an XSPI to another can be configured. This guarantees a latency between the falling edge of the REQ signal of the active XSPI (the active one releases the bus), and the rising edge of the ACK signal to the requesting XSPI (the bus is granted to the requesting one).

The duration is defined by the REQ2ACK_TIME field in the XSPIM_CR register.

29.5 Use cases description

The following table summarizes the use cases corresponding to IO manager modes.

Table 204. Use cases

29.5.1 XSPIs direct octal mode

This is the baseline mode: each XSPI independently drives the corresponding port and high-speed interface. There is no multiplexing.

The configuration selection signal selects the signals used for each high speed interface. These signals come from the XSPI_CR and XSPI_CALxxx register outputs.

Alternate function signals can be routed on NCS2 pins (they are not used for the XSPI bus), nclk clocks are requested in case of 1.8 V HyperBus memory type.

This mode is selected by default through bits XSPIM_CR[1:0].

Figure 217. XSPI direct octal mode

29.5.2 XSPI direct 16-bit mode

This is the baseline mode, completely similar to XSPI octal direct mode, where each XSPI directly drives the corresponding port (XSPI1 connected to Port 1, XSPI2 connected to Port 2). Two DQS (1 per byte) are needed for each 16-bit port, when available.

Figure 218. XSPI direct 16-bit mode

29.5.3 XSPI dual-octal mode

This mode is equivalent to XSPI direct mode, but, for simplicity, only one XSPI interface is represented. Two external octal memories are accessed in parallel, similarly to the dual-quad mode implemented with octal interfaces.

Figure 219. XSPI dual-octal mode

29.5.4 XSPI swapped mode

This mode is similar to XSPI direct mode, but the ports are swapped, to help I/O mapping. The mode is selected by bits XSPIM_CR[1:0].

If XSPIM.CR[0] or XSPIM.CR[1] is toggled in application, XSPI.DCR2 or XSPI.CCR must be written, so that the calibration of the high speed interface is launched according to the new XSPI using it.

Note: In swapped mode, the XSPI2 can be configured in 16-bit mode, and the XSPI1 can be configured in octal mode, to connect an external 16-bit memory on Port 1, and to connect in a concurrent way an octal external memory connected to Port 2 of the I/O manager.

Figure 220. XSPI swapped (octal) mode

29.5.5 Two XSPIs multiplexed mode to Port 1 accessing two external memories, and the third XSPI accessing Port 2

If only one output port is used to access two memories, alternate function signals can be routed to pins corresponding to the other port. This mode is selected by bits XSPIM_CR[1:0].

The arbiter in the IO manager selects XSPI1 or XSPI2 to own the octal-SPI bus according to the existing transfer requests and status of the two MAXTRAN fairness counters.

The external memories can be on separate chips, or embedded in a single multichip package. In this case, each memory requests a dedicated Chip select, selected according to the CSSEL control of the XSPI currently owning the bus.

The configuration signals of the high speed interface toggle when the corresponding XSPI is selected, because the timing characteristics of the two memories can be different.

Figure 221. XSPI multiplexed mode to Port1

29.5.6 Two XSPIs multiplexed mode to Port 2 accessing two external memories, and the third XSPI accessing Port 1

This is similar to XSPI multiplexed mode to Port 1, but the target is Port 2. This mode is selected by bits XSPIM_CR[2:1].

Figure 222. XSPI multiplexed (octal and dual-octal) mode to Port 2

Note: It is possible to connect a 16-bit memory on Port 1, whereas Port 2 uses multiplexing mode on two octal memories.

29.5.7 XSPI1 and XSPI2 drive a single external memory

This is similar to XSPIs multiplexed mode to Port 1, but in this case only one external memory is present. Both CSSEL controls must target the same NCS (NCS1 in Figure 223).

Figure 223. XSPI1 and XSPI2 drive a single external memory (octal mode)

This use case is valid even when Port 2 is used instead of Port 1, and also possible with XSPI1 and XSPI2 interfacing a 16-bit memory (connecting XSPIM_P1_DQS1 to the memory).

29.5.8 A single XSPI drives two external memories

This is a subset of direct mode and corresponds to semi-dynamic switching. There are two target memories, but the arbiter is not used. The software must set the XSPI1 chip selector (bit 24 of the XSPI_CR register) each time the target memory changes.

The baseline use case boots on flash (memory1) and then switches to SRAM (memory2) for the rest of the application.

Figure 224. Single XSPI driving two external memories

This use case shows a configuration using XSPI1 on Port 1. It is also valid if the instance is XSPI2 instead of XSPI1, but with MODE = 1. The use case is also valid when Port 2 is used instead of Port 1, by configuring MODE bit according to the instance (XSPI1 or XSPI2) driving the two external memories.

29.6 XSPIM registers

29.6.1 XSPIM control register (XSPIM_CR)

Address offset: 0x0000

Reset value: 0x0000 0000

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 REQ2ACK_TIME[7:0] : REQ to ACK time

In Multiplexed mode (MUXEN = 1), this field defines the time between two transactions.

The value is the number of XSPI clock cycles - 1

Bits 15:7 Reserved, must be kept at reset value.

Bit 6 CSSEL_OVR_O2 : Chip select selector override setting for XSPI2

0: XSPI2 can only use NCS1 (accesses using NCS2 are ignored)

1: XSPI2 can only use NCS2 (accesses using NCS1 are ignored)

Bit 5 CSSEL_OVR_O1 : Chip select selector override setting for XSPI1

0: XSPI1 can only use NCS1 (accesses using NCS2 are ignored)

1: XSPI1 can only use NCS2 (accesses using NCS1 are ignored)

Bit 4 CSSEL_OVR_EN : Chip select selector override enable

0: CSSEL_OVR_O1 and CSSEL_OVR_O2 bit values are ignored, the chip select signals from OCTOSPIs or XSPIs are transmitted unconditionally

1: CSSEL_OVR_O1 and CSSEL_OVR_O2 bit values are taken into account

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 MODE : XSPI multiplexing mode

0: if MUXEN = 0 direct mode, if MUXEN = 1 arbitration mode to output Port 1

1: if MUXEN = 0 swapped mode, if MUXEN = 1 arbitration mode to output Port 2

Bit 0 MUXEN : Multiplexed mode enable

This bit enables the multiplexing of the two XSPIs.

0: No multiplexing, hence no arbitration

1: XSPI1 and XSPI2 are multiplexed over the same bus

29.6.2 XSPIM register map

Table 205. XSPIM register map and reset values

Refer to Section 2.3: Memory organization for the register boundary addresses.