27. Flexible memory controller (FMC)

The flexible memory controller (FMC) includes three memory controllers:

• • the NOR/PSRAM memory controller
• • the NAND memory controller
• • the synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller

27.1 FMC main features

The FMC functional block makes the interface with: synchronous and asynchronous static memories, SDRAM memories, and NAND flash memory. Its main purposes are:

• • to translate AXI transactions into the appropriate external device protocol
• • to meet the access time requirements of the external memory devices

All external memories share the addresses, data and control signals with the controller. Each external device is accessed by means of a unique Chip Select. The FMC performs only one access at a time to an external device.

The main features of the FMC are the following:

• • Interface with static-memory mapped devices including:
  • – Static random access memory (SRAM)
  • – NOR flash memory/One NAND flash memory
  • – PSRAM (4 memory subregions)
  • – Ferroelectric RAM (FRAM)
  • – NAND flash memory with ECC hardware to check up to 8 Kbytes of data
• • Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• • Burst mode support for faster access to synchronous devices such as NOR flash memory, PSRAM and SDRAM
• • Programmable continuous clock output for asynchronous and synchronous accesses
• • 8-, 16- or 32-bit wide data bus
• • Independent chip-select control for each memory region
• • Independent configuration for each memory region
• • Write enable and byte lane select outputs for use with PSRAM, SRAM and SDRAM devices
• • External asynchronous wait control

At startup the FMC pins must be configured by the user application. The FMC input/output pins which are not used by the application can be used for other purposes.

After reset, the FMC is disabled. Once all the used memory controllers are configured, the FMC must be enabled by setting the FMCEN bit.

The FMC registers that define the external device type and associated characteristics are set at boot time and do not change until the next reset or power-up. If some registers have to be re-configured, the FMC must be disabled (FMCEN bit set to 0x0). However, only few bits can be changed on the fly:

• • FMCEN bit
• • ECCEN and PBEN bits in FMC_PCR register
• • FMC_CSQICR and FMC_CSQIER register bits
• • FMC command sequencer registers and FMC BCH registers
• • WEN bit in the FMC_PCR register
• • MODE[2:0], DS1/DS2, NRFS[3:0] and MRD[13:0] bits in FMC_SDCMR register
• • REIE and CRE bits in the FMC_SDRTR register.

If some parameters have to be modified while the FMC is enabled, the FMC must be first disabled so that no further access is allowed to any memory controller during register modification. Once all needed configurations are updated, enable the FMC as follows:

1. 1. Disable FMC by resetting the FMCEN bit.
2. 2. Wait ISOST[1:0] bits in FMC_SR register to be set to 0b11.
3. 3. Wait until PEF flag is set in the FMC_SR register.
4. 4. Program the registers with new values.
5. 5. Enable the FMC by setting the FMCEN bit.

When the SDRAM controller is available, if the SDCLK clock ratio or refresh rate has to be modified after the initialization phase, the following procedure must be followed.

1. 1. Stop by software, the AXI traffic from/to the SDRAM devices only.
2. 2. Put all the SDRAM devices in self refresh and wait for the CMDOK command completion flag.
3. 3. Change the clock ratio to the new value.
4. 4. Send a normal mode command (NRM) to exit from SR and wait for the CMDOK command completion flag.
5. 5. Send a load mode register command (LMR) as needed to update devices timing (optional)
6. 6. Resume the AXI traffic to SDRAM devices.

27.2 FMC implementation

Table 146. FMC features

27.3 FMC block diagram

The FMC consists of the following main blocks:

• • The NOR flash/PSRAM/SRAM controller
• • The NAND controller
• • The SDRAM controller
• • The AXI interface
• • The AHB interface (including the FMC configuration registers)

The block diagram is shown in the below figure.

Figure 160. FMC block diagram

27.4 FMC internal signals

Table 147 gives the list of FMC internal signals. FMC pins (or external signals) are described in Section 27.8.1: External memory interface signals .

Table 147. FMC internal signals

27.5 AHB interface

The AHB slave interface allows internal CPUs to configure the FMC registers.

The AHB clock (HCLK) is the reference clock for the FMC register accesses.

The FMC registers must be accessed by words (32 bits). For non 32-bit AHB accesses, FMC does not return an AHB bus error and the register value can be corrupted.

27.6 AXI interface

The AXI slave interface allows internal CPUs and other bus master peripherals to access the external memories.

AXI transactions are translated into the external device protocol. As the AXI data bus is 64-bit wide, the AXI transactions might be split into several consecutive 32- or 16- or 8-bit accesses according to data size accesses.

The FMC generates an AXI slave error when one of the following conditions is met:

• • When reading or writing to an FMC memory region (memory region 1 to 4) which is not enabled
• • When reading or writing to any FMC memory region while the FMC is disabled (FMCEN bit is reset)
• • When reading or writing by the command sequencer to NAND memory region while it is disabled
• • When reading or writing to the NOR flash memory region while the MBKEN bit is reset in the FMC_BCRx register
• • When writing to a write-protected SDRAM device (WP bit set in the SDRAM_SDCRx register)
• • When the SDRAM address range is violated (access to a reserved address range)
• • When reading or writing to an SDRAM device with the SDEN bit cleared in the FMC_SDCRx register

The FMC generates an AXI decoder error in the following conditions:

• • When ADDR[31:28] address bits are not supported by the FMC memory region base address following the BMAP[1:0] bits configuration
• • and when an access to an SDRAM or a NAND memory region is performed while the SDRAM or the NAND controller is not present.

The kernel clock for the FMC is the asynchronous fmc_ker_ck clock (refer the Reset and Clock control (RCC) section for details on fmc_ker_ck clock source selection).

27.6.1 Supported memories and transactions

General transaction rules

The requested AXI transaction data size can be 8-, 16-, 32- or 64-bit wide whereas the accessed external device has a fixed data width. This may lead to inconsistent transfers.

Therefore, some simple transaction rules must be followed:

• • AXI transaction size and memory data size must be equal to prevent issues from occurring.

• • AXI transaction size is greater than the memory size:

In this case, the FMC splits the AXI transaction into smaller consecutive memory accesses to meet the external data width.

• • AXI transaction size is smaller than the memory size:

The transfer may or not be consistent depending on the type of external device:

• – Accesses to devices that have the byte select feature (SRAM, ROM, PSRAM, SDRAM)

In this case, the FMC allows read/write transactions and accesses the right data through its byte lanes NBL[3:0].

Bytes to be written are addressed by NBL[3:0].

All memory bytes are read (NBL[3:0] are driven low during read transaction) and the useless ones are discarded.

• – Accesses to devices that do not have the byte select feature (NOR and NAND flash memories)

This situation occurs when a byte access is requested to a 16-bit wide flash memory. Since the device cannot be accessed in Byte mode (only 16-bit words can be read/written from/to the flash memory), write transactions are not allowed while read transactions are allowed (the controller reads the entire 16-bit memory word and uses only the required byte).

Wrap support for NOR flash/PSRAM

Synchronous memories must be configured in Linear burst mode of undefined length as not all masters can issue wrap transactions.

If a master generates a wrap transaction:

• • The read operation is split into two linear burst transactions.
• • The write operation is split into two linear burst transactions.

Configuration registers

The FMC can be configured through a set of registers. Refer to Section 27.8.6 , for a detailed description of the NOR flash/PSRAM controller registers. Refer to Section 27.9.9 , for a detailed description of the NAND flash registers and to Section 27.10.5 for a detailed description of the SDRAM controller registers.

27.7 External device address mapping

From the FMC point of view, the external memory is divided into fixed-size memory regions of 256 Mbytes each (see Table 148 ):

• • Memory region 1 is used to address up to 4 NOR flash memories or PSRAM devices. This region is split into four NOR/PSRAM subregions with four dedicated Chip Selects, as follows:
  • – Subregion 1 - NOR/PSRAM 1
  • – Subregion 2 - NOR/PSRAM 2
  • – Subregion 3- NOR/PSRAM 3
  • – Subregion 4 - NOR/PSRAM 4

Note: The Memory region 1 type attribute must be declared as 'device'.

• • Memory region 5 and 6 are used to address SDRAM devices (one device per region).

For each memory region, the type of memory to be used can be configured by the user application through the Configuration register.

Table 148. FMC memory regions (default mapping)

The mapping of FMC memory regions can be modified through the BMAP[1:0] bits in FMC_BCR1 register. Table 149 shows the configuration to swap the NOR/PSRAM and SDRAM memory regions or remap SDRAM device 1 and 2. Thus allowing to access the SDRAM devices at two different address mapping.

Table 149. FMC memory region remap using BMAP[1:0]

27.7.1 NOR/PSRAM address mapping

ADDR[27:26] bits are used to select one of the four memory subregions as shown in Table 150 .

Table 150. NOR/PSRAM subregion selection

1. 1. ADDR are internal address lines that are translated to external memory.

The ADDR[25:0] bits contain the external memory address. Since ADDR is a byte address whereas the memory is addressed at word level, the address actually issued to the memory varies according to the memory data width, as shown in the following table.

Table 151. NOR/PSRAM External memory address

1. 1. In case of a 16-bit external memory width, the FMC internally uses ADDR[25:1] to generate the address for external memory FMC_A[24:0]. In case of a 32-bit memory width, the FMC internally uses ADDR[25:2] to generate the external address.
   Whatever the external memory width, FMC_A[0] must be connected to external memory address A[0].

27.7.2 NAND flash memory address mapping

The 4 Kbyte NAND flash address bits are mapped according to Table 152 .

Table 152. NAND access memory map

1. 1. Four address LSBs are don't care: each section has 16 bytes mapped to the alias region.

The application software uses the 3 sections to access the NAND flash memory:

• • To send a command to NAND flash memory , the software must write the command value to any memory location in the command section.
• • To specify the NAND flash address that must be read or written , the software must write the address value to any memory location in the address section. Since an address can be 4 or 5 bytes long (depending on the actual memory size), several consecutive write operations to the address section are required to specify the full address.
• • To read or write data , the software reads or writes the data from/to any memory location in the data section.

Since the NAND flash memory automatically increments addresses, there is no need to increment the address of the data section to access consecutive memory locations.

Note: The NAND region has to be accessed as a device and not as memory. Write accesses to command and address sections must be done in Byte mode and aligned with the section base address (offset = 0).

Read and Write accesses to NAND data section must be in Byte mode for 8-bit NAND flash memories and Byte or Half-word mode for 16-bit NAND flash memories.

Read and Write bursts must start at section base address (offset = 0) and must not cross the 16-byte section boundary.

27.7.3 SDRAM address mapping

Two SDRAM regions are available as indicated in Table 153 .

Table 153. SDRAM device selection

The following table shows SDRAM mapping for an 13-bit row, a 11-bit column and 4 internal bank configuration.

Table 154. SDRAM address mapping

1. When interfacing with a 16-bit memory, the FMC internally uses the ADDR[11:1] internal address lines to generate the external address. When interfacing with a 32-bit memory, the FMC internally uses ADDR[12:2] lines to generate the external address. Whatever the memory width, FMC_A[0] has to be connected to the SDRAM A[0].

2. The AutoPrecharge is not supported. However, FMC_A[10] must be connected to SDRAM A[0].

The ADDR[27:0] bits are translated to external SDRAM address depending on the SDRAM controller configuration:

• • Row size: 11, 12 or 13 bits
• • Column size: 8, 9, 10 or 11 bits
• • Number of internal banks: two or four internal banks

The following tables show the SDRAM address mapping versus the SDRAM controller configuration.

Table 155. SDRAM address mapping with 8-bit data bus width ⁽¹⁾⁽²⁾

1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be cleared.

2. Access to Reserved (Res.) address range generates an AXI slave error.

Table 156. SDRAM address mapping with 16-bit data bus width ⁽¹⁾⁽²⁾

1. 1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be cleared.
2. 2. Access to Reserved space (Res.) generates an AXI Slave error.
3. 3. BM0: is the byte mask for 16-bit access.

Table 157. SDRAM address mapping with 32-bit data bus width ⁽¹⁾⁽²⁾

1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be cleared.

2. Access to Reserved space (Res.) generates an AXI slave error.

3. BM[1:0]: is the byte mask for 32-bit access.

27.8 NOR flash/PSRAM controller

The FMC generates the appropriate signal timings to drive the following types of memories:

• • Asynchronous SRAM, FRAM and ROM
  • – 8 bits
  • – 16 bits
  • – 32 bits
• • PSRAM (CellularRAM™)
  • – Asynchronous mode
  • – Burst mode for synchronous accesses with configurable option to split burst access when crossing boundary page for CRAM 1.5.
  • – Multiplexed or non-multiplexed
• • NOR flash memory
  • – Asynchronous mode
  • – Burst mode for synchronous accesses
  • – Multiplexed or non-multiplexed

The FMC outputs a unique Chip Select signal, NE[4:1], per memory region. All the other signals (addresses, data and control) are shared.

The FMC supports a wide range of devices through a programmable timings among which:

• • Programmable wait-states (up to 15)
• • Programmable bus turnaround cycles (up to 15)
• • Programmable output enable and write enable delays (up to 15)
• • Independent read and write timings and protocol to support the widest variety of memories and timings
• • Programmable continuous clock (FMC_CLK) output.

The FMC output Clock (FMC_CLK) is a submultiple of the fmc_ker_ck clock. It can be delivered to the selected external device either during synchronous accesses only or during asynchronous and synchronous accesses depending on the CCKEN bit configuration in the FMC_BCR1 register:

• • If the CCKEN bit is reset, the FMC generates the clock (FMC_CLK) only during synchronous accesses (Read/write transactions).
• • If the CCKEN bit is set, the FMC generates a continuous clock during asynchronous and synchronous accesses. To generate the FMC_CLK continuous clock, memory region 1 must be configured in synchronous mode (see Section 27.8.6: NOR/PSRAM controller registers ). Since the same clock is used for all synchronous memories, when a continuous output clock is generated and synchronous accesses are performed, the AXI data size has to be the same as the memory data width (MWID[1:0]) otherwise the FMC_CLK frequency is changed depending on AXI data transaction (refer to Section 27.8.5: Synchronous transactions for FMC_CLK divider ratio formula).

The size of each memory region is fixed and equal to 64 Mbytes. Each memory region is configured through dedicated registers (see Section 27.8.6: NOR/PSRAM controller registers ).

The programmable memory parameters include access times (see Table 158 ) and support for wait management (for PSRAM and NOR flash accessed in burst mode).

Table 158. Programmable NOR/PSRAM access parameters

27.8.1 External memory interface signals

Table 159 , Table 160 and Table 161 list the signals that are typically used to interface with NOR flash memory, SRAM and PSRAM.

Note: The prefix “N” identifies the signals which are active low.

NOR flash memory, non-multiplexed I/Os

The maximum capacity is 512 Mbits (26 address lines).

NOR flash memory, 16-bit multiplexed I/Os

The maximum capacity is 512 Mbits.

PSRAM/SRAM/FRAM, non-multiplexed I/Os

The maximum capacity is 512 Mbits.

PSRAM, 16-bit multiplexed I/Os

The maximum capacity is 512 Mbits (26 address lines).

27.8.2 Supported memories and transactions

Table 163 below shows an example of the supported devices, access modes and transactions when the memory data bus is 16-bit wide for NOR flash memory, PSRAM and SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in this example.

Table 163. NOR flash/PSRAM: Example of supported memories and transactions

Table 163. NOR flash/PSRAM: Example of supported memories and transactions

27.8.3 General timing rules

Signals synchronization

• • All controller output signals change on the rising edge of the fmc_ker_ck clock
• • In synchronous mode (read or write), all output signals change on the rising edge of fmc_ker_ck clock.
• • NBL signals

They are applicable to memories which support byte enable.

• – The NBL signals are driven low:
  from the start of a read memory transfer and optionally earlier according to NBLSET, when the device requires some setup time from NBL to NCE, for bytes to be written during data transfer and according to the first data bytes during the address transfer.
• – The NBL signals are driven high two FMC_CLK clock cycles after the completion of the read or write transfer.

27.8.4 NOR flash/PSRAM controller asynchronous transactions

Asynchronous static memories (NOR flash, PSRAM, SRAM, FRAM)

• • Signals are synchronized by the internal clock fmc_ker_ck. This clock is not issued to the memory.
• • The FMC always samples the data before deasserting the Chip Select signal NE. This guarantees that the memory data hold timing constraint is met (minimum chip enable high to data transition is usually 0 ns).
• • If the extended mode is enabled (EXTMOD bit is set in the FMC_BCRx register), up to four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D modes for read and write operations. For example, read operation can be performed in mode A and write in mode B. The extended mode is not compatible with the muxed mode (EXTMOD bit must be kept cleared in muxed mode).
• • If the extended mode is disabled (EXTMOD bit is reset in the FMC_BCRx register), the FMC can operate in mode 1 or mode 2 as follows:
  • – Mode 1 is the default mode when SRAM/PSRAM memory type is selected (MTYP[1:0] = 0x0 or 0x01 in the FMC_BCRx register)
  • – Mode 2 is the default mode when NOR memory type is selected (MTYP[1:0] = 0x10 in the FMC_BCRx register).

Mode 1 - SRAM/FRAM/PSRAM (CRAM)

The next figures show the read and write transactions for the supported modes followed by the required configuration of FMC_BCRx, and FMC_BTRx/FMC_BWTRx registers.

Figure 161. Mode 1 read access waveforms

Figure 162. Mode 1 write access waveforms

The DATAHLD time at the end of the read and write transaction guarantee the address and data hold time after the NOE/NWE rising edge. For write, the DATAST value must be greater than zero (DATAST > 0).

Table 164. FMC_BCRx bitfields (mode 1)

Table 165. FMC_BTRx bitfields (mode 1)

Table 165. FMC_BTRx bitfields (mode 1) (continued)

Mode A - SRAM/FRAM/PSRAM (CRAM) OE toggling

Figure 163. Mode A read access waveforms

Figure 164. Mode A write access waveforms

The differences compared with mode 1 are the toggling of NOE and the independent read and write timings.

Table 166. FMC_BCRx bitfields (mode A)

Mode 2/B - NOR flash

Figure 165. Mode 2 and mode B read access waveforms

Figure 166. Mode 2 write access waveforms

Figure 167. Mode B write access waveforms

The differences with mode 1 are the toggling of NWE and the independent read and write timings when extended mode is set (mode B).

Table 169. FMC_BCRx bitfields (mode 2/B)

Note: The FMC_BWTRx register is valid only if the extended mode is set (mode B), otherwise its content is don't care.

Mode C - NOR flash - OE toggling

Figure 168. Mode C read access waveforms

Figure 169. Mode C write access waveforms

The differences compared with mode 1 are the toggling of NOE and the independent read and write timings.

Table 172. FMC_BCRx bitfields (mode C)

Table 173. FMC_BTRx bitfields (mode C)

Table 174. FMC_BWTRx bitfields (mode C)

Mode D - asynchronous access with extended address

Figure 170. Mode D read access waveforms

Figure 171. Mode D write access waveforms

The differences with mode 1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings.

Table 175. FMC_BCRx bitfields (mode D)

Muxed mode - multiplexed asynchronous access to NOR flash memory

Figure 172. Muxed read access waveforms

Figure 173. Muxed write access waveforms

The difference with mode D is the drive of the lower address byte(s) on the data bus.

Table 178. FMC_BCRx bitfields (muxed mode)

WAIT management for asynchronous accesses

If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to accept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register.

If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT becomes inactive. Unlike the data setup phase, the first access phases (Address setup and Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT sensitive and so they are not prolonged.

The data setup phase must be programmed so that WAIT can be detected 4 fmc_ker_ck cycles before the end of the memory transaction. The following cases must be considered:

1. 1. The memory asserts the WAIT signal aligned to NOE/NWE which toggles:

1. 2. The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
   if

then:

otherwise

where max_wait_assertion_time is the maximum time taken by the memory to assert the WAIT signal once NEx/NOE/NWE is low.

Figure 174 and Figure 175 show the number of fmc_ker_ck clock cycles that are added to the memory access phase after WAIT is released by the asynchronous memory (independently of the above cases).

Figure 174. Asynchronous wait during a read access waveforms

• 1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.

Figure 175. Asynchronous wait during a write access waveforms

• 1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.

CellularRAM™ (PSRAM) refresh management

The CellularRAM™ does not allow maintaining the chip select signal (NE) low for longer than the \( t_{CEM} \) timing specified in memory device. This timing can be programmed in the FMC_CFGR register. It defines the maximum duration of the NE low pulse (expressed in fmc_ker_ck cycles) in synchronous mode for PSRAM read or write accesses.

27.8.5 Synchronous transactions

The memory clock, FMC_CLK, is a submultiple of fmc_ker_ck. It depends on the value of CLKDIV.

NOR flash memories specify a minimum time from NADV assertion to FMC_CLK high. To meet this constraint, the FMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access (before NADV assertion). This guarantees that the rising edge of the memory clock occurs in the middle of the NADV low pulse.

Data latency versus NOR memory latency

The data latency is the number of cycles to wait before sampling the data. The DATLAT value must be consistent with the latency value specified in the NOR flash configuration register. The FMC does not include the clock cycle when NADV is low in the data latency count.

Caution: Some NOR flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR flash latency and the FMC DATLAT parameter can be either:

• • NOR flash latency = (DATLAT + 2) CLK clock cycles
• • or NOR flash latency = (DATLAT + 3) CLK clock cycles

Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can be set to its minimum value. As a result, the FMC samples the data and waits long enough to evaluate if the data are valid. Thus the FMC detects when the memory exits latency and real data are processed.

Other memories do not assert NWAIT during latency. In this case the latency must be set correctly for both the FMC and the memory, otherwise invalid data are mistaken for good data, or valid data are lost in the initial phase of the memory access.

Single-burst transfer

When the selected memory region is configured in burst mode for synchronous accesses, if for example a single-burst transaction is requested on 16-bit memories, the FMC performs a burst transaction of length 1 (if the AXI transfer is 16 bits), or length 2 (if the AXI transfer is 32 bits) and deassert the Chip Select signal when the last data is strobed.

Such transfers are not the most efficient in terms of cycles compared to asynchronous read operations. Nevertheless, a random asynchronous access first requires to re-program the memory access mode, which altogether lasts longer.

Cross boundary page for CellularRAM™ 1.5

CellularRAM™ 1.5 does not allow burst access to cross the page boundary. The FMC allows to split automatically the burst access when the memory page size is reached by configuring the CPSIZE bits in the FMC_BCR1 register following the memory page size.

Wait management

For synchronous NOR flash memories, NWAIT is evaluated after the programmed latency period, which corresponds to (DATLAT+2) FMC_CLK clock cycles.

If NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait-states are inserted until NWAIT is inactive (high level when WAITPOL = 0, low level when WAITPOL = 1).

When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) or on the next clock edge (bit WAITCFG = 0).

During wait-state insertion via the NWAIT signal, the controller continues to send clock pulses to the memory, keeping the Chip Select and output enable signals valid. It does not consider the data as valid.

In burst mode, there are two timing configurations for the NOR flash NWAIT signal:

• • The flash memory asserts the NWAIT signal one data cycle before the wait-state (default after reset).
• • The flash memory asserts the NWAIT signal during the wait-state

The FMC supports both NOR flash wait-state configurations, for each Chip Select, thanks to the WAITCFG bit in the FMC_BCRx registers (x = 0 to 3).

Figure 176. Wait configuration waveforms

Figure 177. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)

Table 180. FMC_BCRx bitfields (Synchronous multiplexed read mode)

Figure 178. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)

1. 1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.

Table 182. FMC_BCRx bitfields (Synchronous multiplexed write mode)

Table 182. FMC_BCRx bitfields (Synchronous multiplexed write mode) (continued)

Table 183. FMC_BTRx bitfields (Synchronous multiplexed write mode)

27.8.6 NOR/PSRAM controller registers

The peripheral registers have to be accessed by words (32-bit)

SRAM/NOR flash chip-select control register for memory region x (FMC_BCRx)

Address offset: 0x00 + 0x08 * (x - 1), (x = 1 to 4)

Reset value: 0x0000 30DB, 0x0000 30D2, 0x0000 30D2, 0x0000 30D2

This register contains the control information of each memory region, used for SRAMs, PSRAM, FRAM and NOR flash memories.

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 Reserved, must be kept at reset value.

Bits 23:22 NBLSET[1:0] : Byte lane (NBL) setup

These bits configure the NBL setup timing from NBLx low to Chip select NEx low.

00: NBL setup time is 0 fmc_ker_ck clock cycle.

01: NBL setup time is 1 fmc_ker_ck clock cycle.

10: NBL setup time is 2 fmc_ker_ck clock cycles.

11: NBL setup time is 3 fmc_ker_ck clock cycles.

Bits 21:20 CSCOUNT[1:0] : Chip Select (CS) counter

These bits define the maximum duration of Chip Select low for PSRAM synchronous mode and for each memory region.

The Chip Select counter is loaded into a timer which is decremented using the KCK_FMC while the NE is maintained low during PSRAM read or write access.

When the timer reaches 0, the PSRAM controller splits the current access and toggles NE to allow PSRAM device refresh.

The programmed counter value guarantees a maximum NE pulse width ( \( t_{CEM} \) ) as specified for PSRAM devices.

The counter is reloaded and starts decrementing each time a new access is triggered by a transition of NE from high to low.

0b00: Counter disabled

0b01: NEx deasserted after fmc_ker_ck clock cycle

0b10: NEx deasserted after 64 fmc_ker_ck clock cycles

0b11: NEx deasserted after 256 fmc_ker_ck clock cycles

Note: Most PSRAMs manage refresh transparently and do not require access split. CSCOUNT[1:0] must consequently be left at its default value (counter disabled), otherwise CSCOUNT[1:0] value and access split impact must be checked according to PSRAM timing parameters.

Bit 19 CBURSTRW : Write burst enable

For PSRAM (CRAM) operating in burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register.

0: Write operations are always performed in asynchronous mode

1: Write operations are performed in synchronous mode.

Bits 18:16 CPSIZE[2:0] : CRAM page size

These bits are used for CellularRAM™ 1.5 which does not allow burst accesses to cross the address boundaries between pages. When these bits are configured, the FMC automatically splits the burst access when the memory page size is reached (refer to memory datasheet for page size).

000: No burst split when crossing page boundary. (default after reset).

001: 128 bytes

010: 256 bytes

011: 512 bytes

100: 1024 bytes

Others: Reserved.

Bit 15 ASYNCWAIT : Wait signal during asynchronous transfers

This bit enables/disables wait signal usage by the FMC even during asynchronous transfers.

0: NWAIT signal not taken in to account during asynchronous transfers (default after reset)

1: NWAIT signal taken in to account during asynchronous transfers

This bit enables write timing programming for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations.

0: Values inside FMC_BWTR register not taken into account (default after reset)

1: Values inside FMC_BWTR register taken into account

Note: When the extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows:

• – Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP[1:0] = 0x0 or 0x01)
• – Mode 2 is the default mode when the NOR memory type is selected (MTYP[1:0] = 0x10).

This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode.

0: NWAIT signal disabled (its level not taken into account, no wait-state inserted after the programmed flash latency period)

1: NWAIT signal enabled (its level is taken into account after the programmed latency period to insert wait-states if asserted) (default after reset)

This bit indicates whether write operations to the memory region by the FMC are enabled/disabled:

0: Write operations to the memory region by the FMC disabled. An AXI slave error is reported,

1: Write operations to the memory region by the FMC enabled (default after reset).

The NWAIT signal indicates whether the data from the memory are valid or if a wait-state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait-state or during the wait-state:

0: NWAIT signal active one data cycle before wait-state (default after reset),

1: NWAIT signal active during wait-state (not used for PSRAM).

This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:

0: NWAIT active low (default after reset),

1: NWAIT active high.

This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in burst mode:

0: Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode.

1: Burst mode enable. Read accesses are performed in synchronous mode.

Bits 5:4 MWID[1:0] : Memory data bus width

This bit defines the external memory device width, valid for all type of memories.

• 00: 8 bits
• 01: 16 bits (default after reset)
• 10: 32 bits
• 11: Reserved.

Bits 3:2 MTYP[1:0] : Memory type

This bit defines the type of external memory attached to the corresponding memory region:

• 00: SRAM/ FRAM (default after reset for memory region 2...4)
• 01: PSRAM (CRAM)/FRAM
• 10: NOR flash/OneNAND flash (default after reset for memory region 1)
• 11: Reserved.

Bit 1 MUXEN : Address/data multiplexing enable bit

When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:

• 0: Address/Data non-multiplexed
• 1: Address/Data multiplexed on databus (default after reset)

Bit 0 MBKEN : Memory region enable bit

This bit enables the memory region. After reset memory region 1 is enabled, all others are disabled. Accessing a disabled memory region causes an ERROR on AXI bus.

• 0: Corresponding memory region is disabled
• 1: Corresponding memory region is enabled

SRAM/NOR flash chip-select timing registers for memory region x (FMC_BTRx)

Address offset: 0x04 + 0x8 * (x - 1), (x = 1 to 4)

Reset value: 0x0FFF FFFF

This register contains the control information of each memory region, used for SRAMs, PSRAM and NOR flash memories. If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

These bits are written by software to define the duration of the data hold phase in fmc_ker_ck cycles (refer to Figure 174 to Figure 175 ), used in asynchronous accesses:

For read/write accesses:

00: DATAHLD phase duration = fmc_ker_ck clock cycle * 0 (default, read)/1 (default, write)

01: DATAHLD phase duration = fmc_ker_ck clock cycle * 1 (read)/2 (write)

10: DATAHLD phase duration = fmc_ker_ck clock cycle * 2 (read)/3 (write)

11: DATAHLD phase duration = fmc_ker_ck clock cycle * 3 (read)/4 (write)

These bits specify the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.

00: Access mode A

01: Access mode B

10: Access mode C

11: Access mode D

For synchronous access with read/write burst mode enabled (BURSTEN / CBURSTRW bits set), these bits define the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data.

This timing parameter is not expressed in fmc_ker_ck periods, but in FMC_CLK periods.

For asynchronous access, this value is don't care.

0000: Data latency of 2 FMC_CLK clock cycles for first burst access

1111: Data latency of 17 FMC_CLK clock cycles for first burst access (default value after reset)

These bits define FMC_CLK clock output signal period, expressed in fmc_ker_ck cycles:

0000: FMC_CLK period= 1x fmc_ker_ck period

0001: FMC_CLK period = 2 × fmc_ker_ck periods

0010: FMC_CLK period = 3 × fmc_ker_ck periods

1111: FMC_CLK period = 16 × fmc_ker_ck periods (default value after reset)

This value is don't care when accessing NOR flash memories, SRAM and PSRAM in asynchronous mode.

Note: Refer to Section 27.8.5: Synchronous transactions for FMC_CLK divider ratio formula).

Note: CLKDIV[3:0] bits are don't care when CCLKEN bit of FMC_CFGR is set. In this case FMC_CLK clock output is controlled by CLKDIV of FMC_CFGR.

These bits are written by software to add a delay between the end of current read or write transaction and the next transaction on the same memory region.

This delay allows matching the minimum time between consecutive transactions ( \( t_{EHEL} \) from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access ( \( t_{EHQZ} \) from chip enable high to output Hi-Z). This delay is recommended for mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to a minimum value that respects the following condition:

For FRAMs, the bus turnaround delay must be configured to match the minimum precharge time ( \( t_{PC} \) ). This delay is inserted between all consecutive transactions on the same memory region (read/read, write/write, read/write and write/read) to match the \( t_{PC} \) memory timing, and the Chip select toggles between consecutive accesses.

0000: BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added

...

1111: BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)

Bits 15:8 DATAST[7:0] : Data-phase duration

These bits are written by software to define the duration of the data phase (refer to Figure 174 to Figure 175 ) used in asynchronous accesses:

0000 0000: Reserved.

0000 0001: DATAST phase duration = 1 * fmc_ker_ck clock cycles

0000 0010: DATAST phase duration = 2 * fmc_ker_ck clock cycles

...

1111 1111: DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)

For each memory type and access mode data-phase duration, refer to the respective figure ( Figure 174 to Figure 175 ).

Example of mode 1, write access, DATAST=1:

Data-phase duration= DATAST+1 = 2 *fmc_ker_ck clock cycles.

Note: This value is don't care in synchronous accesses.

Bits 7:4 ADDHLD[3:0] : Address-hold phase duration

These bits are written by software to define the duration of the address hold phase (refer to Figure 170 to Figure 173 ) used in mode D or multiplexed accesses:

0000: Reserved.

0001: ADDHLD phase duration = 1 * fmc_ker_ck clock cycle

0010: ADDHLD phase duration = 2 * fmc_ker_ck clock cycle

...

1111: ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)

For each access mode address-hold phase duration, refer to the respective figure ( Figure 170 to Figure 173 ).

Note: This value is not used in synchronous accesses, and the address hold phase lasts always 1 memory clock period.

Bits 3:0 ADDSET[3:0] : Address setup phase duration

These bits are written by software to define the duration of the address setup phase (refer to Figure 174 to Figure 175 ), used in SRAMs, ROMs and asynchronous NOR flash memories:

0000: ADDSET phase duration = 0 * fmc_ker_ck clock cycle

...

1111: ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)

For each access mode address setup phase duration, refer to the respective figure (refer to Figure 174 to Figure 175 ).

Note: This value is don't care in synchronous accesses.

In muxed mode or mode D, the minimum value for ADDSET is 1.

Note: PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these memories issue the NWAIT signal during the whole latency phase to extend the latency as needed.

On PSRAMs (CRAMs), DATLAT must be configured to 0 so that the FMC quickly exits its latency phase, starts sampling NWAIT from memory, and starts read or write operations when the memory is ready.

This method can be used also with the latest generation of synchronous flash memories, which, unlike older flash memories, issue the NWAIT signal (check the corresponding flash memory datasheet).

Reset value: 0x000F FFFF

This register contains the control information of each memory region. It is used for SRAMs, FRAMs, PSRAMs and NOR flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

These bits are written by software to define the duration of the data hold phase in fmc_ker_ck cycles (refer to Figure 175 ), used in asynchronous write accesses:

• 00: DATAHLD phase duration = \( 1 * fmc\_ker\_ck \) clock cycle (default)
• 01: DATAHLD phase duration = \( 2 * fmc\_ker\_ck \) clock cycle
• 10: DATAHLD phase duration = \( 3 * fmc\_ker\_ck \) clock cycle
• 11: DATAHLD phase duration = \( 4 * fmc\_ker\_ck \) clock cycle

These bits specify the asynchronous access modes as shown in the next timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.

• 00: Access mode A
• 01: Access mode B
• 10: Access mode C
• 11: Access mode D

Bits 27:20 Reserved, must be kept at reset value.

These bits are written by software to add a delay between the end of current write transaction and the next transaction on the same memory region.

For FRAMs, the bus turnaround delay must be configured to match the minimum precharge time ( t _PC ). The bus turnaround delay is inserted between all consecutive transactions on the same memory region (read/read, write/write, read/write and write/read), and the Chip select toggles between consecutive accesses.

\( (BUSTURN + 1) * fmc\_ker\_ck \text{ period} \geq t_{PCmin} \)

• 0000: BUSTURN phase duration = \( 1 * fmc\_ker\_ck \) clock cycle added
• ...
• 1111: BUSTURN phase duration = \( 16 * fmc\_ker\_ck \) clock cycles added (default value after reset)

Bits 15:8 DATAST[7:0] : Data-phase duration.

These bits are written by software to define the data phase duration (refer to Figure 174 to Figure 175 ) used in asynchronous SRAM, PSRAM and NOR flash memory accesses:
0000 0000: Reserved.
0000 0001: DATAST phase duration = 1 * fmc_ker_ck clock cycles
0000 0010: DATAST phase duration = 2 * fmc_ker_ck clock cycles
...
1111 1111: DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)

Bits 7:4 ADDHLD[3:0] : Address-hold phase duration.

These bits are written by software to define the duration of the address hold phase (refer to Figure 172 to Figure 173 ) used in asynchronous multiplexed accesses:
0000: Reserved.
0001: ADDHLD phase duration = 1 * fmc_ker_ck clock cycle
0010: ADDHLD phase duration = 2 * fmc_ker_ck clock cycle
...
1111: ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)

Note: In synchronous NOR flash accesses, this value is not used, and the address hold phase always lasts 1 flash clock period.

Bits 3:0 ADDSET[3:0] : Address setup phase duration.

These bits are written by software to define the duration of the address setup phase in fmc_ker_ck cycles (refer to Figure 174 to Figure 175 ) used in asynchronous accesses:
0000: ADDSET phase duration = 0 * fmc_ker_ck clock cycle
...
1111: ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)

Note: In synchronous accesses, this value is not used, and the address setup phase always lasts 1 flash clock period. In muxed mode, the minimum ADDSET value is 1.

FMC common configuration register (FMC_CFGR)

Address offset: 0x020
Reset value: 0x0000 0000

This register is user to set configuration common to all controllers

Bit 31 FMCEN : FMC enable

This bit enables/disables the FMC.

0: FMC disabled

1: FMC enabled

Bits 30:26 Reserved, must be kept at reset value.

Bits 25:24 BMAP[1:0] : FMC memory region mapping

These bits allow the remapping of SDRAM device 2 or the swapping of FMC NOR/PSRAM and SDRAM memory regions.

00: Default mapping (refer to Table 148 )

01: Devices are remapped (refer to Table 149 )

10: Devices are remapped (refer to Table 149 )

11: All memory region accesses are ignored. A bus error is generated.

Bits 23:21 Reserved, must be kept at reset value.

Bit 20 CCLKEN : Continuous clock enable

This bit enables the FMC_CLK clock output to external memory devices.

0: The FMC_CLK is only generated during the synchronous memory access (read/write transaction). The FMC_CLK clock ratio is defined by the programmed CLKDIV value in the FMC_BCRx register (default after reset).

1: The FMC_CLK is generated continuously during asynchronous and synchronous access. If continuous clock mode is enabled, the synchronous memories connected to all memory regions are clocked by the same clock with the clock ratio defined by CLKDIV in FMC_CFGR. The CLKDIV value in FMC_BWTRx are don't care.

Bits 19:16 CLKDIV[3:0] : Clock divide ratio (for FMC_CLK signal)

These bits define the FMC_CLK clock output signal period, expressed in number of fmc_ker_ck cycles:

0000: FMC_CLK period= 1x fmc_ker_ck period

0001: FMC_CLK period = 2 × fmc_ker_ck periods

0010: FMC_CLK period = 3 × fmc_ker_ck periods

1111: FMC_CLK period = 16 × fmc_ker_ck periods (default value after reset)

This value is don't care when accessing NOR flash memories, SRAM and PSRAM in asynchronous mode.

Note: Refer to Section 27.8.5: Synchronous transactions for FMC_CLK divider ratio formula.

Bits 15:0 Reserved, must be kept at reset value.

27.9 NAND flash controller

The FMC generates the appropriate signal timings to drive 8- and 16-bit NAND flash memories

The NAND memory region is configured through dedicated registers ( Section 27.9.9 ). The programmable memory parameters include access timings (shown in Table 184 ) and ECC configuration.

The NAND controller supports the following features:

• • Programmable page size of 256, 512, 1024, 2048, 4096 or 8192 bytes
• • Programmable memory timings
• • Programmable Error Correction Capability using BCH code or Hamming code
• • Command sequencer: a hardware accelerator for read/write accesses within a page or within a block of configurable size.

This feature is useful when ECC computation is performed.

• • Programmable address offset for ECC bytes programming using the command sequencer
• • Interrupt generation on ECC error detection and page or sector transfer complete

Table 184. Programmable NAND flash access parameters

27.9.1 External memory interface signals

The following tables list the typical signals that are used to interface NAND flash memory.

Note: The “N” prefix identifies the signals which are active low.

8-bit NAND flash memory

Table 185. 8-bit NAND flash memory

Note: Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed.

16-bit NAND flash memory

Note: Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed.

27.9.2 NAND flash supported memories and transactions

Table 187 shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND flash controller are shown in gray.

Table 187. Supported memories and transactions (continued)

27.9.3 Timing diagrams for NAND flash memory

The NAND flash memory region is managed through a set of registers:

• • Control register: FMC_PCR
• • Interrupt status register: FMC_SR
• • ECC register: FMC_HECCR
• • Timing register for Common memory space: FMC_PMEM
• • Timing register for Attribute memory space: FMC_PATT

Each timing configuration register contains three parameters used to define the number of fmc_ker_ck cycles for the different phases of any NAND flash access, plus one parameter that defines the timing to start driving the data bus when a write access is performed.

Figure 179 shows the timing parameter definitions for common memory accesses, knowing that Attribute memory space access timings are similar.

Figure 179. NAND flash controller waveforms for common memory access

1. 1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses.
2. 2. If PWAITEN = 1, the programmed values of (MEMxSET + MEMxHOLD) must be > 1.

1. 1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses.

27.9.4 NAND flash operations

The command latch enable (CLE) and address latch enable (ALE) signals of the NAND flash memory device are driven by address signals from the FMC. This means that to send a command or an address to the NAND flash memory, the CPU has to perform a write to a specific address in its memory space.

A typical page read operation from the NAND flash device requires the following steps:

1. 1. Program and enable the NAND memory region by configuring the FMC_PCR and FMC_PMEM (and for some devices, FMC_PATT, see Section 27.9.5: NAND flash prewait function ) registers according to the characteristics of the NAND flash memory (PWID bits to configure NAND flash data bus width, PWAITEN set or cleared as needed, see Section 27.7.2: NAND flash memory address mapping for timing configuration).
2. 2. The CPU performs a byte write to the common memory space, with a data byte value equal to one flash command byte (for example 0x00 for Samsung NAND flash devices). The NAND flash CLE input is active during the write strobe (low pulse on NWE), so that the written byte is interpreted as a command by the NAND flash memory. Once the command is latched by the memory device, it does not need to be written again for the following page read operations.
3. 3. The CPU can send the start address for a read operation by writing a five-byte address to the common memory or the attribute space followed by the second read command. The NAND flash ALE input is active during the write strobe (low pulse on NWE), so that the written bytes are interpreted as the start address for read operations. Using the attribute memory space allows to use a different FMC timing configuration, which can

be used to implement the prewait function required for some NAND flash memories (see details in Section 27.9.5: NAND flash prewait function ).

1. 4. The controller waits till the NAND flash memory is ready (RNB signal high), before starting a new access to the same memory region or to another memory region.
2. 5. The CPU can then perform byte read operations from the common memory space to read the NAND flash page (data field + Spare field) byte by byte.
3. 6. No CPU command or address write operation is required to read the next NAND flash page. This can be done in three different ways:
   • – by simply performing the operation described in step 5,
   • – a new random address can be accessed by restarting the operation at step 3,
   • – a new command can be sent to the NAND flash device by restarting at step 2.

Note: Non-‘CE don’t care’ NAND flash memories are not supported.
ONFI mode 4 and 5 EDO data output cycle timings are not supported.

27.9.5 NAND flash prewait function

The NAND controller must wait for RNB to be asserted low before sending its next command (see Figure 181 ). This timing constraint is set according to \( t_{WB} \) using MEMHOLD[7:0] bitfield in FMC_PMEM or ATTHOLD[7:0] in FMC_PATT.

Figure 181. Access to NAND flash memory

1. 1. NCE can be deasserted for NAND flash memories since CE is don't care except for very old NAND flash devices that are not considered in this example.
2. 2. RNB sampling can be delayed after \( t_{WB} \) by using ATTHOLD[7:0] bit of FMC_PATT. As an example, if \( fmc\_ker\_clk = 14 \) ns and ATTHOLD[7:0] = 7, the delay is \( 8 * 14 = 112 \) ns. The usual \( t_{WB} \) maximum value is 100 ns and the programmed delay must be higher than \( t_{WB} + 2 * fmc\_ker\_clk \) .

Any CPU read or write access to the NAND flash memory has a delay of \( (\text{MEMHOLD}[7:0] + 1) * \text{fmc\_ker\_ck} \) cycles after the NWE signal is asserted.

The ATTHOLD[7:0] bitfield in FMC_PATT register must be determined to satisfy \( t_{WB} \) timing constraints and selectively apply larger timing constraints to the last command or address byte in CPU mode. When setting ATTHOLD[7:0], the \( 2 * \text{fmc\_ker\_ck} \) delay required for the sampling of RNB by NAND sequencer must also taken into account.

27.9.6 NAND ECC controller

NAND flash memories include a spare memory area (or OOB) at the end of each page. This area is typically used to store some metadata (such as Bad Block Marker information to invalidate the whole page) or for error management functions.

The FMC supports on-the-fly error correction code (ECC) computation during data read/program from/to NAND flash memory. This mechanism reduces the host CPU workload when processing the ECC by software.

The user application can select one out of two algorithms:

• • Hamming code algorithm for 1-bit error code correction and 2-bit error detection per 256, 512, 1024, 2048, 4096 or 8192 bytes.
• • BCH (Bose, Chaudhuri and Hocquenghem) code for 4-bit error code correction and 8-bit error detection or 8-bit error code correction and 16-bit error detection per 512 bytes.

The principle of both ECC controllers is similar: the ECC modules monitor the NAND flash data bus and read/write signals (NCE and NWE) each time the NAND flash memory region is active. The ECC controllers operate as follows:

• • When accessing a NAND flash memory region, the data present on the D[7:0] or D[15:0] bus are latched and used for ECC computation.
• • When accessing any other address in NAND flash memory, the ECC logic is idle, and does not perform any operation. As a result, write operations to define commands or addresses to the NAND flash memory are not taken into account for ECC computation.

Once the desired number of bytes has been read/written from/to the NAND flash memory by the host CPU or DMA, the ECC result registers are updated.

Hamming code

The Hamming code implemented can perform 1-bit error correction and 2-bit error detection per 256, 512, 1024, 2048, 4096 or 8192 bytes read or written from/to the NAND flash memory. It consists in calculating the row and column parity. This algorithm is supported by 8-bit and 16-bit NAND flash memories.

Page write and read sequences with Hamming code are described below.

To perform a page program with Hamming ECC computation:

1. 1. Enable the ECCEN bit in the FMC_PCR register.
2. 2. Write data to the NAND flash memory page. While the NAND page is written, the ECC controller computes the ECC value.
3. 3. Wait until the ECC code is ready (NWRF is set in the FMC_SR register).
4. 4. Read the ECC value available in the FMC_HECCR register and store it in NAND flash spare area.
5. 5. Clear the ECCEN bit and launch the page programming.

To perform a page read with Hamming ECC computation:

1. 1. Enable the ECCEN bit in the FMC_PCR register before reading the NAND page. While the NAND page is read, the ECC block computes the ECC value.
2. 2. Wait until the ECC code is ready (NWRF set in the FMC_SR register).
3. 3. Read the ECC value available in the spare area as well also the ECC value, processed by Hamming controller, available in FMC_HECCR register.
4. 4. If the two ECC values are identical, no correction is required. Otherwise an ECC error occurred, the software correction routine returns information on whether the error can be corrected or not, and corrects it when possible.

Depending on the spare area size, the page can be split into several sectors of identical size. This allows increasing the error correction capability for each page since 1 error can be corrected and 2 errors can be detected for each sector.

Example

For a NAND flash memory with 2 Kbytes + 64 bytes pages, each page can be split into 8 sectors of 256 bytes each. 3 bytes (22 bits) of ECC are required for each sector, which makes 24 bytes (8 * 3 bytes) to be stored in the spare area for the whole page. For the whole 2 Kbyte page, up to 8 errors can be corrected, respectively up to 16 errors detected, provided there is less than 1 error, respectively 2 errors, per sector.

BCH (Bose, Chaudhuri and Hocquenghem) code

To increase the error correction capability, the FMC embeds a BCH (Bose, Chaudhuri and Hocquenghem) encoder and decoder.

It supports 4-bit error code correction and 8-bit error detection or 8-bit error code correction, and 16-bit error detection per sector. BCH encoder/decoder module handles sectors of fixed size, equal to 512 bytes. Each page must consequently be split into 512-byte sectors. The number of parity bytes generated for each sector is given in Table 188 . For 16-bit NAND flash memories, a padding is added to align parity bytes to an even number (8 bytes and 14 bytes for 4-bit and 8-bit BCH code, respectively).

Table 188. Number of ECC parity bytes per sector

The BCH module detects errors and returns the bit position for each sector. To correct the errors, the software needs to flip the error bits at the provided bit position stored in the FMC_BCHPBRx register.

The BCH ECC controller supports 8-bit and 16-bit NAND flash memories.

During a page program operation, the BCH encoder generates the ECC bytes (7 or 13 bytes) for each sector of 512 bytes that must be written in the NAND flash spare area with a programmable offset. It must take into account some metadata at the beginning of the spare area. This operation must be executed for each sector. The BCH encoder does not process the spare area: metadata must have their own error protection mechanism.

The total number of ECC bytes (N) is given by the below equation:

Example

For an 8-bit NAND flash with 4096-byte pages and an error correction capability of 4-bit per 512 bytes, the number of sector per page is 8 (4096 / 512). The total number of ECC bytes is consequently:

The user application has to make sure that the spare area is large enough to store the metadata and parity bytes.

Page program and read sequences with BCH code are described below.

To perform a page program:

1. 1. Enable write access by setting the WEN bit in the FMC_PCR register.
2. 2. Enable the ECC by setting the ECCEN bit in FMC_PCR register.
3. 3. Write 512 data bytes to the sector in the NAND flash memory page. While the sector is written, the BCH encoder computes the ECC value.
4. 4. Wait until the BCH encoder parity bits are available by monitoring EPBRF bit of FMC_BCHISR register.
5. 5. Read the ECC value available in the FMC_BCHPBRx registers and store it in the NAND flash spare area.
6. 6. Disable ECC by resetting the ECCEN bit in FMC_PCR register.
7. 7. Execute again step 2 to 6 for all sectors to be written in NAND flash memory.
8. 8. Launch the page programming.

To perform a page read:

1. 1. Enable read access by resetting the WEN bit in the FMC_PCR register.
2. 2. Enable the ECC by setting the ECCEN bit in FMC_PCR register.
3. 3. Read the NAND page sector (512 bytes).
4. 4. Read the corresponding ECC bytes (7 or 13 bytes) from the NAND flash spare area.
5. 5. During the read of data and parity bits, the syndrome is calculated. Then the error location search is launched.
6. 6. Wait until the decoding error is ready (DERF bit set in the FMC_BCHISR register), then read the decoding results (errors detected if any, correctable or not, number of errors, bit position) in FMC_BCHDSR0 and FMC_BCHDSRx registers.
7. 7. Thanks to the decoding results, the software can correct the errors in the sector (when possible).
8. 8. Disable ECC by resetting the ECCEN bit in FMC_PCR register.
9. 9. Execute again step 2 to 7 for all relevant sectors of the page.

27.9.7 FMC command sequencer

NAND flash page programming and reading can be performed by the CPU as described in the above sections.

Data sector programming/reading as well as ECC byte programming/reading can also be managed automatically by the FMC command sequencer for command and address transfers, and by DMA for data transfers.

The purpose of the command sequencer is to ease the programming/reading of NAND flash pages with ECC computation as well as free the CPU of sequencing tasks. The command sequencer enables the software to work on full NAND flash pages instead of sectors, which is more efficient and essential to achieve high throughput. The sequencer handles all the sectors in the page. It does not support sub-page read or program operations.

One DMA channel is required for write operations and two DMA channels for read operations.

A specific NAND flash page layout must be respected when using the BCH algorithm. See Figure 182 for an example of 2Kbyte page BCH layout.

Figure 182. NAND flash page (2 Kbytes) layout with BCH

Page program sequence

1. 1. A data buffer located in SRAM has to be initialized with the data to be written to the NAND flash page.
2. 2. The CPU configures the FMC command sequencer registers: page program command (0x80), address bytes, change write column command (0x85), ECC address offset, page size, sector size and sector number.
   It also selects the ECC algorithm (Hamming or BCH) and configures one DMA channel to transfer data from the buffer to the NAND flash page.
3. 3. The CPU then launches the sequencer by setting the CSQSTART bit in the FMC_CSQCR register.
4. 4. The command sequencer automatically generates the control and address cycles to the NAND flash memory, following the programmed timings configured either in FMC_PMEM or FMC_PATT register.
5. 5. A DMA request is issued to start data transfer from the data buffer to NAND flash memory.
6. 6. When the full sector is programmed, go to step 7 if ECC is enabled. Otherwise, jump to step 9.
7. 7. The FMC command sequencer automatically issues a change write column command (0x85) followed by two address cycles. The command to be issued and the number of

address cycles are programmed in FMC_CSQCFGR2 register. The address is automatically generated from the programmed ECC address offset.

1. 8. Once the parity bytes are available in ECC encoder (Hamming or BCH) module, they are automatically transferred to the NAND flash spare area. The FMC command sequencer can generate a sector transfer complete interrupt if it has been previously enabled.
2. 9. The sequencer then repeats step 4 (except that it performs only a change write column command instead of a page program command) to step 8 to program the following sectors and their corresponding ECC parity bytes. The ECC address offset is automatically incremented for each sector transfer. When ECC is disabled, the sequencer repeats step 5.
3. 10. The FMC command sequencer can generate a transfer complete interrupt or a transfer complete error interrupt by sector or when all sectors are written.
4. 11. The CPU can program any further metadata in the NAND flash area, taking care not to overwrite parity bytes.
5. 12. The program command (0x10) can then be written to the command section to program the NAND flash memory.
6. 13. An interrupt, if enabled, is generated on the rising edge of the Ready/Busy (RNB) signal to indicate that the page program operation is complete.

Refer to Figure 183 for an overview of the page program sequence with BCH.

Figure 183. Example of 2 Kbyte page program sequence with 4-bit BCH

Page read sequence

1. 1. A data buffer is allocated in SRAM to store the NAND flash page data. A decoding status buffer is also allocated to store result of ECC decoding.
2. 2. The CPU programs the command sequencer registers: the page read first cycle command (0x00), address bytes, the page read second cycle command (0x30), change read column command (0x05), spare area offset, page size, sector size and sector number.

It configures the ECC algorithm if required (Hamming or BCH), one DMA channel to handle data transfers from the NAND flash page to the data buffer, and a second DMA

channel to transfer ECC decoding results from ECC status registers to the RAM decoding status buffer.

1. 3. The CPU then launches the FMC sequencer by setting the CSQSTART bit in the FMC_CSQCR register.
2. 4. The FMC command sequencer issues the command and address cycles to the NAND flash memory.
3. 5. The command sequencer waits for a Ready/Busy (RNB) rising edge to start data transfer.
4. 6. It sends a DMA request to launch the data transfer from the NAND flash page to the data buffer.
5. 7. When all sector data are read, go to step 8 if ECC is enabled, otherwise go to step 9. The FMC command sequencer can generate a sector transfer complete interrupt if it has been previously enabled.
6. 8. When ECC status registers are empty (because the Hamming error code or the BCH error position bits of previous sector have already been read), the ECC command sequencer automatically issues a change read column command (0xE0) followed by two address cycles and by the 0xE0 command, to read ECC bytes from NAND flash memory and store them in ECC registers. These commands as well as the number of address cycles are programmed in the FMC_CSQCFGR2 register (see Figure 184 ).
   
   The address in spare area is extracted from the programmed ECC address offset.
   
   When the Hamming algorithm is used, a DMA request to the second DMA channel is sent to transfer ECC codes (FMC_HPR and FMC_HECCR registers) to the decoding status buffer.
   
   When BCH algorithm is used, once all the parity bytes have been read, the BCH decoder first processes the syndrome to detect errors and then searches for error positions if any.
   
   As the BCH decoder is pipelined, it is possible to start reading a sector even if the decoding of the previous sector is not complete.
   
   In parallel of the following steps, when BCH sector decoding is complete, the new error status is stored in the ECC status registers (FMC_BCHDSR0) and a DMA request to the second DMA channel is sent to transfer data from the status registers to the decoding status buffer located in RAM.

1. 9. The FMC command sequencer then repeats step 4 (except that a change read column command is issued instead of the page read first cycle command) to step 8 to read the other sectors and their corresponding ECC bytes. The addresses are issued and incremented following the page size, number of sectors, spare area address offset address and BCH code selection. When the read sequence is complete, the command sequencer waits for \( t_{RHWL} \) before issuing a new command sequence (refer to Figure 183 ). When ECC is disabled, the sequencer repeats step 6.
2. 10. Once all sectors within a page and the status registers (FMC_BCHDSRx) are transferred by the command sequencer, the ECC controller can generate the transfer complete interrupt or transfer complete error (when enabled).
3. 11. By reading the decoding status buffer, the CPU can start processing the errors corresponding to each sector. If no error has been detected, the page stored in RAM is validated. Otherwise the CPU corrects the error(s) before validating the page buffer in RAM. If there are too many errors, the CPU can detect the page cannot be corrected and invalidate the data buffer.

Following the selected BCH code, if the number of detected errors exceeds the number of correctable errors, this bit is not significant and the DUE bit is set. If the number of errors the detected by the BCH decoder exceeds the maximum number of detectable errors, DEN and DUE bits are not significant.

The DMA channels can also send interrupts each time a data transfer is complete. This allows the CPU to process error(s) in a sector as soon as it is available.

Note: When using the sequencer and DMA channels, the CPU must not read the FMC_BCHPBRx and FMC_BCHDSRx registers before data of all sectors are transferred, that is when TCF flag is set in the FMC_CSQISR register.

Figure 184. Chained-page read command timings

An example of 2 Kbyte page read sequence with BCH is described in Figure 185 . This example corresponds to four 512-byte sectors and 7 ECC bytes per data 512 bytes.

Figure 185. Example of 2-Kbyte page read sequence with 4-bit BCH

The BCH controller resets the ECC computation whenever a page read (0x00), a page program (0x80), a random read (0x05) or a random program command ((0x85) is issued.

When only part of a page is written/read using the BCH, the command sequencer issues a random read/write command sequence only for the number of sectors to be read/written. This is done by programming the number of sector to be processed.

1. 1. Configure the FMC_CSQCFGR1 register: program the command1 and the command 2 (in case of read access), the number of address cycles to be issued, configure the read or write sequence, and select the timings to be used.
2. 2. Configure the address bytes in FMC_CSQAR1 and FMC_CSQAR2 register.
3. 3. In the FMC_CSQCFGR2 register, configure the change write or change read column commands and the timings to be used for ECC. Program the address offset for the random columns in the FMC_CSQAR2 register. Enable the DMA if it is needed for ECC status register transfer.
4. 4. Configure the number of sectors and the address cycle timings in the FMC_CSQCFGR3 register.
5. 5. Configure the ECC sector size, and select read or write access in the FMC_PCR register.
6. 6. Enable the SQSDTEN bit in the FMC_CSQFCGR2 register. The ECCEN bit in the FMC_PCR register kept at 0.
7. 7. Transfer complete, and transfer error complete or sector transfer complete can be enabled through the FMC_CSQIER register.

27.9.8 NAND flash controller interrupt

An interrupt can be generated on the following events:

• • RNB rising edge: an interrupt is generated when a rising edge is detected on RNB NAND flash signal
• • RNB falling edge: an interrupt is generated when a falling edge is detected on RNB NAND flash signal
• • RNB high-level: an interrupt is generated when a high-level is detected on RNB NAND flash signal.
• • Transfer complete: an interrupt is generated when the FMC command sequencer has completed all data transfers for all sectors or when the command sequencer was aborted.
• • Sector complete interrupt: an interrupt is generated when the FMC command sequencer has completed all data transfers for one sector.
• • Sector error interrupt: an interrupt is generated when the FMC command sequencer has completed a sector transfer with at least one error detected.
• • Sector uncorrectable error interrupt: an interrupt is generated when the FMC command sequencer has completed a sector transfer and detected an uncorrectable error.
• • Command transfer complete: the command sequencer has completed the transfer of programmed commands and addresses.
• • BCH encoder parity bits ready: an interrupt is generated when the BCH encoder has finished processing parity bits.
• • BCH decoder syndrome ready: an interrupt is generated when the BCH decoder has finished processing the syndrome and knows if errors have been detected or not.
• • BCH decoder error found: an interrupt is generated when the BCH decoder has detected an error.
• • BCH decoder error ready: an interrupt is generated when the BCH decoder has finished processing errors, has identified error locations and can then correct them.
• • BCH decoder uncorrectable error: an interrupt is generated when the BCH decoder has detected that the errors cannot be corrected (more than four or eight errors according to BCH error correction capability configuration).

The interrupt source can be enabled or disabled separately through the FMC_IER, FMC_CSQIER and FMC_BCHIER registers.

Table 189. FMC NAND controller interrupt request

Table 189. FMC NAND controller Interrupt request (continued)

27.9.9 NAND flash controller registers

NAND flash programmable control register (FMC_PCR)

Address offset: 0x80

Reset value: 0x0007 FE08

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 WEN : Write enable

This bit enables read or write access. It must be configured when using the FMC sequencer or when the ECC with BCH code is enabled. It can only be modified when ECCEN bit is reset.

0: Read access enabled

1: Write access enabled

Bit 24 BCHECC : BCH error correction capability

0: 4-bit BCH (4-bit error correction and 8-bit error detection per 512 bytes)

1: 8-bit BCH (8-bit error correction and 16-bit error detection per 512 bytes)

Bits 23:20 Reserved, must be kept at reset value.

Bits 19:17 ECCSS[2:0] : ECC sector size (used to access spare area)

These bits define the sector size used for the ECC:

000: 256 bytes

001: 512 bytes

010: 1024 bytes

011: 2048 bytes (default)

100: 4096 bytes

101: Reserved.

11X: Reserved.

When the ECC is enabled with BCH code, the sector size must be programmed to 512 bytes.

Bits 16:13 TAR[3:0] : ALE to RE delay.

These bits define the time from ALE low to RE low in number of fmc_ker_ck clock cycles:

where \( t_{fmc\_ker\_ck} \) is the FMC clock period and \( t\_ar \) is the ALE to RE timing of NAND flash memories.

0000: 1 * fmc_ker_ck cycle

1111: 16 * fmc_ker_ck cycles (default)

Bits 12:9 TCLR[3:0] : CLE to RE delay.

These bits define the time from CLE low to RE low in number of fmc_ker_ck clock cycles:

where \( t_{fmc\_ker\_ck} \) is the FMC clock period and \( t\_clr \) is the CLE to RE timing of NAND flash memories.

0000: 1 * fmc_ker_ck cycle

1111: 16 * fmc_ker_ck cycles (default)

Bit 8 ECCALG : ECC algorithm

0: Hamming code is selected (default).

1: BCH code is selected.

Bit 7 Reserved, must be kept at reset value.

Bit 6 ECCEN : ECC computation logic enable bit

0: ECC logic is disabled and reset (default after reset),

1: ECC logic is enabled.

This bit must be kept reset when using the FMC sequencer

Bits 5:4 PWID[1:0] : Data bus width

These bits define the external memory device width.

00: 8 bits (default after reset).

01: 16 bits

1X: Reserved.

Bit 3 Reserved, must be kept at reset value.

Bit 2 PBKEN : NAND flash memory region enable bit

This bit enables the memory region. Accessing a disabled memory region causes an AXI bus error.

0: Corresponding memory region is disabled (default after reset)

1: Corresponding memory region is enabled.

Note: The NAND flash memory region must be disabled only when all NAND flash controller commands are complete.

Bit 1 PWAITEN : Wait feature enable bit

This bit enables the Wait feature for the NAND flash memory region:

0: disabled (default)

1: enabled

Bit 0 Reserved, must be kept at reset value.

FMC status register (FMC_SR)

Address offset: 0x84

Reset value: 0x0000 0053

This register contains information about the AXI interface isolation status and the NAND write requests status. The FMC has to be disabled before modifying some registers. As requests might be pending, it is necessary to wait till the AXI interface is stable and the core of the block is totally isolated from its AXI interface before reconfiguring the registers.

The PEF and NWEF bits indicate the status of the pipe. If Hamming algorithm is used, the ECC is calculated while data are written to the memory. To read the correct ECC, the software must consequently wait until no write request to the NAND controller are pending, by polling PEF and NWRF bits.

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 NWRF : NAND write request flag

This bit provides the status of the write request issued to the NAND flash memory. When this bit is set, all write requests to the NAND controller are served.

0: NAND flash write requests are pending

1: No NAND flash write requests pending

Bit 5 Reserved, must be kept at reset value.

Bit 4 PEF : Pipe Empty Flag

This bit indicates if the pipe contains requests.

Bits 3:2 Reserved, must be kept at reset value.

Bits 1:0 ISOST[1:0] : FMC isolation state with respect to the AXI interface

00: FMC is not isolated; AXI transactions are treated by the FMC and its controllers.

01: FMC has been enabled (FMCEN = 1) and waits for the end of pending AXI transactions (which leads to error responses) before going to “non-isolated” state.

10: FMC has been disabled (FMCEN = 0) and waits for the end of pending AXI transactions before going to isolation state.

11: FMC is isolated from its AXI interface. All AXI requests lead to error responses.

FMC common memory space timing register (FMC_PMEM)

Address offset: 0x88

Reset value: 0x0A0A 0A0A

The FMC_PMEM read/write register contains NAND flash memory region timing information. This information is used to access the NAND flash common memory space for command, address write accesses or data read/write accesses.

Bits 31:24 MEMHIZ[7:0] : Common memory data bus Hi-Z time

These bits define the number of fmc_ker_ck clock cycles (+1) during which the data bus is kept Hi-Z after starting a NAND flash write access to the common memory space. This is only valid for write transactions:

0000 0000: 1 * fmc_ker_ck cycle

0000 0001: 2 * fmc_ker_ck cycles

.....

1111 1111: 256 * fmc_ker_ck cycles

Bits 23:16 MEMHOLD[7:0] : Common memory hold time

These bits define the number of fmc_ker_ck clock cycles (+1) during which the address is held (and data for write accesses) after the command is deasserted (NWE, NOE), during NAND flash read or write accesses to the common memory space:

0000 0000: 1 * fmc_ker_ck cycle

0000 0001: 2 * fmc_ker_ck cycles

.....

1111 1111: 256 * fmc_ker_ck cycles

Bits 15:8 MEMWAIT[7:0] : Common memory wait time

These bits define the minimum number of fmc_ker_ck clock cycles (+1) to assert the command (NWE, NOE), during NAND flash read or write accesses to the common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of fmc_ker_ck:

0000 0000: 1 * fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)

0000 0001: 2 * fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)

.....

1111 1111: 256 * fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)

Bits 7:0 MEMSET[7:0] : Common memory setup time

These bits define the number of fmc_ker_ck clock cycles (+1) to set up the address before the command assertion (NWE, NOE), during NAND flash read or write accesses to the common memory space:

0000 0000: 1 * fmc_ker_ck cycles

0000 0001: 2 * fmc_ker_ck cycles

.....

1111 1111: 256 * fmc_ker_ck cycles

FMC attribute memory space timing registers (FMC_PATT)

Address offset: 0x8C

Reset value: 0x0A0A 0A0A

The FMC_PATT read/write register contains NAND flash memory region timing information. It is used for 8-bit accesses to the NAND flash attribute memory space during the last address write access when the timing differs from previous accesses (for Ready/Busy management, refer to Section 27.9.5: NAND flash prewait function ).

Bits 31:24 ATTHIZ[7:0]: Attribute memory data bus Hi-Z time

These bits define the number of fmc_ker_ck clock cycles (+1) during which the data bus is kept in Hi-Z after starting a NAND flash write access to the attribute memory space. These bits are only valid for write transactions:

0000 0000: 1 * fmc_ker_ck cycle

0000 0001: 2 * fmc_ker_ck cycle

.....

1111 1111: 256 * fmc_ker_ck cycles

Bits 23:16 ATTHOLD[7:0]: Attribute memory hold time

These bits define the number of fmc_ker_ck clock cycles (+1) during which the address is held (and data for write access) after the command deassertion (NWE, NOE), during NAND flash read or write accesses to the attribute memory space:

0000 0000: 1 * fmc_ker_ck cycle

0000 0001: 2 * fmc_ker_ck cycle

.....

1111 1111: 256 * fmc_ker_ck cycles.

Bits 15:8 ATTWAIT[7:0]: Attribute memory wait time

These bits define the minimum number of x fmc_ker_ck (+1) clock cycles to assert the command (NWE, NOE), during NAND flash read or write accesses to the attribute memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of fmc_ker_ck:

0000 0000: 1 * fmc_ker_ck cycle (+ wait cycle introduced by deassertion of NWAIT)

0000 0001: 2 * fmc_ker_ck cycles (+ wait cycle introduced by deassertion of NWAIT)

.....

1111 1111: 256 * fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)

Bits 7:0 ATTSET[7:0]: Attribute memory setup time

These bits define the number of fmc_ker_ck clock cycles (+1) for address set up before the command assertion (NWE, NOE), during NAND flash read or write accesses to the attribute memory space:

0000 0000: 1 * fmc_ker_ck cycle

0000 0001: 2 * fmc_ker_ck cycle

.....

1111 1111: 256 * fmc_ker_ck cycles.

FMC Hamming parity result registers (FMC_HPR)

Address offset: 0x90

Reset value: 0x0000 0000

This register is used during read accesses in conjunction with the FMC sequencer. It contains the current error correction code value computed by the FMC NAND controller Hamming module. When the FMC sequencer reads data from a NAND flash memory page at the correct address, the data read are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area and stored in the and the FMC_HPR, to determine whether a page is valid, and to correct it otherwise. The FMC_HPR register must be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set.

Bits 31:0 HPR[31:0] : Hamming parity result

This field contains the parity value computed by the Hamming ECC computation module.

Table 190 describes the contents of these bitfields.

Table 190. HPR relevant bits

FMC Hamming code ECC result register (FMC_HECCR)

Address offset: 0x94

Reset value: 0x0000 0000

This register contain the current error correction code value computed by the FMC NAND controller Hamming module. When the CPU reads/writes data from/to a NAND flash memory page at the correct address (refer to Section 27.9.6: NAND ECC controller ), the data read/written from/to the NAND flash memory are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS

field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and to correct it otherwise. The FMC_HECCR register must be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set.

Bits 31:0 HECC[31:0] : ECC result

This field contains the value computed by the Hamming ECC computation logic. Table 191 describes the contents of these bitfields.

Table 191. ECC result relevant bits ⁽¹⁾

1. Only the relevant bits according to the sector size are valid.

FMC NAND interrupt enable register (FMC_IER)

Address offset: 0x180

Reset value: 0x0000 0000

This register configures the interrupt capability generation when the RNB signal is connected on FMC interrupt pin. An interrupt can be generated on the rising edge, falling edge or high level detected on the RNB signal.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 IFEE : Interrupt falling edge detection enable bit

0: Interrupt falling edge detection request disabled

1: Interrupt falling edge detection request enabled

Bit 1 IHLE : Interrupt high-level detection enable bit

0: Interrupt high-level detection request disabled

1: Interrupt high-level detection request enabled

Bit 0 IREE : Interrupt rising edge detection enable bit

0: Interrupt rising edge detection request disabled

1: Interrupt rising edge detection request enabled

FMC interrupt status register (FMC_ISR)

Address offset: 0x184

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 IFEF : Interrupt falling edge flag

The flag is set by hardware and cleared by setting the CFEIF bit.

0: No interrupt falling edge occurred

1: Interrupt falling edge occurred

Bit 1 IHLF : Interrupt high-level flag

The flag is set by hardware and cleared by setting the CHLIF bit.

0: No interrupt high-level occurred

1: Interrupt high-level occurred

Bit 0 IREF : Interrupt rising edge flag

The flag is set by hardware and cleared by setting the CREIF bit.

0: No interrupt rising edge occurred

1: Interrupt rising edge occurred

FMC NAND controller interrupt clear register (FMC_ICR)

Address offset: 0x188

Reset value: 0x0000 0000

Writing 1 in one of these bits clears the corresponding flag in the interrupt status register (FMC_ISR).

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 CIFEF : Clear Interrupt falling edge flag

0: No effect

1: Clears the IFEF flag in the FMC_ISR register

Bit 1 CIHLF : Clear Interrupt high-level flag

0: No effect

1: Clears the IHLF flag in the FMC_ISR register

Bit 0 CIREF : Clear Interrupt rising edge flag

0: No effect

1: Clear the IREF flag in the FMC_ISR register

FMC NAND command sequencer control register (FMC_CSQCR)

Address offset: 0x200

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 CSQSTART : Command Sequencer Enable

Writing 1 starts the Command sequencer.

Writing 0 has no effect.

Note: Write this bit to 1 to start the sequencer only when the FMC is enabled by setting FMCCEN bit of FMC_CFGGR to 1 and the NAND flash controller is activated by setting PBKEN bit of FMC_PCR to 1.

Address offset: 0x204

Reset value: 0x0000 0000

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 CMD2T : Command 2 Sequencer timings

This bit specifies if the Command 2 (CMD2) is issued to the NAND flash memory with the timings defined in FMC_PMEM or FMC_PATT register.

0: CMD2 issued with the timings programmed in FMC_PMEM

1: CMD2 issued with the timings programmed in FMC_PATT

Bit 24 CMD1T : Command 1 Sequencer timings

This bit specifies if the Command 1 (CMD1) is issued to the NAND flash memory with the timings programmed in FMC_PMEM or FMC_PATT register.

0: CMD1 issued with the timings programmed in FMC_PMEM

1: CMD1 issued with the timings programmed in FMC_PATT

Bits 23:16 CMD2[7:0] : Command 2 sequencer

These bits specify if the Command 2 is issued by the command sequencer for the command second cycle during read operations. This command is only issued when the CMD2EN bit is set.

Example: CMD2[7:0] bits must be programmed to 0x30 to issue the read column command.

Bits 15:8 CMD1[7:0] : Command 1 sequencer

These bits specify if the Command 1 is issued by the command sequencer for the first cycle during read or write operations.

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 ACYNBR[2:0] : Address Cycle number

These bits define the number of address cycles to be generated by the command sequencer when issuing the command programmed in the registers.

000: No address cycle.

001: 1 address cycle

010: 2 address cycles

011: 3 address cycles

100: 4 address cycles

101: 5 address cycles

Others: Reserved.

Bit 3 Reserved, must be kept at reset value.

Bit 2 DMADEN : Command sequencer DMA request data enable

When this bit is set, the command sequencer generates a DMA request to the first DMA channel, to transfer data from/to NAND flash memory.

0: No DMA request transfer

1: A DMA request transfer

Bit 1 CMD2EN : Command cycle 2 Enable

This bit specifies that the command cycle 2 has to be generated by the command sequencer.

0: Command cycle 2 not issued.

1: Command cycle 2 (programmed CMD2[7:0]) sent by the command sequencer to the NAND flash memory after the address cycles.

Bit 0 Reserved, must be kept at reset value.

FMC NAND command sequencer configuration register 2 (FMC_CSQCFGR2)

Address offset: 0x208

Reset value: 0x0000 0000

This register is used to configure the command sequencer to issue random read/ write commands to read/ write data by sector and automatically read/write data from NAND flash memory at a programmable address offset. This is useful when performing a sector read/write operation followed by an ECC read/write operation in the NAND flash spare area. The command sequencer generates the random commands until all the sectors are read/written.

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 RCMD2T : Command 1 sequencer timings

This bit specifies if the CMD1 is issued to the NAND flash memory with the timings programmed in FMC_PMEM or FMC_PATT register.

0: CMD1 issued with the timings programmed in FMC_PMEM

1: CMD1 issued with the timings programmed in FMC_PATT

Bit 24 RCMD1T : Command 1 sequencer timings

This bit specifies if the CMD1 is issued to the NAND flash memory with the timings flash memory in FMC_PMEM or FMC_PATT register.

0: CMD1 issued with the timings programmed in FMC_PMEM

1: CMD1 issued with the timings programmed in FMC_PATT

Bits 23:16 RCMD2[7:0] : Random Command 2 sequencer

These bits specify that the command 2 is issued by the command sequencer for the second cycle during read operations. This command is only issued when the RCMD2EN bit is set.

Example: the RCMD2 (0xE0) is required to issue the random read column command.

Bits 15:8 RCMD1[7:0] : Random Command 1 sequencer

These bits specify that the command 1 value is issued by the command sequencer for the first cycle during read or write accesses.

Bits 7:3 Reserved, must be kept at reset value.

Bit 2 DMASEN : Command sequencer DMA request decoding status enable

When this bit is set, the command sequencer generates a DMA request to the second DMA channel when valid bits are available in the ECC status register at the end of ECC processing (decoding).

0: No DMA request used for ECC status registers transfer

1: A DMA request used for ECC status registers transfer

Note: This bit must be set only during a page read sequence to offload the saving of the ECC results between sectors by using a second DMA channel.

Bit 1 RCMD2EN : Random Command 2 sequencer enable

This bit enables the command 2 to be issued by the command sequencer during read accesses. This command is issued only when the CMD2SQEN bit is set.

0: Command 2 not issued.

1: Command 2 (CMD2SQ[7:0]) issued by the command sequencer to NAND flash memory after the address cycle.

Bit 0 SQSDTEN : Sequencer spare data transfer enable

This bit enables the sequencer to access the spare data area after each sector transfer. It also enables the ECC when using the sequencer. ECCEN bit in FMC_PCR register must be reset.

0: ECC disabled and spare data area not accessed by the sequencer

1: ECC enabled and spare data area read or programmed by the sequencer after each sector transfer

FMC NAND sequencer configuration register 3 (FMC_CSQCFGR3)

Address offset: 0x20C

Reset value: 0x0000 0000

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 RAC2T : Random Address cycle 2 sequencer timings

This bit specifies if the random Address cycle 2 (ADDC2) is issued to the NAND flash memory with the timings programmed in FMC_PMEM or in FMC_PATT register.

0: Random ADDC2 issued with the timings programmed in FMC_PMEM

1: Random ADDC2 issued with the timings programmed in FMC_PATT

Bit 22 RAC1T : Random Address cycle 1 sequencer timings

This bit specifies if the random Address cycle 1 (ADDC1) is issued to the NAND flash memory with the timings programmed in FMC_PMEM or in FMC_PATT register.

0: Random ADDC1 issued with the timings programmed in FMC_PMEM

1: Random ADDC1 issued with the timings programmed in FMC_PATT

Bit 21 SDT : Spare data transfer sequencer timings

This bit specifies if the spare data transfer for read and write operations from/to the NAND flash memory are performed with the timings programmed in FMC_PMEM or FMC_PATT register.

0: Spare data transfer issued with the timings programmed in FMC_PMEM

1: Spare data transfer issued with the timings programmed in FMC_PATT

Bit 20 AC5T : Address cycle 5 sequencer timings

This bit defines if the Address cycle 5(ADDC1) is issued to the NAND flash memory with the timings programmed in FMC_PMEM or FMC_PATT register.

0: ADDC5 issued with the timings programmed in FMC_PMEM

1: ADDC5 issued with the timings programmed in FMC_PATT

Bit 19 AC4T : Address cycle 4sequencer timings

This bit defines if the Address cycle 4 (ADDC4) is issued to the NAND flash memory with the timings programmed in FMC_PMEM or FMC_PATT register.

0: ADDC4 issued with the timings programmed in FMC_PMEM

1: ADDC4 issued with the timings programmed in FMC_PATT

Bit 18 AC3T : Address cycle 3 sequencer timings

This bit defines if the Address cycle 3 (ADDC3) is issued to the NAND flash memory with the timings programmed in FMC_PMEM or FMC_PATT register.

0: ADDC3 issued with the timings programmed in FMC_PMEM

1: ADDC3 issued with the timings programmed in FMC_PATT

Bit 17 AC2T : Address cycle 2 sequencer timings

This bit defines if the Address cycle 2 (ADDC2) is issued to the NAND flash memory with the timings programmed in FMC_PMEM or FMC_PATT register.

0: ADDC2 issued with the timings programmed in FMC_PMEM

1: ADDC2 issued with the timings programmed in FMC_PATT

Bit 16 AC1T : Address cycle 1 sequencer timings

This bit defines if the Address cycle 1 (ADDC1) is issued to the NAND flash memory with the timings programmed in FMC_PMEM or FMC_PATT register.

0: ADDC1 issued with the timings programmed in FMC_PMEM

1: ADDC1 issued with the timings programmed in FMC_PATT

Bits 15:14 Reserved, must be kept at reset value.

Bits 13:8 SNBR[5:0] : Number of sectors to be read/written

These bits define the number of sectors that are processed by the sequencer. They are used to read/write part of a page or to use the ECC (in particular with the BCH code which requires 512-byte sectors):
000000: 1 sector
000001: 2 sectors
...
111111: 16 sectors
Others: Reserved.

Bits 7:0 Reserved, must be kept at reset value.

FMC NAND command sequencer address register 1 (FMC_CSQAR1)

Address offset: 0x210

Reset value: 0x0000 0000

This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer.

Bits 31:24 ADDC4[7:0] : Address Cycle 4

These bits define the value of address cycle 4 to be issued by the command sequencer during read or write accesses.

Bits 23:16 ADDC3[7:0] : Address Cycle 3

These bits define the value of address cycle 2 to be issued by the command sequencer during read or write accesses.

Bits 15:8 ADDC2[7:0] : Address Cycle 2

These bits define the value of address cycle 2 to be issued by the command sequencer during read or write accesses.

Bits 7:0 ADDC1[7:0] : Address Cycle 1

These bits define the value of address cycle 1 to be issued by the command sequencer during read or write accesses.

FMC NAND command sequencer address register 2 (FMC_CSQAR2)

Address offset: 0x214

Reset value: 0x0000 0000

This register is used to program the fifth address cycle and the address offset in spare area.

Bits 31:16 SAO[15:0] : Spare Area Address Offset

These bits define the offset of the first ECC byte in the spare area for the program sequence.

Note: The minimum SAQ value is 2 since the first two bytes of the spare area are reserved for Bad block marking and metadata.

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:8 Reserved, must be kept at reset value.

Bits 7:0 ADDC5[7:0] : Address Cycle 5

These bits define the value of address cycle 5 to be issued by the command sequencer during read or write accesses.

FMC NAND command sequencer interrupt enable register (FMC_CSQIER)

Address offset: 0x220

Reset value: 0x0000 0000

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CMDTCIE : Command Transfer Complete interrupt enable

0: Command Transfer Complete Interrupt disable
1: Command Transfer Complete Interrupt enable

Bit 3 SUEIE : Sector Uncorrectable Error interrupt enable

0: Command Transfer Complete Interrupt disable
1: Command Transfer Complete Interrupt enable

1. Bit 2 SEIE : Sector Error interrupt enable
   0: Sector Error Interrupt disable
   1: Sector Error Interrupt enable
2. Bit 1 SCIE : Sector Complete interrupt enable
   0: Sector Complete Interrupt disable
   1: Sector Complete Interrupt enable
3. Bit 0 TCIE : Transfer Complete Interrupt enable
   0: Transfer Complete Interrupt disable
   1: Transfer Complete Interrupt enable

FMC NAND command sequencer interrupt status register (FMC_CSQISR)

Address offset: 0x224

Reset value: 0x0000 0000

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CMDTCF : Command Transfer Complete flag

This bit is set when the command sequencer has completed the transfer of programmed commands and addresses.

This bit is cleared by setting CCMDTCF bit. An interrupt can be generated if the CMDTCIE bit is set in the FMC_CSQICR register.

Note: The Sector Transfer Complete interrupt is not needed in sequencer mode.

Bit 3 SUEF : Sector Uncorrectable Error flag

This bit is set by hardware and cleared by writing 1 to the CSUEF bit in FMC_CSQICR.

When this bit is set, it indicates that the command sequencer detected an uncorrectable error when decoding a sector. An interrupt can be generated if the SUEIE bit is set in the FMC_CSQICR register.

Note: The SUEF bit is relevant only for BCH code to indicate uncorrectable errors. It must be ignored for Hamming code.

This bit is set by hardware and cleared by writing 1 to the CSEF bit in FMC_CSQICR.

This bit is set when the command sequencer has completed the sector data transfer with at least one error detection. An interrupt can be generated if the SEIE bit is set in the FMC_CSQICR register.

Note: The SEF bit is relevant only for BCH code to indicate that errors are present. It must be ignored for Hamming code.

This bit is set by hardware and cleared by writing 1 to the CSCF bit in FMC_CSQICR.

This bit is set when the command sequencer has completed the sector data transfer. An interrupt can be generated if the SCIE bit is set in the FMC_CSQICR register.

This bit is set by hardware and cleared by writing 1 to the CTCF bit in FMC_CSQICR.

This bit is set when the command sequencer has transferred all the data for all sectors or when the command sequencer was aborted. An interrupt can be generated if the TCIE bit is set in the FMC_CSQICR register.

FMC NAND command sequencer interrupt clear register (FMC_CSQICR)

Address offset: 0x228

Reset value: 0x0000 0000

Bits 31:5 Reserved, must be kept at reset value.

Writing one clears the CMTCF flag in the FMC_CSQISR register

Writing one clears the SUEF flag in the FMC_CSQISR register

Writing one clears the SEF flag in the FMC_CSQISR register

Writing one clears the SCF flag in the FMC_CSQISR register

Writing one clears the TCF flag in the FMC_CSQISR register

FMC command sequencer error mapping status register (FMC_CSQEMSR)

Address offset: 0x230

Reset value: 0x0000 0000

This register holds a sector error mapping status when the whole transfer is complete.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SEM[15:0] : Sector Error mapping
When SEM[i] bit ( \( 0 \leq i \leq 15 \) ) is set, at least one error has been detected on sector i+1.
As an example, SEM[2] and SEM[1] bits are set when errors are detected in sector 3 and 2.

FMC BCH interrupt enable register (FMC_BCHIER)

Address offset: 0x250

Reset value: 0x0000 0000

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 EPBRIE : Decoder Parity Bits Ready Interrupt enable

• 0: Decoder Parity Bits Ready Interrupt disable
• 1: Decoder Parity Bits Ready Interrupt enable

Bit 3 DSRIE : Decoder Syndrome Ready Interrupt enable

• 0: Decoder Syndrome Ready Interrupt disable
• 1: Decoder Syndrome Ready Interrupt enable

Bit 2 DEFIE : Decoder Error Found Interrupt enable

0: Decoder Error Found Interrupt disable

1: Decoder Error Found Interrupt enable

Bit 1 DERIE : Decoder Error Ready Interrupt enable

0: Decoder Error Ready Interrupt disable

1: Decoder Error Ready Interrupt enable

Bit 0 DUEIE : Decoder Uncorrectable Errors Interrupt enable

0: Decoder Uncorrectable Errors Interrupt disable

1: Decoder Uncorrectable Errors Interrupt enable

FMC BCH interrupt and status register (FMC_BCHISR)

Address offset: 0x254

Reset value: 0x0000 0000

This register holds the status of BCH encoder/decoder after processing each sector. When the sequencer is used, this register is automatically cleared and the corresponding interrupt must not be enabled through FMC_BCHIER register.

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 EPBRF : Encoder Parity Bits Ready flag

This bit is set when the BCH encoder parity bits are available in FMC_BCHPBR1 to 4.

Bit 3 DSRF : Decoder Syndrome Ready flag

This bit is set when the syndrome is ready and DEFF is a valid field.

Bit 2 DEFF : Decoder Error Found flag

This bit is set by hardware and cleared by writing 1 to CDEFF.

This bit indicates that at least one error has been detected in the sector.

Bit 1 DERF : Decoder Error Ready flag

This bit indicates that the decoder has finished searching errors and identifying their location.

The number of errors and their location are available in FMC_BCHDSR0 and FMC_BCHDSR1 to 4, respectively.

Bit 0 DUEF : Decoder Uncorrectable Errors flag

This field indicates that too many errors have been detected in the sector during the BCH decoding and that the sector is uncorrectable.

FMC BCH interrupt clear register (FMC_BCHICR)

Address offset: 0x258

Reset value: 0x0000 0000

Bits 31:5 Reserved, must be kept at reset value.

• Bit 4 CEPBRF : Clear Encoder Parity Bits Ready flag
  Writing 1 clears the EPBRF flag in FMC_BCHISR.
• Bit 3 CDSRF : Clear Decoder Syndrome Ready flag
  Writing 1 clears the DSRF flag in FMC_BCHISR.
• Bit 2 CDEFF : Clear Decoder Error Found flag
  Writing 1 clears the DEFF flag in FMC_BCHISR.
• Bit 1 CDERF : Clear Decoder Error ready flag
  Writing 1 clears the DERF flag in FMC_BCHISR.
• Bit 0 CDUEF : Clear Decoder Uncorrectable Error flag
  Writing 1 clears the DUEF flag in FMC_BCHISR.

FMC BCH parity bits register 1 (FMC_BCHPBR1)

Address offset: 0x260

Reset value: 0x0000 0000

These registers contain the BCH parity bits (BCHPB). For the BCH 4-bit, only BCHPB[51:0] are significant and for the BCH 8-bit BCHPB[103:0] are significant.

Bits 31:0 BCHPB[31:0] : BCH parity bits

Address offset: 0x264

Reset value: 0x0000 0000

Address offset: 0x268

Reset value: 0x0000 0000

Address offset: 0x26C

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Address offset: 0x27C

Reset value: 0x0000 0000

This register contains some fields already available in other registers but that require to be saved when error correction is performed on several sectors at a time (for example a whole NAND flash page). This allows a DMA channel to transfer the content of FMC_BCHDSR0 to 4 to a decoding status buffer.

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 DEN[3:0] : Decoder error number

When DEF bit is set, this field indicates the number of errors detected by the BCH decoder.

Following the selected BCH code, if the number of detected errors exceeds the number of correctable errors, this bit is not significant and DUE bit is set.

If the BCH decoder detects a number of errors that exceeds the maximum number of detectable errors, DEN is not significant.

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 DEF : Decoder error found

This field indicates that the decoder has finished searching errors and identifying their location.

The number of errors and their location are available in FMC_BCHDSR0 and FMC_BCHDSR1 to 4, respectively.

Bit 0 DUE : Decoder uncorrectable error

This field indicates that too many errors have been detected in the sector during the BCH decoding and that the sector is uncorrectable.

If the BCH decoder detects a number of errors that exceeds the maximum number of detectable errors, DUE is not significant.

FMC BCH decoder status register for memory region 1 (FMC_BCHDSR1)

Address offset: 0x280

Reset value: 0x0000 0000

The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 1st and 2nd error bits in EBP1 and EBP2 fields, respectively. If less than 8 errors are detected, the useless EPBx fields (x = 1 to 8) are “don’t care”.

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:16 EBP2[12:0] : Error bit position for error number 2

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:0 EBP1[12:0] : Error bit position for error number 1

FMC BCH decoder status register for memory region 2 (FMC_BCHDSR2)

Address offset: 0x284

Reset value: 0x0000 0000

The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 3rd and 4th error bits in EBP3 and EBP4 fields, respectively. If less than 8 errors are detected, the useless EPBx fields (x = 1 to 8) are don’t care.

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:16 EBP4[12:0] : Error bit position for error number 4

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:0 EBP3[12:0] : Error bit position for error number 3

Address offset: 0x288

Reset value: 0x0000 0000

The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 5th and 6th error bits in EBP5 and EBP6 fields, respectively. If less than 8 errors are detected, the useless EPBx fields (x = 1 to 8) are don't care.

Bits 31:29 Reserved, must be kept at reset value.

Bits 15:13 Reserved, must be kept at reset value.

Address offset: 0x28C

Reset value: 0x0000 0000

The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 7th and 8th error bits in EBP7 and EBP8 fields, respectively. If less than 8 errors are detected, the useless EPBx fields (x = 1 to 8) are don't care.

Bits 31:29 Reserved, must be kept at reset value.

Bits 15:13 Reserved, must be kept at reset value.

27.10 SDRAM controller

27.10.1 SDRAM controller main features

The main features of the SDRAM controller are the following:

• • Two SDRAM devices with control registers
• • 8-bit, 16-bit, 32-bit data bus width with narrow width support using DQM byte masking
• • 11- to 13-bit Address Row, 8- to 11-bit Address Column, 2 to 4 internal banks
  Maximum supported device configurations: 4 x 16 M x 32 bits (256 Mbytes), 4 x 16 M x 16 bits (128 Mbytes), 4 x 16 M x 8 bits (64 Mbytes)
• • 64-bit AXI interface with word, half-word or byte access
• • SDRAM clock ratio programmable to 1, 2 or 3 (fmc_ker_ck, fmc_ker_ck/2 or fmc_ker_ck/3)
• • Automatic row and bank boundary crossing management
• • Multibank back-to-back access
• • Programmable timing parameters
• • Automatic refresh operation with programmable refresh rate
• • Self-refresh mode
• • Power-down mode
• • SDRAM power-up initialization by software
• • CAS latency of 1,2,3

27.10.2 SDRAM External memory interface signals

Table 192. SDRAM signals

1. 1. A[13:0] address depends on the number of row address bits (NR) and the number of column address bits (NC).
   A[10] is also used as a command parameter.
   A[12] is asserted only when NR = 13.
   A[13] is never asserted.

27.10.3 SDRAM controller functional description

All SDRAM controller outputs (signals, address and data) change on the falling edge of the memory clock (SDCLK).

SDRAM initialization

The initialization sequence is managed by software. If the two devices are used, the initialization sequence must be generated simultaneously to device 1 and device 2 by setting DS1 and DS2 bits in the FMC_SDCMR register:

1. 1. Program the memory device features into the FMC_SDCRx register. The SDRAM clock and RPIPE[1:0] must be programmed in the FMC_SDCR1 register.
2. 2. Program the memory device timing into the FMC_SDTR register.
3. 3. Enable each SDRAM device by setting the corresponding SDEN bit in FMC_SDCRx register.
4. 4. Set the FMCEN bit. The SDRAM clock starts when this step is complete.
5. 5. Wait during the recommended delay period (100 µs). Refer to the SDRAM datasheet for the required delay after power-up.
6. 6. Set the MODE[2:0] bitfield to 0x2 and configure the device select bits (DS1 and DS2) in the FMC_SDCMR register to issue a Precharge all banks (PALL) command.
7. 7. Set the MODE[2:0] bitfield to 0x3 (Auto-refresh) and configure the device select bits (DS1 and DS2). The user application can either generate Auto-refresh commands by burst (NRFS[3:0]) in the FMC_SDCMR register or generate consecutive single Auto-refresh commands. Refer to the SDRAM datasheet for the number of Auto-refresh commands that must be issued during the initialization phase.
8. 8. Perform load mode register: configure the MRD[13:0] bitfield in the FMC_SDCMR register, set the MODE[2:0] bitfield to 0x4, and configure the device select bits (DS1 and DS2) in the FMC_SDCMR register to issue a load mode register command to the memory devices. In particular, the burst length (BL) has to be set.

If the mode register value is not the same for both SDRAM devices, this step must be repeated twice, once for each device, and the device select bit has to be set accordingly. For mobile SDRAM devices, the MRD[13:0] bitfield is also used to configure the extended mode register while performing the load mode register.

1. 9. Program the refresh rate in the FMC_SDRTR register. The refresh rate corresponds to the delay between refresh cycles. Its value must be adapted depending on the SDRAM device.
2. 10. Set the SDINIT bit for all the enabled devices in the FMC_SDCRx register, to indicate to the hardware that the initialization procedure has been completed for all the enabled devices.

At the end of this step, the SDRAM device is ready to accept commands. If a system reset occurs during an ongoing SDRAM access, the data bus might still be driven by the SDRAM device.

Therefore, the SDRAM device must be first initialized again after reset before issuing any new access by the NOR flash/PSRAM/SRAM or NAND flash controller.

Any AXI request to SDRAM that is occurring before the end of SDRAM initialization returns a bus error and the request is lost.

During Initialization, only the commands PALL, AR and LMR are accepted, the other commands are ignored.

SDRAM controller write cycle

The SDRAM controller converts AXI single and burst write transfers into single memory accesses. Consecutive write transfers to the same page or to open pages in different banks can be presented as back-to-back write operations to the SDRAM.

Before performing any write access, the SDRAM bank write protection must be disabled by clearing the WP bit in the FMC_SDCRx register.

Figure 186. SDRAM burst write waveforms
(AXI 4-word transfer, no page boundary crossing)

The SDRAM controller always checks the next access.

• • If the next access is in the same row or in another active row, the write operation is carried out, and write commands can be back-to-back.
• • if the next access targets another row (not active), the SDRAM controller generates a Bank precharge command (PRE), activates the new row and initiates a write command.

SDRAM controller read cycle

The SDRAM controller converts single and burst read transfers into single memory accesses. Consecutive read transfers to the same page or to open pages in different banks can be presented as back-to-back read operations from the SDRAM.

Figure 187. SDRAM burst read waveforms
(AXI 4-word transfer, no page boundary crossing)

The address management depends on the next AXI request:

• • Next request is performed at sequential address (burst access)
  In this case, the SDRAM controller increments the address.
• • Next request is not performed at sequential address
  • – If the new read request targets the same row or another active row, the new address is passed to the memory and the master is stalled for the CAS latency period, waiting for the new data from memory.
  • – If the new read request does not target an active row, the SDRAM controller generates a Bank precharge command (PRE), activates the new row, and initiates a read command.

Row and bank boundary management

When a read or write access crosses a row boundary, if the next read or write access is sequential and the current access was performed to a row boundary, the SDRAM controller executes the following operations:

1. 1. Precharge of the active row, using the Bank precharge command (PRE)
2. 2. Activation of the new row
3. 3. Start of a read/write command.

At a row boundary, the automatic activation of the next row is supported for all columns and data bus width configurations.

If necessary, the SDRAM controller inserts additional clock cycles between the following commands:

• • Between Precharge and Activate commands to match TRP[3:0] parameter (only if the next access is in a different row in the same bank),
• • Between Activate and Read commands to match the TRCD[3:0] parameter.