24. Nested vectored interrupt controller (NVIC)

24.1 NVIC features

The NVIC includes the following features:

• Up to 196 maskable interrupt channels (not including the Cortex-M55 interrupt lines)
• 16 programmable priority levels (4 bits of interrupt priority are used)
• Low-latency exception and interrupt handling
• Power management control
• Implementation of system control registers

The NVIC and the processor core interface are closely coupled, which enables low-latency interrupt processing and efficient processing of late-arriving interrupts.

All interrupts, including the core exceptions, are managed by the NVIC.

24.1.1 SysTick calibration value register

The SysTick calibration value (SYST_CALIB) is fixed to 0x3E8. It provides a reference timebase of 1 ms based when the SysTick clock frequency is 1 MHz. To match the 1 ms timebase whatever the application frequency, the SysTick reload value must be programmed as follows in the SYST_RVR register:

• If the SysTick clock source is the 100 MHz CPU clock (HCLK):

\text{reload value} = (F_{\text{HCLK}} \times \text{SYST\_CALIB}) - 1

• If the SysTick clock source is an external clock:

\text{reload value} = ((F_{\text{HCLK}} / 8) \times \text{SYST\_CALIB}) - 1

where $F_{\text{HCLK}}$ refers to the AHB frequency expressed in MHz

For example, to achieve a timebase of 1 ms when the SysTick clock source is the 100 MHz HCLK:

\text{reload value} = (100 \times \text{SYST\_CALIB}) - 1 = 0x1869F

24.1.2 Interrupt and exception vectors

Exception vectors connected to the NVIC are the following: reset, NMI, HardFault, MemManage, BusFault, UsageFault, SVCall, DebugMonitor, PendSV, and SysTick

Table 134. STM32N6x5/x7xx vector table

NVIC position	Priority	Priority type	Acronym	Description	Address
-	-	-	-	Reserved	0x0000 0000
-	-3	Fixed	Reset	Reset	0x0000 0004

Table 134. STM32N6x5/x7xx vector table (continued)

NVIC position	Priority	Priority type	Acronym	Description	Address
-	-2	Fixed	NMI	Non-maskable interrupt. The RCC clock security system (HSE CSS) is linked to the NMI vector.	0x0000 0008
-	-1	Fixed	HardFault	All classes of fault	0x0000 000C
-	0	Fixed	MemManage	Memory management	0x0000 0010
-	1	Settable	BusFault	Prefetch fault, memory-access fault	0x0000 0014
-	2	Settable	UsageFault	Undefined instruction or illegal state	0x0000 0018
-	-	-	Reserved	Reserved	0x0000 001C 0x0000 002B
-	3	Settable	SVCall	System service call via SWI instruction	0x0000 002C
-	4	Settable	Debug Monitor	Debug monitor	0x0000 0030
-	-	-	Reserved	Reserved	0x0000 0034
-	5	Settable	PendSV	Pendable request for system service	0x0000 0038
-	6	Settable	SysTick	System tick timer	0x0000 003C
0	7	Settable	PVD_PVM	PVDOUT or PVM through the EXTI line	0x0000 0040
-	-	-	-	Reserved	0x0000 0044
2	9	Settable	DTS	Thermal sensor interruption	0x0000 0048
3	10	Settable	RCC	RCC global interrupt	0x0000 004C
4	11	Settable	LOCKUP	LOCKUP - No overstack in Cortex-M55	0x0000 0050
5	12	Settable	CACHE_ECC	Cache ECC error	0x0000 0054
6	13	Settable	TCM_ECC	TCM ECC error	0x0000 0058
7	14	Settable	BCKRAM_ECC	Backup RAM interrupts (SEC and DED)	0x0000 005C
8	15	Settable	FPU	FPU safety flag	0x0000 0060
-	16	-	Reserved (product safety)	Reserved	0x0000 0064
10	17	Settable	RTC_S	RTC secure interrupt	0x0000 0068
11	18	Settable	TAMP	TAMP secure and nonsecure synchronous interrupt line	0x0000 006C
12	19	Settable	RIFSC_TAMPER	RIF can generate an interrupt when a laser attack is detected	0x0000 0070
13	20	Settable	IAC	IAC global interrupt	0x0000 0074
14	21	Settable	RCC_S	RCC global secure interrupt	0x0000 0078
-	22	-	Reserved (product secure)	Reserved	0x0000 007C
16	23	Settable	RTC	RTC interrupt	0x0000 0080
17	24	Settable	Reserved	Reserved	0x0000 0084

Table 134. STM32N6x5/x7xx vector table (continued)

NVIC position	Priority	Priority type	Acronym	Description	Address
18	25	Settable	WDGLS	Independent watchdog interrupt	0x0000 0088
19	26	Settable	WWDG	Window watchdog interrupt	0x0000 008C
20	27	Settable	EXTI0	EXTI line 0 interrupt	0x0000 0090
21	28	Settable	EXTI1	EXTI line 1 interrupt	0x0000 0094
22	29	Settable	EXTI2	EXTI line 2 interrupt	0x0000 0098
23	30	Settable	EXTI3	EXTI line 3 interrupt	0x0000 009C
24	31	Settable	EXTI4	EXTI line 4 interrupt	0x0000 00A0
25	32	Settable	EXTI5	EXTI line 5 interrupt	0x0000 00A4
26	33	Settable	EXTI6	EXTI line 6 interrupt	0x0000 00A8
27	34	Settable	EXTI7	EXTI line 7 interrupt	0x0000 00AC
28	35	Settable	EXTI8	EXTI line 8 interrupt	0x0000 00B0
29	36	Settable	EXTI9	EXTI line 9 interrupt	0x0000 00B4
30	37	Settable	EXTI10	EXTI line 10 interrupt	0x0000 00B8
31	38	Settable	EXTI11	EXTI line 11 interrupt	0x0000 00BC
32	39	Settable	EXTI12	EXTI line 12 interrupt	0x0000 00C0
33	40	Settable	EXTI13	EXTI line 13 interrupt	0x0000 00C4
34	41	Settable	EXTI14	EXTI line 14 interrupt	0x0000 00C8
35	42	Settable	EXTI15	EXTI line 15 interrupt	0x0000 00CC
36	43	Settable	SAES	SAES global interrupt	0x0000 00D0
37	44	Settable	CRYP	CRYP global interrupt	0x0000 00D4
38	45	Settable	PKA	PKA global interrupt	0x0000 00D8
39	46	Settable	HASH	HASH global interrupt	0x0000 00DC
40	47	Settable	RNG	RNG global interrupt	0x0000 00E0
-	48	-	Reserved	Reserved	0x0000 00E4
42	49	Settable	MCE1	MCE1 global interrupt	0x0000 00E8
43	50	Settable	MCE2	MCE2 global interrupt	0x0000 00EC
44	51	Settable	MCE3	MCE3 global interrupt	0x0000 00F0
45	52	Settable	MCE4	MCE4 global interrupt	0x0000 00F4
46	53	Settable	ADC12	ADC1/ADC2 global interrupt	0x0000 00F8
47	54	Settable	CSI	CSI global interrupt	0x0000 00FC
48	55	Settable	DCMIPP	DCMIPP global interrupt	0x0000 0100
-	56	-	Reserved	Reserved	0x0000 0104

Table 134. STM32N6x5/x7xx vector table (continued)

NVIC position	Priority	Priority type	Acronym	Description	Address
-	57	-	Reserved	Reserved	0x0000 0108
-	58	-	Reserved	Reserved	0x0000 010C
52	59	Settable	PAHB_ERR	Write posting errors on Cortex-M55 PAHB interface	0x0000 0110
53	60	Settable	NPU0 ⁽¹⁾	NPU mst_ints[0] line	0x0000 0114
54	61	Settable	NPU1 ⁽¹⁾	NPU mst_ints[1] line	0x0000 0118
55	62	Settable	NPU2 ⁽¹⁾	NPU mst_ints[2] line	0x0000 011C
56	63	Settable	NPU3 ⁽¹⁾	NPU mst_ints[3] line	0x0000 0120
57	64	Settable	CACHEAXI ⁽¹⁾	CACHEAXI NPU interrupt cache	0x0000 0124
58	65	Settable	LTDC_LO	LCD low-layer global interrupt	0x0000 0128
59	66	Settable	LTDC_LO_ERR	LCD low-layer error interrupt	0x0000 012C
60	67	Settable	DMA2D	DMA2D global interrupt	0x0000 0130
61	68	Settable	JPEG	JPEG global interrupt	0x0000 0134
62	69	Settable	VENC	VENC global interrupt	0x0000 0138
63	70	Settable	GFXMMU	GFXMMU global interrupt	0x0000 013C
64	71	Settable	GFXTIM	GFXTIM global interrupt	0x0000 0140
65	72	Settable	GPU2D	GPU2D global interrupt	0x0000 0144
66	73	Settable	GPU2D_ERROR	GPU2D error interrupt	0x0000 0148
67	74	Settable	ICACHE	GPU2D cache interrupt	0x0000 014C
68	75	Settable	HPDMA1_CH0	HPDMA1 channel 0 interrupt	0x0000 0150
69	76	Settable	HPDMA1_CH1	HPDMA1 channel 1 interrupt	0x0000 0154
70	77	Settable	HPDMA1_CH2	HPDMA1 channel 2 interrupt	0x0000 0158
71	78	Settable	HPDMA1_CH3	HPDMA1 channel 3 interrupt	0x0000 015C
72	79	Settable	HPDMA1_CH4	HPDMA1 channel 4 interrupt	0x0000 0160
73	80	Settable	HPDMA1_CH5	HPDMA1 channel 5 interrupt	0x0000 0164
74	81	Settable	HPDMA1_CH6	HPDMA1 channel 6 interrupt	0x0000 0168
75	82	Settable	HPDMA1_CH7	HPDMA1 channel 7 interrupt	0x0000 016C
76	83	Settable	HPDMA1_CH8	HPDMA1 channel 8 interrupt	0x0000 0170
77	84	Settable	HPDMA1_CH9	HPDMA1 channel 9 interrupt	0x0000 0174
78	85	Settable	HPDMA1_CH10	HPDMA1 channel 10 interrupt	0x0000 0178
79	86	Settable	HPDMA1_CH11	HPDMA1 channel 11 interrupt	0x0000 017C
80	87	Settable	HPDMA1_CH12	HPDMA1 channel 12 interrupt	0x0000 0180

Table 134. STM32N6x5/x7xx vector table (continued)

NVIC position	Priority	Priority type	Acronym	Description	Address
81	88	Settable	HPDMA1_CH13	HPDMA1 channel 13 interrupt	0x0000 0184
82	89	Settable	HPDMA1_CH14	HPDMA1 channel 14 interrupt	0x0000 0188
83	90	Settable	HPDMA1_CH15	HPDMA1 channel 15 interrupt	0x0000 018C
84	91	Settable	GPDMA1_CH0	GPDMA1 channel 0 interrupt	0x0000 0190
85	92	Settable	GPDMA1_CH1	GPDMA1 channel 1 interrupt	0x0000 0194
86	93	Settable	GPDMA1_CH2	GPDMA1 channel 2 interrupt	0x0000 0198
87	94	Settable	GPDMA1_CH3	GPDMA1 channel 3 interrupt	0x0000 019C
88	95	Settable	GPDMA1_CH4	GPDMA1 channel 4 interrupt	0x0000 01A0
89	96	Settable	GPDMA1_CH5	GPDMA1 channel 5 interrupt	0x0000 01A4
90	97	Settable	GPDMA1_CH6	GPDMA1 channel 6 interrupt	0x0000 01A8
91	98	Settable	GPDMA1_CH7	GPDMA1 channel 7 interrupt	0x0000 01AC
92	99	Settable	GPDMA1_CH8	GPDMA1 channel 8 interrupt	0x0000 01B0
93	100	Settable	GPDMA1_CH9	GPDMA1 channel 9 interrupt	0x0000 01B4
94	101	Settable	GPDMA1_CH10	GPDMA1 channel 10 interrupt	0x0000 01B8
95	102	Settable	GPDMA1_CH11	GPDMA1 channel 11 interrupt	0x0000 01BC
96	103	Settable	GPDMA1_CH12	GPDMA1 channel 12 interrupt	0x0000 01C0
97	104	Settable	GPDMA1_CH13	GPDMA1 channel 13 interrupt	0x0000 01C4
98	105	Settable	GPDMA1_CH14	GPDMA1 channel 14 interrupt	0x0000 01C8
99	106	Settable	GPDMA1_CH15	GPDMA1 channel 15 interrupt	0x0000 01CC
100	107	Settable	I2C1_EV	I2C1 event interrupt	0x0000 01D0
101	108	Settable	I2C1_ER	I2C1 error interrupt	0x0000 01D4
102	109	Settable	I2C2_EV	I2C2 event interrupt	0x0000 01D8
103	110	Settable	I2C2_ER	I2C2 error interrupt	0x0000 01DC
104	111	Settable	I2C3_EV	I2C3 event interrupt	0x0000 01E0
105	112	Settable	I2C3_ER	I2C3 error interrupt	0x0000 01E4
106	113	Settable	I2C4_EV	I2C4 event interrupt	0x0000 01E8
107	114	Settable	I2C4_ER	I2C4 error interrupt	0x0000 01EC
108	115	Settable	I3C1_EV	I3C1 event interrupt	0x0000 01F0
109	116	Settable	I3C1_ER	I3C1 error interrupt	0x0000 01F4
110	117	Settable	I3C2_EV	I3C2 event interrupt	0x0000 01F8
111	118	Settable	I3C2_ER	I3C2 error interrupt	0x0000 01FC
112	119	Settable	TIM1_BRK	TIM1 break interrupt	0x0000 0200

Table 134. STM32N6x5/x7xx vector table (continued)

NVIC position	Priority	Priority type	Acronym	Description	Address
113	120	Settable	TIM1_UP	TIM1 update interrupt	0x0000 0204
114	121	Settable	TIM1_TRG_COM	TIM1 trigger and commutation interrupts	0x0000 0208
115	122	Settable	TIM1_CC	TIM1 capture compare interrupt	0x0000 020C
116	123	Settable	TIM2	TIM2 global interrupt	0x0000 0210
117	124	Settable	TIM3	TIM3 global interrupt	0x0000 0214
118	125	Settable	TIM4	TIM4 global interrupt	0x0000 0218
119	126	Settable	TIM5	TIM5 global interrupt	0x0000 021C
120	127	Settable	TIM6	TIM6 global interrupt	0x0000 0220
121	128	Settable	TIM7	TIM7 global interrupt	0x0000 0224
122	129	Settable	TIM8_BRK	TIM8 break interrupt	0x0000 0228
123	130	Settable	TIM8_UP	TIM18 update interrupt	0x0000 022C
124	131	Settable	TIM8_TRG_COM	TIM8 trigger and commutation interrupts	0x0000 0230
125	132	Settable	TIM8_CC	TIM8 capture compare interrupt	0x0000 0234
126	133	Settable	TIM9	TIM9 global interrupt	0x0000 0238
127	134	Settable	TIM10	TIM10 global interrupt	0x0000 023C
128	135	Settable	TIM11	TIM11 global interrupt	0x0000 0240
129	136	Settable	TIM12	TIM12 global interrupt	0x0000 0244
130	137	Settable	TIM13	TIM13 global interrupt	0x0000 0248
131	138	Settable	TIM14	TIM14 global interrupt	0x0000 024C
132	139	Settable	TIM15	TIM15 global interrupt	0x0000 0250
133	140	Settable	TIM16	TIM16 global interrupt	0x0000 0254
134	141	Settable	TIM17	TIM17 global interrupt	0x0000 0258
135	142	Settable	TIM18	TIM18 global interrupt	0x0000 025C
136	143	Settable	LPTIM1	LPTIM1 global interrupt	0x0000 0260
137	144	Settable	LPTIM2	LPTIM2 global interrupt	0x0000 0264
138	145	Settable	LPTIM3	LPTIM3 global interrupt	0x0000 0268
139	146	Settable	LPTIM4	LPTIM4 global interrupt	0x0000 026C
140	147	Settable	LPTIM5	LPTIM5 global interrupt	0x0000 0270
141	148	Settable	ADF1_FLT0	ADF1 filter 0 global interrupt	0x0000 0274
142	149	Settable	MDF1_FLT0	MDF global Interrupt for filter 0	0x0000 0278
143	150	Settable	MDF1_FLT1	MDF global Interrupt for filter 1	0x0000 027C
144	151	Settable	MDF1_FLT2	MDF global Interrupt for filter 2	0x0000 0280

Table 134. STM32N6x5/x7xx vector table (continued)

NVIC position	Priority	Priority type	Acronym	Description	Address
145	152	Settable	MDF1_FLT3	MDF global Interrupt for filter 3	0x0000 0284
146	153	Settable	MDF1_FLT4	MDF global Interrupt for filter 4	0x0000 0288
147	154	Settable	MDF1_FLT5	MDF global Interrupt for filter 5	0x0000 028C
148	155	Settable	SAI1_A	SAI1 global interrupt A	0x0000 0290
149	156	Settable	SAI1_B	SAI1 global interrupt B	0x0000 0294
150	157	Settable	SAI2_A	SAI2 global interrupt A	0x0000 0298
151	158	Settable	SAI2_B	SAI2 global interrupt B	0x0000 029C
152	159	Settable	SPDIFRX1	SPDIFRX global interrupt	0x0000 02A0
153	160	Settable	SPI1	SPI1 global interrupt	0x0000 02A4
154	161	Settable	SPI2	SPI2 global interrupt	0x0000 02A8
155	162	Settable	SPI3	SPI3 global interrupt	0x0000 02AC
156	163	Settable	SPI4	SPI4 global interrupt	0x0000 02B0
157	164	Settable	SPI5	SPI5 global interrupt	0x0000 02B4
158	165	Settable	SPI6	SPI6 global interrupt	0x0000 02B8
159	166	Settable	USART1	USART1 global interrupt	0x0000 02BC
160	167	Settable	USART2	USART2 global interrupt	0x0000 02C0
161	168	Settable	USART3	USART3 global interrupt	0x0000 02C4
162	169	Settable	UART4	UART4 global interrupt	0x0000 02C8
163	170	Settable	UART5	UART5 global interrupt	0x0000 02CC
164	171	Settable	USART6	UART5 global interrupt	0x0000 02D0
165	172	Settable	UART7	UART5 global interrupt	0x0000 02D4
166	173	Settable	UART8	UART5 global interrupt	0x0000 02D8
167	174	Settable	UART9	UART9 global interrupt	0x0000 02DC
168	175	Settable	USART10	USART10 global interrupt	0x0000 02E0
169	176	Settable	LPUART1	LPUART1 global interrupt	0x0000 02E4
170	177	Settable	XSPI1	XSPI1 global interrupt	0x0000 02E8
171	178	Settable	XSPI2	XSPI2 global interrupt	0x0000 02EC
172	179	Settable	XSPI3	XSPI3 global interrupt	0x0000 02F0
173	180	Settable	FMC	FMC global interrupt	0x0000 02F4
174	181	Settable	SDMMC1	SDMMC1 global interrupt	0x0000 02F8
175	182	Settable	SDMMC2	SDMMC2 global interrupt	0x0000 02FC
176	183	Settable	UCPD1	UCPD global interrupt	0x0000 0300

Table 134. STM32N6x5/x7xx vector table (continued)

NVIC position	Priority	Priority type	Acronym	Description	Address
177	184	Settable	OTG1	USB OTG1 HS global interrupt	0x0000 0304
178	185	Settable	OTG2	USB OTG2 HS global interrupt	0x0000 0308
179	186	Settable	ETH1	Ethernet global interrupt	0x0000 030C
180	187	Settable	FDCAN1_IT0	FDCAN1 interrupt 0	0x0000 0310
181	188	Settable	FDCAN1_IT1	FDCAN1 interrupt 1	0x0000 0314
182	189	Settable	FDCAN2_IT0	FDCAN2 interrupt 0	0x0000 0318
183	190	Settable	FDCAN2_IT1	FDCAN2 interrupt 1	0x0000 031C
184	191	Settable	FDCAN3_IT0	FDCAN3 interrupt 0	0x0000 0320
185	192	Settable	FDCAN3_IT1	FDCAN3 interrupt 1	0x0000 0324
186	193	Settable	FDCAN_CU	Clock calibration unit interrupt line (FDCAN1 only)	0x0000 0328
187	194	Settable	MDIOS	MDIOS global interrupt	0x0000 032C
188	195	Settable	DCMI_PSSI	DCMI/PSSI global interrupt	0x0000 0330
189	196	Settable	WAKEUP_PIN	Wake-up pin interrupts	0x0000 0334
190	197	Settable	CTI0	Debug monitor (Cortex-M55 related)	0x0000 0338
191	198	Settable	CTI1	Debug monitor (Cortex-M55 related)	0x0000 033C
-	199	-	Reserved	Reserved	0x0000 0340
193	200	Settable	LTDC_UP	LCD up-layer global interrupt	0x0000 0344
194	201	Settable	LTDC_UP_ERR	LCD up-layer error interrupt	0x0000 0348

1. Reserved on STM32N6x5xx devices.