22. Chrom-GRC (GFXMMU)

22.1 GFXMMU introduction

The Chrom-GRC (GFXMMU) is a graphical oriented memory management unit aimed to optimize memory usage according to the display shape.

22.2 GFXMMU main features

• • Fully programmable display shape to physically store only the visible pixel
• • Up to 4 virtual buffers
• • Each virtual buffer have 3072 or 4096 bytes per line and 1024 lines
• • Each virtual buffer can be physically mapped to any system memory
• • Packing and unpacking operation to store 32-bit pixel data into 24-bit packed
• • Interrupt in case of buffer overflow (1 per buffer)
• • Interrupt in case of memory transfer error

22.3 GFXMMU functional and architectural description

The GFXMMU is responsible of address resolution to convert the virtual buffer address into the physical buffer address.

22.3.1 GFXMMU block diagram

Figure 135. GFXMMU block diagram

22.3.2 GFXMMU internal signals

22.3.3 Virtual memory

The GFXMMU provides a virtual memory space seen by the system masters. This virtual memory space is divided into four virtual buffers.

Virtual buffer

A virtual buffer is seen by any system master as a continuous memory space representing a virtual frame buffer of 1024 lines.

Each line is divided into 256 12-byte or 16-byte blocks depending on the BS bit of the GFXMMU configuration register (GFXMMU_CR).

When the address translation is enabled setting the address translation enable (ATE) bit of the graphic MMU configuration register (GFXMMU_CR), each line can be configured individually to be mapped onto a physical memory.

Depending on the display shape and size, only the necessary blocks are mapped to a physical memory location. This mapping is done programming the LUT entry for each line:

• • The enable of the line
• • The number of the first “visible” block
• • The number of the last “visible” block
• • The address offset of the line within the physical buffer

The “visible” blocks can be arranged in the physical buffer in a continuous way programming the address offset of each line.

The LUT is common to all the buffers i.e. all the buffers have the same “shape”.

Figure 136. Virtual buffer

Virtual buffer overview

For a frame buffer coded in 32 bpp or 16 bpp, the virtual buffer can be configured to have 12-byte or 16-byte blocks. This results in a virtual frame buffer of 768 x 1024 or 1024 x 1024 pixels for 32 bpp and 1536 x 1024 or 2048 x 1024 for 16 bpp.

For a frame buffer coded in 24 bpp, the virtual buffer must be configured to have 12-byte blocks to have an integer number of pixel per lines. This results in a virtual frame buffer of 1024 x 1024 pixels for 24 bpp.

Each buffer can be physically mapped anywhere in the physical memory thanks to:

• • The physical buffer base address (PBBA) field of the GFXMMU buffer x configuration register (GFXMMU_BxCr). It configures the physical location of the 8-Mbyte area where the buffer is mapped.
• • The physical buffer location respective to the physical buffer base address is defined by the physical buffer offset (PBO) field of the GFXMMU buffer x configuration register (GFXMMU_BxCr).

Figure 137. Virtual buffer and physical buffer memory map

The buffer can not overflow the 8-Mbyte boundary of the zone defined by its base address. In case of overflow, the buffer x overflow flag (BxOF) of the GFXMMU status register (GFXMMU_SR) is set and an interrupt is generated if the buffer x overflow interrupt enable (BxOIE) bit of the GFXMMU configuration register (GFXMMU_CR) is set.

Virtual buffer application use case

As the physical locations are independently configurable, the four virtual buffers can be physically mapped to non continuous locations. This allows for example to have the four buffers mapped on to four different SDRAM banks and avoid extra precharge cycles accessing the SDRAM.

As a consequence, one buffer must be used by the CPU/Graphic accelerator for frame buffer calculation while an other one must be used by the LTDC.

The two remaining buffers can be used as a graphical library requiring extra drawing buffers.

22.3.4 Packing and unpacking

When addressing 24bpp frame buffers, the virtual buffer must be configured in 12-byte block mode to have an integer number of pixel per block.

Nevertheless, it is possible to access these 24-bit data as if they were unpacked in a 32-bit word.

The packing mode is enabled, per buffer setting the buffer x packing enable (BxPE) bit of the graphic MMU configuration register (GFXMMU_CR).

When the packing mode is enabled and the 12-byte mode is selected, the access to the buffer are done as in 16-byte mode, but either the most significant byte or the less significant byte is ignored to transform each 32-bit word into a 24-bit word.

The ignored byte is selected with the buffer x packing mode (BxPM) bit of the graphic MMU configuration register (GFXMMU_CR).

During write operation MSB or LSB is ignored. During read operation, the ignored MSB or LSB is replaced by the 8-bit default value programmed in the default alpha (DA) field of the graphic MMU default alpha register (GFXMMU_DAR)

The buffer x packing enable (BxPE) bit has no effect when the graphic MMU is configured in 16-byte block.

22.3.5 MMU architecture

The MMU block is responsible of the address resolution. It receives the 24-bit address and returns the physical 23-bit address and a valid signals to indicate the address is physically mapped or not. The MMU also checks overflow of a area boundary.

The MMU LUT is implemented as a 1024 x 35-bit RAM

Figure 138. MMU block diagram

Line block decoder

The line block decoder is generating the block number and the line number according the address.

Look up RAM

The look up RAM is a 1024 x 35-bit RAM with the following fields:

• • 1-bit line enable
• • 8-bit first valid block
• • 8-bit last valid block
• • 18-bit for line offset

As the RAM is bigger than a word, each entry is split into two words on the memory map. The write access are done in two steps:

1. 1. Write the first word with enable/first valid block/last valid block in the GFXMMU_LUTxL memory location (internally buffered).
2. 2. Write the second word with line offset in the GFXMMU_LUTxH memory location (effective write into the memory together with the internally buffered value).

A write in the LUT can happen any time but it can lead to inconsistencies if a master is using the MMU at the same time. As the CPU has the priority during LUT programming, this may slow down MMU calculation.

There is no restriction during read operations, but this may slow down CPU as the MMU has the priority on LUT accesses.

Block validation/comparator

This block is checking if the block is valid.

A block is considered as valid (physically mapped) when:

• • Line is enable.
• • The block number is greater or equal to the first valid block.
• • The block number is lower or equal to the last valid block.

When the block is valid, the physical address generated is considered as correct.

If the result of the MMU evaluation is not valid, the write operations are ignored, and read operations return the default 32-bit value stored in the default value (DV) field of the GFXMMU default value register (GFXMMU_DVR).

Block offset address calculation within the buffer

The block number is added to the line offset to get the offset of the block within the physical buffer.

As a consequence, the line offset stored in the LUT is given by the following formula:

with:

• • The maximum value for the line offset is when all the block of all the line are used. As the consequence the line offset for the last line can be maximum:
  1023 x 256 = 0x3:FF00
• • The minimum value for the line offset is when the last block of the first line is the first valid block: -255 = - 0xFF i.e 0x3:FF01

As the consequence the full range of the line offset entry of the LUT is used.

Carry is not taken into account as this stage to be able to perform negative offset calculations (values from 0x3:FF01 to 0x3:FFFF)

As the block offset is within a 4-Mbyte buffer, the address generated is 22-bit wide.

Block offset address calculation

Once the offset of the block within the buffer has been calculated, this value is added to the offset of the block respective to the physical buffer base address.

The offset of the blocks are defined in registers as shown in Figure 139 :

Figure 139. Block validation/comparator implementation

The resulting address and the buffer offset address must be on 23-bit.

The carry is taken into account to trigger address overflow. The carry is propagated to the GFXMMU status register (GFXMMU_SR) to set the buffer x overflow flag (BxOF).

Example of calculation

Consider the following configuration for virtual buffer 0:

• • 16-byte block mode
• • First visible block of line 0: block 7
• • Number of visible block in line 0: 10
• • First visible block of line 1: block 6
• • Number of visible block in line 1: 12
• • Address of the physical buffer: 0xC020:0000

The configuration must be:

• • The base address of the physical buffer 0: 0xC000:0000
• • The offset of buffer 0: 0x20:0000
• • First visible block of line 0: block 7
• • Last visible block of line 0: block 16
• • Block 0 offset of line 0: (0 - 7) = -0x7 = 0x3:FFF9
• • First visible block of line 1: block 6
• • Last visible block of line 1: block 17
• • Block 0 offset of line 1: (10 - 6) = (0xA - 0x6) = 0x4

As a consequence:

• the physical address of block 7 of line 0 is:

\( 0xC000:0000 + 0x20:0000 + (0x3:FFF9 + 0x7 \text{ without carry}) \times 0x10 = 0xC020:0000 \)

• the physical address of block 16 of line 0 is:

\( 0xC000:0000 + 0x20:0000 + (0x3:FFF9 + 0x10 \text{ without carry}) \times 0x10 = 0xC020:0090 \)

• the physical address of block 6 of line 1 is:

\( 0xC000:0000 + 0x20:0000 + (0x4 + 0x6 \text{ without carry}) \times 0x10 = 0xC020:00A0 \)

• the physical address of block 17 of line 1 is:

\( 0xC000:0000 + 0x20:0000 + (0x4 + 0x11 \text{ without carry}) \times 0x10 = 0xC020:0150 \)

For the same example in 12-byte mode, the user has the same configuration regarding the offsets but the addresses are different in the physical buffer:

• the physical address of block 7 of line 0 is:

\( 0xC000:0000 + 0x20:0000 + (0x3:FFF9 + 0x7 \text{ without carry}) \times 0x0C = 0xC020:0000 \)

• the physical address of block 16 of line 0 is:

\( 0xC000:0000 + 0x20:0000 + (0x3:FFF9 + 0x10 \text{ without carry}) \times 0x0C = 0xC020:006C \)

• the physical address of block 6 of line 1 is:

\( 0xC000:0000 + 0x20:0000 + (0x4 + 0x6 \text{ without carry}) \times 0x0C = 0xC020:0078 \)

• the physical address of block 17 of line 1 is:

\( 0xC000:0000 + 0x20:0000 + (0x4 + 0x11 \text{ without carry}) \times 0x0C = 0xC020:00FC \)

22.4 GTZC TZIC GFXMMU interrupts

An interrupt can be produced on the following events:

• Buffer 0 overflow
• Buffer 1 overflow
• Buffer 2 overflow
• Buffer 3 overflow
• AXI master error

Separate interrupt enable bits are available for flexibility.

Table 127. GFXMMU interrupt requests

22.5 GFXMMU registers

22.5.1 GFXMMU configuration register (GFXMMU_CR)

Address offset: 0x0000

Reset value: 0x0000 0000

Bit 31 B3PM : Buffer 3 packing mode

This bit selects the byte to be removed during packing operations on buffer 3

0: MSB is removed

1: LSB is removed

Bit 30 B3PE : Buffer 3 packing enable

This bit enables the packing on buffer 3.

The packing is functional only if the block size is configured in 12-byte mode. In 16-byte mode, this bit is ignored.

0: Packing is disabled

1: Packing is enable

Bit 29 B2PM : Buffer 2 packing mode

This bit selects the byte to be removed during packing operations on buffer 2

0: MSB is removed

1: LSB is removed

Bit 28 B2PE : Buffer 2 packing enable

This bit enables the packing on buffer 2.

The packing is functional only if the block size is configured in 12-byte mode. In 16-byte mode, this bit is ignored.

0: Packing is disabled

1: Packing is enable

Bit 27 B1PM : Buffer 1 packing mode

This bit selects the byte to be removed during packing operations on buffer 1

0: MSB is removed

1: LSB is removed

Bit 26 B1PE : Buffer 1 packing enable

This bit enables the packing on buffer 1.

The packing is functional only if the block size is configured in 12-byte mode. In 16-byte mode, this bit is ignored.

0: Packing is disabled

1: Packing is enable

Bit 25 B0PM : Buffer 0 packing mode

This bit selects the byte to be removed during packing operations on buffer 0

0: MSB is removed

1: LSB is removed

Bit 24 B0PE : Buffer 0 packing enable

This bit enables the packing on buffer 0.

The packing is functional only if the block size is configured in 12-byte mode. In 16-byte mode, this bit is ignored.

0: Packing is disabled

1: Packing is enable

Bits 23:16 Reserved, must be kept at reset value.

Bit 15 ATE : Address translation enable

This bit enables the address translation based on the values programmed in the LUT.

0: Address translation is disable

1: Address translation is enable

Bits 14:7 Reserved, must be kept at reset value.

Bit 6 BS : Block size

This bit defines the size of the blocks

0: 16-byte blocks

1: 12-byte blocks

Bit 5 Reserved, must be kept at reset value.

Bit 4 AMEIE : AXI master error interrupt enable

This bit enables the AXI master error interrupt.

0: Interrupt disable

1: Interrupt enabled

Bit 3 B3OIE : Buffer 3 overflow interrupt enable

This bit enables the buffer 3 overflow interrupt.

0: Interrupt disable

1: Interrupt enabled

Bit 2 B2OIE : Buffer 2 overflow interrupt enable

This bit enables the buffer 2 overflow interrupt.

0: Interrupt disable

1: Interrupt enabled

Bit 1 B1OIE : Buffer 1 overflow interrupt enable

This bit enables the buffer 1 overflow interrupt.

0: Interrupt disable

1: Interrupt enabled

Bit 0 B0OIE : Buffer 0 overflow interrupt enable

This bit enables the buffer 0 overflow interrupt.

0: Interrupt disable

1: Interrupt enabled

22.5.2 GFXMMU status register (GFXMMU_SR)

Address offset: 0x0004

Reset value: 0x0000 0000

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 AMEF : AXI master error flag

This bit is set when an AXI error happens during a transaction. It is cleared by writing 1 to CAMEF.

Bit 3 B3OF : Buffer 3 overflow flag

This bit is set when an overflow occurs during the offset calculation of the buffer 3. It is cleared by writing 1 to CB3OF.

Bit 2 B2OF : Buffer 2 overflow flag

This bit is set when an overflow occurs during the offset calculation of the buffer 2. It is cleared by writing 1 to CB2OF.

Bit 1 B1OF : Buffer 1 overflow flag

This bit is set when an overflow occurs during the offset calculation of the buffer 1. It is cleared by writing 1 to CB1OF.

Bit 0 B0OF : Buffer 0 overflow flag

This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF.

22.5.3 GFXMMU flag clear register (GFXMMU_FCR)

Address offset: 0x0008

Reset value: 0x0000 0000

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CAMEF : Clear AXI master error flag

Writing 1 clears the AXI master error flag in the GFXMMU_SR register.

Bit 3 CB3OF : Clear buffer 3 overflow flag

Writing 1 clears the buffer 3 overflow flag in the GFXMMU_SR register.

• Bit 2 CB2OF : Clear buffer 2 overflow flag
  Writing 1 clears the buffer 2 overflow flag in the GFXMMU_SR register.
• Bit 1 CB1OF : Clear buffer 1 overflow flag
  Writing 1 clears the buffer 1 overflow flag in the GFXMMU_SR register.
• Bit 0 CB0OF : Clear buffer 0 overflow flag
  Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register.

22.5.4 GFXMMU default value register (GFXMMU_DVR)

Address offset: 0x0010

Reset value: 0x0000 0000

Bits 31:0 DV[31:0] : Default value
This field indicates the default 32-bit value which is returned when a master accesses a virtual memory location not physically mapped.

22.5.5 GFXMMU default alpha register (GFXMMU_DAR)

Address offset: 0x0014

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 DA[7:0] : Default alpha
This field indicates the default 8-bit value which is merged with the 24-bit value when a master accesses a virtual memory location in packed mode.

22.5.6 GFXMMU buffer x configuration register (GFXMMU_BxCR)

Address offset: 0x0020 + 0x4 * x, (x = 0 to 3)

Reset value: 0x0000 0000

Bits 31:23 PBBA[31:23] : Physical buffer base address
Base address MSB of the physical buffer.

Bits 22:4 PBO[22:4] : Physical buffer offset
Offset of the physical buffer.

Bits 3:0 Reserved, must be kept at reset value.

22.5.7 GFXMMU LUT entry x low (GFXMMU_LUTxL)

Address offset: 0x1000 + 0x8 * x, (x = 0 to 1023)

Reset value: 0x0000 0000

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 LVB[7:0] : Last valid block
Number of the last valid block of line number X.

Bits 15:8 FVB[7:0] : First valid block
Number of the first valid block of line number x.

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 EN : Enable
Line enable.
0: Line is disabled (no MMU evaluation is performed)
1: Line is enabled (MMU evaluation is performed)

22.5.8 GFXMMU LUT entry x high (GFXMMU_LUTxH)

Address offset: 0x1004 + 0x8 * x, (x = 0 to 1023)

Reset value: 0x0000 0000

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:0 LO[17:0] : Line offset

Line offset of line number x expressed in number of blocks

22.5.9 GFXMMU register map

Table 128. GFXMMU register map and reset values

Table 128. GFXMMU register map and reset values (continued)

Refer to Section 2.3: Memory organization for the register boundary addresses.