18. High-performance direct memory access controller (HPDMA)

18.1 HPDMA introduction

The high-performance direct memory access (HPDMA) controller is a bus master and system peripheral.

The HPDMA is used to perform programmable data transfers between memory-mapped peripherals, and/or memories via linked-lists, upon the control of an off-loaded CPU.

18.2 HPDMA main features

• • Single bidirectional 64-bit AXI master and single bidirectional 32-bit AHB master
• • Memory-mapped data transfers from a source to a destination:
  • – Peripheral-to-memory
  • – Memory-to-peripheral
  • – Memory-to-memory
  • – Peripheral-to-peripheral
  Transfer arbitration based on a 4-grade programmed priority at channel level:
  • – One high-priority traffic class, for time-sensitive channels (queue 3)
  • – Three low-priority traffic classes, with a weighted round-robin allocation for non time-sensitive channels (queues 0, 1, 2)
• • Per channel event generation, on any of the following events: transfer complete, half-transfer complete, data transfer error, user setting error, link transfer error, completed suspension, and trigger overrun
• • Per channel interrupt generation, with separately programmed interrupt enable per event
• • 16 concurrent HPDMA channels:
  • – Per channel FIFO for queuing source and destination transfers (see Section 18.3.1 )
  • – Intra-channel HPDMA transfers chaining via programmable linked-list into memory, supporting two execution modes: run-to-completion and link step mode
• • Per linked-list item within a channel:
  • – Separately programmed source and destination transfers
  • – Programmable data handling between source and destination: byte-based reordering, packing or unpacking, padding or truncation, sign extension and left/right realignment
  • – Programmable number of data bytes to be transferred from the source, defining the block level
  • – Linear source and destination addressing: either fixed or contiguously incremented addressing, programmed at block level, between successive burst transfers
  • – 2D source and destination addressing: programmable signed address offsets between successive burst transfers (non-contiguous addressing within a block,

1. combined with programmable signed address offsets between successive blocks, at a second 2D/repeated block level, for a reduced set of channels (see Section 18.3.1 )
2. • – Support for scatter-gather (multi-buffer transfers), data interleaving and deinterleaving via 2D addressing
   • – Selection of programmable HPDMA request and trigger
   • – Generation of programmable HPDMA half-transfer and transfer-complete event
   • – Pointer to the next linked-list item and its data structure in memory, with automatic update of the HPDMA linked-list control registers
   • – Channel abort and restart
   • • Debug:
     • – Channel suspend and resume support
     • – Channel status reporting, including FIFO level, and event flags
   • • TrustZone support:
     • – Support for secure and nonsecure HPDMA transfers, independently at a first channel level, and independently at a source/destination and link sublevels
     • – Secure and nonsecure interrupts reporting, resulting from any of the respectively secure and nonsecure channels
     • – TrustZone-aware AHB slave port, protecting any HPDMA secure resource (register, bitfield) from a nonsecure access
   • • Privileged/unprivileged support:
     • – Support for privileged and unprivileged HPDMA transfers, independently at channel level
     • – Privileged-aware AHB slave port
   • • Channel isolation support:
     • – Support for compartmented DMA transfers, independently at channel level, via compartment IDs (named CIDs)
     • – CID-aware interrupts reporting
     • – CID-aware AHB slave port, with integrated semaphores for a concurrent control, from any of the CPUs

18.3 HPDMA implementation

18.3.1 HPDMA channels

A given HPDMA channel x is implemented with the following features and intended use.

To make the best use of the HPDMA performance, the following table lists some general recommendations, allowing the user to select and allocate a channel, given its implemented FIFO size and the requested HPDMA transfer.

Table 84. Implementation of HPDMA1 channels

18.3.2 HPDMA allowed AXI maximum burst length

For a data transfer, the user has to program:

• – the source (and destination) burst length that a given channel x ideally performs, via SBL_1[5:0] (and respectively DBL_1[5:0]) field in HPDMA_CxTR1.
• – the allocated master port, AXI or AHB, on which this source (or destination) data transfer must be performed, via SAP (or respectively DAP) field in HPDMA_CxTR1.

Caution: The maximum allowed AXI burst length is restricted to 16:

1. 1. if SAP = 0 (AXI allocated port): the maximum allowed value of SBL_1[5:0] is 15.
2. 2. if DAP = 0 (AXI allocated port): the maximum allowed value of DBL_1[5:0] is 15.

18.3.3 HPDMA in low-power modes

The HPDMA wake-up feature is implemented in the device low-power modes as per the table below.

Table 85. HPDMA1 in low-power modes

18.3.4 HPDMA requests

An HPDMA request from a peripheral can be assigned to a HPDMA channel x, via REQSEL[7:0] in HPDMA_CxTR2, provided that SWREQ = 0.

The HPDMA requests mapping is specified in the table below.

Table 86. Programmed HPDMA1 request

Table 86. Programmed HPDMA1 request (continued)

Table 86. Programmed HPDMA1 request (continued)

Table 86. Programmed HPDMA1 request (continued)

Table 86. Programmed HPDMA1 request (continued)

18.3.5 HPDMA block requests

Some HPDMA requests must be programmed as a block request, and not as a burst request. Then BREQ in HPDMA_CxTR2 must be set for a correct HPDMA execution of the requested peripheral transfer at the hardware level.

Table 87. Programmed HPDMA1 request as a block request

18.3.6 HPDMA channels with peripheral early termination

An HPDMA channel, if implemented with this feature, can support the early termination of the data transfer from the peripheral which does also support this feature.

Table 88. HPDMA1 channel with peripheral early termination

This HPDMA support is activated when the channel x is programmed with HPDMA_CxTR2.PFREQ = 1. Then, the peripheral itself can initiate and request a data transfer completion, before the HPDMA has transferred the whole block (see Section 18.4.14 for more details).

Table 89. Programmed HPDMA1 request with peripheral early termination

18.3.7 HPDMA triggers

An HPDMA trigger can be assigned to an HPDMA channel x, via TRIGSEL[6:0] in HPDMA_CxTR2, provided that TRIGPOL[1:0] defines a rising or a falling edge of the selected trigger (TRIGPOL[1:0] = 01 or TRIGPOL[1:0] = 10).

Table 90. Programmed HPDMA1 trigger

Table 90. Programmed HPDMA1 trigger (continued)

Table 90. Programmed HPDMA1 trigger (continued)

Table 90. Programmed HPDMA1 trigger (continued)

18.4 HPDMA functional description

18.4.1 HPDMA block diagram

Figure 72. HPDMA block diagram

18.4.2 HPDMA channel state and direct programming without any linked-list

After an HPDMA reset, an HPDMA channel x is in idle state. When the software writes 1 into the HPDMA_CxCR.EN enable control bit, the channel takes into account the value of the different channel configuration registers (HPDMA_CxXXX), switches to the active/non-idle state, and starts to execute the corresponding requested data transfers.

After enabling/starting an HPDMA channel transfer by writing 1 into HPDMA_CxCR.EN, an HPDMA channel interrupt on a complete transfer notifies the software that the HPDMA channel is back in idle state (EN is then deasserted by hardware), and that the channel is ready to be reconfigured then enabled again.

The figure below illustrates this HPDMA direct programming without any linked-list (HPDMA_CxLLR = 0).

Figure 73. HPDMA channel direct programming without linked-list (HPDMA_CxLLR = 0)

graph TD
    subgraph "Channel state = Idle"
    Init[Initialize DMA channel
keeping DMA_CxLLR[31:0] = 0] 
    Reconfig[Reconfigure DMA channel
keeping DMA_CxLLR[31:0] = 0]
    Enable[Enable DMA channel]
    end

    Init --> Enable
    Reconfig --> Enable

    subgraph "Channel state = Active"
    Valid{Valid user
setting?}
    Transfer[Executing the data transfer
from the register file]
    NoError{No transfer
error?}
    SetUSEF[Setting USEF = 1
Disabling DMA channel]
    SetDTEF[Setting DTEF = 1
Disabling DMA channel]
    SetTCF[Setting TCF = 1
Disabling DMA channel]
    end

    Enable --> Valid
    Valid -- Y --> Transfer
    Valid -- N --> SetUSEF
    Transfer --> NoError
    NoError -- N --> SetDTEF
    NoError -- Y --> SetTCF

    End([End])
    SetUSEF --> End
    SetDTEF --> End
    SetTCF --> End
    End --> Reconfig
  

MSv62626V1

18.4.3 HPDMA channel suspend and resume

The software can suspend on its own a channel still active, with the following sequence:

1. 1. The software writes 1 into the HPDMA_CxCR.SUSP bit.
2. 2. The software polls the suspended flag HPDMA_CxSR.SUSPF until SUSPF = 1, or waits for an interrupt previously enabled by writing 1 to HPDMA_CxCR.SUSPIE. Wait for the channel to be effectively in suspended state means wait for the completion of any ongoing HPDMA transfer over its master ports. Then the software can observe, in a steady state, any read register or bitfield that is hardware modifiable.

Note: An ongoing HPDMA transfer can be a data transfer (a source/destination burst transfer,) or a link transfer for the internal update of the linked-list register file from the next linked-list item.

1. 3. The software safely resumes the suspended channel by writing 0 to HPDMA_CxCR.SUSP.

Figure 74. HPDMA channel suspend and resume sequence

graph TD; subgraph State1 [Channel state = Active]; A[Suspend the DMA channel<br/>(write 1 to CxCR.SUSP)]; A --> B{SUSPF=1?}; B -- N --> A; B -- Y --> State2; end; subgraph State2 [Channel state = Suspended and Idle]; C[Receiving suspended interrupt]; D[Resume the DMA channel<br/>(write 0 to CxCR.SUSP)]; C --> D; D --> State3; end; subgraph State3 [Channel state = Active]; end; State2 --> State3;

Note: A suspend and resume sequence does not impact the HPDMA_CxCR.EN bit. Suspending a channel (transfer) does not suspend a started trigger detection.

18.4.4 HPDMA channel abort and restart

Alternatively, like for aborting a continuous HPDMA transfer with a circular buffering or a double buffering, the software can abort, on its own, a still active channel with the following sequence:

1. 1. The software writes 1 into the HPDMA_CxCR.SUSP bit.
2. 2. The software polls suspended flag HPDMA_CxSR.SUSPF until SUSPF = 1, or waits for an interrupt previously enabled by writing 1 to HPDMA_CxCR.SUSPIE. Wait for the channel to be effectively in suspended state means wait for the completion of any ongoing HPDMA transfer over its master port.
3. 3. The software resets the channel by writing 1 to HPDMA_CxCR.RESET. This causes the reset of the FIFO, the reset of the channel internal state, the reset of the HPDMA_CxCR.EN bit, and the reset of the HPDMA_CxCR.SUSP bit.
4. 4. The software safely reconfigures the channel. The software must reprogram hardware-modified HPDMA_CxBR1, HPDMA_CxSAR, and HPDMA_CxDAR.

1. In order to restart the aborted then reprogrammed channel, the software enables it again by writing 1 to the HPDMA_CxCR.EN bit.

Figure 75. HPDMA channel abort and restart sequence

    graph TD
      subgraph Active_State [Channel state = Active]
        A1[Suspend the DMA channel
write 1 to CxCR.SUSP] --> D1{SUSPF=1?}
        D1 -- N --> A1
      end
      D1 -- Y --> S1
      subgraph Suspended_State [Channel state = Suspended and Idle]
        S1[Receiving suspended
interrupt]
      end
      S1 --> R1[Reset the DMA channel
write 1 to CxCR.RESET]
      R1 --> I1
      subgraph Idle_State [Channel state = Idle]
        I1[Reconfigure the DMA channel] --> I2[Enable the DMA channel]
      end
      I2 --> A2[Channel state = Active]
  

18.4.5 HPDMA linked-list data structure

Alternatively to the direct programming mode, a channel can be programmed by a list of transfers, known as a list of linked-list items (LLI). Each LLI is defined by its data structure.

For a channel x, the base address in memory of the data structure of a next \( LLI_{n+1} \) is the sum of the following:

• • the link base address of the channel x (in HPDMA_CxLBAR)
• • the link address offset LA[15:2] bitfield in HPDMA_CxLLR, that is the updated result from the data structure of the previous \( LLI_n \) of the channel x

The data structure for each LLI can be specific.

A linked-list data structure is addressed following the value of UT1, UT2, UB1, USA, UDA, and ULL bits, plus UB2 and UT3 when present, in HPDMA_CxLLR.

In linked-list mode, each HPDMA linked-list register (HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR or HPDMA_CxLLR,

plus HPDMA_CxTR3 or HPDMA_CxBR2 when present) is conditionally and automatically updated from the next linked-list data structure in the memory, following the current value of HPDMA_CxLLR that was conditionally updated from the linked-list data structure of the previous LLI.

Caution: The user must program the pointer to the next linked-list data structure (HPDMA_CxLLR[15:0]) not to exceed the 64-Kbyte addressable space defined by the link base address register (HPDMA_CxLBAR). The complete linked-list data structure must be included in the 64-Kbyte addressable space.

Static linked-list data structure

For example, when the update bits (UT1, UT2, UB1, USA, UDA, and ULL, plus UB2 and UT3 when present) in HPDMA_CxLLR are all asserted, the linked-list data structure in the memory is maximal with:

• • for channels without 2D addressing capability: six contiguous 32-bit locations, including HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR, and HPDMA_CxLLR (see Figure 76) and including the first linked-list register file (LLI ₀ ), and the next LLIs (LLI ₁ , LLI ₂ ,...) in the memory
• • for channels with 2D addressing capability: eight contiguous 32-bit locations, including HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR, and HPDMA_CxLLR, plus HPDMA_CxTR3 and HPDMA_CxBR2 (see Figure 77), including the first linked-list register file (LLI ₀ ), and the next LLIs (LLI ₁ , LLI ₂ ,...) in the memory

Figure 76. Static linked-list data structure (all Uxx = 1) of a linear addressing channel x

Figure 77. Static linked-list data structure (all Uxx = 1) of a 2D addressing channel x

Dynamic linked-list data structure

Alternatively, the memory organization for the full list of LLIs can be compacted with specific data structure for each LLI.

If UT1 = 0 and UT2 = 1, the link address offset of HPDMA_CxLLR points to the updated value of HPDMA_CxTR2, instead of HPDMA_CxTR1 which is not to be modified (see Figure 78).

Example: if UT1 = UB1 = USA = 0, and if UT3 = UB2 = 0 when channel x is with 2D addressing, and if UT2 = UDA = ULL = 1, the next LLI does not contain an (updated) value for HPDMA_CxTR1, nor HPDMA_CxBR1, nor HPDMA_CxSAR, nor HPDMA_CxTR3, nor HPDMA_CxBR2 when channel x is with 2D addressing. The next LLI contains an updated value for HPDMA_CxTR2, HPDMA_CxDAR, and HPDMA_CxLLR, as shown in Figure 79.

18.4.6 Linked-list item transfer execution

An \( LLI_n \) transfer is the sequence of:

1. 1. a data transfer: the HPDMA executes the data transfer as described by the HPDMA internal register file (this data transfer can be void/null for \( LLI_0 \) ).
2. 2. a conditional link transfer: the HPDMA automatically and conditionally updates its internal register file by the data structure of the next \( LLI_{n+1} \) , as defined by the HPDMA_CxLLR value of the \( LLI_n \) .

Note: The initial data transfer, as defined by the internal register file ( \( LLI_0 \) ), can be null (HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxTR2.PFREQ = 0), provided that UB1 is set in HPDMA_CxLLR (meaning there is a non-null data transfer described by the next \( LLI_1 \) in the memory to be executed).

Depending on the intended HPDMA use, an HPDMA channel x can be executed as described by the full linked-list (run-to-completion mode, HPDMA_CxCR.LSM = 0), or can be programmed for a single execution of a LLI (link step mode, HPDMA_CxCR.LSM = 1), as described in the next sections.

18.4.7 HPDMA channel state and linked-list programming in run-to-completion mode

When HPDMA_CxCR.LSM = 0 (in full-list execution mode, execution of the full sequence of LLIs, named run-to-completion mode), an HPDMA channel x is initially programmed, started

by writing 1 to HPDMA_CxCR.EN, and after completed at channel level.
The channel transfer is:

• • configured with at least the following:
  • – the first \( LLI_0 \) , internal linked-list register file: HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR, and HPDMA_CxLLR, plus HPDMA_CxTR3 and HPDMA_CxBR2 when present
  • – the last \( LLI_N \) described by the linked-list data structure in memory, as defined by HPDMA_CxLLR reflecting the before last \( LLI_{N-1} \)
• • completed when HPDMA_CxLLR[31:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0, if BRC[10:0] is present and HPDMA_CxBR1.BNDT[15:0] = 0, at the end of the last \( LLI_{N-1} \) transfer

HPDMA_CxLLR[31:0] = 0 is the condition of a linked-list based channel completion, and means the following:

• • The 16 low significant bits HPDMA_CxLLR.LA[15:0] of the next link address are null.
• • All bits HPDMA_CxLLR.Uxx are null (UT1, UT2, UB1, USA, UDA, and ULL, plus UB2 and UT3 when present).

The channel may never be completed when HPDMA_CxLLR.LSM = 0:

• • If the last \( LLI_N \) is recursive, pointing to itself as a next LLI, in one of the following:
  • – HPDMA_CxLLR.ULL = 1 and HPDMA_CxLLR.LA[15:2] is updated with the same value.
  • – HPDMA_CxLLR.ULL = 0
• • If \( LLI_N \) points to a previous LLI

At the regular data transfer completion at a block level, HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 (if present). Alternatively, a block transfer may be early completed by a peripheral (such as an I3C in Rx mode), and then BNDT[15:0] is not null (see Section 18.4.14 for more details).

In the typical run-to-completion mode, the allocation of an HPDMA channel, including its fine programming, is done once during the HPDMA initialization. In order to have a reserved data communication link and HPDMA service during run-time, for continuously repeated transfers (from/to a peripheral respectively to/from memory or for memory-to-memory transfers). This reserved data communication link can consist of a channel, or the channel can be shared and a repeated transfer consists of a sequence of LLIs.

Figure 80 depicts the HPDMA channel execution and its registers programming in run-to-completion mode.

Note: Figure 80 is not intended to illustrate how often a TCEF can be raised, depending on the programmed value of TCEM[1:0] in HPDMA_CxTR2. It can be raised at (each) block completion, at (each) 2D block completion, at (each) LLI completion, or only at channel completion. In run-to-completion mode, whatever is the value of TCEM[1:0], at the channel completion, the hardware always set TCEF = 1 and disables the channel.

In Figure 80 , BNDT ≠ 0 is the typical condition for starting the first data transfer. This condition becomes (BNDT ≠ 0 and PFREQ = 1) if the peripheral requests a data transfer with early termination (see Section 18.3.6 ).

Figure 80. HPDMA channel execution and linked-list programming in run-to-completion mode (HPDMA_CxCR.LSM = 0)

graph TD; subgraph Idle [Channel state = Idle]; Init[Initialize DMA channel] --> Enable[Enable DMA channel]; end; Enable --> Active [Channel state = Active]; subgraph Active; Valid1{Valid user setting?}; BNDT{BNDT ≠ 0?}; Exec[Executing once the data transfer from the register file]; NoError1{No transfer error?}; LLR{LLR ≠ 0?}; LoadLLI[Loading next LLI into the register file]; NoError2{No transfer error?}; Valid2{Valid user setting?}; TCF[Setting TCF = 1 Disabling DMA channel]; USEF1[Setting USEF = 1 Disabling DMA channel]; DTEF[Setting DTEF = 1 Disabling DMA channel]; USEF2[Setting USEF = 1 Disabling DMA channel]; End[/End/]; Init --> Valid1; Valid1 -- N --> USEF1; Valid1 -- Y --> BNDT; BNDT -- N --> DTEF; BNDT -- Y --> Exec; Exec --> NoError1; NoError1 -- N --> DTEF; NoError1 -- Y --> LLR; LLR -- N --> Valid2; LLR -- Y --> LoadLLI; LoadLLI --> NoError2; NoError2 -- N --> USEF2; NoError2 -- Y --> Valid2; Valid2 -- N --> USEF1; Valid2 -- Y --> TCF; TCF --> End; USEF1 --> Reconfig[Reconfigure DMA channel]; DTEF --> Reconfig; USEF2 --> Reconfig; Reconfig --> Valid1;

MSv62631V1

Run-time inserting a \( LLI_n \) via an auxiliary channel, in run-to-completion mode

The start of the link transfer of the \( LLI_{n-1} \) (start of the \( LLI_n \) loading) can be conditioned by the occurrence of a trigger, when programming the following bitfields of HPDMA_CxTR2 in the data structure of the \( LLI_{n-1} \) :

• • TRIGM[1:0] = 10 (link transfer triggering mode)
• • TRIGPOL[1:0] = 01 or 10 (rising or falling edge)
• • TRIGSEL[6:0] (see Section 18.3.7 for the trigger selection details)

Another auxiliary channel y can be used to store the channel x \( LLI_n \) in the memory, and to generate a transfer complete event hpdma_chy_tc. By selecting this event as the input trigger of the link transfer of the \( LLI_{n-1} \) of the channel x, the software can pause the primary channel x after its \( LLI_{n-1} \) data transfer, until it is indeed written the \( LLI_n \) .

Figure 81 depicts such a dynamic elaboration of a linked-list of a primary channel x, via another auxiliary channel y.

Caution: This use case is restricted to an application with an \( LLI_{n-1} \) data transfer that does not need a trigger. The triggering mode of this \( LLI_{n-1} \) is used to load the next \( LLI_n \) .

18.4.8 HPDMA channel state and linked-list programming in link step mode

When HPDMA_CxCR.LSM = 1 (in link step execution mode, single execution of one LLI), a channel transfer is executed and completed after each single execution of a LLI, including its (conditional) data transfer and its (conditional) link transfer.

An HPDMA channel transfer can be programmed at an LLI level, started by writing 1 into HPDMA_CxCR.EN, and after completed at LLI level:

• • The current LLI _n transfer is described with the following:
  • – HPDMA_CxTR1 defines the source/destination elementary single/burst transfers.
  • – HPDMA_CxBR1 defines the number of bytes at a block level (BNDT[15:0]), and for channels with 2D addressing it defines also the number of blocks at a

2D/repeated block level (BRC[10:0]+1), and the incrementing/decrementing mode for address offsets.

• – HPDMA_CxTR2 defines the input control (request, trigger), and the output control (transfer-complete event) of the transfer.
• – HPDMA_CxSAR and HPDMA_CxDAR define the source/destination transfer start address.
• – HPDMA_CxTR3 for channels with 2D addressing defines the source/destination additional address offset between burst transfers.
• – HPDMA_CxBR2 for channels with 2D addressing defines the source/destination additional address offset between blocks at a 2D/repeated block level.
• – HPDMA_CxLLR defines the data structure, and the address offset of the next \( LLI_{n+1} \) in the memory.
• • The current \( LLI_n \) transfer is completed after the single execution of the current \( LLI_n \) :
  • – after the (conditional) data transfer completion (when HPDMA_CxBR1.BRC[10:0] = 0 if BRC[10:0] is present, and HPDMA_CxBR1.BNDT[15:0] = 0)
  • – after the (conditional) update of the HPDMA link register file from the data structure of the next \( LLI_{n+1} \) in memory

Note: If an LLI is recursive (pointing to itself as a next LLI, either HPDMA_CxLLR.ULL = 1 and HPDMA_CxLLR.LA[15:2] is updated with the same value, or HPDMA_CxLLR.ULL = 0), a channel in link step mode is completed after each repeated single execution of this LLI.

At the regular data transfer completion at a block level, HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 (if present). Alternatively, a block transfer can be early completed by a peripheral (such as an I3C in Rx mode), and then BNDT[15:0] is not null (see Section 18.4.14 for more details).

The link step mode can be used to elaborate dynamically LLIs in memory during run-time. The software can be facilitated by using a static data structure for any \( LLI_n \) (all update bits of HPDMA_CxLLR have a static value, \( LLI_n.LLR.LA = LLI_{n-1}.LLR.LA + \text{constant} \) ).

Figure 82 depicts the HPDMA channel execution mode, and its programming in link step mode.

Note: Figure 82 is not intended to illustrate how often a TCEF can be raised, depending on the programmed value of TCEM[1:0] in HPDMA_CxTR2. It can be raised at (each) block completion, at (each) 2D block completion, at (each) LLI completion, or only at the last LLI data transfer completion. In link step mode, the channel is disabled after each single execution of a LLI, and depending on the value of TCEM[1:0] a TCEF is raised or not. In Figure 82 , BNDT ≠ 0 is the typical condition for starting the first data transfer. This condition becomes BNDT ≠ 0 and PFREQ = 1 if the peripheral requests a data transfer with early termination (see Section 18.3.6 ).

Figure 82. HPDMA channel execution and linked-list programming in link step mode (HPDMA_CxCR.LSM = 1)

graph TD; subgraph Idle [Channel state = Idle]; Init[Initialize DMA channel] --> Enable[Enable DMA channel]; end; Enable --> Active [Channel state = Active]; subgraph Active; Valid1{Valid user setting?}; BNDT{BNDT ≠ 0?}; Exec[Executing once the data transfer from the register file]; NoError1{No transfer error?}; LLR{LLR ≠ 0?}; Executing[Loading next LLI into the register file]; NoError2{No transfer error?}; Valid2{Valid user setting?}; USEF1[Setting USEF = 1 Disabling DMA channel]; DTEF[Setting DTEF = 1 Disabling DMA channel]; ULEF[Setting ULEF = 1 Disabling DMA channel]; USEF2[Setting USEF = 1 Disabling DMA channel]; TCF[Setting TCF = 1 Disabling DMA channel]; End[/End/]; Reconfig[Reconfigure DMA channel]; Init --> Valid1; Valid1 -- N --> USEF1; Valid1 -- Y --> BNDT; BNDT -- N --> USEF1; BNDT -- Y --> Exec; Exec --> NoError1; NoError1 -- N --> DTEF; NoError1 -- Y --> LLR; LLR -- N --> TCF; LLR -- Y --> Executing; Executing --> NoError2; NoError2 -- N --> ULEF; NoError2 -- Y --> Valid2; Valid2 -- N --> USEF2; Valid2 -- Y --> TCF; USEF1 --> End; DTEF --> End; ULEF --> End; USEF2 --> End; TCF --> End; End --> Reconfig; Reconfig --> Init;

MSv62633V1

Run-time adding a \( LLI_{n+1} \) in link step mode

During run-time, the software can defer the elaboration of the \( LLI_{n+1} \) (and next LLIs), until/after the HPDMA executed the transfer from the \( LLI_{n-1} \) and loaded the \( LLI_n \) from the memory, as shown in the figure below.

Figure 83. Building \( LLI_{n+1} \) : HPDMA dynamic linked-lists in link step mode

sequenceDiagram
    participant DMA Channel
    participant CPU
    Note right of DMA Channel: LSM = 1 with 2-stage linked-list programming: DMA executes LLI_{n-1} and loads LLI_n while CPU builds LLI_{n+1}
    DMA Channel->>DMA Channel: LLI_{n-2} transfer
    DMA Channel->>CPU: Transfer complete interrupt
    CPU->>DMA Channel: Enable DMA channel
    Note left of DMA Channel: LLI_{n-1} transfer
    DMA Channel->>DMA Channel: Executing LLI_{n-1} data transfer
    DMA Channel->>DMA Channel: Loading LLI_n
    DMA Channel->>CPU: Transfer complete interrupt
    CPU->>DMA Channel: Build and store LLI_{n+1}
    CPU->>DMA Channel: Enable DMA channel
    DMA Channel->>DMA Channel: LLI_n transfer
    Note right of DMA Channel: MSv62634V1

Run-time replacing an \( LLI_n \) with a new \( LLI_{n'} \) in link step mode (in linked-list register file)

In this link step mode, during run-time, the software can build and insert a new \( LLI_{n'} \) , after the HPDMA executed the transfer from the \( LLI_{n-1} \) , and loaded a formerly elaborated \( LLI_n \) from the memory by overwriting directly the linked-list register file with the new \( LLI_{n'} \) , as shown in Figure 84.

Figure 84. Replace with a new LLI _n in register file in link step mode

sequenceDiagram
    participant DMA as DMA channel
    participant CPU as CPU
    Note right of DMA: LSM = 1 with 1-stage linked-list programming:
Overwriting the (pre)loaded LLIn linked-list register file with
a new LLIn directly in linked-list register file.
DMA executes LLIn-1 and load LLIn, then CPU builds and overwrites LLIn

    DMA->>DMA: Executing LLIn-1 data transfer
    DMA->>DMA: Loading LLIn
    DMA->>CPU: Transfer complete interrupt
    CPU->>CPU: Build LLIn and overwrite linked-list register file
    CPU->>CPU: Enable DMA channel
    CPU->>DMA: 
    DMA->>DMA: Executing LLIn data transfer
    DMA->>DMA: Loading LLIn+1
    DMA->>CPU: Transfer complete interrupt
    CPU->>CPU: Build LLIn+1 and overwrite linked-list register file
    CPU->>CPU: Enable DMA channel
    CPU->>DMA: 
    DMA->>DMA: LLIn+1 transfer
    DMA->>CPU: Transfer complete interrupt

MSV62635V1

Run-time replacing an \( LLI_n \) with a new \( LLI_{n'} \) in link step mode (in the memory)

The software can build and insert a new \( LLI_{n'} \) and \( LLI_{n+1'} \) in the memory, after HPDMA executed the transfer from the \( LLI_{n-1} \) , and loaded a formerly elaborated \( LLI_n \) from the memory, by overwriting partly the linked-list register file (HPDMA_CxBR1.BNDT[15:0] to be null, and HPDMA_CxLLR to point to new \( LLI_{n'} \) ) as shown in Figure 85.

Figure 85. Replace with a new \( LLI_{n'} \) and \( LLI_{n+1'} \) in memory in link step mode (option 1)

sequenceDiagram
    participant DMA Channel
    participant CPU

    Note left of DMA Channel: LLI_{n-1} transfer
    rect rgb(240, 240, 240)
    DMA Channel->>DMA Channel: Executing LLI_{n-1} data transfer
    DMA Channel->>DMA Channel: Loading LLI_n
    end
    DMA Channel-->>CPU: Transfer complete interrupt
    
    CPU->>CPU: Build LLI_{n'} and LLI_{n+1'} in memory
    CPU->>CPU: Write DMA_CxBR1.BNDT = 0
Write DMA_CxLLR to point to new LLI_{n'}
    CPU->>CPU: Enable DMA channel
    
    Note left of DMA Channel: LLI_{n'} transfer
    rect rgb(240, 240, 240)
    DMA Channel->>DMA Channel: Loading LLI_{n'}
    end
    DMA Channel-->>CPU: Transfer complete interrupt
    
    CPU->>CPU: Enable DMA channel
    
    Note left of DMA Channel: LLI_{n+1'} transfer
    rect rgb(240, 240, 240)
    DMA Channel->>DMA Channel: Executing LLI_{n+1'} data transfer
    DMA Channel->>DMA Channel: Loading LLI_{n+1'}
    end
    DMA Channel-->>CPU: Transfer complete interrupt

Run-time replacing a \( LLI_n \) with a new \( LLI_{n'} \) in link step mode

Other software implementations exist. Meanwhile the HPDMA executes the transfer from the \( LLI_{n-1} \) and loads a formerly elaborated \( LLI_n \) from the memory (or even earlier), the software can do the following:

1. 1. Disable the NVIC for not being interrupted by the interrupt handling.
2. 2. Build a new \( LLI_{n'} \) and a new \( LLI_{n+1'} \) .
3. 3. Enable again the NVIC for the channel interrupt (transfer complete) notification.

The software in the interrupt handler for \( LLI_{n-1} \) is then restricted to overwrite HPDMA_CxBR1.BNDT[15:0] to be null and HPDMA_CxLLR to point to new \( LLI_{n'} \) , as shown in the figure below.

Figure 86. Replace with a new \( LLI_{n'} \) and \( LLI_{n+1'} \) in memory in link step mode (option 2)

sequenceDiagram
    participant DMA as DMA channel
    participant CPU as CPU

    Note over DMA: LLI_{n-1} transfer
    DMA->>DMA: Executing LLI_{n-1} data transfer
    DMA->>DMA: Loading LLI_n
    DMA->>CPU: Transfer complete interrupt
    
    Note over CPU: CPU operations
    CPU->>CPU: Disable NVIC DMA irq channel
    CPU->>CPU: Build LLI_{n'} & LLI_{n+1'} in memory
    CPU->>CPU: Enable NVIC DMA irq channel
    CPU->>CPU: Write DMA_CxBR1.BNDT = 0
    CPU->>CPU: Write DMA_CxLLR to point to new LLI_{n'}
    CPU->>CPU: Enable DMA channel

    Note over DMA: LLI_{n'} transfer
    DMA->>DMA: Loading LLI_{n'}
    DMA->>CPU: Transfer complete interrupt
    CPU->>CPU: Enable DMA channel

    Note over DMA: LLI_{n+1'} transfer
    DMA->>DMA: Executing LLI_{n+1'} data transfer
    DMA->>DMA: Loading LLI_{n+1'}
    DMA->>CPU: Transfer complete interrupt
    

18.4.9 HPDMA channel state and linked-list programming

The software can reconfigure a channel when the channel is disabled (HPDMA_CxCR.EN = 0), and update the execution mode (HPDMA_CxCR.LSM) to change from/to run-to-completion mode to/from link step mode.

In any execution mode, the software can:

• • reprogram \( LLI_{n+1} \) in the memory to finally complete the channel by this \( LLI_{n+1} \) (clear the HPDMA_CxLLR of this \( LLI_{n+1} \) ), before this \( LLI_{n+1} \) is loaded/used by the HPDMA channel
• • abort and reconfigure the channel with an LSM update (see Section 18.4.4. )

In link step mode, the software can clear LSM after each a single execution of any LLI, during \( LLI_{n-1} \) .

Figure 87 shows the overall and unified HPDMA linked-list programming, whatever is the execution mode.

Note: Figure 87 is not intended to illustrate how often a TCEF can be raised, depending on the programmed value of TCEM[1:0] in HPDMA_CxTR2. It can be raised at (each) block completion, at (each) 2D block completion, at (each) LLI completion, or only at the last LLI data transfer completion. In run-to-completion mode, whatever is the value of TCEM[1:0], at the channel completion the hardware always set TCEF = 1 and disables the channel. In link step mode, the channel is disabled after each single execution of a LLI, and depending on the value of TCEM[1:0] a TCEF is raised or not.

In Figure 87 , BNDT \( \neq \) 0 is the typical condition for starting the first data transfer. This condition becomes BNDT \( \neq \) 0 and PFREQ = 1 if the peripheral requests a data transfer with early termination (see Section 18.3.6 ).

Figure 87. HPDMA channel execution and linked-list programming

graph TD; subgraph Idle [Channel state = Idle]; Init[Initialize DMA channel] --> Enable[Enable DMA channel]; end; Enable --> Active [Channel state = Active]; subgraph Active; Valid1{Valid user setting?}; BNDT{BNDT ≠ 0?}; Exec[Executing once the data transfer from the register file]; NoError1{No transfer error?}; LLR{LLR ≠ 0?}; LoadLLI[Loading next LLI into the register file]; NoError2{No transfer error?}; Valid2{Valid user setting?}; LSM{LSM = 1?}; Valid1 -- N --> Disable1[Setting USEF = 1
Disabling DMA channel]; BNDT -- N --> Disable2[Setting DTEF = 1
Disabling DMA channel]; Exec --> NoError1; NoError1 -- N --> Disable2; NoError1 -- Y --> LLR; LLR -- N --> End[/End/]; LLR -- Y --> LoadLLI; LoadLLI --> NoError2; NoError2 -- N --> Disable3[Setting ULEF = 1
Disabling DMA channel]; NoError2 -- Y --> Valid2; Valid2 -- N --> Disable4[Setting USEF = 1
Disabling DMA channel]; Valid2 -- Y --> LSM; LSM -- N --> End; LSM -- Y --> Disable5[Setting TCF = 1
Disabling DMA channel]; Disable1 --> Reconfig[Reconfigure DMA channel]; Disable2 --> Reconfig; Disable3 --> Reconfig; Disable4 --> Reconfig; Disable5 --> Reconfig; Reconfig --> Init;

MSv62638V1

18.4.10 HPDMA FIFO-based transfers

There is a single transfer operation mode: the FIFO mode. There are FIFO-based transfers. Any channel x is implemented with a dedicated FIFO whose size is defined by dma_fifo_size[x] (see Section 18.3.1 for more details).

HPDMA burst

A programmed transfer at the lowest level is an HPDMA burst.

An HPDMA burst is a burst of data received from the source, or a burst of data sent to the destination. A source (and destination) burst is programmed with a burst length by SBL_1[5:0] (respectively DBL_1[5:0] ), and with a data width defined by SDW_LOG2[1:0] (respectively DDW_LOG2[1:0] ) in HPDMA_CxTR1 .

The addressing mode after each data (named beat) of an HPDMA burst is defined by SINC and DINC in HPDMA_CxTR1 , for source and destination respectively: either a fixed addressing or an incremented addressing with contiguous data.

The start and next addresses of an HPDMA source/destination burst (defined by HPDMA_CxSAR and HPDMA_CxDAR ) must be aligned with the respective data width.

The table below lists the main characteristics of an HPDMA burst.

Table 91. Programmed HPDMA source/destination burst

1. When S/DBL_1[5:0] = 0, burst is of length 1. Then burst can be also named as single.

2. As highlighted in Section 18.3.2 , the maximum allowed AXI burst length is 16. The user must set SBL_1[5:0] lower or equal to 15 if the source allocated port is AXI (if SAP = 0). The user must set DBL_1[5:0] lower or equal to 15 if the destination allocated port is AXI (if DAP = 0).

The next burst address in the above table is the next source/destination default address pointed by HPDMA_CxSAR or HPDMA_CxDAR , once the programmed source/destination burst is completed. This default value refers to the fixed/contiguously incremented address.

HPDMA burst with 2D addressing

When the channel has additional 2D addressing feature, this default value refers to the value without taking into account the two programmed incremented or decremented offsets. These two additional offsets (with a null default value) are applied:

• • after each completed source/destination burst, as defined respectively by HPDMA_CxTR2.SAO[12:0]/DAO[12:0] and HPDMA_CxBR1.SDEC/DDEC
• • after each completed block, as defined respectively by HPDMA_CxBR2.BRSAO[15:0]/BRDAO[15:0] and HPDMA_CxBR1.BRSDEC/BRDDEC)

Then, a 2D/repeated block can be addressed with a first programmed address jump after each completed burst, and with a second programmed address jump after each block, as depicted by Figure 88 with a 2D destination buffer.

Figure 88. Programmed 2D addressing

HPDMA FIFO-based burst

In FIFO-mode, a transfer generally consists of two pipelined and separated burst transfers:

• • one burst from the source to the FIFO over the allocated source master port, as defined by HPDMA_CxTR1.SAP
• • one burst from the FIFO to the destination over the allocated destination master port, as defined by HPDMA_CxTR1.DAP

HPDMA source burst

The requested source burst transfer to the FIFO can be scheduled as early as possible over the allocated port, depending on the current FIFO level versus the programmed burst size (when the FIFO is ready to get one new burst from the source):

where:

• • FIFO level is the current filling level of the FIFO, in bytes.
• • \( 2^{\text{dma\_fifo\_size}[x]} \) is half the FIFO size of channel x, in bytes (see Section 18.3.1 for the implementation details and dma_fifo_size[x] value).
• • \( (\text{SBL\_1}[5:0]+1) * 2^{\text{SDW\_LOG2}[1:0]} \) is the size of the programmed source burst transfer, in bytes.

Based on the channel priority (HPDMA_CxCR.PRIO[1:0]), this ready FIFO-based source transfer is internally arbitrated versus the other requested and active channels.

HPDMA destination burst

The requested destination burst transfer from the FIFO can be scheduled as early as possible over the allocated port, depending on the current FIFO level versus the programmed burst size (when the FIFO is ready to push one new burst to the destination):

where:

• • FIFO level is the current filling level of the FIFO, in bytes.
• • \( (\text{DBL\_1}[5:0]+1) * 2^{\text{DDW\_LOG2}[1:0]} \) is the size of the programmed destination burst transfer, in bytes.

Based on the channel priority, this ready FIFO-based destination transfer is internally arbitrated versus the other requested and active channels.

HPDMA burst versus source block size, 1- or 4-Kbyte address boundary and FIFO size

The programmed source/destination HPDMA burst is implemented with an AHB/AXI burst as is, unless one of the following conditions is met:

• • When half of the FIFO size of the channel x is lower than the programmed source/destination burst size, the programmed source/destination HPDMA burst is implemented with a series of singles or bursts of a lower size. Each transfer is of a size that is lower than or equal than half of the FIFO size, without any user constraint.
• • If the source block size (HPDMA_CxBR1.BNDT[15:0]) is not a multiple of the source burst size but is a multiple of the data width of the source burst (HPDMA_CxTR1.SDW_LOG2[1:0]), the HPDMA modifies and shortens bursts into

singles or bursts of lower length, in order to transfer exactly the source block size, without any user constraint.

• • if the source/destination burst transfer have crossed the 1- or 4-Kbyte address boundary on, respectively, an AHB or AXI transfer, the HPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB/AXI protocol, without any user constraint.
• • If the source/destination burst length exceeds 16 on a AHB transfer, or if the source/destination burst on an AXI transfer is both with fixed addressing and with a burst length which exceeds 16, the HPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB/AXI protocol, without any user constraint.

In any case, the HPDMA keeps ensuring source/destination data (and address) integrity without any user constraint. The current FIFO level (software readable in HPDMA_CxSR) is compared to and updated with the effective transfer size, and the HPDMA re-arbitrates between each AHB/AXI single or burst transfer, possibly modified.

Based on the channel priority, each single or burst of a lower burst size versus the programmed burst, is internally arbitrated versus the other requested and active channels.

Note: In linked-list mode, the HPDMA read transfers related to the update of the linked-list parameters from the memory to the internal HPDMA registers, are scheduled over the link allocated port, as programmed by HPDMA_CxCR.LAP.

HPDMA data handling: byte-based reordering, packing/unpacking, padding/truncation, sign extension, and left/right alignment

The data handling is controlled by HPDMA_CxTR1. The source/destination data width of the programmed burst is byte, half-word, word, or double-word, as per SDW_LOG2[1:0] and DDW_LOG2[1:0] (see Table 92 ).

The user can configure the data handling between transferred data from the source and transfer to the destination. More specifically, programmed data handling is orderly performed with:

1. 1. Byte-based source reordering
   • – If SBX = 1 and if the source data width is a word or a double-word (for AXI source bus, SAP = 0), the two bytes of the unaligned half-word at the middle of each source data word are exchanged.
2. 2. Data-width conversion by packing, unpacking, padding, or truncation, if destination data width is different than the source data width, depending on PAM[1:0]:
   • – If destination data width > source data width, the post SBX source data is either right-aligned and padded with 0s, or sign extended up to the destination data width, or is FIFO queued and packed up to the destination data width.
   • – If destination data width < source data width, the post SBX data is either right-aligned and left-truncated down to the destination data width, or is FIFO queued and unpacked and streamed down to the destination data width.

1. 3. Byte-based destination re-ordering:
   • – If DBX = 1 and if the destination data width is not a byte, the two bytes are exchanged within the aligned post PAM[1:0] half-words.
   • – If DHX = 1 and if the destination data width is neither a byte nor a half-word, the two aligned half-words are exchanged within the aligned post PAM[1:0] words.
   • – If DWX = 1 and if the destination data width is a double-word and if the selected destination port (via DAP) is 64-bit capable, the two aligned words are exchanged within aligned (post PAM[1:0]) double-words.

Note: Left-alignment with 0s-padding can be achieved by programming both a right-alignment with a 0s-padding, and a destination byte-based re-ordering.

The table below lists the possible data handling from the source to the destination.

Table 92. Programmed data handling

Table 92. Programmed data handling (continued)

Table 92. Programmed data handling (continued)

Table 92. Programmed data handling (continued)

Table 92. Programmed data handling (continued)

Table 92. Programmed data handling (continued)

Table 92. Programmed data handling (continued)

Table 92. Programmed data handling (continued)

Table 92. Programmed data handling (continued)

Table 92. Programmed data handling (continued)

Table 92. Programmed data handling (continued)

1. 1. Data stream is timely ordered starting from the byte with the lowest index (B ₀ ).
2. 2. RA= right aligned, LA = left aligned, RT = right truncated, LT = left truncated, OP = zero bit padding up to the destination data width, SE = sign bit extended up to the destination data width.
3. 3. RA= right aligned. LA = left aligned. RT = right truncated. LT = left truncated.
4. 4. OP= zero-bit padding up to the destination data width. SE = sign bit extended up to the destination data width.
5. 5. if DDW_LOG2[1:0] = 11 and if the selected destination port (via DAP) is 64-bit capable. If DDW_LOG2[1:0] = 11 and the selected destination port is not 64-bit capable, a user setting error (USEF) is reported.
6. 6. if SDW_LOG2[1:0] = 11 and if the selected source port (via SAP) is 64-bit capable. If SDW_LOG2[1:0] = 11 and the selected source port is not 64-bit capable, a user setting error (USEF) is reported.

18.4.11 HPDMA transfer request and arbitration

HPDMA transfer request

As defined by HPDMA_CxTR2, a programmed HPDMA data transfer is requested with one of the following:

• • a software request if the control bit SWREQ = 1: This is used typically by the CPU for a data transfer from a memory-mapped address to another memory mapped address (memory-to-memory, GPIO to/from memory)
• • an input hardware request coming from a peripheral if SWREQ = 0: The selection of the HPDMA hardware peripheral request is driven by REQSEL[7:0] (see Section 18.3.5 ). The selected hardware request can be one of the following:
  • – an hardware request from a peripheral configured in HPDMA mode (for a transfer from/to the peripheral data register respectively to/from the memory)
  • – an hardware request from a peripheral for its control register update from the memory
  • – an hardware request from a peripheral for a read of its status registers transferred to the memory

Caution: The user must not assign the same input hardware peripheral HPDMA request via HPDMA_CxTR.REQSEL[7:0] to two different channels, if at a given time this request is asserted by the peripheral, and each channel is ready to execute this requested data transfer. There is no user setting error reporting.

HPDMA transfer request for arbitration

A ready FIFO-based HPDMA source single/burst transfer (from the source address to the FIFO) to be scheduled over the allocated master port (HPDMA_CxTR1.SAP) is arbitrated based on the channel priority (HPDMA_CxCR.PRIO[1:0]) versus the other simultaneous requested HPDMA transfers to the same master port.

A ready FIFO-based HPDMA destination single/burst transfer (from the FIFO to the destination address) to be scheduled over the allocated master port (HPDMA_CxTR1.DAP) is arbitrated based on the channel priority (HPDMA_CxCR.PRIO[1:0]) versus the other simultaneous requested HPDMA transfers to the same master port.

An arbitrated HPDMA requested link transfer consists of one 32-bit read from the linked-list data structure in the memory to one of the linked-list registers (HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR, HPDMA_CxTR3, HPDMA_CxBR2 or HPDMA_CxLLR). Each 32-bit read from the memory is arbitrated with the same channel priority as for data transfers, in order to be scheduled over the allocated master port (HPDMA_CxCR.LAP).

Whatever the requested data transfer is programmed with a software request for a memory-to-memory transfer (HPDMA_CxTR2.SWREQ = 1), or with a hardware request (HPDMA_CxTR2.SWREQ = 0) for a memory-to-peripheral transfer or a peripheral-to-memory transfer and whatever is the hardware request type, re-arbitration occurs after each granted single/burst transfer.

When an hardware request is programmed from a destination peripheral (HPDMA_CxTR2.SWREQ = 0 and HPDMA_CxTR2.DREQ = 1), the first memory read of a (possibly 2D/repeated) block (the first ready FIFO-based source burst request), is gated by the occurrence of the corresponding and selected hardware request. This first read request

to memory is not taken into account earlier by the arbiter (not as soon as the block transfer is enabled and executable).

HPDMA arbitration

The HPDMA arbitration is directed from the 4-grade assigned channel priority (HPDMA_CxCR.PRIO[1:0]). The arbitration policy, as illustrated in Figure 89 , is defined by:

• • one high-priority traffic class (queue 3), dedicated to the assigned channels with priority 3, for time-sensitive channels

This traffic class is granted via a fixed-priority arbitration against any other low-priority traffic class. Within this class, requested single/burst transfers are round-robin arbitrated.

• • three low-priority traffic classes (queues 0, 1 or 2) for non time-sensitive channels with priority 0, 1 or 2

Each requested single/burst transfer within this class is round-robin arbitrated, with a weight that is monotonically driven from the programmed priority:

• – Requests with priority 0 are allocated to the queue 0.
• – Requests with priority 1 are allocated and replicated to the queue 0 and queue 1.
• – Requests with priority 2 are allocated and replicated to the queue 0, queue 1, and queue 2.
• – Any queue 0, 1 or 2 equally grants any of its active input requests in a round-robin manner, provided there are simultaneous requests.
• – Additionally, there is a second stage for the low-traffic with a round-robin arbiter that fairly alternates between simultaneous selected requests from queue 0, queue 1 and queue 2.

Figure 89. HPDMA arbitration policy

graph LR
    P0[Request PRIO=0] --> Q0[Queue 0 RRA]
    P1[Request PRIO=1] --> Q0
    P1 --> Q1[Queue 1 RRA]
    P2[Request PRIO=2] --> Q0
    P2 --> Q1
    P2 --> Q2[Queue 2 RRA]
    P3[Request PRIO=3] --> Q3[Queue 3 RRA]
    
    Q0 --> RRA2[RRA Stage 2]
    Q1 --> RRA2
    Q2 --> RRA2
    
    RRA2 -- Low --> FPA[FPA]
    Q3 -- High --> FPA
    
    FPA --> GR[Granted request]

HPDMA arbitration and bandwidth

With this arbitration policy, the following is guaranteed:

• • equal maximum bandwidth between requests with same priority
• • reserved bandwidth (noted as \( B_{Q3} \) ) to the time-sensitive requests (with priority 3)
• • residual weighted bandwidth between different low-priority requests (priority 0 versus priority 1 versus priority 2).

The two following examples highlight that the weighted round-robin arbitration is driven by the programmed priorities:

• Example 1: basic application with two non time-sensitive HPDMA requests: req0 and req1. There are the following programming possibilities:
  • – If they are assigned with same priority, the allocated bandwidth by the arbiter to req0 ( \( B_{\text{req0}} \) ) is equal to the allocated bandwidth to req1 ( \( B_{\text{req1}} \) ).
    
    \[ B_{\text{req0}} = B_{\text{req1}} = 1/2 * (1 - B_{\text{Q3}}) \]
  • – If req0 is assigned to priority 0 and req1 to priority 1, the allocated bandwidth to req0 ( \( B_{\text{P0}} \) ) is 3 times less than the allocated bandwidth to req1 ( \( B_{\text{P1}} \) ).
    
    \[ B_{\text{req0}} = B_{\text{P0}} = 1/2 * 1/2 * (1 - B_{\text{Q3}}) = 1/4 * (1 - B_{\text{Q3}}) \]
    \[ B_{\text{req1}} = B_{\text{P1}} = (1/2 + 1) * 1/2 * (1 - B_{\text{Q3}}) = 3/4 * (1 - B_{\text{Q3}}) \]
  • – If req0 is assigned to priority 0 and req1 to priority 2, the allocated bandwidth to req0 ( \( B_{\text{P0}} \) ) is 5 times less than the allocated bandwidth to req1 ( \( B_{\text{P2}} \) ).
    
    \[ B_{\text{req0}} = B_{\text{P0}} = 1/2 * 1/3 * (1 - B_{\text{Q3}}) = 1/6 * (1 - B_{\text{Q3}}) \]
    \[ B_{\text{req1}} = B_{\text{P2}} = (1/2 + 1 + 1) * 1/3 * (1 - B_{\text{Q3}}) = 5/6 * (1 - B_{\text{Q3}}) \]

The above computed bandwidth calculation is based on a theoretical input request, always active for any HPDMA clock cycle. This computed bandwidth from the arbiter must be weighted by the frequency of the request given by the application, that cannot be always active and may be quite much variable from one HPDMA client (example I2C at 400 kHz) to another one (PWM at 1 kHz) than the above x3 and x5 ratios.

• Example 2: application where the user distributes a same non-null N number of HPDMA requests to every non time-sensitive priority 0, 1 and 2. The bandwidth calculation is then the following:
  • – The allocated bandwidth to the set of requests of priority 0 ( \( B_{\text{P0}} \) ) is
    
    \[ B_{\text{P0}} = 1/3 * 1/3 * (1 - B_{\text{Q3}}) = 1/9 * (1 - B_{\text{Q3}}) \]
  • – The allocated bandwidth to the set of requests of priority 1 ( \( B_{\text{P1}} \) ) is
    
    \[ B_{\text{P1}} = (1/3 + 1/2) * 1/3 * (1 - B_{\text{Q3}}) = 5/18 * (1 - B_{\text{Q3}}) \]
  • – The allocated bandwidth to the set of requests of priority 2 ( \( B_{\text{P2}} \) ) is
    
    \[ B_{\text{P2}} = (1/3 + 1/2 + 1) * 1/3 * (1 - B_{\text{Q3}}) = 11/18 * (1 - B_{\text{Q3}}) \]
  • – The allocated bandwidth to any request n ( \( B_n \) ) among the N requests of that priority Pi (i = 0 to 2) is \( B_n = 1/N * B_{\text{Pi}} \)
  • – The allocated bandwidth to any request n of priority i ( \( B_{n, \text{Pi}} \) ) is
    
    \[ B_{n, \text{P0}} = 1/N * 1/9 * (1 - B_{\text{Q3}}) \]
    \[ B_{n, \text{P1}} = 1/N * 5/18 * (1 - B_{\text{Q3}}) \]
    \[ B_{n, \text{P2}} = 1/N * 11/18 * (1 - B_{\text{Q3}}) \]

In this example, when the master port bus bandwidth is not totally consumed by the time-sensitive queue 3, the residual bandwidth is such that 2.5 times less bandwidth is allocated to any request of priority 0 versus priority 1, and 5.5 times less bandwidth is allocated to any request of priority 0 versus priority 2.

More generally, assume that the following requests are present:

• • I requests ( \( I \geq 0 \) ) assigned to priority 0
  If \( I > 0 \) , these requests are noted from \( i = 0 \) to \( I-1 \) .
• • J requests ( \( J \geq 0 \) ) assigned to priority 1
  If \( J > 0 \) , these requests are noted from \( j = 0 \) to \( J-1 \) .
• • K requests ( \( K > 0 \) ) assigned to priority 2
  These requests are noted from \( k = 0 \) to \( K-1 \)
• • L requests ( \( L \geq 0 \) ) assigned to priority 3
  If \( L > 0 \) , these requests are noted from \( l = 0 \) to \( L-1 \) .

As \( B_{Q3} \) is the reserved bandwidth to time-sensitive requests, the bandwidth for each request L with priority 3 is:

• • \( B_l = B_{Q3} / L \) for \( L > 0 \) (else: \( B_l = 0 \) )

The bandwidth for each non-time sensitive queue is:

• • \( B_{Q0} = 1/3 * (1 - B_{Q3}) \)
• • \( B_{Q1} = 1/3 * (1 - B_{Q3}) \)
• • \( B_{Q2} = 1/3 * (1 - B_{Q3}) \)

The bandwidth for the set of requests with priority 0 is:

• • \( B_{P0} = I / (I + J + K) * B_{Q0} \)

The bandwidth for each request i with priority 0 is:

• • \( B_i = B_{P0} / I \) for \( L > 0 \) (else \( B_{P0} = 0 \) )

The bandwidth for the set of requests with priority 1 and routed to queue 0 is:

• • \( B_{P1,Q0} = J / (I + J + K) * B_{Q0} \)

The bandwidth for the set of requests with priority 1 and routed to queue 1 is:

• • \( B_{P1,Q1} = J / (J + K) * B_{Q1} \)

The total bandwidth for the set of requests with priority 1 is:

• • \( B_{P1} = B_{P1,Q0} + B_{P1,Q1} \)

The bandwidth for each request j with priority 1 is:

• • \( B_j = B_{P1} / J \) for \( J > 0 \) (else \( B_j = 0 \) )

The bandwidth for the set of requests with priority 2 and routed to queue 0 is:

• • \( B_{P2,Q0} = K / (I + J + K) * B_{Q0} \)

The bandwidth for the set of requests with priority 2 and routed to queue 1 is:

• • \( B_{P2,Q1} = K / (J + K) * B_{Q1} \)

The bandwidth for the set of requests with priority 2 and routed to queue 2 is:

• • \( B_{P2,Q2} = B_{Q2} \)

The total bandwidth for the set of requests with priority 2 is:

• • \( B_{P2} = B_{P2,Q0} + B_{P2,Q1} + B_{P2,Q2} \)

The bandwidth for each request k with priority 2 is:

• • \( B_k = B_{P2} / K \) ( \( K > 0 \) in the general case)

Thus finally the maximum allocated residual bandwidths for any \( i, j, k \) non-time sensitive request are:

• • in the general case (when there is at least one request \( k \) with a priority 2 ( \( K > 0 \) )):
  • – \( B_i = 1/I * 1/3 * I/(I + J + K) * (1 - B_{Q3}) \)
  • – \( B_j = 1/J * 1/3 * [J/(I + J + K) + J/(J + K)] * (1 - B_{Q3}) \)
  • – \( B_k = 1/K * 1/3 * [K/(I + J + K) + K/(J + K) + 1] * (1 - B_{Q3}) \)
• • in the specific case (when there is no request \( k \) with a priority 2 ( \( K = 0 \) )):
  • – \( B_i = 1/I * 1/2 * I/(I + J) * (1 - B_{Q3}) \)
  • – \( B_j = 1/J * 1/2 * [J/(I + J) + 1] * (1 - B_{Q3}) \)

Consequently, the HPDMA arbiter can be used as a programmable weighted bandwidth limiter, for each queue and more generally for each request/channel. The different weights are monotonically resulting from the programmed channel priorities.

18.4.12 HPDMA triggered transfer

A programmed HPDMA transfer can be triggered by a rising/falling edge of a selected input trigger event, as defined by HPDMA_CxTR2.TRIGPOL[1:0] and HPDMA_CxTR2.TRIGSEL[6:0] (see Section 18.3.7 for the trigger selection).

The triggered transfer, as defined by the trigger mode in HPDMA_CxTR2.TRIGM[1:0], can be at LLI data transfer level, to condition the first burst read of a block, the first burst read of a 2D/repeated block (for channel \( x = 12 \) to \( 15 \) ), or each programmed burst read/write. The trigger mode can also be programmed to condition the LLI link transfer (see TRIGM[1:0] in HPDMA channel \( x \) transfer register 2 (HPDMA_CxTR2) for more details).

Trigger hit memorization and trigger overrun flag generation

The HPDMA monitoring of a trigger for a channel \( x \) is started when the channel is enabled/loading with a new active trigger configuration: rising or falling edge on a selected trigger (respectively TRIGPOL[1:0] = 01 or TRIGPOL[1:0] = 10).

The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer. If a new trigger is detected, this hit is internally memorized to grant the next transfer, as long as the defined rising/falling edge and TRIGSEL[6:0] are not modified, and the channel is enabled.

Transferring a next \( LLI_{n+1} \) , that updates HPDMA_CxTR2 with a new value for any of TRIGSEL[6:0] or TRIGPOL[1:0], resets the monitoring, trashing the possible memorized hit of the formerly defined \( LLI_n \) trigger.

Caution: After a first new trigger, \( hit_{n+1} \) is memorized. If another trigger \( hit_{n+2} \) is detected, and if the \( hit_n \) triggered transfer is still not completed, \( hit_{n+2} \) is lost and not memorized. A trigger overrun flag is reported (HPDMA_CxSR.TOF = 1) and an interrupt is generated if enabled (if HPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun.

The figure below illustrates the trigger hit, memorization, and overrun in the configuration example with a block-level trigger mode and a rising edge trigger polarity.

Figure 90. Trigger hit, memorization and overrun waveform

Note: The user can assign the same input trigger event to different channels. This can be used to trigger different channels on a broadcast trigger event.

18.4.13 HPDMA circular buffering with linked-list programming

HPDMA circular buffering for memory-to-peripheral and peripheral-to-memory transfers, with a linear addressing channel

For a circular buffering, with a continuous memory-to-peripheral (or peripheral-to-memory) transfer, the software must set up a channel with half-transfer and complete-transfer event/interrupt generation (HPDMA_CxCR.HTIE = 1 and HPDMA_CxCR.TCIE = 1), in order to enable a concurrent buffer software processing.

LLI ₀ is configured for the first block transfer with the linear addressing channel. A continuously-executed LLI ₁ is needed to restore the memory source (or destination) start address for the memory-to-peripheral transfer (respectively the peripheral-to-memory). The HPDMA automatically reloads the initially programmed HPDMA_CxBR1.BNDT[15:0] when a block transfer is completed, and there is no need to restore HPDMA_CxBR1.

The figure below illustrates this programming with a linear addressing HPDMA channel and a source circular buffer.

Figure 91. HPDMA circular buffer programming: update of the memory start address with a linear addressing channel

Note:

With a 2D addressing channel, a single LLI can be used with \( HPDMA\_CxBR1.BRC[10:0] = 1 \) . The user can program a negative memory block address offset with \( HDMA\_CxBR2 \) and \( HDMA\_CxBR1 \) , in order to jump back to the memory source or destination start address.

If the circular buffering must be executed after some other transfers over the shared HPDMA channel x, the before-last \( LLI_{N-1} \) in the memory is needed to configure the first block transfer. The last \( LLI_N \) restores the memory source (or destination) start address in memory-to-peripheral transfer (respectively in peripheral-to-memory).

The figure below illustrates this programming with a linear addressing shared HPDMA channel, and a source circular buffer.

Figure 92. Shared HPDMA channel with circular buffering: update of the memory start address with a linear addressing channel

18.4.14 HPDMA transfer in peripheral flow-control mode

A peripheral with the peripheral flow-control mode feature can decide to early terminate an HPDMA block transfer, provided that the allocated channel is implemented with this feature (see Section 18.3.6 ).

If the related HPDMA channel x is also programmed in peripheral flow-control mode (HPDMA_CxTR2.PFREQ = 1):

• • The HPDMA block transfer starts as follows:
  • – If HPDMA_CxBR1.BNDT[15:0] \( \neq \) 0, the programmed value is internally taken into account by the HPDMA hardware.
  • – If HPDMA_CxBR1.BNDT[15:0] = 0, the HPDMA hardware internally considers a 64-Kbyte value for the maximum source block size to be transferred.
• • The HPDMA block transfer is completed as soon as the first occurrence of any of the following condition occurs:
  • – when HPDMA_CxBR1.BNDT[15:0] = 0
  • – when the peripheral early terminates the block. The complete transfer event is generated if programmed, depending on HPDMA_CxTR2. Then the software can read the current number of transferred bytes from the source (HPDMA_CxBR1.BNDT[15:0]), and/or read the current source or destination address of the buffer in memory (HPDMA_CxSAR[31:0] or HPDMA_CxDAR[31:0]).

In peripheral flow-control mode:

• • a destination peripheral with a hardware requested transfer is not supported; memory-to-peripheral transfer is not supported.
• • Data packing from a source peripheral is not supported.
• • 2D/repeated block is not supported.
• • HPDMA_CxBR1.BNDT[15:0] must be programmed as a multiple of the source (peripheral) burst size.

18.4.15 HPDMA secure/nonsecure channel

The HPDMA controller is compliant with the TrustZone hardware architecture at channel level, partitioning all its resources so that they exist in one of the secure and nonsecure worlds at any given time.

Any channel x is a secure or nonsecure hardware resource, as configured by HPDMA_SECCFGR.SECx.

When a channel x is configured in secure state by a secure and privileged agent, the following access control rules are applied:

• • A nonsecure read access to a bitfield of this channel is forced to return 0, except for HPDMA_SECCFGR, HPDMA_PRIVCFGR, HPDMA_RCFGLOCKR, and HPDMA_CxSEMCR that are readable by a nonsecure agent.
• • A nonsecure write access to a bitfield of this channel has no impact.

When a channel x is configured in secure state, a secure agent can configure separately as secure or nonsecure the HPDMA data transfer from the source (HPDMA_CxTR1.SSEC), and to the destination (HPDMA_CxTR1.DSEC).

When a channel x is configured in secure state and in linked-list mode, the loading of the next linked-list data structure from the HPDMA memory into its register file, is automatically performed with secure transfers via the HPDMA_CxCR.LAP allocated master port.

The HPDMA generates a secure bus that reflects HPDMA_SECCFGR, to keep the other peripherals informed of the secure/nonsecure state of each HPDMA channel x.

The HPDMA also generates a security illegal access pulse signal on an illegal nonsecure access to a secure HPDMA register. This signal is routed to the TrustZone interrupt controller.

When the secure software must switch a channel from a secure state to a nonsecure state, the secure software must abort the channel or wait until the secure channel is completed before switching. This is needed to dynamically re-allocate a channel to a next nonsecure transfer as a nonsecure software is not allowed to do so, and must have HPDMA_CxCR.EN = 0 before the nonsecure software can reprogram HPDMA_CxCR for a next transfer. The secure software can reset not only the channel x (HPDMA_CxCR.RESET = 1), but also the full channel x register file to its reset value.

18.4.16 HPDMA privileged/unprivileged channel

Any channel x is a privileged or unprivileged hardware resource, as configured by a privileged agent via HPDMA_PRIVCFGR.PRIVx.

When a channel x is configured in a privileged state by a privileged agent, the following access control rules are applied:

• • An unprivileged read access to a bitfield of this channel is forced to return 0, except for HPDMA_PRIVCFGR, HPDMA_SECCFGR, HPDMA_CxCIDCFGR and HPDMA_CxSEMCR that are readable by an unprivileged agent.
• • An unprivileged write access to a bitfield of this channel has no impact.

When a channel is configured in a privileged (or unprivileged) state, the source and destination data transfers are privileged (respectively unprivileged) transfers over the AHB/AXI master port.

When a channel is configured in a privileged (or unprivileged) state and in linked-list mode, the loading of the next linked-list data structure from the HPDMA memory into its register file, is automatically performed with privileged (respectively unprivileged) transfers, via the HPDMA_CxCR.LAP allocated master port.

The HPDMA generates a privileged bus that reflects HPDMA_PRIVCFGR, to keep the other peripherals informed of the privileged/unprivileged state of each HPDMA channel x.

Additionally, the HPDMA generates a privileged illegal access pulse signal on an illegal unprivileged access to a privileged HPDMA register. This signal can be used or not, depending on the product (see the system security section for more details).

When the privileged software must switch a channel from a privileged state to an unprivileged state, the privileged software must abort the channel, or wait until the privileged channel is completed before switching. This is needed to dynamically re-allocate a channel to a next unprivileged transfer, as an unprivileged software is not allowed to do so, and must have HPDMA_CxCR.EN = 0 before the unprivileged software can reprogram the HPDMA_CxCR for a next transfer. The privileged software can reset not only the channel x (HPDMA_CxCR.RESET = 1), but also the full channel x register file to its reset value.

HPDMA compartmented channel

The HPDMA controller performs bus transfers over its master port, under the control of a resource isolation domain identification named compartment identification (CID), at a channel level. For more details about resource isolation and CID, refer to the system security section.

18.4.17 HPDMA error management

The HPDMA can manage and report to the user a transfer error, as follows, depending on the root cause.

Data transfer error

On a bus access (as an AHB/AXI single or a burst) to the source or the destination

• • The source or destination target reports an AHB/AXI error.
• • The programmed channel transfer is stopped (HPDMA_CxCR.EN cleared by the HPDMA hardware). The channel status register reports an idle state (HPDMA_CxSR.IDLEF = 1) and the data error (HPDMA_CxSR.DTEF = 1).

• • After an HPDMA data transfer error, the user must perform a debug session, taking care of the product-defined memory mapping of the source and destination, including the protection attributes.
• • After an HPDMA data transfer error, the user must issue a channel reset (set HPDMA_CxCR.RESET) to reset the hardware HPDMA channel data path and the FIFO content, before the user enables again the same channel for a next transfer.

Link transfer error

On a tentative update of a HPDMA channel register from the programmed LLI in the memory:

• • The linked-list memory reports an AHB/AXI error.
• • The programmed channel transfer is stopped (HPDMA_CxCR.EN cleared by the HPDMA hardware), the channel status register reports an idle state (HPDMA_CxSR.IDLEF = 1), and the link error (HPDMA_CxSR.ULEF = 1).
• • After an HPDMA link error, the user must perform a debug session, taking care of the product-defined memory mapping of the linked-list data structure (HPDMA_CxLBAR and HPDMA_CxLLR), including the protection attributes.
• • After an HPDMA link error, the user must explicitly write the linked-list register file (HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR, and HPDMA_CxLLR, plus HPDMA_CxTR3 and HPDMA_CxBR2 when present), before the user enables again the same channel for a next transfer.

User setting error

On a tentative execution of an HPDMA transfer with an unauthorized user setting:

• • The programmed channel transfer is disabled (HPDMA_CxCR.EN forced and cleared by the HPDMA hardware), preventing the next unauthorized programmed data transfer from being executed. The channel status register reports an idle state (HPDMA_CxSR.IDLEF = 1), and a user setting error (HPDMA_CxSR.USEF = 1).
• • After an HPDMA user setting error, the user must perform a debug session, taking care of the HPDMA channel programming. A user setting error can be caused by one of the following:
  • – a programmed null source block size without a programmed update of this value from the next LLI _i (HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxLLR.UB1 = 0)
  • – a programmed non-null source block size being not a multiple of the programmed data width of a source burst transfer (HPDMA_CxBR1.BNDT versus HPDMA_CxTR1.SDW_LOG2)
  • – when in packing/unpacking mode (if PAM[1] = 1), a programmed non-null source block size being not a multiple of the programmed data width of a destination burst transfer (HPDMA_CxBR1.BNDT versus HPDMA_CxTR1.DDW_LOG2)
  • – a programmed unaligned source start address being not a multiple of the programmed data width of a source burst transfer (HPDMA_CxSAR versus HPDMA_CxTR1.SDW_LOG2)
  • – for a channel with 2D addressing, a programmed unaligned source address offset being not a multiple of the programmed data width of a source burst transfer (HPDMA_CxTR3.SAO versus HPDMA_CxTR1.SDW_LOG2)

• – for a channel with 2D addressing, a programmed unaligned block repeated source address offset being not a multiple of the programmed data width of a source burst transfer (HPDMA_CxBR2.BRSAO versus HPDMA_CxTR1.SDW_LOG2)
• – a programmed unaligned destination start address, being not a multiple of the programmed data width of a destination burst transfer (HPDMA_CxDAR versus HPDMA_CxTR1.DDW_LOG2)
• – for a channel with 2D addressing, a programmed unaligned destination address offset being not a multiple of the programmed data width of a destination burst transfer (HPDMA_CxTR3.DAO versus HPDMA_CxTR1.DDW_LOG2)
• – for a channel with 2D addressing, a programmed unaligned block repeated destination address offset being not a multiple of the programmed data width of a destination burst transfer (HPDMA_CxBR2.BRDAO versus HPDMA_CxTR1.DDW_LOG2)
• – a programmed source burst data width being superior than the data width of the allocated AXI/AHB source port (HPDMA_CxTR1.SDW_LOG2 and HPDMA_CxTR1.SAP vs the implemented AXI/AHB port data width).
• – a programmed destination burst data width being superior than the data width of the allocated AXI/AHB destination port (HPDMA_CxTR1.DDW_LOG2 and HPDMA_CxTR1.DAP vs the implemented AXI/AHB port data width).
• – a programmed linked-list item \( LLI_{n+1} \) with a null data transfer (HPDMA_CxLLR.UB1 = 1 and HPDMA_CxBR1.BNDT[15:0] = 0)

18.5 HPDMA in debug mode

When the device enters debug mode (core halted), any channel x can be individually either continued (default) or suspended, depending on the programmable control bit in the DBGMCU module.

Note: In debug mode, HPDMA_CxSR.SUSPF is not altered by a suspension from the programmable control bit in the DBGMCU module. In this case, HPDMA_CxSR.IDLEF can be checked to know the completion status of the channel suspension.

18.6 HPDMA in low-power modes

Table 93. Effect of low-power modes on HPDMA

1. Refer to Section 18.3.3 to know which Stop mode is supported.

18.7 HPDMA interrupts

There is one HPDMA interrupt line for each channel, and separately for each CPU (if several ones in the devices).

Table 94. HPDMA interrupt requests

An HPDMA channel x event can be:

• • a transfer complete
• • a half-transfer complete
• • a transfer error, due to either:
  • – a data transfer error
  • – an update link error
  • – a user setting error completed suspension
• • a trigger overrun

Note: When a channel x transfer complete event occurs, the output signal hpdma_chx_tc is generated as a high pulse of one clock cycle.

An interrupt is generated following any xx event, provided that both:

• • the corresponding interrupt event xx is enabled (HPDMA_CxCR.xxIE = 1)
• • the corresponding event flag is cleared (HPDMA_CxSR.xxF = 0). This means that, after a previous same xx event occurrence, a software agent must have written 1 into the corresponding xx flag clear control bit (write 1 into HPDMA_CxFR.xxF).

TCF (transfer complete) and HTF (half transfer) events generation is controlled by HPDMA_CxTR2.TCEM[1:0] as follows:

• • A transfer-complete event is a block transfer complete, a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode HPDMA_CxTR2.TCEM[1:0].
• • A half-transfer event is a half-block transfer, or a half 2D/repeated block transfer, depending on the transfer complete event mode HPDMA_CxTR2.TCEM[1:0].

A half-block transfer occurs when half of the source block size bytes (rounded-up integer of \( HPDMA\_CxBR1.BNDT[15:0] / 2 \) ) is transferred to the destination.

A half 2D/repeated block transfer occurs when half of the repeated blocks (rounded-up integer of \( (HPDMA\_CxBR1.BRC[10:0] + 1) / 2 \) ) is transferred to the destination.

See HPDMA channel x transfer register 2 (HPDMA_CxTR2) for more details.

Note: The interrupt mode must be used (not the polling mode) to be notified on a half transfer when the write data transaction has been completed over the AXI destination allocated port (written at the destination memory-mapped address), and not just before when has been issued, at HPDMA level, this AXI burst transaction.

A transfer error rises in one of the following situations:

• • during a single/burst data transfer from the source or to the destination (DTEF)
• • during an update of an HPDMA channel register from the programmed LLI in memory (ULEF)
• • during a tentative execution of an HPDMA channel with an unauthorized setting (USEF)

The user must perform a debug session to correct the HPDMA channel programming versus the USEF root causes list (see Section 18.4.17 ).

A trigger overrun is described in Trigger hit memorization and trigger overrun flag generation .

18.8 HPDMA registers

The HPDMA registers must be accessed with an aligned 32-bit word data access.

18.8.1 HPDMA secure configuration register (HPDMA_SECCFGR)

Address offset: 0x000

Reset value: 0x0000 0000

A write access to this register must be secure and privileged. A read access may be secure or nonsecure, privileged or unprivileged and with any CID.

A write access is ignored at bit level if the corresponding channel x is locked ( \( HPDMA\_RCFGLOCKR.LOCKx = 1 \) ).

This register can mix information from different CIDs. If a channel x is configured as CID filtered ( \( HPDMA\_CxCIDCFGR.CFEN = 1 \) ), the SECx bit can be written only by an authorized CID (and secure and privileged) agent. If the debug domain feature is activated, an access to this register is granted to the debug domain CID, regardless of any CID filtering.

This register must be written when HPDMA_CxCR.EN = 0.

This register is read-only when HPDMA_CxCR.EN = 1.

This register must be programmed at a bit level, at the initialization/closure of an HPDMA channel (when HPDMA_CxCR.EN = 0), to securely allocate individually any channel x to the secure or nonsecure world.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SECx : Secure state of channel x (x = 15 to 0)

0: Nonsecure
1: Secure

18.8.2 HPDMA privileged configuration register (HPDMA_PRIVCFGR)

Address offset: 0x004

Reset value: 0x0000 0000

A write access to this register must be privileged. A read access can be privileged or unprivileged, secure or nonsecure, and with any CID.

This register can mix secure and nonsecure information. If a channel x is configured as secure (HPDMA_SECCFGR.SECx = 1), the PRIVx bit can be written only by a secure (and privileged) agent.

This register can mix information from different CIDs. If a channel x is configured as CID filtered (HPDMA_CxCIDCFGR.CFEN = 1), the PRIVx bit can be written only by an authorized CID (and privileged) agent. If the debug domain feature is activated, an access to this register is granted to the debug domain CID, regardless of any CID filtering.

A write access is ignored at bit level if the corresponding channel x is locked (HPDMA_RCFGLOCKR.LOCKx = 1).

This register must be written when HPDMA_CxCR.EN = 0.

This register is read-only when HPDMA_CxCR.EN = 1.

This register must be programmed at a bit level, at the initialization/closure of a HPDMA channel (HPDMA_CxCR.EN = 0), to individually allocate any channel x to the privileged or unprivileged world.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PRIVx : Privileged state of channel x (x = 15 to 0)

0: Unprivileged

1: Privileged

18.8.3 HPDMA configuration lock register (HPDMA_RCFGLOCKR)

Address offset: 0x008

Reset value: 0x0000 0000

This register can be written by a software agent with secure privileged and trusted domain CID attributes in order to individually lock, for example at boot time, the secure privileged and CID attributes of any HPDMA channel/resource (to lock the setting of HPDMA_SECCFGR, HPDMA_PRIVCFGR, and HPDMA_CxCIDCFGR for any channel x at, for example at boot time).

A read access may be privileged or unprivileged, secure or nonsecure, and with any CID.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 LOCKx : Lock of the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset (x = 15 to 0)

This bit is cleared after reset and, once set, it cannot be reset until a global HPDMA reset.

0: Secure privilege and CID configuration of the channel x is writable.

1: Secure privilege and CID configuration of the channel x is not writable.

18.8.4 HPDMA nonsecure masked interrupt status register (HPDMA_MISR)

Address offset: 0x00C

Reset value: 0x0000 0000

This register is a read register.

This is a nonsecure register, containing the masked interrupt status bit MISx for each nonsecure channel x (channel x configured with HPDMA_SECCFGR.SECx = 0). It is a logical OR of all the flags of HPDMA_CxSR, each source flag being enabled by the corresponding interrupt enable bit of HPDMA_CxCR.

Every bit is deasserted by hardware when writing 1 to the corresponding flag clear bit in HPDMA_CxFCR.

If a channel x is in secure state (HPDMA_SECCFGR.SECx = 1), a read access to the masked interrupt status bit MISx of this channel x returns zero.

This register can mix privileged and unprivileged information, depending on the privileged state of each channel HPDMA_PRIVCFGR.PRIVx. A privileged software can read the full nonsecure interrupt status. An unprivileged software is restricted to read the status of unprivileged (and nonsecure) channels, other privileged bitfields returning zero.

This register can mix information from different CIDs. If a channel x is configured as CID filtered (HPDMA_CxCIDCFGR.CFEN = 1), the MISx bit can be read only by an authorized CID agent, else it is returned zero. If the debug domain feature is activated, an access to this register is granted to the debug domain CID, regardless of any CID filtering.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 MISx : Masked interrupt status of channel x (x = 15 to 0)

0: No interrupt occurred on channel x.

1: An interrupt occurred on channel x.

18.8.5 HPDMA secure masked interrupt status register (HPDMA_SMISR)

Address offset: 0x010

Reset value: 0x0000 0000

This is a secure read register, containing the masked interrupt status bit MISx for each secure channel x (HPDMA_SECCFGR.SECx = 1). It is a logical OR of all the HPDMA_CxSR flags, each source flag being enabled by the corresponding HPDMA_CxCR interrupt enable bit.

Every bit is deasserted by hardware when securely writing 1 to the corresponding HPDMA_CxFCR flag clear bit.

This register does not contain any information about a nonsecure channel.

This register can mix privileged and unprivileged information, depending on the privileged state of each channel HPDMA_PRIVCFGR.PRIVx. A privileged software can read the full secure interrupt status. An unprivileged software is restricted to read the status of unprivileged and secure channels, other privileged bitfields returning zero.

This register can mix information from different CIDs. If a channel x is configured as CID filtered (HPDMA_CxCIDCFGR.CFEN = 1), the MISx bit can be read only by an authorized

CID agent, else it is returned zero. If the debug domain feature is activated, an access to this register is granted to the debug domain CID, regardless of any CID filtering.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 MISx : Masked interrupt status of the secure channel x (x = 15 to 0)

0: No interrupt occurred on the secure channel x.

1: An interrupt occurred on the secure channel x.

18.8.6 HPDMA channel x linked-list base address register (HPDMA_CxLBAR)

Address offset: 0x050 + 0x80 * x (x = 0 to 15)

Reset value: 0x0000 0000

This register must be written by a privileged software. It is either privileged readable or not, depending on the privileged state of the channel x HPDMA_PRIVCFG.R.PRIVx.

This register is either secure or nonsecure depending on the secure state of the channel x (HPDMA_SECCFG.R.SECx).

This register is CID-filtered depending on the CID configuration of the channel x (HPDMA_CxCIDCFG.R.CFEN = 1). If the debug domain feature is activated, an access to this register is granted to the debug domain CID, regardless of any CID filtering.

This register must be written when HPDMA_CxCR.EN = 0.

This register is read-only when HPDMA_CxCR.EN = 1.

This channel-based register is the linked-list base address of the memory region, for a given channel x, from which the LLIs describing the programmed sequence of the HPDMA transfers, are conditionally and automatically updated.

This 64-Kbyte aligned channel x linked-list base address is offset by the 16-bit HPDMA_CxLLR register that defines the word-aligned address offset for each LLI.

Bits 31:16 LBA[31:16] : Linked-list base address of HPDMA channel x

Bits 15:0 Reserved, must be kept at reset value.

18.8.7 HPDMA channel x CID register (HPDMA_CxCIDCFGR)

Address offset: 0x054+ 0x80 * x (x = 0 to 15)

Reset value: 0x0000 0000

This channel-based register can be written by the secure, privileged, and trusted domain CID, in order to individually configure the CID allocation of any HPDMA channel x. If the debug domain feature is activated, a read/write access to this register is granted to the debug domain CID, regardless of any CID filtering.

This register must be written when the resource configuration of the channel x is unlocked (HPDMA_RCFGLOCKR.LOCKx = 0) and when the channel is disabled (HPDMA_CxCR.EN = 0).

A read access may be privileged or unprivileged, secure or nonsecure, and with any CID.

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SEM_WLIST_CID6 : White-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)

• 0: CID6 black-listed in the semaphore-based CID allocation pool
• 1: CID6 white-listed in the semaphore-based CID allocation pool

Bit 21 SEM_WLIST_CID5 : White-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)

• 0: CID5 black-listed in the semaphore-based CID allocation pool
• 1: CID5 white-listed in the semaphore-based CID allocation pool

Bit 20 SEM_WLIST_CID4 : White-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)

• 0: CID4 black-listed in the semaphore-based CID allocation pool
• 1: CID4 white-listed in the semaphore-based CID allocation pool

Bit 19 SEM_WLIST_CID3 : White-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)

• 0: CID3 black-listed in the semaphore-based CID allocation pool
• 1: CID3 white-listed in the semaphore-based CID allocation pool

Bit 18 SEM_WLIST_CID2 : White-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)

• 0: CID2 black-listed in the semaphore-based CID allocation pool
• 1: CID2 white-listed in the semaphore-based CID allocation pool

1. Bit 17 SEM_WLIST_CID1 : White-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)
2. • 0: CID1 black-listed in the semaphore-based CID allocation pool
   • 1: CID1 white-listed in the semaphore-based CID allocation pool
3. Bit 16 SEM_WLIST_CID0 : White-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)
4. • 0: CID0 black-listed in the semaphore-based CID allocation pool
   • 1: CID0 white-listed in the semaphore-based CID allocation pool
5. Bits 15:7 Reserved, must be kept at reset value.
6. Bits 6:4 SCID[2:0] : Allocation of a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)
7. • 000: CID0 allocated to the channel x
   • 001: CID1 allocated to the channel x
   • 010: CID2 allocated to the channel x
   • 011: CID3 allocated to the channel x
   • 100: CID4 allocated to the channel x
   • 101: CID5 allocated to the channel x
   • 110: CID6 allocated to the channel x
   • 111: Reserved (write ignored)
8. Bits 3:2 Reserved, must be kept at reset value.
9. Bit 1 SEM_EN : Semaphore mode enable (for the CID allocation policy to the channel x)
10. • 0: Semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0].
    • 1: Semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX.
11. Note: If SEM_EN = 1 and if a trusted domain or debug domain CID agent clears this bit, then the HPDMA hardware automatically clears the HPDMA_CxSEMCR.SEM_MUTEX.
12. Bit 0 CFEN : CID filtering enable of the channel x
13. • 0: CID filtering disabled for when accessing a channel x register/bitfield
    • 1: CID filtering enabled for when accessing a channel x register/bitfield
14. Note: If CFEN = 1 and if a trusted domain or debug domain CID agent clears this bit, then the HPDMA hardware automatically clears the HPDMA_CxSEMCR.SEM_MUTEX.

18.8.8 HPDMA channel x semaphore control register (HPDMA_CxSEMCR)

Address offset: 0x058+ 0x80 * x (x = 0 to 15)

Reset value: 0x0000 0000

When the secure, privileged and trusted domain has set up the channel x in semaphore mode (HPDMA_CxCIDCFGR.SEM_EN = 1), this register is used during run-time by an

authorized white-listed CID agent, in order to take and after possibly release the control of the channel x.

A read access may be privileged or unprivileged, secure or nonsecure, and with any CID.

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:4 SEM_CCID[2:0] : Current CID allocated to the channel x (in semaphore mode)

This read-only bitfield is internally updated when a white-listed CID took the control of the channel x, in semaphore mode. If SEM_MUTEX = 0, this same CID also released it.

000: CID0 is the last white-listed CID that took the control of the channel x.

001: CID1 is the last white-listed CID that took the control of the channel x.

010: CID2 is the last white-listed CID that took the control of the channel x.

011: CID3 is the last white-listed CID that took the control of the channel x.

100: CID4 is the last white-listed CID that took the control of the channel x.

101: CID5 is the last white-listed CID that took the control of the channel x.

110: CID6 is the last white-listed CID that took the control of the channel x.

111: Reserved

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 SEM_MUTEX : Mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)

If the channel x is in secure state (HPDMA_SECCFGR.SECx = 1), this bit can only be written by a secure agent. If the channel x is in privileged state (HPDMA_PRIVCFGR.PRIVx = 1), this bit can only be written by a privileged agent.

If the channel x is CID-filtered (HPDMA_CxCIDCFGR.CFEN = 1) and in semaphore mode (HPDMA_CIDCFGR.SEM_EN = 1), this bit can only be written either by an authorized (white-listed) CID agent to take the control, or by the same (white-listed) CID agent to release the control.

Condition: write

0: Release the control of the channel x (in semaphore mode) to any white-listed CID.

1: Take the control of the channel x (in semaphore mode), from one of the white-listed CID pool.

Condition: read

0: Channel x CID-free (not currently under the control of any white-listed CID)

1: Channel x CID-allocated (currently taken and under the control of one white-listed CID)

Note: This bit must be written when HPDMA_CxCR.EN = 0. This bit is read-only when HPDMA_CxCR.EN = 1.

When SEM_EN or CFEN bit is cleared in HPDMA_CxSEMCR, the HPDMA hardware automatically clears this SEM_MUTEX bit.

18.8.9 HPDMA channel x flag clear register (HPDMA_CxFCR)

Address offset: 0x05C+ 0x80 * x (x = 0 to 15)

Reset value: 0x0000 0000

This is a write register, secure or nonsecure depending on the secure state of channel x (HPDMA_SECCFGR.SECx) and privileged or unprivileged, depending on the privileged state of the channel x (HPDMA_PRIVCFGR.PRIVx).

This register is CID-filtered depending on the CID configuration of the channel x (HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, an access to this register is granted to the debug domain CID, regardless of any CID filtering.

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 TOF : Trigger overrun flag clear

0: No effect

1: Corresponding TOF flag cleared

Bit 13 SUSPF : Completed suspension flag clear

0: No effect

1: Corresponding SUSPF flag cleared

Bit 12 USEF : User setting error flag clear

0: No effect

1: Corresponding USEF flag cleared

Bit 11 ULEF : Update link transfer error flag clear

0: No effect

1: Corresponding ULEF flag cleared

Bit 10 DTEF : Data transfer error flag clear

0: No effect

1: Corresponding DTEF flag cleared

Bit 9 HTF : Half-transfer flag clear

0: No effect

1: Corresponding HTF flag cleared

Bit 8 TCF : Transfer complete flag clear

0: No effect

1: Corresponding TCF flag cleared

Bits 7:0 Reserved, must be kept at reset value.

18.8.10 HPDMA channel x status register (HPDMA_CxSR)

Address offset: 0x060 + 0x80 * x (x = 0 to 15)

Reset value: 0x0000 0001

This is a read register, reporting the channel status.

This register is secure or nonsecure, depending on the secure state of channel x (HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of the channel (HPDMA_PRIVCFGR.PRIVx).

This register is CID-filtered depending on the CID configuration of the channel x (HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, an access to this register is granted to the debug domain CID, regardless of any CID filtering.

Bits 31:25 Reserved, must be kept at reset value.

Bits 24:16 FIFOL[8:0] : Monitored FIFO level

Number of available write beats in the FIFO, in units of the programmed destination data width (see Section 18.8.12: HPDMA channel x transfer register 1 (HPDMA_CxTR1) DDW_LOG2[1:0], in units of bytes, half-words, words or double-words).

Note: After having suspended an active transfer, the user may need to read FIFOL[8:0], additionally to HPDMA_CxBR1.BDNT[15:0] and HPDMA_CxBR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (HPDMA_CxSR.SUSPF = 1).

Bit 15 Reserved, must be kept at reset value.

Bit 14 TOF : Trigger overrun flag

• 0: No trigger overrun event
• 1: A trigger overrun event occurred.

Bit 13 SUSPF : Completed suspension flag

• 0: No completed suspension event
• 1: A completed suspension event occurred.

Bit 12 USEF : User setting error flag

• 0: No user setting error event
• 1: A user setting error event occurred.

Bit 11 ULEF : Update link transfer error flag

• 0: No update link transfer error event
• 1: A master bus error event occurred while updating a linked-list register from memory.

Bit 10 DTEF : Data transfer error flag

• 0: No data transfer error event
• 1: A master bus error event occurred on a data transfer.

0: No half-transfer event

1: A half-transfer event occurred.

A half-transfer event is either a half-block transfer or a half 2D/repeated block transfer, depending on the transfer complete event mode (HPDMA_CxTR2.TCEM[1:0]).

A half-block transfer occurs when half of the bytes of the source block size (rounded up integer of HPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination.

A half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (HPDMA_CxBR1.BRC[10:0]+1)/2)) has been transferred to the destination.

0: No transfer complete event

1: A transfer complete event occurred.

A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (HPDMA_CxTR2.TCEM[1:0]).

Bits 7:1 Reserved, must be kept at reset value.

0: Channel not in idle state

1: Channel in idle state

This idle flag is deasserted by hardware when the channel is enabled (HPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately reported).

This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state).

18.8.11 HPDMA channel x control register (HPDMA_CxCR)

Address offset: 0x064 + 0x80 * x (x = 0 to 15)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of the channel x (HPDMA_PRIVCFGR.PRIVx).

This register is CID-filtered depending on the CID configuration of the channel x (HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, an access to this register is granted to the debug domain CID, regardless of any CID filtering.

This register is used to control a channel (activate, suspend, abort or disable it).

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:22 PRIO[1:0] : Priority level of the channel x HPDMA transfer versus others

• 00: Low priority, low weight
• 01: Low priority, mid weight
• 10: Low priority, high weight
• 11: High priority

Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.

Bits 21:18 Reserved, must be kept at reset value.

Bit 17 LAP : Linked-list allocated port

This bit is used to allocate the master port for the update of the HPDMA linked-list registers from the memory.

• 0: Port 0 (AXI) allocated
• 1: Port 1 (AHB) allocated

Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.

Bit 16 LSM : Link step mode

0: Channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present.

1: Channel executed once for the current LLI

First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0, if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by HPDMA_CxLLR. Then channel execution is completed.

Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.

Bit 15 Reserved, must be kept at reset value.

Bit 14 TOIE : Trigger overrun interrupt enable

• 0: Interrupt disabled
• 1: Interrupt enabled

Bit 13 SUSPIE : cCompleted suspension interrupt enable

• 0: Interrupt disabled
• 1: Interrupt enabled

Bit 12 USEIE : User setting error interrupt enable

• 0: Interrupt disabled
• 1: Interrupt enabled

Bit 11 ULEIE : Update link transfer error interrupt enable

• 0: Interrupt disabled
• 1: Interrupt enabled

Bit 10 DTEIE : Data transfer error interrupt enable

• 0: Interrupt disabled
• 1: Interrupt enabled

Bit 9 HTIE : Half-transfer complete interrupt enable

• 0: Interrupt disabled
• 1: Interrupt enabled

Bit 8 TCIE : Transfer complete interrupt enable

• 0: Interrupt disabled
• 1: Interrupt enabled

Bits 7:3 Reserved, must be kept at reset value.

Bit 2 SUSP : Suspend

Writing 1 to RESET in this register causes the hardware to deassert this SUSP bit, whatever is written into this SUSP. Else:

Software must write 1 in order to suspend an active channel (a channel with an ongoing HPDMA transfer over its master ports).

The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in Figure 74 .

0: Write: resume channel, read: channel not suspended

1: Write: suspend channel, read: channel suspended

Bit 1 RESET : Reset

This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0).

The reset is effective when the channel is in steady state, meaning one of the following:

- active channel in suspended state (HPDMA_CxSR.SUSPF = 1 and

HPDMA_CxSR.IDLEF = HPDMA_CxCR.EN = 1)

- channel in disabled state (HPDMA_CxSR.IDLEF = 1 and HPDMA_CxCR.EN = 0).

After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (HPDMA_CxBR1, HPDMA_CxSAR and HPDMA_CxDAR) before enabling again the channel (see the programming sequence in Figure 75 ).

0: No channel reset

1: Channel reset

Bit 0 EN : Enable

Writing 1 to RESET in this register causes the hardware to deassert this EN bit, whatever is written into this bit 0. Else:

This bit is deasserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, for example if LSM = 1 at the end of a single execution of the LLI).

Else, this bit can be asserted by software.

Writing 0 into this EN bit is ignored.

0: Write: ignored, read: channel disabled

1: Write: enable channel, read: channel enabled

18.8.12 HPDMA channel x transfer register 1 (HPDMA_CxTR1)

Address offset: 0x090 + 0x80 * x (x = 0 to 15)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (HPDMA_SECCFGR.SECx) except for secure DSEC and SSEC, privileged or unprivileged, depending on the privileged state of the channel x in HPDMA_PRIVCFGR.PRIVx.

This register is CID-filtered depending on the CID configuration of the channel x (HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, an access to this register is granted to the debug domain CID, regardless of any CID filtering.

This register controls the transfer of a channel x.

This register must be written when HPDMA_CxCR.EN = 0.

This register is read-only when HPDMA_CxCR.EN = 1.

This register must be written when the channel is completed. Then the hardware has de-asserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block, 2D/repeated block, LLI, or full linked-list.

In linked-list mode, during the link transfer, this register is automatically updated by HPDMA from the memory if HPDMA_CxLLR.UT1 = 1.

Bit 31 DSEC : Security attribute of the HPDMA transfer to the destination

If HPDMA_SECCFGR.SECx = 1 and the access is secure:

0: HPDMA transfer nonsecure

1: HPDMA transfer secure

This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when HPDMA_SECCFGR.SECx = 1. A secure write is ignored when HPDMA_SECCFGR.SECx = 0.

When HPDMA_SECCFGR.SECx is deasserted, this DSEC bit is also deasserted by hardware (on a secure reconfiguration of the channel as nonsecure), and the HPDMA transfer to the destination is nonsecure.

Bit 30 DAP : Destination allocated port

This bit is used to allocate the master port for the destination transfer

0: Port 0 (AXI) allocated

1: Port 1 (AHB) allocated

Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.

Bit 29 Reserved, must be kept at reset value.

If the destination data size is not a double-word, this bit is ignored.

If the destination data size is a double-word and if destination bus is AXI (DAP = 0):

0: No word-based exchanged within double-word

1: The two consecutive (post PAM) words are exchanged in each destination double-word.

If the destination data size is shorter than a word, this bit is ignored.

If the destination data size is a word or double-word and if destination bus is AXI (DAP = 0):

0: No half-word-based exchanged within word

1: The two consecutive (post PAM) half-words are exchanged in each destination word.

If the destination data size is a byte, this bit is ignored.

If the destination data size is not a byte:

0: No byte-based exchange within half-word

1: The two consecutive (post PAM) bytes are exchanged in each destination half-word.

The burst length unit is one data named beat within a burst. If DBL_1[5:0] = 0, the burst can be named as single. Each data/beat has a width defined by the destination data width DDW_LOG2[1:0].

Caution: As highlighted in Section 18.3.2 , the maximum allowed AXI burst length is 16. The user must set DBL_1[5:0] lower or equal to 15 if the destination allocated port is AXI (if DAP = 0).

Note: If a burst transfer crossed a 1- or 4-Kbyte address boundary on respectively an AHB or AXI transfer, the HPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB/AXI protocol.

If the burst length exceeds 16 on an AHB transfer, or if the burst on an AXI transfer is both with fixed addressing (DINC = 0) and with a burst length which exceeds 16, the HPDMA modifies and shortens the programmed burst into bursts of lower length, to be compliant with the AHB or AXI protocol.

If a burst transfer is of length greater than the FIFO size of the channel x, the HPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with HPDMA re-arbitration between effective and lower singles/bursts, but the data integrity is guaranteed.

0: Fixed burst

1: Contiguously incremented burst

The destination address, pointed by HPDMA_CxDAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.

Bit 18 Reserved, must be kept at reset value.

Bits 17:16 DDW_LOG2[1:0] : Binary logarithm of the destination data width of a burst, in bytes

00: Byte

01: Half-word (2 bytes)

10: Word (4 bytes)

11: Double-word (8 bytes)

Note: A destination burst data width must be less or equal to the implemented data width of the allocated AXI/AHB destination port via the DAP bit (it is recommended to be equal for best performance). Otherwise a user setting error is reported and no transfer is issued.

A destination burst transfer must have an aligned destination i) address (HPDMA_CxDAR[2:0]), ii) address offset HPDMA_CxTR3.DAO[2:0] if present, with its destination data width (DDW_LOG2[2:0]). Otherwise a user setting error is reported and no transfer is issued.

When configured in packing mode (PAM[1] = 1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (see HPDMA_CxBR1.BNDT[2:0] versus DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.

Bit 15 SSEC : Security attribute of the HPDMA transfer from the source

If HPDMA_SECCFGR.SECx = 1 and the access is secure:

0: HPDMA transfer nonsecure

1: HPDMA transfer secure

This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when HPDMA_SECCFGR.SECx = 1. A secure write is ignored when HPDMA_SECCFGR.SECx = 0.

When HPDMA_SECCFGR.SECx is deasserted, this SSEC bit is also deasserted by hardware (on a secure reconfiguration of the channel as nonsecure), and the HPDMA transfer from the source is nonsecure.

Bit 14 SAP : Source allocated port

This bit is used to allocate the master port for the source transfer

0: Port 0 (AXI) allocated

1: Port 1 (AHB) allocated

Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.

Bit 13 SBX : Source byte exchange within the unaligned half-word of each source word

If the source data width is shorter than a word, this bit is ignored.

If the source data width is a word or a double-word, and if source bus is AXI (SAP = 0):

0: No byte-based exchange within the unaligned half-word of each source word

1: The two consecutive bytes within the unaligned half-word of each source word are exchanged.

Bits 12:11 PAM[1:0] : Padding/alignment mode

If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored.

Else, in the following enumerated values, the condition PAM_1 is when destination data width is higher than source data width, and the condition PAM_2 is when source data width is higher than destination data width.

Condition: PAM_1

00: Source data is transferred as right aligned, padded with 0s up to the destination data width

01: Source data is transferred as right aligned, sign extended up to the destination data width

10-11: Successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer

Condition: PAM_2

00: Source data is transferred as right aligned, left-truncated down to the destination data width

01: Source data is transferred as left-aligned, right-truncated down to the destination data width

10-11: Source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination

Note: If the transfer from the source peripheral is configured with peripheral flow-control mode (SWREQ = 0 and PFREQ = 1 and DREQ = 0), and if the destination data width > the source data width, packing is not supported.

Bit 10 Reserved, must be kept at reset value.

Bits 9:4 SBL_1[5:0] : Source burst length minus 1, between 0 and 63

The burst length unit is one data named beat within a burst. If SBL_1[5:0] = 0, the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0].

Caution: As highlighted in Section 18.3.2 , the maximum allowed AXI burst length is 16. The user must set SBL_1[5:0] lower or equal to 15 if the source allocated port is AXI (if SAP = 0).

Note: If a burst transfer crossed a 1- or 4-Kbyte address boundary on respectively an AHB or an AXI transfer, the HPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol.

If the burst length exceeds 16 on a AHB transfer, or if the burst on a AXI transfer is both with fixed addressing (SINC = 0) and with a burst length which exceeds 16, the HPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with HPDMA re-arbitration between effective and lower singles/bursts, but the data integrity is guaranteed.

Bit 3 SINC : Source incrementing burst

0: Fixed burst

1: Contiguously incremented burst

The source address, pointed by HPDMA_CxSAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.

Bit 2 Reserved, must be kept at reset value.

Bits 1:0 SDW_LOG2[1:0] : Binary logarithm of the source data width of a burst in bytes

00: Byte

01: Half-word (2 bytes)

10: Word (4 bytes)

11: Double-word (8 bytes)

Note: A source burst data width must be less or equal to the implemented data width of the allocated AXI/AHB source port via the SAP bit (it is recommended to be equal for best performance). Otherwise a user setting error is reported and no transfer is issued.

A source block size must be a multiple of the source data width (HPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued.

A source burst transfer must have an aligned source i) address (HPDMA_CxSAR[2:0]), ii) address offset HPDMA_CxTR3.SAO[2:0] if present, with its source data width (SDW_LOG2[1:0]). Otherwise a user setting error is reported and no transfer is issued.

18.8.13 HPDMA channel x transfer register 2 (HPDMA_CxTR2)

Address offset: 0x094 + 0x80 * x (x = 0 to 15)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of channel x (HPDMA_PRIVCFGR.PRIVx).

This register is CID-filtered depending on the CID configuration of the channel x (HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, a write access to this register is granted to the debug domain CID, regardless of any CID filtering.

This register controls the transfer of a channel x.

This register must be written when HPDMA_CxCR.EN = 0.

This register is read-only when HPDMA_CxCR.EN = 1.

This register must be written when the channel is completed (the hardware deasserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block, 2D/repeated block, LLI, or full linked-list.

In linked-list mode, during the link transfer, this register is automatically updated by HPDMA from the memory, if HPDMA_CxLLR.UT2 = 1.

Bits 31:30 TCEM[1:0] : Transfer complete event mode

These bits define the transfer granularity for the transfer complete and half-transfer complete events generation.

00: At block level (when HPDMA_CxBR1.BNDT[15:0] = 0): The complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

Note: If the initial LLI ₀ data transfer is null/void (directly programmed by the internal register file with HPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half-transfer event is generated.

01: if the channel is not 2D addressing capable: same as 00; if the channel is 2D addressing capable: at 2D/repeated block level, meaning when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block.

Note: If the initial LLI ₀ data transfer is null/void (directly programmed by the internal register file with HPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half-transfer event is generated.

10: At LLI level: The complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half-transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for a 2D addressing capable channel), if any data transfer.

Note: If the initial LLI ₀ data transfer is null/void (directly programmed by the internal register file with HPDMA_CxBR1.BNDT[15:0] = 0), then the half-transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI ₁ .

11: At channel level: The complete transfer event is generated at the end of the last LLI transfer. The half-transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated.

Bits 29:26 Reserved, must be kept at reset value.

Bits 25:24 TRIGPOL[1:0] : Trigger event polarity

These bits define the polarity of the selected trigger event input defined by TRIGSEL[6:0].

00: No trigger (masked trigger event)

01: Trigger on the rising edge

10: Trigger on the falling edge

11: Same as 00

Bit 23 Reserved, must be kept at reset value.

Bits 22:16 TRIGSEL[6:0] : Trigger event input selection

These bits select the trigger event input of the HPDMA transfer (as per Section 18.3.7 ), with an active trigger event if TRIGPOL[1:0] ≠ 00.

Bits 15:14 TRIGM[1:0] : Trigger mode

These bits define the transfer granularity for its conditioning by the trigger.

If the channel x is enabled (HPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored.

Else, an HPDMA transfer is conditioned by at least one trigger hit:

00: at block level: the first burst read of each block transfer is conditioned by one hit trigger. This is also valid for a 2D addressing capable channel: for each block even if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] ≠ 0.

01: if the channel is not 2D addressing capable: same as 00; if the channel is 2D addressing capable: at 2D/repeated block level, meaning the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger.

10: at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

11: at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger.

– If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned.

– If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit.

The HPDMA monitoring of a trigger for channel x is started when the channel is enabled/loading with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10).

The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[6:0] is not modified, and the channel is enabled.

Transferring a next LLI _n+1 that updates the HPDMA_CxTR2 with a new value for any of TRIGSEL[6:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLI _n trigger.

After a first new trigger hit _n+1 is memorized, if another second trigger hit _n+2 is detected and if the hit _n triggered transfer is still not completed, hit _n+2 is lost and not memorized. A trigger overrun flag is reported (HPDMA_CxSR.TOF = 1), and an interrupt is generated if enabled (HPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun.

Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ = 1 or (SWREQ = 0 and DREQ = 0)), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger.

When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1/4-Kbyte boundary address crossing maximum burst length versus AHB/AXI protocol): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger.

Bit 13 Reserved, must be kept at reset value.

Bit 12 PFREQ : Hardware request in peripheral flow control mode

Important: If a given channel x is not implemented with this feature, this bit is reserved and PFREQ is not present (see Section 18.3.6 for the list of the implemented channels with this feature).

If the channel x is activated (HPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:

0: The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion.

1: The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 18.3.6 for more details).

Note: In peripheral flow control mode, there are the following restrictions:

• - no 2D/repeated block support (HPDMA_CxBR1.BRC[10:0] must be set to 0 if present)
• - the peripheral must be set as the source of the transfer (DREQ = 0).
• - data packing to a wider destination width is not supported (if destination width > source data width, HPDMA_CxTR1.PAM[1] must be set to 0).
• - HPDMA_CxBR1.BNDT[15:0] must be set as a multiple of the source (peripheral) burst size.

Bit 11 BREQ : Block hardware request

If the channel x is activated (HPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:

0: The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

1: The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 18.3.5).

Bit 10 DREQ : Destination hardware request

This bit is ignored if channel x is activated (HPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else:

0: Selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)

1: Selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)

Note: If the channel x is activated (HPDMA_CxCR.EN is asserted) with SWREQ = 0 and PFREQ = 1 (peripheral hardware request with peripheral flow-control mode), any software assertion to this DREQ bit is ignored: in peripheral flow-control mode, only a peripheral-to-memory transfer is supported.

Bit 9 SWREQ : Software request

This bit is internally taken into account when HPDMA_CxCR.EN is asserted.

0: No software request. The selected hardware request REQSEL[7:0] is taken into account.

1: Software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored.

Bit 8 Reserved, must be kept at reset value.

Bits 7:0 REQSEL[7:0] : Hardware request selection

These bits are ignored if channel x is activated (HPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per Section 18.3.4 .

Caution: The user must not assign a same input hardware request (same REQSEL[7:0] value) to different active HPDMA channels (HPDMA_CxCR.EN = 1 and HPDMA_CxTR2.SWREQ = 0 for these channels). The HPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting.

18.8.14 HPDMA channel x block register 1 (HPDMA_CxBR1)

Address offset: 0x098 + 0x80 * x (x = 0 to 11)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of channel x (HPDMA_PRIVCFGR.PRIVx).

This register is CID-filtered depending on the CID configuration of the channel x (HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, a write access to this register is granted to the debug domain CID, regardless of any CID filtering.

This register controls the transfer of a channel x at a block level.

This register must be written when HPDMA_CxCR.EN = 0.

This register is read-only when HPDMA_CxCR.EN = 1.

This register must be written when channel x is completed (then the hardware has de-asserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block, 2D/repeated block, LLI, or full linked-list.

In linked-list mode, during the link transfer:

• • if HPDMA_CxLLR.UB1 = 1, this register is automatically updated by the HPDMA from the next LLI in memory.
• • If HPDMA_CxLLR.UB1 = 0 and if there is at least one linked-list register to be updated from the next LLI in memory, this register is automatically and internally restored with the programmed value for the bitfield BNDT[15:0].
• • If all the update bits HPDMA_CxLLR.Uxx are null and if HPDMA_CxLLR.LA[15:0] ≠ 0, the current LLI is the last one and is continuously executed: this register is automatically and internally restored with the programmed value for BNDT[15:0] after each execution of this final LLI
• • If HPDMA_CxLLR = 0, this register and BNDT[15:0] are kept as null, channel x is completed.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BNDT[15:0] : Block number of data bytes to transfer from the source

Block size transferred from the source. When the channel is enabled, this bitfield becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1.

Once the last data transfer is completed (BNDT[15:0] = 0):

• - if HPDMA_CxLLR.UB1 = 1, this bitfield is updated with the LLI in the memory.
• - if HPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this bitfield is internally restored to the programmed value.
• - if all HPDMA_CxLLR.Uxx = 0 and if HPDMA_CxLLR.LA[15:0] = 0, this bitfield is internally restored to the programmed value (infinite/continuous last LLI).
• - if HPDMA_CxLLR = 0, this bitfield is kept as zero following the last LLI data transfer.

Note: A non-null source block size must be a multiple of the source data width (BNDT versus HPDMA_CxTR1.SDW_LOG2). Else a user setting error is reported and no transfer is issued.

When configured in packing mode (HPDMA_CxTR1.PAM[1] = 1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT versus HPDMA_CxTR1.DDW_LOG2). Else a user setting error is reported and no transfer is issued.

18.8.15 HPDMA channel x alternate block register 1 (HPDMA_CxBR1)

Address offset: 0x098 + 0x80 * x (x = 12 to 15)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of channel x (HPDMA_PRIVCFGR.PRIVx).

This register is CID-filtered depending on the CID configuration of the channel x (HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, a write access to this register is granted to the debug domain CID, regardless of any CID filtering.

This register controls the transfer of a channel x at a block level.

This register must be written when HPDMA_CxCR.EN = 0.

This register is read-only when HPDMA_CxCR.EN = 1.

This register must be written when channel x is completed (then the hardware has de-asserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block, 2D/repeated block, LLI, or full linked-list.

In linked-list mode, during the link transfer:

• • if HPDMA_CxLLR.UB1 = 1, this register is automatically updated by the HPDMA from the next LLI in memory.
• • If HPDMA_CxLLR.UB1 = 0 and if there is at least one linked-list register to be updated from the next LLI in memory, this register is automatically and internally restored with the programmed value for the bitfields BNDT[15:0] and BRC[10:0].
• • If all the update bits HPDMA_CxLLR.Uxx are null and if HPDMA_CxLLR.LA[15:0] ≠ 0, the current LLI is the last one and is continuously executed: this register is automatically and internally restored with the programmed value for the bitfields BNDT[15:0] and BRC[10:0] after each execution of this final LLI

• • If HPDMA_CxLLR = 0, BNDT[15:0] and BRC[10:0] are kept as null, channel x is completed.

Bit 31 BRDDEC : Block repeat destination address decrement

0: At the end of a block transfer, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxBR2.BRDAO to the current HPDMA_CxDAR value (current destination address)

1: At the end of a block transfer, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRDAO from the current HPDMA_CxDAR value (current destination address)

Note: On top of this increment/decrement (depending on BRDDEC), HPDMA_CxDAR is in the same time also updated by the increment/decrement (depending on DDEC) of the HPDMA_CxTR3.DAO value, as it is usually done at the end of each programmed burst transfer.

Bit 30 BRSDC : Block repeat source address decrement

0: At the end of a block transfer, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxBR2.BRSAO to the current HPDMA_CxSAR value (current source address)

1: At the end of a block transfer, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRSAO from the current HPDMA_CxSAR value (current source address)

Note: On top of this increment/decrement (depending on BRSDC), HPDMA_CxSAR is in the same time also updated by the increment/decrement (depending on SDEC) of the HPDMA_CxTR3.SAO value, as it is done after any programmed burst transfer.

Bit 29 DDEC : destination address decrement

0: At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)

1: At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)

Bit 28 SDEC : source address decrement

0: At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)

1: At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)

Bit 27 Reserved, must be kept at reset value.

Bits 26:16 BRC[10:0] : Block repeat counter

This bitfield contains the number of repetitions of the current block (0 to 2047).

When the channel is enabled, this bitfield becomes read-only. After decrements, this bitfield indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer.

Once the last block transfer is completed ( \( BRC[10:0] = BNDT[15:0] = 0 \) ):

• – If \( HPDMA\_CxLLR.UB1 = 1 \) , all \( HPDMA\_CxBR1 \) bitfields are updated by the next LLI in the memory.
• – If \( HPDMA\_CxLLR.UB1 = 0 \) and if there is at least one not null Uxx update bit, this bitfield is internally restored to the programmed value.
• – if all \( HPDMA\_CxLLR.Uxx = 0 \) and if \( HPDMA\_CxLLR.LA[15:0] \neq 0 \) , this bitfield is internally restored to the programmed value (infinite/continuous last LLI).
• – if \( HPDMA\_CxLLR = 0 \) , this bitfield is kept as zero following the last LLI and data transfer.

Bits 15:0 BNDT[15:0] : Block number of data bytes to transfer from the source

Block size transferred from the source. When the channel is enabled, this bitfield becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred.

\( BNDT[15:0] \) is programmed in number of bytes, maximum source block size is 64 Kbytes -1.

Once the last data transfer is completed ( \( BNDT[15:0] = 0 \) ):

• - if \( HPDMA\_CxLLR.UB1 = 1 \) , this bitfield is updated with the LLI in the memory.
• - if \( HPDMA\_CxLLR.UB1 = 0 \) and if there is at least one not null Uxx update bit, this bitfield is internally restored to the programmed value.
• - if all \( HPDMA\_CxLLR.Uxx = 0 \) and if \( HPDMA\_CxLLR.LA[15:0] \neq 0 \) , this bitfield is internally restored to the programmed value (infinite/continuous last LLI).
• - if \( HPDMA\_CxLLR = 0 \) , this bitfield is kept as zero following the last LLI data transfer.

Note: A non-null source block size must be a multiple of the source data width (BNDT versus HPDMA_CxTR1.SDW_LOG2). Else a user setting error is reported and no transfer is issued.

When configured in packing mode ( \( HPDMA\_CxTR1.PAM[1] = 1 \) and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT versus HPDMA_CxTR1.DDW_LOG2). Else a user setting error is reported and no transfer is issued.

18.8.16 HPDMA channel x source address register (HPDMA_CxSAR)

Address offset: \( 0x09C + 0x80 \times x \) ( \( x = 0 \) to \( 15 \) )

Reset value: \( 0x0000\ 0000 \)

This register is secure or nonsecure depending on the secure state of channel \( x \) (HPDMA_SECCFGR.SEC \( x \) ), and privileged or unprivileged, depending on the privileged state of channel \( x \) (HPDMA_PRIVCFGR.PRIV \( x \) ).

This register is CID-filtered depending on the CID configuration of the channel \( x \) (HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, an access to this register is granted to the debug domain CID, regardless of any CID filtering.

This register configures the source start address of a transfer.

This register must be written when HPDMA_CxCR.EN = 0.

This register is read-only when HPDMA_CxCR.EN = 1, and continuously updated by hardware, in order to reflect the address of the next burst transfer from the source.

This register must be written when the channel is completed (then the hardware has deasserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block, 2D/repeated block, LLI, or full linked-list.

In linked-list mode, during the link transfer, this register is automatically updated by the HPDMA from the memory if HPDMA_CxLLR.USA = 1.

This bitfield is the pointer to the address from which the next data is read.

During the channel activity, depending on the source addressing mode (HPDMA_CxTR1.SINC), this bitfield is kept fixed or incremented by the data width (HPDMA_CxTR1.SDW_LOG2[1:0]) after each burst source data, reflecting the next address from which data is read.

During the channel activity, this address is updated after each completed source burst, consequently to:

• – the programmed source burst; either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (HPDMA_CxTR1.SINC = 1), then the additional address offset value is the programmed burst size, as defined by HPDMA_CxTR1.SBL_1[5:0] and HPDMA_CxTR1.SDW_LOG2[1:0]
• – the additional source incremented/decremented offset value as programmed by HPDMA_CxBR1.SDEC and HPDMA_CxTR3.SAO[12:0]
• – once/if completed source block transfer, for a channel x with 2D addressing capability (x = 12 to 15). additional block repeat source incremented/decremented offset value as programmed by HPDMA_CxBR1.BRSDEC and HPDMA_CxBR2.BRSAO[15:0]

In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by HPDMA from the memory, provided the LLI is set with HPDMA_CxLLR.USA = 1.

Note: A source address must be aligned with the programmed data width of a source burst (SA versus HPDMA_CxTR1.SDW_LOG2). Else, a user setting error is reported and no transfer is issued.

When the source block size is not a multiple of the source burst size and is a multiple of the source data width, the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional HPDMA_CxTR3.SAO[12:0] is not applied.

18.8.17 HPDMA channel x destination address register (HPDMA_CxDAR)

Address offset: 0x0A0 + 0x80 * x (x = 0 to 15)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of channel x (HPDMA_PRIVCFGR.PRIVx).

This register is CID-filtered depending on the CID configuration of the channel x (HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, an access to this register is granted to the debug domain CID, regardless of any CID filtering.

This register configures the destination start address of a transfer.

This register must be written when HPDMA_CxCR.EN = 0.

This register is read-only when HPDMA_CxCR.EN = 1, and continuously updated by hardware, in order to reflect the address of the next burst transfer to the destination.

This register must be written when the channel is completed (then the hardware has deasserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block, 2D/repeated block, LLI, or full linked-list.

In linked-list mode, during the link transfer, this register is automatically updated by HPDMA from the memory if HPDMA_CxLLR.UDA = 1.

Bits 31:0 DA[31:0] : destination address

This bitfield is the pointer to the address from which the next data is written.

During the channel activity, depending on the destination addressing mode (HPDMA_CxTR1.DINC), this bitfield is kept fixed or incremented by the data width (HPDMA_CxTR1.DDW_LOG2[1:0]) after each burst destination data, reflecting the next address from which data is written.

During the channel activity, this address is updated after each completed destination burst, consequently to:

1. • – the programmed destination burst; either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (HPDMA_CxTR1.DINC = 1), then the additional address offset value is the programmed burst size, as defined by HPDMA_CxTR1.DBLE[5:0] and HPDMA_CxTR1.DDW_LOG2[1:0]
   • – the additional destination incremented/decremented offset value as programmed by HPDMA_CxBR1.DDEC and HPDMA_CxTR3.DAO[12:0]
   • – once/if completed destination block transfer, for a channel x with 2D addressing capability, the additional block repeat destination incremented/decremented offset value as programmed by HPDMA_CxBR1.BRDDEC and HPDMA_CxBR2.BRDAO[15:0]
2. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by the HPDMA from the memory, provided the LLI is set with HPDMA_CxLLR.UDA = 1.

Note: A destination address must be aligned with the programmed data width of a destination burst (DA versus HPDMA_CxTR1.DDW_LOG2). Else, a user setting error is reported and no transfer is issued.

18.8.18 HPDMA channel x transfer register 3 (HPDMA_CxTR3)

Address offset: \( 0x0A4 + 0x80 * x \) ( \( x = 12 \) to \( 15 \) )

Reset value: \( 0x0000\ 0000 \)

This register is secure or nonsecure depending on the secure state of channel x (HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of channel x (HPDMA_PRIVCFGR.PRIVx).

This register is CID-filtered depending on the CID configuration of the channel x (HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, a write access to this register is granted to the debug domain CID, regardless of any CID filtering.

This register controls the transfer of a channel x.

This register must be written when HPDMA_CxCR.EN = 0.

This register is read-only when HPDMA_CxCR.EN = 1.

This register must be written when the channel is completed (then the hardware has deasserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block, 2D/repeated block, LLI, or full linked-list.

In linked-list mode, during the link transfer, this register is automatically updated by the HPDMA from the memory if HPDMA_CxLLR.UT3 = 1.

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:16 DAO[12:0] : Destination address offset increment

The destination address, pointed by HPDMA_CxDAR, is incremented or decremented (depending on HPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (HPDMA_CxTR1.DINC = 1).

Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO versus HPDMA_CxTR1.DDW_LOG2). Else, a user setting error is reported and no transfer is issued.

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:0 SAO[12:0] : Source address offset increment

The source address, pointed by HPDMA_CxSAR, is incremented or decremented (depending on HPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (HPDMA_CxTR1.SINC = 1).

Note: A source address offset must be aligned with the programmed data width of a source burst (SAO versus HPDMA_CxTR1.SDW_LOG2). Else a user setting error is reported and none transfer is issued.

When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional HPDMA_CxTR3.SAO[12:0] is not applied.

18.8.19 HPDMA channel x block register 2 (HPDMA_CxBR2)

Address offset: 0x0A8 + 0x80 * x (x = 12 to 15)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of channel x (HPDMA_PRIVCFGR.PRIVx).

This register is CID-filtered depending on the CID configuration of the channel x (HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, a write access to this register is granted to the debug domain CID, regardless of any CID filtering.

This register controls the transfer of a channel x at a 2D/repeated block level.

This register must be written when HPDMA_CxCR.EN = 0.

This register is read-only when HPDMA_CxCR.EN = 1.

This register must be written when the channel is completed (then the hardware has deasserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block, 2D/repeated block, LLI, or full linked-list.

In linked-list mode, during the link transfer, this register is automatically updated by the HPDMA from the memory if HPDMA_CxLLR.UB2 = 1.

Bits 31:16 BRDAO[15:0] : Block repeated destination address offset

For a channel with 2D addressing capability, this bitfield is used to update (by addition or subtraction depending on HPDMA_CxBR1.BRDDEC) the current destination address (HPDMA_CxDAR) at the end of a block transfer.

Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO versus HPDMA_CxTR1.DDW_LOG2). Else a user setting error is reported and no transfer is issued.

BRDAO[15:0] must be set to 0 in peripheral flow-control mode (if HPDMA_CxTR2.PFREQ = 1).

Bits 15:0 BRSAO[15:0] : Block repeated source address offset

For a channel with 2D addressing capability, this bitfield is used to update (by addition or subtraction depending on HPDMA_CxBR1.BRSDEC) the current source address (HPDMA_CxSAR) at the end of a block transfer.

Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO versus HPDMA_CxTR1.SDW_LOG2). Else a user setting error is reported and no transfer is issued.

BRSAO[15:0] must be set to 0 in peripheral flow-control mode (if HPDMA_CxTR2.PFREQ = 1).

18.8.20 HPDMA channel x linked-list address register (HPDMA_CxLLR)

Address offset: 0x0CC + 0x80 * x (x = 0 to 11)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of channel x (HPDMA_PRIVCFGR.PRIVx).

This register is CID-filtered depending on the CID configuration of the channel x (HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, a write access to this register is granted to the debug domain CID, regardless of any CID filtering.

This register configures the data structure of the next LLI in the memory and its address pointer. A channel transfer is completed when this register is null.

This register must be written when HPDMA_CxCR.EN = 0.

This register is read-only when HPDMA_CxCR.EN = 1.

This register must be written when the channel is completed (then the hardware has deactivated HPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block, 2D/repeated block, LLI, or full linked-list.

In linked-list mode, during the link transfer, this register is automatically updated by the HPDMA from the memory if HPDMA_CxLLR.ULL = 1.

This bit controls the update of HPDMA_CxTR1 from the memory during the link transfer.

0: No HPDMA_CxTR1 update

1: HPDMA_CxTR1 update

This bit controls the update of HPDMA_CxTR2 from the memory during the link transfer.

0: No HPDMA_CxTR2 update

1: HPDMA_CxTR2 update

This bit controls the update of HPDMA_CxBR1 from the memory during the link transfer.

If UB1 = 0 and if HPDMA_CxLLR ≠ 0, the linked-list is not completed.

HPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer.

0: No HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

1: HPDMA_CxBR1 update

This bit controls the update of HPDMA_CxSAR from the memory during the link transfer.

0: No HPDMA_CxSAR update

1: HPDMA_CxSAR update

This bit is used to control the update of HPDMA_CxDAR from the memory during the link transfer.

0: No HPDMA_CxDAR update

1: HPDMA_CxDAR update

Bits 26:17 Reserved, must be kept at reset value.

This bit is used to control the update of HPDMA_CxLLR from the memory during the link transfer.

0: No HPDMA_CxLLR update

1: HPDMA_CxLLR update

If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:2] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list HPDMA register file.

Else, this bitfield is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list HPDMA internal register file (HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR, and HPDMA_CxLLR).

Caution: the user must program this pointer not to exceed the 64-Kbyte addressable space defined by the link base address register HPDMA_CxLBAR. The complete linked-list data structure must be included in the 64-Kbyte addressable space.

Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.

Bits 1:0 Reserved, must be kept at reset value.

18.8.21 HPDMA channel x alternate linked-list address register (HPDMA_CxLLR)

Address offset: 0x0CC + 0x80 * x (x = 12 to 15)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of channel x (HPDMA_PRIVCFGR.PRIVx).

This register is CID-filtered depending on the CID configuration of the channel x (HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, a write access to this register is granted to the debug domain CID, regardless of any CID filtering.

This register configures the data structure of the next LLI in the memory and its address pointer. A channel transfer is completed when this register is null.

This register must be written when HPDMA_CxCR.EN = 0.

This register is read-only when HPDMA_CxCR.EN = 1.

This register must be written when the channel is completed (then the hardware has deasserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block, 2D/repeated block, LLI, or full linked-list.

In linked-list mode, during the link transfer, this register is automatically updated by the HPDMA from the memory if HPDMA_CxLLR.ULL = 1.

Bit 31 UT1: Update HPDMA_CxTR1 from memory

This bit controls the update of HPDMA_CxTR1 from the memory during the link transfer.

0: No HPDMA_CxTR1 update

1: HPDMA_CxTR1 update

Bit 30 UT2: Update HPDMA_CxTR2 from memory

This bit controls the update of HPDMA_CxTR2 from the memory during the link transfer.

0: No HPDMA_CxTR2 update

1: HPDMA_CxTR2 update

Bit 29 UB1: Update HPDMA_CxBR1 from memory

This bit controls the update of HPDMA_CxBR1 from the memory during the link transfer.

If UB1 = 0 and if HPDMA_CxLLR ≠ 0, the linked-list is not completed.

HPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer.

0: No HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

1: HPDMA_CxBR1 update

Bit 28 USA : Update HPDMA_CxSAR from memory

This bit controls the update of HPDMA_CxSAR from the memory during the link transfer.

0: No HPDMA_CxSAR update

1: HPDMA_CxSAR update

Bit 27 UDA : Update HPDMA_CxDAR register from memory

This bit is used to control the update of HPDMA_CxDAR from the memory during the link transfer.

0: No HPDMA_CxDAR update

1: HPDMA_CxDAR update

Bit 26 UT3 : Update HPDMA_CxTR3 from memory

This bit controls the update of HPDMA_CxTR3 from the memory during the link transfer.

0: No HPDMA_CxTR3 update

1: HPDMA_CxTR3 update

Bit 25 UB2 : Update HPDMA_CxBR2 from memory

This bit controls the update of HPDMA_CxBR2 from the memory during the link transfer.

0: No HPDMA_CxBR2 update

1: HPDMA_CxBR2 update

Bits 24:17 Reserved, must be kept at reset value.

Bit 16 ULL : Update HPDMA_CxLLR register from memory

This bit is used to control the update of HPDMA_CxLLR from the memory during the link transfer.

0: No HPDMA_CxLLR update

1: HPDMA_CxLLR update

Bits 15:2 LA[15:2] : Pointer (16-bit low-significant address) to the next linked-list data structure

If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:2] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list HPDMA register file.

Else, this bitfield is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list HPDMA internal register file (HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR and HPDMA_CxLLR).

Caution: the user must program this pointer not to exceed the 64-Kbyte addressable space defined by the link base address register HPDMA_CxLBAR. The complete linked-list data structure must be included in the 64-Kbyte addressable space.

Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.

Bits 1:0 Reserved, must be kept at reset value.

18.8.22 HPDMA register map

Table 95. HPDMA register map and reset values