17. Peripherals interconnect matrix
17.1 Introduction
Several peripherals have direct connections between them. This allows autonomous communication and or synchronization between peripherals, saving CPU resources, thus power supply consumption. In addition, these hardware connections remove software latency, and improve the predictability of the system design.
Depending on peripherals, these interconnections can operate in various power modes: Run, Standby, Sleep, and Stop modes.
17.2 Connection summary
The table below summarizes which master can access which memory-mapped resource.
Table 83. Connectivity matrix
| Resource | GFXMMU | STM | AHBSRAM1/2 | BKPSRAM | FMC | XSPI1/2/3 | FLEXRAM | AXISRAM1/2 | AXISRAM3/4/5/6 | VENCRAM/ AXISRAM8 | BootROM | CACHEAXI/ AXISRAM7 | ITCM | DTCM | AHBx/APBx |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CPU M-AXI | X | X | X | X | X | X | X | X | X | X | X | X | X (1) | X (1) | X |
| CPU P-AHB | - | - | - | - | - | - | - | - | - | - | - | - | - | - | X (2) |
| AXI_AP | X | X | X | X | X | X | X | X | X | X | - | X | - | - | X |
| TRACE | - | - | - | - | X | X | X | X | - | X | - | - | - | - | - |
| NPU | - | - | - | - | X | X | X | X | X | - | - | X | - | X | - |
| GPU_M0/1 | X | - | - | - | X | X | X | X | X | X | - | X | - | - | - |
| GPU_CL | - | - | - | - | X | X | X | X | X | X | - | X | - | - | - |
| ETH1 | - | - | - | - | X | X | X | X | X | X | - | X | - | - | - |
| HPDMA1 AXI | - | - | X | X | X | X | X | X | X | X | - | X | X | X | X |
| HPDMA1 AHB | - | - | X | X | X | X | X | X | X | X | - | X | - | - | X |
| GPDMA1 | - | - | X | X | X | X | X | X | X | X | - | X | - | - | X |
| SDMMC1/2 | - | - | - | - | X | X | X | X | X | X | - | X | - | - | - |
| OTG1/2 | - | - | - | - | X | X | X | X | X | X | - | X | - | - | - |
| DCMIPP | - | - | - | - | X | X | X | X | X | X | - | X | - | - | - |
| DMA2D | X | - | - | - | X | X | X | X | X | X | - | X | - | - | - |
| LTDC | X | - | - | - | X | X | X | X | X | X | - | X | - | - | - |
| VENC | - | - | - | - | X | X | X | X | X | - | - | X | - | - | - |
| GFXMMU | - | - | - | - | X | X | X | X | X | X | - | X | - | - | - |
1. The CPU accesses internally to its DTCM and ITCM. The DAP uses the CPU internal to reach TCMs.
2. By default, the CPU uses P-AHB master port to reach the AHBx/APBx target.