16. System configuration controller (SYSCFG)

STM32N6x5/x7xx devices feature a set of configuration registers. The SYSCFG manages:

• • Cortex-M55 internal settings (such as TCM, CACHE, or vectors)
• • interconnect, security, and memory settings
• • compensation cells

16.0.1 I/O compensation cell

The I/O compensation cell generates an 8-bit value (4 bits for N-MOS and 4 bits for P-MOS) for the I/O buffer that depends upon PVT operating conditions (process, voltage, temperature).

These bits are used to control the current slew-rate and output impedance in the I/O buffer. Five compensation cells are embedded: one for I/Os supplied by \( V_{DD} \) , and four for I/Os supplied by \( V_{DDIO2} \) , \( V_{DDIO3} \) , \( V_{DDIO4} \) , and \( V_{DDIO5} \) .

By default, the compensation cells are disabled, and a fixed code is applied to all I/Os.

When enabled, the compensation cell tracks the PVT, and the 4-bit APSRC and ANSRC values are available in SYSCFG_xCCSR (with \( x = V_{DD} \) , \( V_{DDIO2} \) , \( V_{DDIO3} \) , \( V_{DDIO4} \) , or \( V_{DDIO5} \) ) once the corresponding READY is set in SYSCFG_xCCSR.

If CS is cleared in SYSCFG_xCCR, and READY is set, I/Os receive the APSRC and ANSRC values that result from the compensation cell.

To optimize the trimming, these values can be adjusted using RAPSRC and RANSRC in SYSCFG_xCCR (see Figure 71 ).

To reduce the power consumption, it is recommended to copy the values from SYSCFG_xCCSR to SYSCFG_xCCR. When the result is ready, set CS and disable the compensation cell.

Figure 71. I/O compensation cell control overview

    graph TD
        subgraph BSEC
            OTP[OTP fuses]
            COMPCELL[COMPCELL 3:0]
        end
        subgraph SYSCFG_REG [SYSCFG_xCCCR / SYSCFG_xCCSR registers]
            APSRC[APSRC 3:0 / ANSRC 3:0]
            RAPSRC[RAPSRC 3:0 / RANSRC 3:0]
            READY_REG[READY]
            CS[CS]
            EN[EN]
        end
        subgraph IO_CELL [I/O compensation cell]
            COMP_MEAS[Compensation measurement]
            MUX{MUX}
            LEVEL[Level shifter]
        end
        subgraph PADRING [Padring section X]
            IO1[I/O]
            IO2[I/O]
            IO3[I/O]
            IO4[I/O]
            IO_VERT[I/O]
        end

        OTP --> COMPCELL
        COMPCELL -- RESTRIM 4 --> COMP_MEAS
        COMP_MEAS -- AxSRC 10 --> MUX
        APSRC -- 4+4 --> MUX
        RAPSRC -- 4+4 --> MUX
        MUX -- RAxSRC 4+4 --> LEVEL
        LEVEL -- 4+4 --> IO1
        IO1 --- IO2 --- IO3 --- IO4
        IO4 --- IO_VERT

        READY_REG --> COMP_MEAS
        EN --> COMP_MEAS
        CS --> MUX
        COMP_MEAS -- READY --> READY_REG
    

16.1 SYSCFG registers

16.1.1 SYSCFG boot pin control register (SYSCFG_BOOTCR)

Address offset: 0x000

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 BOOT1_PD : BOOT1 pin pull-down disable

This is used to save power when BOOT1 pin is connected to V _DD .

0: Pull-down enabled. The BOOT1 pin can be left open and takes a value of 0 if open.

1: Pull-down disabled. The BOOT1 pin must not be left open.

Bit 0 BOOT0_PD : BOOT0 pin pull-down disable

This is used to save power when BOOT0 pin is connected to V _DD .

0: Pull-down enabled. The BOOT0 pin can be left open and takes a value of 0 if open.

1: Pull-down disabled. The BOOT0 pin must not be left open.

16.1.2 SYSCFG Cortex-M55 control register (SYSCFG_CM55CR)

Address offset: 0x004

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 LOCKDCAIC : Disable access to the instruction cache direct cache access registers DCAICLR and DCAICRR.

Bit 20 LOCKSAU : Prevent changes to secure SAU memory regions already programmed.

Bit 19 LOCKNSMPU : Prevent changes to nonsecure MPU memory regions already programmed.

Bit 18 LOCKSMPU : Prevent changes to programmed secure MPU memory regions.

Bit 17 LOCKNSVTOR : Prevent changes to the nonsecure vector table base address.

Bit 16 LOCKSVTAIRCR : Prevent changes to:

• - the secure vector table base address
• - handling of secure interrupt priority
• - BusFault, HardFault, and NMI security target settings in the processor

Bits 15:6 Reserved, must be kept at reset value.

Bits 5:0 FPU_IT_EN[5:0] : Enable FPU exception

• bit 5: Input abnormal interrupt enable
• bit 4: Inexact interrupt enable
• bit 3: Underflow operation interrupt enable
• bit 2: Overflow interrupt enable
• bit 1: Divide-by-zero interrupt enable
• bit 0: Invalid operation interrupt enable

16.1.3 SYSCFG Cortex-M55 TCM control register (SYSCFG_CM55TCMCR)

Address offset: 0x008

Reset value: 0x0000 0087

Reset on pwr_vsw_rstn.

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 DTCMWSDISABLE : Disable wait-state applied by default on extended DTCM memory.

Bit 23 ITCMWSDISABLE : Disable wait-state applied by default on extended ITCM memory.

Bits 22:19 Reserved, must be kept at reset value.

Bit 18 LOCKDTGU : Disable writes to registers associated with the DTCM interface security gating.

Bit 17 LOCKITGU : Disable writes to registers associated with the ITCM interface security gating.

Bit 16 LOCKTCM : Disable writes to registers associated with the TCM region

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:4 CFGDT CMSZ[3:0] : Select DTCM memory size

0x8: 128 Kbytes (default value)

0x9: 256 Kbytes

Others: Reserved

Bits 3:0 CFGIT CMSZ[3:0] : Select ITCM memory size

0x7: 64 Kbytes (default value)

0x8: 128 Kbytes

0x9: 256 Kbytes

Others: Reserved

Note: CFGDT CMSZ and CFGIT CMSZ must be written in the same data access, because they are write-once bitfields locked together. Writing only one of them blocks write-access to the other up to the next power-on reset.

16.1.4 SYSCFG Cortex-M55 memory RW margin register (SYSCFG_CM55RWMCR)

Address offset: 0x00C

Reset value: 0x0000 1020

Reset by system reset.

Bits 31:14 Reserved, must be kept at reset value.

1. Bit 13 BC2_CACHE : Biasing level adjust input recommended for Vnom + 10%
   Its setting gives a higher value of rise on V _SS -core voltage to give enough head room for retention.
2. Bit 12 BC1_CACHE : Biasing level adjust input recommended for Vnom.
   Its setting gives a smaller value of rise on V _SS -core voltage to give enough head room for retention.
3. Bits 11:8 RM_CACHE[3:0] : External read/write (RW) margin inputs for caches memories
4. Bit 7 RME_CACHE : RW margin enable input for caches memories
   0: Default RW margin settings
   1: Use external pin RW margin setting
5. Bit 6 BC2_TCM : Biasing level adjust input recommended for Vnom + 10%
   Its setting gives a higher value of rise on V _SS -core voltage to give enough head room for retention.
6. Bit 5 BC1_TCM : Biasing level adjust input recommended for Vnom
   Its setting gives a smaller value of rise on V _SS -core voltage to give enough head room for retention.
7. Bits 4:1 RM_TCM[3:0] : External RW margin inputs for TCM memories
8. Bit 0 RME_TCM : RW margin enable input for TCM memories
   0: Default RW margin settings
   1: Use external pin RW margin setting

16.1.5 SYSCFG Cortex-M55 SVTOR control register (SYSCFG_INITSVTORCR)

Address offset: 0x010

Reset value: 0x1800 0000

Reset by system reset.

Bits 31:7 SVTOR_ADDR[24:0] : Secure vector table base address

Bits 6:0 Reserved, must be kept at reset value.

16.1.6 SYSCFG Cortex-M55 NSVTOR control register (SYSCFG_INITNSVTORCR)

Address offset: 0x014

Reset value: 0x0800 0000

Reset by system reset.

Bits 31:7 NSVTOR_ADDR[24:0] : Nonsecure vector table base address

Bits 6:0 Reserved, must be kept at reset value.

16.1.7 SYSCFG Cortex-M55 reset type control register (SYSCFG_CM55RSTCR)

Address offset: 0x018

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 LOCKUP_NMI_EN : Select action to perform on a lockup state on the core

0: Lockup state must be recovered from NVIC interrupt (default value)

1: Lockup generates a NMI on the core.

Bit 1 LOCKUP_RST_EN : Select action to perform on a lockup state on the core

0: Lockup state must be recovered from interrupt (default value)

1: Lockup requests a warm reset to the RCC.

Bit 0 CORE_RESET_TYPE : Select reset to apply on core upon SYSRESETREQ

0: Warm reset (default value)

1: Power-on reset

16.1.8 SYSCFG Cortex-M55 P-AHB write posting control register (SYSCFG_CM55PAHBWPR)

Address offset: 0x01C

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 PAHB_ERROR_ACK : Error capture in write posting buffer

• 0: Error capture
• 1: Clean error

16.1.9 SYSCFG VENCRAM control register (SYSCFG_VENCRAMCR)

Address offset: 0x020

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 VENCRAM_EN : VENCRAM allocation VENC if active, or to system (if VENC inactive)

• 0: VENCRAM reserved for the VENC
• 1: VENCRAM available for the system (VENC inactive)

16.1.10 SYSCFG potential tamper reset register (SYSCFG_POTTAMPRSTCR)

Address offset: 0x024

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 POTTAMPERSETMASK :

This bit can be set by software to mask PKA, SAES, CRYP, and HASH reset, in case of potential tamper.

0: PKA, SAES, CRYP, and HASH reset in case of potential tamper

1: PKA, SAES, CRYP, and HASH not reset in case of potential tamper

16.1.11 SYSCFG NPUNIC QoS control register (SYSCFG_NPUNICQOSCR)

Address offset: 0x028

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:20 CPUSS_AWQOS[3:0] : NPUNIC write QoS information for master port from CPUSS

Bits 19:16 CPUSS_ARQOS[3:0] : NPUNIC read QoS information for master port from CPUSS

Bits 15:12 NPU2_AWQOS[3:0] : NPUNIC write QoS information for NPU2 master port

Bits 11:8 NPU2_ARQOS[3:0] : NPUNIC read QoS information for NPU2 master port

Bits 7:4 NPU1_AWQOS[3:0] : NPUNIC write QoS information for NPU1 master port

Bits 3:0 NPU1_ARQOS[3:0] : NPUNIC read QoS information for NPU1 master port

16.1.12 SYSCFG AHB-AXI bridge early write response control register (SYSCFG_ICNEWRCR)

Address offset: 0x034

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 USB2_EARLY_WR_RSP_ENABLE:

0: Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction.

1: Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response.

Bit 2 USB1_EARLY_WR_RSP_ENABLE:

0: Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction.

1: Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response.

Bit 1 SDMMC2_EARLY_WR_RSP_ENABLE:

0: Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction.

1: Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response.

Bit 0 SDMMC1_EARLY_WR_RSP_ENABLE:

0: Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction.

1: Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response.

16.1.13 SYSCFG ICN clock gating control register (SYSCFG_ICNCGCR)

Address offset: 0x038

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 CPU_NOC_CG_DISABLE: CPU_NOC clock gating disable

0: CPU_NOC clock gating enabled (default value)

1: CPU_NOC clock gating disabled

Bit 1 CPU_NIC_CG_DISABLE: CPU_NIC clock gating disable

0: CPU_NIC clock gating enabled (default value)

1: CPU_NIC clock gating disabled

Bit 0 NPU_NOC_CG_DISABLE: NPU_NOC clock gating disable

0: NPU_NOC clock gating enabled (default value)

1: NPU_NOC clock gating disabled

16.1.14 SYSCFG V _DDIO4 compensation cell control register (SYSCFG_VDDIO4CCCR)

Address offset: 0x044

Reset value: 0x0000 0078

Reset by system reset.

Bits 31:10 Reserved, must be kept at reset value.

Note: CS = 0 is not taken into account until READY = 1. Whenever CS, RANSRC[3:0], and RAPSRC[3:0] are used for I/O compensation, the compensation cell must be not enabled (EN = 0, which is the case after a reset).

Note: The HSI oscillator must be enabled and ready (controlled in RCC) before EN can be set to 1. The HSI oscillator can be disabled only if EN is set to 0.

16.1.15 SYSCFG V _DDIO4 compensation cell status register (SYSCFG_VDDIO4CCSR)

Address offset: 0x048

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 READY : Provides the compensation cell status of I/Os supplied by \( V_{DDIO4} \)

0: \( V_{DDIO4} \) I/O compensation cell not ready

1: \( V_{DDIO4} \) I/O compensation cell ready

Bits 7:4 APSRC[3:0] : This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors.

This code is applied to the I/O compensation cell when CS = 0 in SYSCFG_VDDIO4CCCR, and READY = 1 in this register.

Bits 3:0 ANSRC[3:0] : This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors.

This code is applied to the I/O compensation cell when CS = 0 in SYSCFG_VDDIO4CCCR, and READY = 1 in this register.

16.1.16 SYSCFG \( V_{DDIO5} \) compensation cell control register (SYSCFG_VDDIO5CCCR)

Address offset: 0x04C

Reset value: 0x0000 0078

Reset by system reset.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 CS : Selects the code to be applied for the compensation cell of I/Os supplied by \( V_{DDIO5} \) .

0: \( V_{DDIO5} \) I/O code from the cell (available in the SYSCFG_VDDIO5CCSR)

1: \( V_{DDIO5} \) I/O code from RANSRC[3:0] and RAPSRC[3:0] in this register

Note: CS = 0 is not taken into account until READY = 1. Whenever CS, RANSRC[3:0], and RAPSRC[3:0] are used for I/O compensation, the compensation cell must be not enabled (EN = 0, which is the case after a reset).

Bit 8 EN : Enables the compensation cell of I/Os supplied by \( V_{DDIO5} \) .

0: \( V_{DDIO5} \) I/O compensation cell disabled

1: \( V_{DDIO5} \) I/O compensation cell enabled

Note: The HSI oscillator must be enabled and ready (controlled in RCC) before EN can be set to 1. The HSI oscillator can be disabled only if EN is set to 0.

Bits 7:4 RAPSRC[3:0] : These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1.

Bits 3:0 RANSRC[3:0] : These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when CS = 1.

16.1.17 SYSCFG V _DDIO5 compensation cell status register (SYSCFG_VDDIO5CCSR)

Address offset: 0x050

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 READY : Provides the compensation cell status of I/Os supplied by V _DDIO5

0: V _DDIO5 I/O compensation cell not ready

1: V _DDIO5 I/O compensation cell ready

Bits 7:4 APSRC[3:0] : This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors.

This code is applied to the I/O compensation cell when CS = 0 in SYSCFG_VDDIO5CCCR, and READY = 1 in this register.

Bits 3:0 ANSRC[3:0] : This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors.

This code is applied to the I/O compensation cell when CS = 0 in SYSCFG_VDDIO5CCCR, and READY = 1 in this register.

16.1.18 SYSCFG V _DDIO2 compensation cell control register (SYSCFG_VDDIO2CCCR)

Address offset: 0x054

Reset value: 0x0000 0078

Reset by system reset.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 CS : Selects the code to apply for the compensation cell of I/Os supplied by VDDIO2.

0: V _{D DIO2} I/O code from the cell (available in the SYSCFG_VDDIO2CCSR)

1: V _{D DIO2} I/O code from RANSRC[3:0] and RAPSRC[3:0] in this register

Note: CS = 0 is not taken into account until READY = 1. Whenever CS, RANSRC[3:0], and RAPSRC[3:0] are used for I/O compensation, the compensation cell must be not enabled (EN = 0, which is the case after a reset).

Bit 8 EN : Enables the compensation cell of I/Os supplied by VDDIO2.

0: V _{D DIO2} I/O compensation cell disabled

1: V _{D DIO2} I/O compensation cell enabled

Note: The HSI oscillator must be enabled and ready (controlled in RCC) before EN can be set to 1. The HSI oscillator can be disabled only if EN is set to 0.

Bits 7:4 RAPSRC[3:0] : These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1.

Bits 3:0 RANSRC[3:0] : These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when CS = 1.

16.1.19 SYSCFG V _{D DIO2} compensation cell status register (SYSCFG_VDDIO2CCSR)

Address offset: 0x058

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 READY : Provides the compensation cell status of I/Os supplied by V _{D DIO2}

0: V _{D DIO2} I/O compensation cell not ready

1: V _{D DIO2} I/O compensation cell ready

Bits 7:4 APSRC[3:0] : This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors.

This code is applied to the I/O compensation cell when CS = 0 in SYSCFG_VDDIO2CCCR, and READY = 1 in this register.

Bits 3:0 ANSRC[3:0] : This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors.

This code is applied to the I/O compensation cell when CS = 0 in SYSCFG_VDDIO2CCCR, and READY = 1 in this register.

16.1.20 SYSCFG V _DDIO3 compensation cell control register (SYSCFG_VDDIO3CCCR)

Address offset: 0x05C

Reset value: 0x0000 0078

Reset by system reset.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 CS : Selects the code to be applied for the compensation cell of I/Os supplied by VDDIO3.

0: V _DDIO3 I/O code from the cell (available in the SYSCFG_VDDIO3CCSR)

1: V _DDIO3 I/O code from RANSRC[3:0] and RAPSRC[3:0] in this register

Note: CS = 0 is not taken into account until READY = 1. Whenever CS, RANSRC[3:0], and RAPSRC[3:0] are used for I/O compensation, the compensation cell must be not enabled (EN = 0, which is the case after a reset).

Bit 8 EN : Enables the compensation cell of I/Os supplied by VDDIOx.

0: V _DDIO3 I/O compensation cell disabled

1: V _DDIO3 I/O compensation cell enabled

Note: The HSI oscillator must be enabled and ready (controlled in RCC) before EN can be set to 1. The HSI oscillator can be disabled only if EN is set to 0.

Bits 7:4 RAPSRC[3:0] : These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1.

Bits 3:0 RANSRC[3:0] : These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when CS = 1.

16.1.21 SYSCFG V _DDIO3 compensation cell status register (SYSCFG_VDDIO3CCSR)

Address offset: 0x060

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 READY : Provides the compensation cell status of I/Os supplied by \( V_{DDIO3} \)

0: \( V_{DDIO3} \) I/O compensation cell not ready

1: \( V_{DDIO3} \) I/O compensation cell ready

Bits 7:4 APSRC[3:0] : This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors.

This code is applied to the I/O compensation cell when the CS = 0 in SYSCFG_VDDIO3CCCR, and READY = 1 in this register.

Bits 3:0 ANSRC[3:0] : This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors.

This code is applied to the I/O compensation cell when the CS = 0 in SYSCFG_VDDIO3CCCR, and READY = 1 in this register.

16.1.22 SYSCFG \( V_{DD} \) compensation cell control register (SYSCFG_VDDCCR)

Address offset: 0x064

Reset value: 0x0000 0078

Reset by system reset.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 CS : Selects the code to be applied for the compensation cell of I/Os supplied by \( V_{DD} \) .

0: \( V_{DD} \) I/O code from the cell (available in the SYSCFG_VDDCCSR)

1: \( V_{DD} \) I/O code from RANSRC[3:0] and RAPSRC[3:0]

Note: CS = 0 is not taken into account until READY = 1. Whenever CS, RANSRC[3:0] and RAPSRC[3:0] are used for I/O compensation when the compensation cell is not enabled (EN = 0, which is the case after a reset).

Bit 8 EN : Enables the compensation cell of I/Os supplied by \( V_{DD} \) .

0: \( V_{DD} \) I/O compensation cell disabled

1: \( V_{DD} \) I/O compensation cell enabled

Note: The HSI oscillator must be enabled and ready (controlled in RCC) before EN can be set to 1. The HSI oscillator can be disabled only if EN is set to 0.

Bits 7:4 RAPSRC[3:0] : These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1.

Bits 3:0 RANSRC[3:0] : These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when CS = 1.

16.1.23 SYSCFG V _DD compensation cell status register (SYSCFG_VDDCCSR)

Address offset: 0x068

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 READY : Provides the compensation cell status of I/Os supplied by V _DD

0: V _DD I/O compensation cell not ready

1: V _DD I/O compensation cell ready

Bits 7:4 APSRC[3:0] : This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors.

This code is applied to the I/O compensation cell when CS = 0 in SYSCFG_VDDCCCR, and READY = 1.

Bits 3:0 ANSRC[3:0] : This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors.

This code is applied to the I/O compensation cell when CS = 0 in SYSCFG_VDDCCCR, and READY = 1.

16.1.24 SYSCFG control timer break register (SYSCFG_CBR)

Address offset: 0x06C

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:11 Reserved, must be kept at reset value.

1. Bit 10 CM55TCML : Cortex-M55 TCM double ECC error lock
   This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Cortex-M55 TCM double ECC error signal connection to TIM1/8/15/16/17 break inputs.
   0: Cortex-M55 TCM double ECC error signal disconnected from TIM1/8/15/16/17 break inputs
   1: Cortex-M55 TCM double ECC error signal connected to TIM1/8/15/16/17 break inputs
2. Bit 9 CM55CACHEL : Cortex-M55 cache double ECC error lock
   This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Cortex-M55 cache double ECC error signal connection to TIM1/8/15/16/17 break inputs.
   0: Cortex-M55 cache double ECC error signal disconnected from TIM1/8/15/16/17 break inputs
   1: Cortex-M55 cache double ECC error signal connected to TIM1/8/15/16/17 break inputs
3. Bit 8 BKPRAML : Backup SRAM double ECC error lock
   This bit is set by software and cleared only by a system reset. It can be used to enable and lock the backup SRAM double ECC error signal connection to TIM1/8/15/16/17 break inputs.
   0: Backup SRAM double ECC error signal disconnected from TIM1/8/15/16/17 break inputs
   1: Backup SRAM double ECC error signal connected to TIM1/8/15/16/17 break inputs
4. Bits 7:3 Reserved, must be kept at reset value.
5. Bit 2 PVDEN : PVD lock enable
   This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/8/15/16/17 break input, as well as the PVDE in PWR_CR2.
   0: PVD interrupt disconnected from TIM1/8/15/16/17 break input. PVDE bits can be programmed by the application.
   1: PVD interrupt connected to TIM1/8/15/16/17 break input. PVDE and bits are read only.
6. Bit 1 Reserved, must be kept at reset value.
7. Bit 0 CM55L : CM55 lockup lock enable
   This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Cortex-M55 lockup (HardFault) output connection to TIM1/8/15/16/17 break inputs.
   0: Cortex-M55 lockup output disconnected from TIM1/8/15/16/17 break inputs
   1: Cortex-M55 lockup output disconnected from TIM1/8/15/16/17 break inputs

16.1.25 SYSCFG DMA CID secure control register (SYSCFG_SEC_AIDCR)

Address offset: 0x070

Reset value: 0x0000 0001

Reset by system reset.

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 DMACID_SEC[2:0] : Secure user accesses to the DMA present this programmed CID.

16.1.26 SYSCFG FMC retiming logic control register (SYSCFG_FMC_RETIMECR)

Address offset: 0x074

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 SDFBCLK_180 : Delay on feedback clock

0: No delay on the feedback clock

1: Half a cycle delay on the feedback clock

Bit 1 CFG_RETIME_TX : Retiming on Tx path

0: No retiming on Tx path

1: Retiming on Tx path

Bit 0 CFG_RETIME_RX : Retiming on Rx path

0: No retiming on Rx path

1: Retiming on Rx path

16.1.27 SYSCFG NPU RAM interleaving control register (SYSCFG_NPU_ICNCR)

Address offset: 0x078

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 INTERLEAVING_ACTIVE : Control interleaving on NPU RAMs

0: Interleaving disabled

1: Interleaving enabled

16.1.28 SYSCFG boot pin status register (SYSCFG_BOOTSR)

Address offset: 0x100

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 BOOT1 : BOOT1 pin value

0: BOOT1 pin connected to V _SS (or left open if BOOT1_PD = 0 in SYSCFG_BOOTCR)

1: BOOT1 pin connected to V _DD

Bit 0 BOOT0 : BOOT0 pin value

0: BOOT0 pin connected to V _SS (or left open if BOOT0_PD = 0)

1: BOOT0 pin connected to V _DD

16.1.29 SYSCFG AHB write posting address error register (SYSCFG_AHBWP_ERROR_SR)

Address offset: 0x104

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:0 PAHB_ERROR_ADDR[31:0] : Reports address of the first error in P-AHB write-posting buffer

16.1.30 SYSCFG SMPS observable signals through HDP selection configuration register (SYSCFG_SMPSHDPCTR)

Address offset: 0x400

Reset value: 0x0000 0000

Reset by system reset.

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 SMPSHDPSEL[3:0] :

0000: Standard run mode (no HDP)

1100: Analyze fsm mode analysis

1101: Analyze fsm mos analysis

1110: Analyze fsm rampe analysis

1111: Analyze fsm mode analysis

Others: Reserved

16.1.31 SYSCFG DMA CID nonsecure control register (SYSCFG_SECPRIV_AIDCR)

Address offset: 0x800

Reset value: 0x0000 0001

Reset by system reset.

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 DMACID_SECPRI[2:0] : Secure privilege accesses to the DMA present this programmed CID.

16.1.32 SYSCFG device ID register (SYSCFG_DEVICEID)

Address offset: 0x0FF0

Reset value: 0xXXXX 6XXX

Bits 31:16 REV_ID[15:0] : Silicon revision

0x1000: Revision A

0x2000: Revision B

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 DEV_ID[11:0] : Device identifier

0x486: STM32N6x5/x7xx

16.1.33 SYSCFG register map

Table 82. SYSCFG register map and reset values

Table 82. SYSCFG register map and reset values (continued)

Table 82. SYSCFG register map and reset values (continued)

Refer to Section 2.3 for the register boundary addresses.