14. Reset and clock control (RCC)

The RCC manages the clock and reset generation for the whole microcontroller.

The operating modes to which this section refers are defined in Section 13.6.1: Operating modes of the PWR.

14.1 RCC main features

• • AHB-Lite bus interface
• • RIF (resource isolation framework) aware
• • Reset part:
  • – Generation of local and system reset
  • – Bidirectional pin to reset the microcontroller and/or external devices
  • – WWDG and IWDG reset supported
  • – Power-on (POR) and brownout (BOR) resets initiated by the PWR
• • Clock generation:
  • – Generation and dispatching of clocks for the complete device
  • – Four separate PLLs using integer or fractional ratios
  • – Clock gating to reduce power dissipation
  • – Two external oscillators:
    • > High-speed external oscillator (HSE) supporting a wide range of crystals from 8 to 48 MHz (when the USBHSPHY is used, the HSE frequency must be 19.2, 20, or 24 MHz)
    • > Low-speed external oscillator (LSE) for a 32.768 kHz crystal
  • – Four internal oscillators:
    • > High-speed internal oscillator (HSI)
    • > Low-power internal oscillator (MSI)
    • > Low-speed internal oscillator (LSI)
    • > High-speed internal secure oscillator (HSIS)
  • – Buffered clock outputs for external devices
  • – Generation of two types of interrupt lines:
    • > Dedicated interrupt lines for clock failure management
    • > General interrupt line for other events (separated into secure and nonsecure)
  • – Clock generation handling in Stop and Standby modes

14.2 RCC power domains

RCC interfaces with four power domains, namely core ( \( V_{DDCORE} \) ), retention ( \( V_{DD} \) , \( V_{RET} \) ), backup ( \( V_{SW} \) , \( V_{BKP} \) ), and analog ( \( V_{DDA18ADC} \) ).

14.3 RCC block diagram

Figure 34. RCC block diagram

14.4 RCC pins and internal signals

Table 64. RCC input/output signals connected to package pins or balls

1. Bidirectional reset pin with embedded weak pull-up resistor.

The RCC exchanges signals with all components of the product. Table 65 shows only the most significant internal signals.

Table 65. RCC internal input/output signals (continued)

14.5 Functional description of RCC reset

The RCC handles the reset generation for the complete product, using events coming from different sources:

• assertion of the NRST pin from an external device
• a failure on the supply voltage applied to \( V_{DD} \) or \( V_{BAT} \)
• an exit from Standby mode
• a watchdog timeout
• a software command

The reset scope depends on the source that generates it.

14.5.1 Reset from the PWR

The PWR provides several reset signals to the RCC:

• power-on/off reset signal (pwr_por_rstn): asserted when the \( V_{DD} \) supply is lower than the \( V_{POR} \) threshold
• brownout reset signal (pwr_bor_rstn): asserted when the \( V_{DD} \) supply is lower than the \( V_{BOR} \) threshold
• core reset signal (pwr_okin_vcore_rstn): asserted when the \( V_{DDCORE} \) supply is not valid or available

Note: \( V_{DDCORE} \) is switched off when the product is in Standby mode. When the system exits Standby mode, pwr_okin_vcore_rstn is asserted while \( V_{DDCORE} \) from the regulator is not valid. pwr_okin_vcore_rstn is also asserted when the \( V_{DD} \) supply is not valid.

• \( V_{SW} \) domain reset signal (pwr_vsw_rstn): asserted when the \( V_{SW} \) supply is lower than the expected threshold

Refer to Table 66 for more details.

Figure 35. Simplified reset circuit

MSV70467V2

14.5.2 System and application resets (sys_rst, nreset_rstn)

A system reset ( sys_rst ) resets most of the registers to their default values, unless otherwise specified in the register description (summary in Table 66 ).

A system reset can be generated from one of the following sources:

• • an assertion of the NRST pin (external reset)

• • a reset from the power-on/off reset block (pwr_por_rstn)
• • a reset from the brownout reset block (pwr_bor_rstn), see Section 13.5.2: Brownout reset (BOR) for a detailed description of the BOR function
• • a reset from the independent watchdogs (iwdg_out_rst)
• • an exit from Standby mode (rcc_vcore_rst)
• • a reset from the window watchdogs depending on WWDG configuration (wwdg_out_rst)
• • a software reset (SFTRESET) signal, connected to SYSRESETREQ from the Cortex-M55 core
• • a lockup reset (LCKRESET) signal, connected to LOCKUP from the Cortex-M55 core
• • a reset from the low-power mode security reset, depending on the option byte configuration (lpwr_rst)

The application reset (nreset_rstn) is similar to the system reset, but it is not asserted when the system exits Standby mode.

Note: The sys_rst is actually a combination the native internal reset signal (int_sys_rstn) and the debug Standby reset signal (dbg_stdby_rstn). Some registers are reset by int_sys_rstn only. See Section 14.6.13 for more details about dbg_stdby_rstn.

The SYSRESETREQ bit in Cortex-M55 must be set to force a software reset on the device. Refer to the Cortex-M55 with FPU Technical Reference Manual for more details. There is also a SYSCFG register, which affects SYSRESETREQ.

14.5.3 NRST reset

The NRST is active low. A pulse stretcher guarantees a minimum reset pulse duration of 20 µs (see the datasheet for details). The NRST assertion can also be extended by adding the C _R capacitor.

It is not recommended to leave the NRST pin unconnected. When not used, connect this pin to ground via a 4.7 to 10 nF capacitor (C _R in Figure 35 ). As shown in Figure 35 , a filter is present to suppress spurious coming from the NRST pin.

14.5.4 Low-power mode security reset (lpwr_rst)

To prevent critical applications from mistakenly entering a low-power mode, two low-power mode security resets are available. When enabled through RST_STOP and RST_STDBY option bytes, a system reset (sys_rst) is generated if the following conditions are met:

• • The CPU mistakenly enters Stop mode.
  This type of reset is enabled by setting RST_STOP user option byte. If a Stop mode entry sequence is successfully executed, a system reset is generated.
• • The system mistakenly enters Standby mode.
  This type of reset is enabled by setting RST_STDBY user option byte. If a Standby mode entry sequence is successfully executed, a system reset is generated.

LPWRRSTF bit in RCC_RSR indicates that a low-power mode security reset occurred (see row 8 in Table 67 ).

The lpwr_rst input is activated when a low-power mode security reset is required. This signal is generated by the PWR.

See Section 5: OTP mapping (OTP) for additional information, and Table 54: Operating mode summary for the overview of existing power modes.

14.5.5 Backup domain reset

A backup domain reset (rcc_vsw_rst) is generated when one of the following occurs:

• • a software reset, triggered by setting VSWRST in RCC_BDCR: the BKPSRAM is not affected.
• • V _SW voltage outside the operating range: the BKPSRAM content is no longer valid.

The RCC_BDCR register and all bitfields in the backup domain (including RTC) return to their reset values: these include RTCEN, RTCLPEN, RTCPRE, RTCSEL, LSECSSRA, LSECSSD, LSECSSON, LSERDY, LSERDYF, LSEON, LSEDRV, LSEEXT, LSEBYP, LSEGON.

See Section 13.4.4: Backup domain and Section 3: System security for additional information.

14.5.6 CoreSight debug reset

CoreSight debug components can be reset in three different ways:

• • using the DAP by setting CDBGRSTREQ in DP_CTRLSTAT

This asserts the debug reset request signal (cdbgrstreq) connected to the RCC. The RCC then asserts the debug reset (rcc_dbg_rst), and a handshake signal cdbgrstack acknowledges the DAP request. The debug reset remains asserted while cdbgrstreq is asserted (see Figure 35 for details).

• • when the application sets DBGRST in RCC_MISCSTR

This asserts the rcc_dbg_rst reset, which is deasserted when DBGRST is cleared to 0.

• • when a V _DDCORE power-on reset occurs (rcc_vcore_rst)

This reset is asserted after a POR, or when the product exits Standby mode.

Refer to Section 14.5.6 for details.

14.5.7 Option-byte loading

As shown in Figure 37 , the option-byte loading (OBL via OTP_LD) sequence happens after a POR or a pin reset.

The system reset (sys_rst) is released only after the OBL has completed.

The BSEC manages an OTP array of fuse words, which hold the option-byte configuration for the device. This configuration must be set every time an app_rstn is asserted, and the system stays in reset until this configuration has been properly loaded (fuse_ok signal is received from the BSEC module).

The BSEC handles the following reset sources:

• • a main reset (bsec_rstn) asserted when an app_rstn is asserted
• • a scratch reset (bsec_srstn) asserted when a pwr_por_rstn is asserted
• • a hot reset (bsec_hrstn) asserted when fuse_ok is low

14.5.8 Reset of peripherals

The application can reset individually any peripheral, whenever requested. This can be done via registers named RCC_xxxxRSTR ( xxxx is the bus name on which the peripheral is connected).

To reset a peripheral, the corresponding reset bit must be set to 1 (peripheral clock not required), and then set back to 0 (peripheral clock must be enabled and running in advance). There is no need to enable a peripheral clock to reset a peripheral.

Caution: PKA, CRYP, SAES, and HASH may be reset directly in hardware upon a tamper event.

14.5.9 Reset pulse control (RPCTL)

The RPCTL allows the application to control the minimum activation time of the NRST pad. This feature is particularly helpful because some external devices may require a specific reset duration. In addition, the internal reset pulse, for example from IWDG, may be too short for external devices.

The RPCTL is located in the V _DD domain, and is reset only after a power-on reset.

The RPCTL is controlled by MRD[4:0] in RCC_RDCR .

If MRD is 0, then the RPCTL is bypassed. The minimum activation time in this case is given by the pulse stretcher embedded in the reset pad (typically 20 μs).

If MRD is non-0, then the rising edge of cmd_pad_rst causes NRST to be immediately driven low, for at least the duration set by MRD[4:0] . The duration of the reset is unchanged if the cmd_pad_rst signal is active for longer than the duration set by MRD[4:0] . The minimum activation time is between 1 and 31 ms.

The RPCTL uses the LSI clock to measure time. When the cmd_pad_rst goes high, the RPCTL requests the LSI clock to control the reset duration. If the LSI was not enabled by another function, it may take some microseconds before obtaining LSI ready (T _{LSI_SU} ).

Figure 36 shows two scenarios.

Figure 36. NRST reset pulse control

14.5.10 Reset coverage summary

Table 66 gives a detailed view of the coverage of the most important reset sources.

Note: When \( V_{DD} \) is not valid, \( V_{DDCORE} \) is not valid as well.

Table 66. Reset coverage summary ⁽¹⁾

1. 'X' means that the function is reset by the corresponding reset line. '-' means that the function is not reset by the corresponding reset line.

2. pwr_por_rstn is asserted when the voltage applied to \( V_{DD} \) is not valid. When pwr_por_rstn is asserted, the rcc_vcore_rst, NRST, sys_rst, and nreset_rstn are asserted as well.

1. 3. rcc_vcore_rst is asserted when the voltage applied to VDD is not valid, or when the system exits Standby mode (because \( V_{DDCORE} \) is switched off). When rcc_vcore_rst is asserted, sys_rst and pwr_dbg_rst are asserted as well.
2. 4. When nreset_rstn is asserted, sys_rst is asserted as well.

14.5.11 Reset source identification

The CPU can identify the reset source by checking reset flags in RCC_RSR or PWR_CSR3 registers.

The CPU can clear flags in RCC_RSR by setting RMVF bit in this register.

Table 67 shows how the status bits behave according to the situation that generated the reset. For example, when an IWDG timeout occurs (row 7), if the CPU reads RCC_RSR during the boot phase, both PINRSTF and IWDGRSTF bits are set, indicating that the IWDG also generated a pin reset.

Table 67. Reset source identification ⁽¹⁾

1. Grayed cells highlight the register bits that are set.

2. The SBF bit is located in PWR_CSR3 register.

14.5.12 Power-on and wake-up sequences

For detailed diagrams, refer to Section 13.4.1: System supply startup in the PWR.

The time interval between the event that exits the device from a low-power, and the moment where the CPU is able to execute code, depends on the system state and on its configuration. Figure 37 shows the most usual examples.

Power-on wake-up sequence

The sequence shown in Figure 37 gives the most significant phases of the power-on wake-up. It is the longest sequence since the circuit was not powered.

Note: This sequence remains unchanged whatever \( V_{BAT} \) is present or not.

Boot from pin reset (NRST)

When a pin reset occurs, \( V_{DD} \) is still present. As a result:

• the regulator settling time is faster since the reference voltage is already stable
• the HSI restart delay may be needed if the HSI was not enabled when the NRST occurred, otherwise this restart delay phase is skipped.

Boot from system standby

When waking up from system standby, the reference voltage is stable since \( V_{DD} \) has not been removed. As a result, the regulator settling time is fast. Since \( V_{DDCORE} \) was not present, the restart delay for the HSI and HSIS cannot be skipped.

sys_rst remains asserted until HSIS runs and the memory repair completes.

Restart from system stop

When restarting from system stop, \( V_{DD} \) is still present. As a result, the sequence is mainly composed of two steps:

1. The regulator settling time reaches \( V_{OS1} \) (default voltage).
2. HSI/MSI restart delay. This step can be skipped if HSISTOPEN = MSISTOPEN = 1 in RCC_STOPCR.

sys_rst remains asserted until HSIS runs.

Figure 37. Boot sequences versus system states

14.6 Functional description of RCC clocks

The RCC provides a wide choice of clock generators:

• HSI (high-speed internal oscillator) clock: ~ 8, 16, 32, or 64 MHz

• • HSE (high-speed external oscillator) clock: 8 to 48 MHz
• • LSE (low-speed external oscillator) clock: 32 kHz
• • LSI (low-speed internal oscillator) clock: ~ 32 kHz
• • MSI (low-power internal oscillator) clock: ~ 4 or 16 MHz

The RCC offers a high flexibility for the application to select the appropriate clock for the CPU and peripherals (in particular for peripherals that require a specific clock, such as SPI/I2S and SAI).

To optimize the power consumption, each clock source can be switched ON or OFF independently.

The RCC provides up to four PLLs; each of them can be configured in integer mode (with or without SSCG - spread spectrum clock generation), or fractional mode.

As shown in the Figure 38 , the RCC offers two clock outputs (MCO1 and MCO2), with flexibility on the clock selection and frequency adjustment.

The SCGU (system clock generation unit) contains several prescalers to configure the CPU and bus matrix clock frequencies.

The PKSU (peripheral kernel clock selection unit) provides several dynamic switches, which give a large choice of kernel clock distribution to peripherals.

The PKEU (peripheral kernel clock enable unit) performs the peripheral kernel clock gating. The SCEU (system clock enable unit) performs the clock gating for the bus interface, cores, and the bus matrix.

Figure 38. Top-level clock tree

MSV70469V5

14.6.1 Clock naming convention

The RCC provides clocks to the complete circuit. To avoid misunderstandings, the following terms are used in this document:

• • Peripheral clocks provided by the RCC to the peripherals

Two kinds of clock are available, namely bus interface and kernel clocks

A peripheral receives from the RCC a bus interface clock to access its registers, and thus control the peripheral operation. This clock is generally the AHB, APB, or AXI clock, depending on which bus the peripheral is connected to. Some peripherals need only a bus interface clock.

Some peripherals require also a dedicated clock (named kernel clock) to handle the interface function. As an example, SAI must generate specific and accurate master clock frequencies, which require dedicated kernel clock frequencies.

An advantage of decoupling the bus interface clock from the kernel clock is that the bus clock can be changed without reprogramming the peripheral.

• • CPU clock: derived from a dedicated system clock (sysa_ck), is asynchronous to the bus clocks.
• • Bus matrix clocks: provided to the different bridges (APB, AHB, AXI, or NoC), are derived from a system clock (sysb_ck).
• • NPU and NPU AXI clocks: the NPU clock is derived from a dedicated system clock, sysc_ck, also used for the AXI matrix close to the NPU.
• • AXISRAM1/2 clocks: derived from sysb_ck.
• • AXISRAM3/4/5/6 clocks: derived from sysd_ck.

14.6.2 Oscillator description

Table 68 shows the oscillator states versus system modes, when the oscillators are enabled via registers. Available means that the resource can be used if activated via registers.

Table 68. Oscillator states versus system modes

1. If STOPWUCK = 0.

2. If STOPWUCK = 1.

3. HSI can remain activated in Stop mode if HSISTOPEN = 1, or if a peripheral selecting HSI generates a kernel clock request. Caution: HSI must be off if the PWR is programmed to use SVOS low.

4. MSI can remain activated in Stop mode if MSISTOPEN = 1, or if the peripheral selecting MSI generates a kernel clock request. Caution: MSI must be off if the PWR is programmed to use SVOS low.

HSE oscillator

The HSE allows the application to provide a very accurate high-speed clock for the device. The HSE can generate an internal clock from two sources:

• • external clock source (analog or digital)
• • external crystal/ceramic resonator

Refer to the datasheet for the values of CL1, CL2, and R1.

Figure 39. HSE clock source

External clock source (HSE bypass)

In this mode, the oscillator is not used, and an external clock source must be provided to the OSC_IN pin. The external clock can be low swing (analog) or digital.

In order to allow the boot ROM to detect in which configuration the HSE is used, a resistor (R1) must be connected to GND or \( V_{DD} \) (see Figure 39 ).

The resistor must be connected to GND when the HSE uses an external digital clock, and to \( V_{DD} \) when the HSE is using an external analog clock. The resistor must be removed if a crystal or ceramic resonator is used.

The external clock signal can be digital or analog (square, sinus, or triangle). An analog clock signal with a reduced amplitude is supported thanks to an internal clock squarer.

The input signal must have a duty cycle close to 50% (refer to the datasheet for additional information).

This mode is selected when HSEBYP = 1 in RCC_HSECFGR and HSEON = 1 in RCC_CR. In case of an analog clock input (low swing) HSEEXT must be set to 0 in RCC_HSECFGR. For a digital clock input, HSEEXT must be set to 1.

Figure 40. HSE clock generation

External crystal/ceramic resonator

A crystal/resonator can be connected as shown in Figure 39 : the crystal/resonator and the load capacitors must be placed as close as possible to the oscillator pins in order to minimize the output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected crystal or ceramic resonator. Refer to the electrical characteristics section of the datasheet for more details.

The oscillator mode is enabled by setting HSEBYP = 0 and HSEON = 1.

HSE ready logic

The HSERDY flag indicates when a valid clock is available at HSE output (hse_ck). When the HSE is enabled (HSEON = 1), the HSERDY flag goes to 1 when 1024 valid cycles of HSE have been detected. The hse_ck clock is not released until HSERDY goes to 1.

An interrupt can be generated if enabled in RCC_CIER.

HSE controls

The HSE can be switched on and off through HSEON.

The HSE is automatically disabled by hardware when the system enters Stop or Standby mode (see Table 68 ).

The HSE clock can also be driven to MCO1 and MCO2 outputs, and used as clock source for other application components.

HSE programming sequence

In order to initialize the HSE, the application must follow this sequence:

1. 1. Make sure the HSE is not directly or indirectly used as system clock. If it is, switch to the HSI or MSI as clock source for system clock.
2. 2. Disable the HSE by writing 0 to HSEON.
3. 3. Check that the HSE is disabled by waiting HSERDY = 0.
4. 4. If the oscillator mode is needed, select the oscillator mode with HSEBYP = 0.
5. 5. If an external clock is connected to OSC_IN:
   • – Select the bypass mode by setting HSEBYP = 1.

1. • – If the input clock is a full-swing digital signal, set HSEEXT = 1.
   • – If the input clock is a low-swing signal, set HSEEXT = 0.
2. 1. Enable again the HSE by writing 1 to HSEON.
   2. Wait for HSERDY = 1, then the HSE is ready for use.

LSE oscillator

The LSE allows the application to provide a very accurate low-frequency clock for the device. The LSE can generate an internal clock from two possible sources:

• • external user clock
• • external crystal/ceramic resonator

External clock source (LSE bypass)

In this mode, the oscillator is not used, and an external clock source must be provided to the OSC32_IN pin. The OSC32_OUT pin must be left high-Z.

The external clock signal can have a frequency up to 32.768 kHz, and can be digital or analog (square, sinus, or triangle). An analog clock signal with a reduced amplitude is supported thanks to an internal clock squarer. The input signal must have a duty cycle close to 50%. Refer to the datasheet for additional information.

This mode is selected by setting LSEBYP = 1 in RCC_LSECFGR, and LSEON = 1 in RCC_CR. In case of an analog clock input (low swing), LSEEXT must be set to 0 in RCC_LSECFGR. For a digital clock input, LSEEXT must be set to 1.

Figure 41. LSE clock generation

External crystal/ceramic resonator source (LSE crystal)

The LSE clock is generated from a 32.768 kHz crystal or ceramic resonator. It provides a low-power highly accurate clock source to the RTC for clock/calendar, or other timing functions. A crystal/resonator can be connected as shown in Figure 39. The crystal/resonator and the load capacitors must be placed as close as possible to the oscillator pins to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected crystal or ceramic resonator. Refer to the electrical characteristics section of the datasheet for more details.

The oscillator mode is selected by setting LSEBYP bit to 0 and LSEON bit to 1.

The LSE offers a programmable driving capability (LSEDRV in RCC_LSECFGR) to modulate the amplifier driving capability. This driving capability is chosen according to the external crystal/ceramic component requirement to ensure a stable oscillation.

The driving capability must be set before enabling the LSE oscillator.

Warning: The driving capability must not be changed when the LSE is enabled. The LSE behavior is not guaranteed in that case.

LSE ready logic

The LSE offers an LSERDY flag, which indicates whether the LSE clock is available or not. When the LSE is enabled (LSEON = 1), LSERDY goes to 1 in RCC_SR when a certain number of valid LSE clock cycles has been detected. The lse_ck clock is not released until LSERDY goes to 1.

When LSEBYP = 0, the RCC waits 4096 clocks cycles before activating the LSERDY flag. When LSEBYP = 1, the RCC waits 16 clocks cycles.

An interrupt can be generated if enabled in RCC_CIER.

LSE controls

LSEBYP, LSEEXT, LSEDRV, and LSEON are write-protected by DBP in PWR_DBPCR. In order to modify the bits, DBP must be set 1.

The LSE oscillator is switched on and off using the LSEON bit.

The LSE remains enabled when the system enters Stop, Standby, or V _BAT mode (see Table 68 ).

The LSE clock can also be driven to MCOx outputs, and used as clock source for external components.

LSE programming sequence

To initialize the LSE, the application must follow the sequence hereafter:

1. 1. Set DBP = 1 in PWR_DBPCR in order to allow write access.
2. 2. Disable the LSE by writing to 0 to LSEON.
3. 3. Check that the LSE is disabled by waiting LSERDY = 0.
4. 4. If the oscillator mode is needed:
   • – Select the oscillator mode by setting LSEBYP = 0.
   • – Configure LSEDRV (if needed).
5. 5. If an external clock is connected to OSC32_IN:
   • – Select the bypass mode by setting LSEBYP = 1.
   • – If the input clock is a full-swing digital signal, set LSEEXT = 1.
   • – If the input clock is a low-swing signal, set LSEEXT = 0.
6. 6. enable again the LSE by writing 1 to LSEON.
7. 7. Wait for LSERDY = 1, then the LSE is ready for use.
8. 8. If no further changes are needed, set DBP = 0 in PWR_DBPCR to write-protect the settings.

If the RTC is used, the LSE bypass must not be configured in digital mode, but in low-swing analog mode (default value after reset).

HSI oscillator

The HSI block provides the default clock to the device. It is a high-speed internal RC oscillator that can be used directly as system clock, peripheral clock, or as PLL input. A predivider allows the application to select an HSI output frequency of 8, 16, 32, or 64 MHz. This predivider is controlled by the HSIDIV in RCC_HSICFGR.

The HSI advantages are the following:

• • low-cost clock source (no external crystals required)
• • faster startup time than HSE (a few microseconds)
• • reduced power consumption

The HSI frequency, even with frequency calibration, is less accurate than an external crystal oscillator or ceramic resonator.

HSI controls

The HSI can be switched on and off using HSION in RCC_CR. The HSIRDY flag in RCC_SR indicates if the HSI is stable or not. At startup, the HSI output clock is not released until HSIRDY is set to 1 by hardware.

The HSI clock can also be used as a backup source (auxiliary clock) if the HSE fails (see CSS on HSE ).

The HSI can be disabled or not when the system enters Stop mode (see Table 68 ).

The HSI clock can also be driven to MCOx outputs, and used as clock source for other application components.

Care must be taken when the HSI is used as kernel clock for communication peripherals. The application must take into account the following parameters:

• • the time interval between the moment where the peripheral generates a kernel clock request, and the moment where the clock is really available
• • the frequency accuracy

HSI calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process variations. That is why each device is factory calibrated by STMicroelectronics to achieve an ACC _HSI accuracy (refer to the product datasheet for more information).

After a power-on reset or pin reset, the factory calibration value is loaded in HSICAL[8:0] in RCC_HSICFGR.

If the application is subject to voltage or temperature variations, this may affect the RC oscillator frequency. The user application can trim the HSI frequency using HSITRIM[6:0] in RCC_HSICFGR.

Figure 42. HSI calibration flow

Note: The HSI clock divided by eight is also used for PAD compensation mechanism, and must be enabled if the PAD compensation mechanism is activated. Refer to Section 16: System configuration controller (SYSCFG) for additional details.

MSI oscillator

The MSI is a low-power RC oscillator that can be used directly as system clock, peripheral clock, or PLL input.

However, the following point must be considered: If the MSI clock is currently used as kernel clock for some peripherals, the application must ensure that the MSI frequency change does not disturb these peripherals.

The MSI advantages are the following:

• • low-cost clock source (no external crystals required)
• • faster startup time than HSE (a few microseconds)
• • very low-power consumption

The MSI provides a clock frequency of 4 MHz (default MSIFREQSEL) or 16 MHz, while the HSI is able to provide a clock up to 64 MHz.

The MSI frequency, even with frequency calibration, is less accurate than an external crystal oscillator or ceramic resonator.

MSI controls

The MSI can be switched on and off through the MSION in RCC_CR. The MSIRDY flag in RCC_SR indicates whether the MSI is stable or not. At startup, the MSI output clock is not released until MSIRDY is set by hardware.

The MSI can be disabled or not when the system enters Stop mode (see Table 68 ).

The MSI clock can also be driven to MCOx outputs, and used as clock source for other application components.

Even if the MSI settling time is faster than the HSI, care must be taken when the MSI is used as kernel clock for communication peripherals: the application must take into account the following parameters:

• • the interval between the moment when the peripheral generates a kernel clock request, and the moment when the clock is really available
• • the frequency precision

MSI calibration

RC oscillator frequencies can vary because of manufacturing process variations. Each device is factory calibrated by ST to achieve the specified ACC _MSI accuracy (refer to the product datasheet for more information).

After a power-on or pin reset, the factory calibration value for 4 MHz is loaded in MSICAL[7:0] in RCC_MSICFGR.

If MSIFREQSEL is set to 16 MHz in RCC_MSICFGR, a different calibration value is provided by the BSEC.

Voltage or temperature variations can affect the RC oscillator frequency. The user application can trim the MSI frequency using MSITRIM[4:0] in RCC_MSICFGR.

Figure 43. MSI calibration flow

HSIS oscillator

The HSIS is a 64 MHz RC oscillator to clock only the BSEC. It is always activated after pwr_por_rstn or app_rstn reset.

When the system goes into Stop or Standby mode, the HSIS clock is disabled by hardware. Refer to Section 14.6.7 for additional information.

HSIS calibration

RC oscillator frequencies can vary from one device to another, due to manufacturing process variations. To compensate for this, there is an HSISCAL[8:0] input on the oscillator.

The BSEC provides two calibration values (ambient and not ambient). The RCC selects between these two values using a select signal from the BSEC.

After a power-on reset, or pad reset, the factory calibration value is loaded in HSISCAL[8:0].

LSI oscillator

The LSI acts as a very low-power clock source that can be kept running when the system is in Stop or Standby mode for the IWDG and the auto-wake-up unit (AWU). The clock frequency is around 32 kHz. For more details, refer to the electrical characteristics section of the datasheet.

The LSI can be switched on and off using LSION. The LSIRDY flag indicates whether the LSI oscillator is stable or not. If an independent watchdog is started either by hardware or software, the LSI is forced on, and cannot be disabled.

The LSI remains enabled when the system enters Stop or Standby mode (see Table 68 ).

At LSI startup, the clock is not provided until the hardware sets LSIRDY. An interrupt can be generated if enabled in RCC_CIER.

The LSI clock can also be driven to MCOx outputs, and used as a clock source for other application components.

14.6.3 Clock security system (CSS)

The CSS can detect a failure of either (or both) LSE and HSE oscillators. There are signals that can be connected to the TAMP (rcc_lsecss_fail and rcc_hsecss_fail), and signals for the interrupt controller (rcc_lsecss_it, rcc_hsecss_it, and rcc_it).

CSS on HSE

The CSS can be enabled by software via HSECSSON. This bit can be enabled even when HSEON = 0.

The CSS on HSE is activated when the HSE is enabled and ready, and when the software sets HSECSSON = 1. The CSS on HSE does no longer work when the HSE is disabled. For example, this function does not work when the system is in Stop mode.

HSECSSON cannot be cleared directly by software. It is cleared by hardware when a system reset occurs, or when the system enters Standby mode (see Section 14.5.2 ).

On an HSE failure, an HSI injection feature can automatically inject a divided HSI clock in replacement at the root of the HSE tree. Users of the failed HSE keep running, but potentially at a slightly lower frequency. The HSI injected clock is adapted to the HSE frequency by an integer division. The PLLs relocks, but at the same or lower speed.

To enable the automatic HSI injection, first configure HSECSSBPRE in RCC_HSECFGR, then set HSECSSBYP = 1.

The HSI division ratio is configured with HSECSSBPRE. For instance, with the HSI at 64 MHz and an HSE at 48 MHz, the division ratio must be configured to 2x (HSECSSBPRE = 1): a failed HSE is replaced by a clock at \( 64 / 2 = 32 \) MHz.

When the CSS on HSE is enabled, the following actions are done by the RCC if a failure is detected:

• • If the HSI injection feature is enabled, the HSI oscillator is forced active, and the HSE clock is replaced by hsi_css_ck.
• • rcc_hsecss_fail is asserted.
• • The clock failure event (rcc_hsecss_fail) is also sent to the break inputs of advanced-control timers (TIM1/8/15/16/17).
• • An NMI interrupt is generated to inform the software about the failure (rcc_hsecss_it). This allows the MCU to perform rescue operations. The NMI interrupt is asserted until HSECSSF = 0 in RCC_CICR. The HSECSSF flag can be cleared by setting HSECSSC = 1.
• • A tamper event can also be triggered to clear content of backup registers and BKPSRAM.

CSS on LSE

A CSS on the LSE oscillator can be enabled by software by programming LSECSSON. This bit is disabled by hardware if one of the following conditions is met:

• • after a \( V_{SW} \) hardware reset (pwr_vsw_rst)
• • after a \( V_{SW} \) software reset via VSWRST bit

The software can also disable the CSS after an LSE failure detection.

The CSS on LSE works in all modes (Run, Stop, and Standby modes) including \( V_{BAT} \) mode.

The LSECSS provides a re-arm feature, offering the possibility to the software to re-arm the LSECSS, and to re-enable the LSE clock when a failure has been detected. This feature allows the application to decide if the LSE must be provided again to the RTC even if a failure occurred, or if another action must be performed. For example, the application can decide to reset the \( V_{SW} \) domain only if a certain number of consecutive LSE failures occurred, within a time window.

The LSECSS offers two flag signals:

• • the LSECSSD able to retain an LSE failure even in \( V_{BAT} \) mode
• • the LSECSSF used to generate an interrupt in case of LSE failure (flag not affected by a failure detected when the product is in \( V_{BAT} \) mode)

The sequence hereafter describes the LSE that enables sequence with the CSS enabled:

1. 1. Follow the LSE enable procedure given in LSE programming sequence , except the last step.
2. 2. Select the LSE clock via RTCSEL[1:0].
3. 3. Set the LSECSSON bit to 1.
4. 4. If no further changes are needed, clear DBP to 0 in PWR_DBPCR to write-protect accesses.

Note: The LSECSSON bit must be enabled after the LSE is enabled (LSEON set by software) and ready (LSERDY set by hardware), and after the RTC clock has been selected through RTCSEL.

If a failure is detected on the LSE, the hardware does the following:

• • The LSE clock is no more delivered to the RTC.
• • RTCSEL, LSECSSON, and LSEON are not changed by the hardware.
• • A failure event is generated (rcc_lsecss_fail). This event allows the system to wake up from Standby mode, but also to protect the backup registers and BKPSRAM via TAMP. This event is also generated in \( V_{BAT} \) mode.
• • The LSECSSF is activated (except in \( V_{BAT} \) mode) in order to generate an interrupt (rcc_lsecss_it, enabled by LSECSSIE).
• • The LSECSSD is activated as well, retaining the first LSE failure even in \( V_{BAT} \) mode.

On the software side, different actions can be taken according to the application requirements. Three different cases are described hereafter in order to illustrate the hardware behavior, they can also be combined. The application can also decide to handle LSE failure differently.

Case A

The application no longer wants to use LSE when a failure is detected:

1. 1. Unlock registers by setting DBP in PWR_DBPCR to 1.

1. 2. Disable the CSS function (this step is mandatory):
   1. a) Clear LSECSSF if the interrupt was enabled for this event.
   2. b) Clear LSECSSON to 0.
   3. c) Clear LSEON to 0 in order to disable the LSE.
2. 3. Change the clock source for the RTC if needed:
   1. a) Clear RTCEN to 0 to disable the RTC clock.
   2. b) Enable the new clock source for the RTC.
   3. c) Set RTCPRE if HSE is a new clock source.
   4. d) Select the proper clock source via RTCSEL.
   5. e) Set RTCEN to 1 to enable the RTC clock.
3. 4. The application must perform specific actions for TAMP events if enabled (see Section 4: Boot and security control (BSEC) and Section 61: Real-time clock (RTC) ).
   • • Lock registers by clearing DBP to 0 in PWR_DBPCR

Case B

The application wants to re-initialize the \( V_{SW} \) domain:

1. 1. Unlock registers by setting the DBP bit of PWR_DBPCR to 1
2. 2. Perform a VSW reset by setting VSWRST bit to 1, then back to 0.
3. 3. The application must perform specific actions for TAMP events if enabled (see Section 4: Boot and security control (BSEC) and Section 61: Real-time clock (RTC) ).
4. 4. Re-initialize all components of the \( V_{SW} \) domain.
5. 5. Lock registers by clearing DBP to 0 in PWR_DBPCR.

Case C

The application tries to reuse LSE when a failure is detected:

1. 1. If the number of failures in a given time window is higher than a given threshold then go to case A or B. Otherwise, continue to next step.
2. 2. Unlock registers by setting DBP to 1 in PWR_DBPCR.
3. 3. Clear LSECSSF if interrupt was enabled for this event.
4. 4. The application must perform specific actions for TAMP events if enabled (see Section 4: Boot and security control (BSEC) and Section 61: Real-time clock (RTC) ).
5. 5. Clear LSECSSON to 0.
6. 6. Rearm the LSECSS function by writing 1 to LSECSSRA, then back to 0.
7. 7. Wait for LSERDY = 1. The LSERDY flag must go to 1 after the oscillator settling time delay plus, 4096 periods of LSE clock. If it is not the case, it probably means that the LSE failure is permanent. LSECSSON cannot be set to 1. It is recommended to execute case A or B.
8. 8. Set LSECSSON to 1.
9. 9. When LSECSSON = 1, the LSE is enabled, and protected by LSECSS.
10. 10. Lock registers by clearing DBP to 0 in PWR_DBPCR.

14.6.4 Clock output generation (MCO1/MCO2)

There are two MCO1 and MCO2 microcontroller clock output pins. A clock source can be selected for each output. The selected clock can be divided thanks to a configurable prescaler (refer to Figure 38 for additional information on signal selection).

MCO1 and MCO2 are enabled using MCO1EN and MCO2EN in RCC_MISCENR.

The GPIO port corresponding to each MCO pin must be programmed in alternate function mode.

MCO1 and MCO2 are controlled via MCO1PRE[3:0], MCO1SEL[2:0], MCO2PRE[3:0], and MCO2SEL[2:0] located in RCC_CCIPR5.

MCO1PRE and MCO2PRE dividers provide a clock with a duty cycle of 50% for even divisions values, and around 53% for odd division values.

Note: MCO1 and MCO2 are available in Run, Stop, and Sleep modes.

Caution: The clock provided to the MCOx outputs must not exceed the maximum pin speed (refer to the product datasheet for information about the supported pin speed).

Table 69 shows the signals available on each MCO output.

Table 69. Clock output selection

14.6.5 PLL description

The RCC features four PLLs with the same features.

A typical allocation is:

• • PLL1, clocks to the CPU, buses, and storage (XSPI, SDMMC)
• • PLL2, clocks to NPU and audio peripherals
• • PLL3, clocks to CACHEAXI RAM and Ethernet
• • PLL4, clocks to display, camera, FDCAN, and other peripherals

Each PLL has the following features:

• • FREF frequency range:
  • – 5 to 1200 MHz in integer mode
  • – 10 to 1200 MHz in fractional mode
• • VCO frequency range from 800 to 3200 MHz
• • Three working modes:

• – fractional mode, using a 24-bit delta-sigma modulator (DSM)
• – integer mode
• – spread spectrum mode to reduce EMI. The fully digital spread spectrum clock generator (SSCG) is used in that case.

The internal post-dividers (POSTDIV1, POSTDIV2) are powered-off by default. They must be powered-on when the PLL is in use (PLLxPDIVEN).

The active post-dividers (ICx) are outside the PLL design. Each post-divider has a 4-way multiplexer before it, which can select any PLL output as input.

The DIVMx divider in RCC_PLLxCFGR1 must be properly programmed to keep the PFD input frequency below 50 MHz.

Figure 44. PLL block diagram

graph LR
    subgraph PLL_Block
    FREF[FREF 5-1200 MHz] --> DIV1["+1..63"] --> PFD
    PFD --> CP --> LPF --> VCO[VCO 800-3200 MHz]
    VCO --> FB_DIV["+16..640 int / +20..320 frac"] --> PFD
    VCO --> PD1["+ 1-7"] --> PD2["+ 1-7"] --> MUX
    FREF --> MUX
    MUX --> FOUTPOSTDIV
    SSCG --> DIV2["+1..15"] --> PFD
    DSM --> FB_DIV
    DAC --> LPF
    VCO --> LockDetect --> LOCK
    end
  

The PLL is enabled by setting PLLxON to 1 in RCC_CR. PLLxRDY in RCC_SR indicates that the PLL is ready (locked).

The DIVNx loop divider must be programmed to achieve the expected VCO output frequency before enabling the PLL. Changing the value on-the-fly can result in a spike on the VCO output proportional to the PFD frequency step. A frequency step of more than 0.01% per PFD clock period must be avoided. The SSCG typically steps the frequency by less than 0.005% per PFD clock period, so does not generate spikes.

The VCO output range must be respected.

The clock from FOUTPOSTDIV has a 50% duty-cycle ( \( \pm 3\% \) ).

The ICx post-dividers provide clocks with 50% duty-cycle when dividing by an even value.

If an ICx post-divider enable is set to 0, its value can be changed without disabling any PLL.

The PLLs are disabled by hardware when the system enters Stop or Standby mode.

PLLs using HSE as reference clock are also disabled by hardware if an HSE failure is detected.

PLL programming recommendations

• • Before enabling the PLLs, the user must ensure that the reference frequency (FREF) provided to the PLL is stable and in the correct range.
• • POSTDIV1 and POSTDIV2 must be set to 1.
• • PLLxPDIVN must be set to 1 to output the clock FOUTPOSTDIV.
• • When a PLL output is used, PLLxON and PLLxRDY must be set to 1. The application can then set any connected post-divider enable bits to 1 (in RCC_DIVEN).
• • When a PLL output is not used, PLLxON must be cleared to 0. The application must also set any connected post-divider enable bits to 0 (in RCC_DIVEN).

Caution: The 4 MHz setting for the MSI oscillator cannot be used as FREF.

The PLLs can work in three different modes:

• • integer
• • fractional
• • spread spectrum

Using PLLs in integer mode

The PLLx works in integer mode when the delta-sigma modulator (DSM) is loaded with a 0 value, and PLLxMODSSDIS = 1.

To load 0 into the DSM and to set DIVN, use the following sequence:

1. 1. Clear PLLxON to 0.
2. 2. Set DIVN value (valid range 16 to 640).
3. 3. Clear DIVNFRAC (in RCC_PLLxCFGR2) and PLLxMODDSEN to 0.
4. 4. Set PLLxMODSSRST to 1.
5. 5. Set PLLxON to 1.

Caution: Do not update DIVN after the PLL has been enabled.

The VCO frequency (F _VCO ) and output frequency expressions are the following:

Using the PLLs in fractional mode

This mode is enabled when DSM ≠ 0, PLLxMODDSEN = 1, and PLLxMODSSDIS = 1.

To load the value into the DSM perform the following sequence:

1. 1. Clear PLLxON to 0.
2. 2. Set DIVN value (valid range 20 to 320).
3. 3. Set DIVNFRAC (in RCC_PLLxCFGR2) to the required value, and set PLLxMODDSEN = DACEN 1.
4. 4. Set PLLxMODSSRST to 1.
5. 5. Set PLLxON to 1.

Caution: Do not update DIVN and DIVNFRAC after the PLL has been enabled.
The minimum FREF is 10 MHz in fractional mode.

The VCO frequency ( \( F_{VCO} \) ) and output frequency expressions are the following:

Using PLLs in spread spectrum mode

The spread spectrum mode is activated when the DSM is loaded with 0, and PLLxMODSSDIS is cleared to 0. This feature is available for all PLLs.

The spread spectrum method is to modulate the VCO frequency with a low-frequency triangular signal, in order to spread the clock energy into a wider frequency band. The amount of emitted EMI is then reduced.

The spread spectrum modulation is adjusted using the following fields:

• • MODDIV[3:0] to adjust the modulation frequency
• • MODSPR[4:0] to adjust the modulation depth (or modulation index)
• • MODSPRDW to define if the modulation is centered around the VCO frequency (center-spread), or lowered with respect to VCO frequency (down-spread)

MODDIV[3:0], MODSPR[4:0] and MODSPRDW are in RCC_PLLxCFGR3.

Figure 45 shows the SSCG modulating the nominal frequency ( \( F_N \) ), when MODSPRDW = 0 (center-spread), and MODSPRDW = 1 (down-spread). The nominal frequency is that output by the PLL in integer mode, when no clock spreading is applied.

Down-spread guarantees that the PLL output frequency does not exceed the programmed frequency value when SSCG is enabled.

Figure 45. Spread spectrum modulation

The peak modulation depth (in percentage) is given by the formula \( M_D (\%) = \text{MODSPR} / 10 \) .

Note: Modulation is turned off when MODSPR = 0.

The modulation frequency ( \( F_{MOD} \) ) is given by:

where 128 is the number of points in the internal wave table.

Note: When the PLL is locked, \( F_{CLKSSCG} = F_{PFD} \) . The upper limit of the frequency of modulation ( \( F_{MOD} \) ) is set by the PLL bandwidth. The PLL bandwidth limits the maximum modulation to \( F_{CLKSSCG} / 200 \) , where \( F_{CLKSSCG} = F_{REF} / DIVM \) or 50 MHz, whichever is lower.

To use the spread spectrum feature, to do the following:

1. 1. Program the PLL to the nominal frequency ( \( F_N \) ) using the \( F_{OUTPOSTDIV} \) formula from Using PLLs in integer mode
2. 2. Compute the MODDIV value according to the desired modulation frequency ( \( F_{MOD} \) ):

1. 3. Compute the MODSPR value according to the desired modulation depth ( \( M_D \) ).
2. 4. Set the MODSPRDW value according to the desired modulation type (center-spread or down-spread).
3. 5. Compute DIVN accordingly ( \( DIVNFRAC=0 \) ):

1. 6. Clear PLLxMODSSDIS, PLLxMODDSEN, and DACEN to 0.
2. 7. Set PLLxMODSSRST to 1, and clear PLLxON to 0. PLLxON must be held at 0 for 1 \( \mu\text{s} \) to make sure the PLL is fully reset.
3. 8. Set PLLxON, PLLxMODDSEN, and DACEN to 1 (see Note: ).
4. 9. Wait until the first edge of CLKSSCG, and then clear PLLxMODSSRST to 0 (this can be done before or after the PLL is locked).

Note: The spread spectrum accuracy relies on the PLL fractional-N capability, so MODDSEN and DACEN must be set to 1.

The user can check \( F_{MIN} \) , \( F_{MAX} \) as follows:

• • Calculate \( F_N \) as above.
• • If MODSPRDW = 0 (center-spread):
  \( F_{MIN} = F_N \times (1 - M_D / 100) \) and \( F_{MAX} = F_N \times (1 + M_D / 100) \)
• • If MODSPRDW = 1 (down-spread):
  \( F_{MIN} = F_N \times (1 - M_D / 100) \) and \( F_{MAX} = F_N \)

Programming sequence for spread spectrum mode

The programming sequence to enable SSCG and the PLL is:

1. 1. Deassert PLLxMODSSRST.
2. 2. Set PLLxDIVN, PLLxDIVNFRAC, and PLLxMODSSDIS to 0.
3. 3. Assert PLLxMODDSEN and PLLxDACEN.
4. 4. Assert PLLxMODSSRST and deassert PLLxON.
5. 5. PLLxON must be deasserted for 1µs to make sure PLL is fully reset. Then assert PLLxON.
6. 6. Wait until PLLxRDY is asserted, then deassert PLLxMODSSRST.

14.6.6 System clocks

System clock selection

After a system reset, the HSI is selected as system clock (sys[a,b,c,d]_ck), and all PLLs are switched off.

The system clock can be stopped by hardware when the system enters Stop or Standby mode.

When the system runs, the user can select system clocks (sys[a,b,c,d]_ck) from the four following sources:

• • HSE
• • HSI
• • MSI
• • ic[1,2,6,11]_ck

This function is controlled by programming RCC_CFGR1. A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source that is not yet ready is selected, the switch occurs when the clock source is ready.

The SYSSW only selects the ic[2,6,11]_ck if all three IC dividers are enabled.

SWS bits in RCC_CFGR1 indicate which clock sources are currently selected. Other status bits in RCC_CR indicate which clock(s) is (are) ready.

System clock generation

Figure 46 shows a simplified view of the clock distribution for the CPU and buses. All the dividers shown in the block diagram can be changed on-the-fly, without generating timing violations. This feature is a very simple solution to adapt bus frequencies to application needs, thus optimizing the power consumption.

The AXI sys_bus_ck is divided by HPRE to generate the AHB clock. HPRE is controlled by RCC_CFGR2.

In addition to the divide values shown, PPRE1, PPRE2, PPRE4, and PPRE5 can divide by 32, 64, and 128.

There is almost no clock protection, so the software must avoid configurations that can block the system.

Note: The application must respect the maximum allowed frequencies: \( F_{CPUmax} \) and \( F_{BUSmax} \) . \( F_{BUS} \) represents the maximum allowed frequency for AHB and AXI buses (refer to the datasheet for the maximum values).
The trace clock ( ck_cpu_tpiu ) is generated from sys_cpu_ck clock, divided by eight. For additional information, refer to Clock distribution for trace and debug .

Figure 46. Core and bus clock generation

1. 1. Dividers values can be changed on-the-fly. All dividers have 50% duty-cycles.

14.6.7 Clock generation in Stop and Standby modes

When the system enters Stop mode, all clocks (system and kernel) are stopped, and the following clock sources are disabled as well:

• • MSI, HSI
• • HSE
• • PLL1, PLL2, PLL3, PLL4

Note: The MSI and HSI stay active based on xxxSTOPEN bits in RCC_STOPCR.

HSIS is also disabled.

The content of the RCC registers is not altered, except CPUSW and SYSSW, forced to HSI or MSI (depending on STOPWUCK value), and PLLxON and HSEON, set to 0.

HSION and MSION are also modified, depending on STOPWUCK (see Table 70 ).

When the CPU requests to go in Stop mode, the RCC first stops all requested clocks, and informs the PWR that all clocks have been properly stopped. As shown in Figure 47 , three main signals are used to control power transitions:

• • rcc_pwrds: used to indicate to the PWR that the RCC stopped all clocks. The PWR can then go to Stop or Standby mode.
• • pwr_wkup is used to indicate to the RCC to re-enable the clocks.
• • The exti_wkup is used to indicate to the PWR that an event requests to exit the system from Stop mode.

Figure 47. Key signals controlling low-power modes

graph LR
    WE[Wake-up events] --> EXTI[EXTI]
    EXTI -- exti_wkup --> PWR[PWR]
    PWR -- pwr_wkup --> RCC[RCC]
    RCC -- rcc_pwrds --> PWR
    SC((sys_ck)) --> EXTI
    SC --> PWR
    SC --> RCC
  

Exiting Stop mode

When the device exits system Stop mode via a wake-up event, HSIS is started automatically.

Note: sys_rst is only deasserted after HSIS has successfully started.

The application can select which other oscillator (HSI and/or MSI) is used to restart the system. STOPWUCK in RCC_CFGR1 selects the oscillator used as system clock. Table 70 describes their behavior.

Table 70. STOPWUCK description

During Stop mode

There are two specific cases where the HSI or MSI can be enabled during system Stop mode:

• • When a dedicated peripheral requests the kernel clock, the peripheral receives the HSI or MSI according to the kernel clock source selected for this peripheral (via PERxSEL).
• • When HSISTOPEN or MSISTOPEN are set in RCC_STOPCR, the HSI and MSI are kept running during Stop mode but the outputs are gated. The clock is then available immediately when the system exits Stop mode, or when a peripheral requests the kernel clock (see Table 71 for details).

Caution: HSI and MSI are always off in Stop mode when the PWR is set to SVOS low.

Table 71. HSISTOPEN and MSISTOPEN behavior

1. \( t_{su(HSI)} \) and \( t_{su(MSI)} \) are the startup times of the HSI and MSI oscillators (see the datasheet for their values).

When the microcontroller exits Standby mode, the HSI is selected as system and kernel clock. RCC registers are reset to their initial values except for the backup domain configurations (LSE in RCC_CR/RCC_LSECFG, RTC in RCC_CCIPR7, RCC_BDCR), and the reset cause (RCC_RSR, RCC_HWRCSR).

Caution: When leaving Stop mode without reset (but not from Standby mode), the RCC returns in the same state as before, except for the software that has been forced to select the STOPWUCK source. When leaving Standby mode, the application can restore previous CPU clock settings, if needed.

Caution: If the system clock switch selection (SYSSW) is HSI or MSI oscillator, STOPWUCK (system clock selection after a wake-up from system Stop) must select the same oscillator.

14.6.8 Peripheral clock distribution

Some peripherals are designed to work with two different clock domains, operating asynchronously:

• • a domain synchronous with the register and bus interface (ckg_bus_perx clock)
• • a domain generally synchronous with the peripheral (kernel clock)

Other peripherals only need a bus interface clock, hence the user application has more freedom to choose an optimized clock frequency for the CPU, bus matrix, and for the kernel part of the peripheral. The user can change the bus frequency without reprogramming peripherals (example: an ongoing transfer with UART is not disturbed if its APB clock is changed on-the-fly).

Table 72 summarizes the clocks from RCC to the peripherals. The clock named per_ck is the output of a mux (see Figure 38 ).

Table 72. Peripheral clock distribution summary

Table 72. Peripheral clock distribution summary (continued)

Table 72. Peripheral clock distribution summary (continued)

Table 72. Peripheral clock distribution summary (continued)

Table 72. Peripheral clock distribution summary (continued)

Table 72. Peripheral clock distribution summary (continued)

Table 72. Peripheral clock distribution summary (continued)

Table 72. Peripheral clock distribution summary (continued)

Table 72. Peripheral clock distribution summary (continued)

1. 1. 'A' means that the kernel clock is asynchronous with respect to bus interface clock.
2. 2. 'S' means that the kernel clock is synchronous with respect to bus interface clock.
3. 3. Reset value.
4. 4. Reset value.
5. 5. The RTC switch is in the VSW voltage domain.

Clock distribution for the NPU

Figure 48. Clock distribution for the NPU

MSv70479V2

Clock distribution for graphic blocks (GPU, LTDC, DCMIPP, and PSSI)

Figure 49. Clock distribution for PSSI, CSI, and DCMIPP

Figure 50. Clock distribution for GPU, ICACHE, and GFXMMU

The PSSI receives an AHB clock and a kernel clock (pxclk). The pxclk can be provided either by an external device via PSSI_PIXCK pin, or by the RCC.

Note: The clock generated by the RCC is provided to pxclk input by the feedback path of the PSSI_PIXCK pin. The drive of the PSSI_PIXCK is controlled by the PSSI.

Figure 51. Clock distribution for LTDC

Figure 52. Clock distribution for VENC

Clock distribution for OTG1, OTG2, and UCPD1

Figure 53 shows the clock distribution for:

• • USB Type-C Power Delivery block (UCPD1): uses ucpd1_ker_ck as kernel clock. ucpd1_ker_ck is directly generated from the HSI output divided by four.
• • OTGPHYx: embeds a PLL that accepts a reference input frequency of 19.2, 20, or 24 MHz. The reference clock can be selected among one of the following:
  • – hse_div2_osc_ck
  • – hse_div2_ck
  • – ic15_ck
  • – per_ck

hse_div2_osc_ck is direct from the HSE oscillator, without the tempo delay. It can be selected to be HSE or HSE/2.

The OTGPHYx provides a 60 MHz clock (phyck) to the OTGx.

• • OTGx: uses the phyck when working in HS or FS mode.

The reference clock selection for the OTGPHYx is performed by a simple multiplexer. To change the clock source, the application must use the following sequence:

1. 1. Disable the OTGPHYx clock by clearing OTGPHYxEN to 0.
2. 2. Change the clock source selector (OTGPHYxSEL) to the desired value.
3. 3. Enable the OTGPHYx clock by setting OTGPHYxEN to 1.

Clocks provided by the RCC are controlled by enable bits in RCC_AHB5ENR.

Note: Before programming OTG1PHYCTL_CR, OTG1EN must be asserted (the OTG1PHYCTL_CR logic requires the clock enabled by OTG1EN).

Figure 53. Clock distribution for OTG1, OTG2, and UCPD1

Clock distribution for ETH1

Kernel Ethernet clocks are provided by the RCC, who provides also clock selectors (CLK_SEL, REF_CLK_SEL, SEL), and clock enables for TX and RX used in the ETHSS.

Note: Bus and PTP clocks are gated via ETH1MACEN and ETH1MACLPEN bits.

Figure 54. Clock distribution for ETH1

The ETH1 can generate a reference clock to the external PHY via the ETH1_CLK pin. The ETH1_CLK is generated only if all the following conditions are met:

• • ETH1EN is enabled.
• • The system is in Run or Sleep mode.
• • The clock source for ck_ker_eth1 is available.

The clock management for ETH is very flexible and based on the PHY interface mode (MII, RMII, or RGMII). All clock signals (enables, selection, and pins) are shown in Figure 55.

Figure 55. Clock management for ETH1

Clock distribution for MDIOS

MDIOS (MDIO slave) clocks are provided by the RCC.

Figure 56. Clock distribution for MDIOS

Clock distribution for FMC, XSPIs, and SDMMCs

The FMC kernel clock can be chosen between four different sources. For each XSPI, a clock switch can be used to select between four different sources. Each XSPI can be enabled independently.

The following steps are needed to correctly configure XSPI switches:

1. 1. Switch on the desired clock source.
2. 2. Ensure the clock source is ready, and conditions described above are met.
3. 3. Set XSPIxSEL to the desired position.
4. 4. Enable the XSPI clock (XSPIxEN = 1).

The XSPIs provide a clock to the external memory with a duty-cycle distortion lower than 5%. To this end, the kernel clock provided to the XSPIs has a typical duty cycle of 50%. In addition, the XSPIs embed a prescaler allowing clock division by even ratios.

Figure 57. Clock distribution for FMC and MCE4

Figure 58. Clock distribution for XSPIs and MCE1/2/3

The SDMMC1 and SDMMC2 have separate kernel clocks. A clock switch allows the selection between four different sources. Each SDMMC can be enabled independently.

When an SDMMC is enabled via its SDMMCxEN bit, the associated SDMMC_SYSCONF is also enabled.

The application must configure the SDMMC to match the duty-cycle constraint of the interface clock.

For example, if the SDMMC works in SDR50, a kernel clock of 50 MHz, with a duty cycle better than 30-70% is enough. If the SDMMC works in DDR50, it is recommended to provide a kernel clock of 100 MHz, and to divide the frequency of the kernel clock by two, using the SDMMC divider, to ensure a duty-cycle very close to 50% for the SDMMC_CK.

Figure 59. Clock distribution for SDMMCx and companions

Clock distribution for ADC1/2

If the application requires that the ADC is precisely triggered by a TIMx timer without any uncertainty (fixed trigger latency), ck_tim1 must be selected as the kernel clock source. The other clock sources are asynchronous to TIMx, which results in an uncertain trigger instant due to the resynchronization between the two clock domains. The LPTIMx timers are also asynchronous.

The ADCPRE[7:0] divide value is set in RCC_CCIPR1.

clk_adc_sync is generated by Pulse-gen, one ck_tim1 cycle before the adc_ck rising edge.

Figure 60. Clock distribution for ADCs

Clock distribution for RTC/AWU clock

The rtc_ck clock source can be one of the following:

• • hse_rtc_ck (hse_ker_ck divided by a programmable prescaler)
• • lse_ck
• • lsi_ck clock

The source clock is selected by programming RTCSEL and RTCPRE in RCC_CCIPR7. RTCSEL and RTCPRE are write-protected by DBP bit in PWR_DBPCR. In order to modify the bits, DBP must be set 1.

This selection cannot be modified without resetting the backup domain.

Figure 61. Clock distribution for RTC

If the LSE is selected as RTC clock, the RTC works normally even if the backup or the V _DD supply disappears.

The LSE clock is in the backup domain, whereas the other oscillators are not, with the following consequences:

• • If LSE is selected as RTC clock, the RTC continues to work even if the \( V_{DD} \) supply is switched off, provided the \( V_{BAT} \) supply is maintained.
• • If LSI is selected as the RTC clock, the AWU state is not guaranteed if the \( V_{DD} \) supply is powered off.
• • If the HSE clock is used as RTC clock, the RTC state is not guaranteed if the \( V_{DD} \) supply is powered off, or if the \( V_{VDDCORE} \) supply is powered off. In addition, the HSE is not available if the system goes to Stop mode.

rtc_ker_ck is enabled through RTCEN in RCC_APB4ENR.

The RTC bus interface clock (APB clock) is enabled through RTCAPBEN in RCC_APB4ENR, and RTCAPBLPEN in RCC_APB4LLPENR.

Note: To read the RTC calendar register when the APB clock frequency is less than seven times the RTC clock frequency ( \( F_{APB} < 7 \times F_{RTCCLK} \) ), the software must read the calendar time and date registers twice. Data are correct if the second read access to RTC_TR gives the same result of the first one. Otherwise, a third read access must be performed.

Clock distribution for watchdogs

The RCC provides the clock for the two watchdogs: the independent watchdog (IWDG), connected to the LSI, and the window watchdog (WWDG), connected to the APB clock.

If an IWDG is started by either hardware option or software access, the LSI is forced on, and cannot be disabled. After the LSI oscillator setup delay, the clock is provided to the IWDG.

The WWDG clock (pclk1) can be enabled by setting WWDGEN in RCC_APB1ENR. The software cannot stop WWDG down-counting by clearing WWDGEN to 0. The WWDG is frozen when the device goes to Stop mode.

Figure 62. Clock distribution for IWDG and WWDG

Clock distribution for trace and debug

The clock generation for the trace and debug is controlled by the DBGMCU.

DBGCLKEN in DBGMCU_CR allows the application to provide a clock to the debug components. This clock can also be enabled via the debug access port.

The trace clock generation is controlled via TRACECLKEN in DBGMCU_CR.

Figure 63. Clock distribution for trace and debug

14.6.9 General clock concept overview

The RCC handles the distribution of the CPU, bus interface, and peripheral clocks for the system, according to the CPU operating mode (refer to Section 14.6.1 for details on clock definitions).

For each peripheral, the application can control the activation/deactivation of its kernel and bus interface clocks. Before using a peripheral, the CPU must enable it (by setting PERxEN to 1), and define if it remains active in Sleep mode (by setting PERxLPEN to 1). This is called allocation of a peripheral by the CPU (refer to Section 14.6.10 for more details).

The peripheral allocation is used:

• • by the RCC to automatically control the clock gating according to the CPU modes
• • by the PWR to control V _DDCORE supply voltages

Memory handling

The CPU can access all memory areas available in the device:

• • AXISRAM1 to AXISRAM6, CACHEAXI RAM, and FLEXRAM
• • AHBSRAM1 and AHBSRAM2
• • BKPSRAM

CACHEAXI RAM, and VENCRAM are disabled by default, see RCC embedded memories enable register (RCC_MEMENR) . The CPU must enable them before using these memories.

Read or write accesses to a peripheral register or memory, without the clocks enabled in the RCC registers, result in a system freeze. A system reset is required to unlock this.

If the access is performed by a debug interface (as an example, from a debug session inside an IDE), then a power-on reset is required to unlock the device, as the debug interface is not affected by a system reset.

Note: The memory interface clocks (flash memory and RAM interfaces) can be stopped by software during Sleep mode (via SRAMyLPEN bits).

Refer to Section 14.6.11 and Section 14.6.12 for details on clock enabling.

14.6.10 Peripheral allocation

The CPU can allocate a peripheral (and hence control its kernel and bus interface clock) by setting the dedicated PERxEN bit to 1. The CPU can control the peripheral clock gating when it is in Sleep mode via PERxLPEN bits.

The peripheral allocation bits (PERxEN bits) are used by the hardware to provide the kernel and bus interface clocks to the peripherals. These bits are also used to link peripherals to the CPU. The hardware can then safely gate peripheral clocks and bus matrix clocks, according to CPU states.

Clock switches and gating

• Clock switching delays

The input selected by the clock switches can be changed dynamically without generating spurs or timing violation. For example, if PERxSEL (in Figure 64) goes from 0 to 1, the switch first disables the clock output using the currently selected clock (in0_ck), and enables again the clock output using the new selected clock (in1_ck). Disable and enable commands are re-synchronized to their respective clocks. If one of the two clocks are not present, the sequence cannot be completed, and no clock is output. To recover from this situation, the user must either provide a valid clock to in1_ck input, or set back PERxSEL to 0.

During the transition from one input to another, the kernel clock provided to the peripheral is gated, in the worst case, during two or three clock cycles of the new selected clock.

As shown in Figure 64, both input clocks must be present during transition time.

Figure 64. Kernel clock switching

• Clock enabling delays

In the same way, the clock gating logic synchronizes the enable command (coming generally from a kernel clock request, or PERxEN bits) with the selected clock, in order to avoid generation of spurious:

• – A maximum delay of two periods of the enabled clock can occur between the enable command and the first rising edge of the clock. The enable command can

be the rising edge of PERxEN in RCC_xxxxENR, or a kernel clock request asserted by a peripheral.

• – A maximum delay of 1.5 periods of the disabled clock can occur between the disable command and the last falling edge of the clock. The disable command can be the falling edge of PERxEN in RCC_xxxxENR, or a kernel clock request released by a peripheral.

Note: Both kernel and bus interface clocks are affected by this re-synchronization delay.

14.6.11 Peripheral clock-gating control

As mentioned previously, each peripheral requires one or several bus interface clocks, named rcc_perx_bus_ck (for peripheral 'x'). These clocks can be an APB, AHB, or AXI clock, according to which bus(es) the peripheral is connected.

The clocks used as bus interface for peripherals can be aclk[s,a,n] , hclk[m,u,e] , hclk[5:1] , pclk[5:4] , pclk[2:1] , or ck_timg[1,2] , depending on the bus connected to each peripheral.

Some peripherals also require dedicated clocks for their communication interface. These clocks are generally asynchronous with respect to the bus interface clock. They are named kernel clocks ( perx_ker_ck ). Both bus interface and kernel clocks can be gated according to several conditions detailed hereafter.

As shown in Figure 65 , enabling kernel and bus interface clocks of each peripheral depends on several input signals:

• • PERxEN and PERxLPEN bits
  PERxEN represents the peripheral enable (allocation) bit for the CPU. The CPU can write these bits to 1 via RCC_xxxxENR.
• • CPU state ( cpu_sleep and cpu_deep sleep signals)
• • kernel clock request ( perx_ker_ckreq ) of the peripheral itself, when the feature is available

Refer to Section 14.6.10 for more details.

Figure 65. Enable logic details for peripheral kernel clock

The clocks for all AHB and APB buses (AHBM, AHB1/2/3/4/5, APB1/2/4/5) are automatically enabled when a dependent peripheral is active. This may induce a chain: a peripheral activation activates the APB that activates the AHB, and activates the AHBM.

For instance, the manual UART4 activation induces the automatic APB1 activation (APB1 is used to configure the UART4). This induces the automatic AHB1 bus activation (AHB1 is needed to drive the APB1). This induces the activation of the central AHBM matrix (AHBM is needed to drive the AHB1).

High-bandwidth interconnect

The NoC and the two NPU AXI bus clocks (ck_icn_npu and ck_icn_npuc, see Figure 48 ) are permanently enabled in Run and Sleep modes, and permanently disabled in Stop and Standby modes.

An internal automatic clock-gating optimizes the NoC power consumption: when no transaction is ongoing in a bus section, an automatic clock-gating clocks and gates this bus.

The NPU interconnect clock (ck_icn_npu) can be disabled by setting ACLKNEN = 0 (disabled in Run and Sleep modes), or ACLKNLPEN = 0 (disabled in Sleep mode only). If the clock is disabled, the NPU cannot work (no interconnect downstream), and the CPU cannot access AXISRAM3/4/5/6, the CACHEAXI RAM, or the FLEXRAM.

The clock of the NPU interconnect (ck_icn_npuc) can be disabled by setting ACLKNCEN = 0 (disabled in Run and Sleep modes), or ACLKNCLPEN = 0 (disabled in Sleep mode only). If the clock is disabled, neither the CPU or NPU can access AXISRAM3/4/5/6, the CACHEAXI, the CACHEAXI RAM, or the FLEXRAM.

Table 74 gives a detailed description of the enabling logic of the peripheral clocks for peripherals located in the CPU domain and allocated by the CPU.

Table 74. Peripheral clock enabling

Table 74. Peripheral clock enabling (continued)

The kernel clock is provided to the peripherals when one of the following conditions is met:

1. 1. The CPU is in Run mode and the peripheral is enabled.
2. 2. The CPU is in Sleep mode and the peripheral is enabled with PERxLPEN = 1.
3. 3. The CPU is in Stop mode, the peripheral is enabled with PERxLPEN = 1, the peripheral generates a kernel clock request, and the selected clock is hsi_ker_ck or msi_ker_ck.
4. 4. The CPU is in Stop mode, the peripheral is enabled with PERxLPEN = 1, and the kernel source clock of the peripheral is lse_ck or lsi_ck.

The bus interface clock is provided to the peripherals only when conditions 1 or 2 are met.

14.6.12 CPU and bus matrix clock-gating control

The clocks of the CPU, AHB/AXI bridges, and APB buses are enabled as follows:

• • The CPU clock (rcc_cpu_ck) is enabled when the CPU is in Run or Sleep mode.
• • The AXI bridge clock is enabled when the CPU is in Run or Sleep mode.
• • The AHB bus matrix clock is enabled if one of the following conditions is met:
  • – The CPU is in Run mode.
  • – The CPU is in Sleep mode, and at least one peripheral connected to this bridge has both its PERxEN and PERxLPEN set to 1.
  • – The CPU is in Sleep mode, and AHB1, 2, 3, 4, or 5 has its clock enabled.
• • The clocks of AHB1/2/3/4/5 bridges are enabled when one of the following conditions is met:

• – The CPU is in Run mode.
• – The CPU is in Sleep mode, and at least one peripheral connected to this bus has both its PERxEN and PERxLPEN set to 1.
• – The CPU is in Sleep mode, and the APB bus connected to the AHB bridge has its clock enabled.
• • The APB1/2/4/5 clock buses are enabled when one of the following conditions is met:
  • – The CPU is in Run mode.
  • – The CPU is in Sleep mode, and at least one peripheral connected to this bus has both its PERxEN and PERxLPEN set to 1.

Refer to Section 14.6.11 for details on the automatic clock-gating for AHBMEN, and all AHB/APB buses.

14.6.13 Low-power emulation modes

To ease the device debug, the RCC is able to handle an emulation mode for Stop and Standby modes.

Sleep emulation mode

The Sleep emulation mode is controlled by DBGSLEEP in DBGMCU_CR. When the processor goes to Sleep mode with DBGSLEEP = 1, the processor clock, the clocks of all enabled peripherals, debug parts, and interconnect are maintained activated.

Stop emulation mode

The Stop emulation mode is controlled by DBGSTOP in DBGMCU_CR. When the processor goes to Stop mode with DBGSTOP = 1:

• • The processor, peripheral, and interconnect clocks remain active.
• • The debug clock is active (ck_bus2_dbg, see Figure 46 ), and all debug parts remain clocked. All PLLs and OSCs remain active.

When a wake-up event occurs:

• • The peripheral waking up the system sends the interrupt to the NVIC via the EXTI.
• • If the PWR asserts the pwr_wkup signal, the RCC exits Stop mode. The RCC selects HSI or MSI as system clock, depending on STOPWUCK. The CPU exits Stop mode.

Standby emulation mode

The Standby emulation mode is controlled by DBGSTBY in DBGMCU_CR.

When the system goes to Standby mode with DBGSTBY = 1 and dbg_stdby_rstn = 0:

• • the V _DDCORE voltage is not switched-off
• • all CPU, interconnect, and peripherals are under reset except the debug part
• • all PLLs and OSCs remain active
• • the debug part is clocked
• • peripherals on V _SW or V _DD domains are not reset

The system exits Standby mode when dbg_stdby_rstn is deasserted:

• • the RCC deasserts the rcc_pwrds signal
• • all peripherals are removed from reset
• • the RCC enters Run state

14.7 RCC interrupts

The RCC provides the following interrupt lines:

• • rcc_it : general interrupt line that provides events when PLLs or oscillators are ready (for nonsecure bits)
• • rcc_s_it : general interrupt line that provides events when PLLs or oscillators are ready (for secure bits)
• • rcc_hsecss_it : interrupt line dedicated to the failure detection of the HSE CSS
• • rcc_lsecss_it : interrupt line dedicated to the failure detection of the LSE CSS

The interrupt enable is controlled via RCC_CIER , except for the HSE CSS failure. When the HSE CSS feature is enabled, the interrupt generation cannot be masked.

The interrupt flags can be checked via RCC_CIFR , and these flags can be cleared via RCC_CICR .

Note: The interrupt flags are not relevant if the corresponding interrupt enable bit is not set.

Table 75 gives a summary of the interrupt sources and the way to control them.

Table 75. Interrupt sources and control

1. The security system feature must be enabled ( LSECSSON = 1 ) to generate interrupts.

2. This interrupt cannot be masked when the security system feature is enabled ( HSECSSON = 1 ).

14.8 RCC application information

14.8.1 HSE crystal auto-detection

The software can detect the frequency of the crystal connected to the HSE. The crystal choices are 19.2, 20.0, 24.0, 38.4, 40.0, 48.0 MHz. The closest crystal frequencies are 19.2 and 20 MHz (differing ~4%).

Measurement uses a timer clocked by a fast clock, triggered by the slower clock. Using the PWM input mode of input capture, it is possible to measure the full period of the slow clock.

LSE reference

If available, the LSE can trigger TIM16 to count hse_ck ticks. This is crystal accurate (better than using HSI).

Configure a PLL to generate (HSE * 8) MHz. Then set SYSSW to select ic2_ck for sysb_ck = ck_timg (TIMPRE = 1). This means sys_bus_ck relates to the HSE frequency.

LSE is connected to TIM16 - TI1_2.

Example: the multiplication by eight of hse_ck gives
\( (40 \times 1000 \times 8) / 32.768 = 9765 \) counts, and \( (38.4 \times 1000 \times 8) / 32.768 = 9375 \) counts.

19.2, 20, 24, 38.4, 40, 48 = 4687, 4882, 5859, 9375, 9765, 11718 counts

sys_bus_ck = 153.6, 160, 192, 307.2, 320, 384 MHz

HSI reference

HSI can be used when LSE is not available. A trimmed HSI can vary by \( \pm 4\% \) (at \( 3\sigma \) ) across the full temperature range. This means that 19.2 and 20 MHz cannot be differentiated reliably.

If the DTS is available, the user can measure the temperature to compensate for the HSI drift.

The RCC generates an hse_cal_ck signal, which is HSE divided by 1024. This signal is connected to TIM17 - TI1_2.

hse_cal_ck has an expected frequency between 19.2 to 50 kHz. The HSI is about 64 MHz. To get 300 MHz, select HSI as input to a PLL, then ic2_ck for sysb_ck = ck_timg (TIMPRE = 1).

Example: The division by 1024 of hse_ck gives \( 300 \times 1024 / 40 = 7680 \) counts, and \( 300 \times 1024 / 38.4 = 8000 \) counts.

19.2, 20, 24, 38.4, 40, 48 = 16000, 15360, 12800, 8000, 7680, 6400 counts

A less accurate method is to use hse_ck output on MCO divided by 16. This gives, for example: \( 300 \times 16 / 40 = 120 \) counts, and \( 300 \times 16 / 38.4 = 125 \) counts.

19.2, 20, 24, 38.4, 40, 48 = 250, 240, 200, 125, 120, 100 counts

14.8.2 Calibration and clock frequency measurement using TIMx

Most of the clock source generator frequencies can be measured by means of the input capture of TIMx.

Calibrating HSI or MSI with the LSE

The main purpose of connecting the LSE to a TIMx input capture is to accurately measure the HSI or MSI. This requires to use the HSI or MSI as sys_bus_ck either directly, or via a PLL. The number of system clock counts between consecutive edges of the LSE signal gives a measurement of the internal clock period. Taking advantage of the high precision of LSE crystals (typically a few tens of ppm), the user can determine the internal clock frequency with the same resolution, and trim the source to compensate for variations due to manufacturing, temperature, or voltage.

The ratio between the two clock frequencies affects the measurement precision. The greater the ratio, the more accurate the calculation.

HSI and MSI oscillators have dedicated user-accessible calibration bits for this purpose (see RCC_HSICFGR and RCC_MSICFGR). When the HSI or MSI is used via a PLL, it is also possible to fine-tune the sys_bus_ck using the fractional divider of the PLL.

Calibrating LSI with HSI

The LSI frequency can also be measured. This is useful for applications that do not have a crystal. The ultra-low-power LSI oscillator has a large manufacturing process variation. The LSI clock frequency can be measured using the more precise HSI clock source. Using this measurement, the user can obtain a more accurate RTC timebase timeout (when LSI is used as RTC clock source), and/or a more accurate IWDG timeout.

14.8.3 Clock monitoring

Monitoring HSI with LSE

The purpose is to assist the software calibration procedure when the HSI frequency drifts out of a predefined range because of environmental variation (for example, temperature).

This monitoring can be enabled in all system modes where HSI is used, except Standby and V _BAT modes. When enabled, the number of HSI clock ticks between consecutive edges of the LSE clock is counted.

The HSI monitoring control is based on RCC_HSIMCR and RCC_HSIMSR.

The following steps can be used to enable the monitoring:

1. 1. Enable LSE signal:
   1. a) Set DBP = 1 in PWR_DBPCR.
   2. b) Write 1 to LSEON.
   3. c) Wait for LSERDY = 1.
   4. d) Set DBP = 0 in PWR_DBPCR.
2. 2. Set up HSI clock period monitoring:
   1. a) Write 1 to HSIMONEN in RCC_HSIMCR to start the monitoring.

14.8.4 Clock frequency limits

The maximum frequencies that can be set for each peripheral are detailed in Table 76 .

Table 76. Maximum peripheral clock frequencies

As an example, the PLL configuration to achieve these frequencies would use HSI as reference clock (64 MHz), and program the VCO of PLL1, 2, 3, and 4, to respectively, 800, 993.52, 875, and 514.5 MHz.

14.9 RCC security

The system RIF protects bus accesses to the RCC and peripheral registers.

The RIFSC indicates if an access to the RCC or other peripherals is secure and/or privileged. Signals are connected from the RIFSC to the RCC to communicate this information. The notation for these signals is S, P.

The RCC is able to protect register bits from being modified by nonsecure and unprivileged accesses.

If a peripheral RISUP is programmed as secure (or privileged), the peripheral clock and reset bits become secure (or privileged).

If the peripheral is TrustZone-aware, the peripheral clock and reset bits become secure (or privileged) as soon as at least one function is configured as secure (or privileged) by RIFSC.

Peripheral configuration registers inside the RCC can be also be made secure (or privileged) via a global override bit (PERSEC in RCC_SECCFGR3, PERPRIV in RCC_PRIVCFGR3).

After an application reset or system reset, the RCC does not filter any access until the trusted agent has configured the system.

14.9.1 Internal register protection

The following can be made secure and/or privileged (via RCC_SECCFGRx and RCC_PRIVCFGRx):

• • internal and external oscillators (HSE, LSE, HSI, MSI, LSI)
• • PLLs and AHB prescalers
• • system clock-source selection
• • MCO clock outputs
• • reset flags
• • automatic internal oscillator wake-up configuration

There are four access controls for RCC registers:

• • SEC (secure)
• • PRIV (privileged)
• • LOCK (locked SEC and PRIV)
• • PUB (public)

SEC (in RCC_SECCFGRx)

xxxSEC defines the secure status required for a write to the xxx configuration registers (for example, HSISEC for the HSI oscillator). When this bit is set, configuration register bits are writable by secure software only. This bit can be locked (cannot be changed) with the xxxLOCK bit, and is readable by all. Write access to RCC_SECCFGRx is controlled by S, P.

PRIV (in RCC_PRIVCFGRx)

xxxPRIV defines the privileged status required for a write to the xxx configuration registers (such as HSIPRIV for the HSI oscillator). When this bit is set, the configuration register bits are writable only by privileged software. This bit can be locked (cannot be changed) with the xxxLOCK bit, and is readable by all. Write access to RCC_PRIVCFGRx is controlled by xxxSEC, P. xxxPRIV can be set/cleared by write to 1 registers.

LOCK (in RCC_LOCKCFGRx)

xxxLOCK, when set, locks definitively xxxSEC and xxxPRIV settings: xxxLOCK is readable by all. Write access to RCC_LOCKCFGRx is controlled by S, P. xxxLOCK is a set-once bit.

PUB (in RCC_PUBCFGRx)

xxxPUB grants read access to configuration/status bits, regardless of security or privilege.

For example, if HSIPUB bit is set, any software can read the HSI oscillator configuration and status. If not set then normal access controls are enforced.

xxxPUB is readable by all. Write access to RCC_PUBCFGRx is controlled by xxxSEC and xxxPRIV. xxxPUB can be set/cleared by write-to-1 registers.

14.9.2 Internal register write-protection

There are different controls for write-protecting a register bit.

• • xxxLOCK bits (described above)
• • other internal protection logic (controlled from internal or external signals)

Only protection logic using the pwr_lock_backup signal is implemented.

14.10 RCC registers

14.10.1 RCC control register (RCC_CR)

Address offset: 0x0

Reset value: 0x0000 0008

This register is used to enable the RCC oscillators and PLLs in Run or Sleep mode.

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 PLL4ON : PLL4 enable

This bit is reset by int_sys_rstn. It is security-protected by PLL4SEC or PLL4PRIV, and is publicly readable if PLL4PUB = 1. It can be set with PLL4ONS, and cleared with PLL4ONC. This bit is set and reset by software. It cannot be cleared if PLL4 is currently used to generate the CPU or system clock.

0: PLL4 is OFF (default after reset)

1: PLL4 is ON

This bit is reset by int_sys_rstn . It is security-protected by PLL3SEC or PLL3PRIV , and is publicly readable if PLL3PUB = 1. It can be set with PLL3ONS , and cleared with PLL3ONC . This bit is set and reset by software. It cannot be cleared if PLL3 is currently used to generate the CPU or system clock.

0: PLL3 is OFF (default after reset)
1: PLL3 is ON

This bit is reset by int_sys_rstn . It is security-protected by PLL2SEC or PLL2PRIV , and is publicly readable if PLL2PUB = 1. It can be set with PLL2ONS , and cleared with PLL2ONC . This bit is set and reset by software. It cannot be cleared if PLL2 is currently used to generate the CPU or system clock.

0: PLL2 is OFF (default after reset)
1: PLL2 is ON

This bit is reset by int_sys_rstn . It is security-protected by PLL1SEC or PLL1PRIV , and is publicly readable if PLL1PUB = 1. It can be set with PLL1ONS , and cleared with PLL1ONC . This bit is set and reset by software. It cannot be cleared if PLL1 is currently used to generate the CPU or system clock.

0: PLL1 is OFF (default after reset)
1: PLL1 is ON

Bits 7:5 Reserved, must be kept at reset value.

This bit is reset by int_sys_rstn . It is security-protected by HSESEC or HSEPRIV , and is publicly readable if HSEPUB = 1. It can be set with HSEONS , and cleared with HSEONC . This bit is set and reset by software.

0: HSE is OFF (default after reset)
1: HSE is ON

This bit is reset by int_sys_rstn . It is security-protected by HSISEC or HSIPRIV , and is publicly readable if HSIPUB = 1. It can be set with HSIONS , and cleared with HSIONC . This bit is set and reset by software.

0: HSI is OFF
1: HSI is ON (default after reset)

This bit is reset by int_sys_rstn . It is security-protected by MSISEC or MSIPRIV , and is publicly readable if MSIPUB = 1. It can be set with MSIONS , and cleared with MSIONC . This bit is set and reset by software.

0: MSI is OFF (default after reset)
1: MSI is ON

This bit is reset by rcc_vsw_rstn . It is in the V _BKP voltage domain. It is write-protected by the pwr_lock_backup_n signal. It is security-protected by LSESEC , LSEPRIV , and is publicly readable if LSEPUB = 1. It can be set with LSEONS , and cleared with LSEONC . This bit is set and reset by software.

0: LSE is OFF (default after reset)
1: LSE is ON

Bit 0 LSION : LSI oscillator enable

This bit is reset by nreset_rstn. It is in the V _RET voltage domain. This bit is security-protected by LSISEC or LSIPRIV, and is publicly readable if LSIPUB = 1. It can be set with LSIONS, and cleared with LSIONC. This bit is set and reset by software.

0: LSI is OFF (default after reset)

1: LSI is ON

14.10.2 RCC status register (RCC_SR)

Address offset: 0x4

Reset value: 0x0000 0000

This register is used to retrieve the status the RCC oscillators and PLLs.

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 PLL4RDY : PLL4 clock ready flag

This bit is security-protected by PLL4SEC or PLL4PRIV, and is publicly readable if PLL4PUB = 1. It is set by hardware to indicate that the PLL4 is locked.

0: PLL4 unlocked (default after reset)

1: PLL4 locked

Bit 10 PLL3RDY : PLL3 clock ready flag

This bit is security-protected by PLL3SEC or PLL3PRIV, and is publicly readable if PLL3PUB = 1. It is set by hardware to indicate that the PLL3 is locked.

0: PLL3 unlocked (default after reset)

1: PLL3 locked

Bit 9 PLL2RDY : PLL2 clock ready flag

This bit is security-protected by PLL2SEC or PLL2PRIV, and is publicly readable if PLL2PUB = 1. it is set by hardware to indicate that the PLL2 is locked.

0: PLL2 unlocked (default after reset)

1: PLL2 locked

Bit 8 PLL1RDY : PLL1 clock ready flag

This bit is security-protected by PLL1SEC or PLL1PRIV, and is publicly readable if PLL1PUB = 1. It is set by hardware to indicate that the PLL1 is locked.

0: PLL1 unlocked (default after reset)

1: PLL1 locked

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 HSERDY : HSE clock ready flag

This bit is security-protected by HSESEC or HSEPRIV, and is publicly readable if HSEPUB = 1.

It is set by hardware to indicate that the HSE oscillator is stable.

0: HSE not ready (default after reset)

1: HSE ready

Bit 3 HSIRDY : HSI clock ready flag

This bit is security-protected by HSISEC or HSIPRIV, and is publicly readable if HSIPUB = 1.

It is set by hardware to indicate that the HSI oscillator is stable.

0: HSI not ready (default after reset)

1: HSI ready

Bit 2 MSIRDY : MSI clock ready flag

This bit is security-protected by MSISEC or MSIPRIV, and is publicly readable if MSIPUB = 1.

It is set and reset by hardware to indicate that the MSI oscillator is stable.

0: MSI not ready (default after reset)

1: MSI ready

Bit 1 LSERDY : LSE clock ready flag

This bit is security-protected by LSESEC or LSEPRIV, and is publicly readable if LSEPUB = 1. It is set and reset by hardware to indicate that the LSE oscillator is stable. This bit requires 6 cycles of lse_ck before it is deasserted.

0: LSE not ready (default after reset)

1: LSE ready

Bit 0 LSIRDY : LSI clock ready flag

This bit is security-protected by LSISEC or LSIPRIV, and is publicly readable if LSIPUB = 1. It is set by hardware to indicate that the LSI oscillator is stable.

0: LSI not ready (default after reset)

1: LSI ready

14.10.3 RCC Stop mode control register (RCC_STOPCR)

Address offset: 0x8

Reset value: 0x0000 0002

This register is used to enable the RCC oscillators in Stop mode.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 HSISTOPEN : HSI oscillator enable

This bit is reset by int_sys_rstn . It is security-protected by HSISEC or HSIPRIV , and is publicly readable if HSIPUB = 1. It can be set with HSISTOPENS , and cleared with HSISTOPENC . This bit is set and reset by software.

0: HSI is OFF

1: HSI is ON (default after reset)

Bit 0 MSISTOPEN : MSI oscillator enable

This bit is reset by int_sys_rstn . It is security-protected by MSISEC or MSIPRIV , and is publicly readable if MSIPUB = 1. It can be set with MSISTOPENS , and cleared with MSISTOPENC . This bit is set and reset by software.

0: MSI is OFF (default after reset)

1: MSI is ON

14.10.4 RCC configuration register 1 (RCC_CFGR1)

Address offset: 0x20

Reset value: 0x0000 0000

This register controls the selection of the CPU and system clocks, and their status (see Figure 46 for various SYSSW inputs). The register is reset by sys_rstn , and is in the \( V_{CORE} \) voltage domain.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 SYSSWS[1:0] : System clock switch status

This bitfield is security-protected by SYSSEC , SYSPRIV , and is publicly readable if SYSPUB = 1. It is set and reset by hardware to show the source of the system bus clocks ( sys_bus_ck ).

00: hsi_ck selected as sysb_ck, sysb_ck, sysd_ck system clocks (default after reset)

01: msi_ck selected as sysb_ck, sysb_ck, sysd_ck system clocks

10: hse_ck selected as sysb_ck, sysb_ck, sysd_ck system clocks

11: ic2_ck selected as sysb_ck, ic6_ck selected as sysb_ck, ic11_ck as sysd_ck system clocks

Bits 27:26 Reserved, must be kept at reset value.

Bits 25:24 SYSSW[1:0] : System clock switch selection

This bitfield is security-protected by SYSSEC , SYSPRIV , and is publicly readable if SYSPUB = 1. It is set by the software to select the source of the system bus clocks ( sys_bus_ck ).

00: hsi_ck selected as system clock (default after reset)

01: msi_ck selected as system clock

10: hse_ck selected as system clock

11: ic2_ck selected as system clock

Bits 23:22 Reserved, must be kept at reset value.

Bits 21:20 CPUSWS[1:0] : CPU clock switch status

This bitfield is security-protected by SYSSEC, SYSPRIV, and is publicly readable if SYSPUB = 1. It is set and reset by hardware to show the source of the CPU clock (sys_cpu_ck).

• 00: hsi_ck selected as system clock (default after reset)
• 01: msi_ck selected as system clock
• 10: hse_ck selected as system clock
• 11: ic1_ck selected as system clock

Bits 19:18 Reserved, must be kept at reset value.

Bits 17:16 CPUSW[1:0] : CPU clock switch selection

This bitfield is security-protected by SYSSEC, SYSPRIV, and is publicly readable if SYSPUB = 1. It is set by the software to select the source of the CPU clock (sys_cpu_ck).

• 00: hsi_ck selected as system clock (default after reset)
• 01: msi_ck selected as system clock
• 10: hse_ck selected as system clock
• 11: ic1_ck selected as system clock

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 STOPWUCK : System clock selection after a wake up from system stop

This bit is security-protected by SYSSEC, SYSPRIV, and is publicly readable if SYSPUB = 1. It is set and reset by software to select the system wake-up clock from system stop.

• 0: HSI selected as wake-up clock from system stop (default after reset)
• 1: MSI selected as wake-up clock from system stop

14.10.5 RCC configuration register 2 (RCC_CFGR2)

Address offset: 0x24

Reset value: 0x0010 0000

This register controls the division factors of the central clocks: AHB, APB, and timer. It is reset by sys_rstn, and is in the V _CORE voltage domain.

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:24 TIMPRE[1:0] : Timer clock prescaler selection

This bitfield is security-protected by a SEC signal from RIFSC, the SYSSEC bit, a PRIV signal from RIFSC, or the SYSPRIV bit, and is publicly readable if SYSPUB = 1. It is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains.

• 00: timg_ck = sys_bus_ck (default after reset)
• 01: timg_ck = sys_bus_ck / 2
• 10: timg_ck = sys_bus_ck / 4
• 11: timg_ck = sys_bus_ck / 8

Bit 23 Reserved, must be kept at reset value.

This bitfield is security-protected by SYSSEC or SYSPRIV, and is publicly readable if SYSPUB = 1. It is set and reset by software to control the division factor of the clocks between the system AXI bus and the configuration AHB bus. The AXI sys_bus_ck source clock is divided in function of HPRE, to generate the AHB clock.

The division ratio is as follows:

000: sys_bus2_ck = sys_bus_ck

001: sys_bus2_ck = sys_bus_ck / 2 (default after reset)

010: sys_bus2_ck = sys_bus_ck / 4

011: sys_bus2_ck = sys_bus_ck / 8

100: sys_bus2_ck = sys_bus_ck / 16

101: sys_bus2_ck = sys_bus_ck / 32

110: sys_bus2_ck = sys_bus_ck / 64

111: sys_bus2_ck = sys_bus_ck / 128

Bit 19 Reserved, must be kept at reset value.

This bitfield is security-protected by SYSSEC or SYSPRIV, and is publicly readable if SYSPUB = 1. It is set and reset by software to control the division factor of rcc_pclk5.

000: rcc_pclk5 = sys_bus2_ck (default after reset)

001: rcc_pclk5 = sys_bus2_ck / 2

010: rcc_pclk5 = sys_bus2_ck / 4

011: rcc_pclk5 = sys_bus2_ck / 8

100: rcc_pclk5 = sys_bus2_ck / 16

101: rcc_pclk5 = sys_bus2_ck / 32

110: rcc_pclk5 = sys_bus2_ck / 64

111: rcc_pclk5 = sys_bus2_ck / 128

Bit 15 Reserved, must be kept at reset value.

This bitfield is security-protected by SYSSEC or SYSPRIV, and is publicly readable if SYSPUB = 1. It is set and reset by software to control the division factor of rcc_pclk4.

000: rcc_pclk4 = sys_bus2_ck (default after reset)

001: rcc_pclk4 = sys_bus2_ck / 2

010: rcc_pclk4 = sys_bus2_ck / 4

011: rcc_pclk4 = sys_bus2_ck / 8

100: rcc_pclk4 = sys_bus2_ck / 16

101: rcc_pclk4 = sys_bus2_ck / 32

110: rcc_pclk4 = sys_bus2_ck / 64

111: rcc_pclk4 = sys_bus2_ck / 128

Bits 11:7 Reserved, must be kept at reset value.

Bits 6:4 PPRE2[2:0] : CPU domain APB2 prescaler

This bitfield is security-protected by SYSSEC or SYSPRIV, and is publicly readable if SYSPUB = 1. It is set and reset by software to control the division factor of rcc_pclk2.

• 000: rcc_pclk2 = sys_bus2_ck (default after reset)
• 001: rcc_pclk2 = sys_bus2_ck / 2
• 010: rcc_pclk2 = sys_bus2_ck / 4
• 011: rcc_pclk2 = sys_bus2_ck / 8
• 100: rcc_pclk2 = sys_bus2_ck / 16
• 101: rcc_pclk2 = sys_bus2_ck / 32
• 110: rcc_pclk2 = sys_bus2_ck / 64
• 111: rcc_pclk2 = sys_bus2_ck / 128

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 PPRE1[2:0] : CPU domain APB1 prescaler

This bitfield is security-protected by SYSSEC or SYSPRIV, and is publicly readable if SYSPUB = 1. Is it set and reset by software to control the division factor of rcc_pclk1.

• 000: rcc_pclk1 = sys_bus2_ck (default after reset)
• 001: rcc_pclk1 = sys_bus2_ck / 2
• 010: rcc_pclk1 = sys_bus2_ck / 4
• 011: rcc_pclk1 = sys_bus2_ck / 8
• 100: rcc_pclk1 = sys_bus2_ck / 16
• 101: rcc_pclk1 = sys_bus2_ck / 32
• 110: rcc_pclk1 = sys_bus2_ck / 64
• 111: rcc_pclk1 = sys_bus2_ck / 128

14.10.6 RCC backup domain protection register (RCC_BDCR)

Address offset: 0x2C

Reset value: 0x0000 0000

This register controls the reset of the backup domain. It is reset by pwr_vsw_rstn, and is in the V _BKP voltage domain.

Bit 31 VSWRST : V _switch (V _SW ) domain software reset.

This bit is write-protected by the pwr_lock_backup_n signal. It is security-protected by a SEC signal from RIFSC, the RSTSEC bit, a PRIV signal from RIFSC, or the RSTPRIV bit, and is publicly readable if RSTPUB = 1. Writing 1 to this VSWRST bit by software generates a pulse that resets the V _SW domain.

• 0: V _SW domain not reset (default after reset)
• 1: V _SW domain reset

Bits 30:0 Reserved, must be kept at reset value.

14.10.7 RCC reset status register for hardware (RCC_HWSRSR)

Address offset: 0x30

Reset value: 0x00A0 0000

This register is used to monitor the resets that occurred. It is reset by pwr_por_rstn, and is in the V _BKP voltage domain.

Bit 31 Reserved, must be kept at reset value.

Bit 30 LPWRRSTF : Illegal Stop or Standby flag

This bit is set by hardware when the CPU goes erroneously in Stop or Standby mode. It is reset by software by writing HWRMVF.
0: No illegal reset occurred (default after power-on reset)
1: Illegal Stop or Standby reset occurred

Bit 29 Reserved, must be kept at reset value.

Bit 28 WWDGRSTF : Window watchdog reset flag

This bit is set by hardware when a window watchdog reset occurs. it is reset by software by writing HWRMVF.
0: No window watchdog reset occurred from WWDG (default after power-on reset)
1: Window watchdog reset occurred from WWDG

Bit 27 Reserved, must be kept at reset value.

Bit 26 IWDGRSTF : Independent watchdog reset flag

This bit is set by hardware when an independent watchdog reset occurs. It is reset by software by writing HWRMVF.
0: No independent watchdog reset occurred (default after power-on reset)
1: Independent watchdog reset occurred

Bit 25 Reserved, must be kept at reset value.

Bit 24 SFTRSTF : Software system reset flag

This bit is set by hardware when the software system reset is due to the CPU. The CPU can generate a software system reset by writing SYSRESETREQ in AIRCR register of the CPU. This bit is reset by software by writing HWRMVF.
0: No software system reset occurred (default after power-on reset)
1: A software system reset has been generated by the CPU.

Bit 23 PORRSTF : POR/PDR reset flag

This bit is set by hardware when a POR/PDR occurs. it is reset by software by writing HWRMVF.
0: No POR/PDR occurred
1: POR/PDR occurred (default after power-on reset)

Bit 22 PINRSTF : Pin reset flag (NRST)

This bit is set by hardware when a reset from pin occurs. it is reset by software by writing HWRMVF.

0: No reset from pin occurred

1: Reset from pin occurred (default after power-on reset)

Bit 21 BORRSTF : BOR reset flag

This bit is set by hardware when a BOR occurs (pwr_bor_rst). it is reset by software by writing HWRMVF.

0: No BOR occurred

1: BOR occurred (default after power-on reset)

Bits 20:18 Reserved, must be kept at reset value.

Bit 17 LCKRSTF : CPU lockup reset flag

This bit is set by hardware when a reset from a CPU lockup occurs. Is it reset by software by writing RMVF.

0: No reset from CPU lockup occurred

1: Reset from CPU lockup occurred

Bit 16 RMVF : Remove reset flag

This bit is write-protected by the security bit. It is security-protected by a SEC signal from RIFSC, the RSTSEC bit, a PRIV signal from RIFSC, or the RSTPRIV bit, and is publicly readable if RSTPUB = 1. This bit is written by software to clear the value of the reset flags in this register.

0: Clear of the reset flags not activated (default after power-on reset)

1: Clear the value of the reset flags

Bits 15:0 Reserved, must be kept at reset value.

14.10.8 RCC reset register (RCC_RSR)

Address offset: 0x34

Reset value: 0x00A0 0000

This register is used to monitor the resets that occurred. It is reset by pwr_por_rstn, and is in the V _BKP voltage domain.

Bit 31 Reserved, must be kept at reset value.

Bit 30 LPWRRSTF : Illegal Stop or Standby flag

This bit is set by hardware when the CPU goes erroneously in Stop or Standby mode. It is reset by software by writing RMVF.

0: No illegal reset occurred (default after power-on reset)

1: Illegal Stop or Standby reset occurred

Bit 29 Reserved, must be kept at reset value.

1. Bit 28 WWDGRSTF : Window watchdog reset flag
   This bit is set by hardware when a window watchdog reset occurs. It is reset by software by writing RMVF.
   0: No window watchdog reset occurred from WWDG (default after power-on reset)
   1: Window watchdog reset occurred from WWDG
2. Bit 27 Reserved, must be kept at reset value.
3. Bit 26 IWDGRSTF : Independent watchdog reset flag
   This bit is set by hardware when an independent watchdog reset occurs. It is reset by software by writing RMVF.
   0: No independent watchdog reset occurred (default after power-on reset)
   1: Independent watchdog reset occurred
4. Bit 25 Reserved, must be kept at reset value.
5. Bit 24 SFTRSTF : Software system reset flag
   This bit is set by hardware when the software system reset is due to the CPU. The CPU can generate a software system reset by writing SYSRESETREQ in AIRCR register of the CPU. This bit is reset by software by writing RMVF.
   0: No software system reset occurred (default after power-on reset)
   1: A software system reset has been generated by the CPU.
6. Bit 23 PORRSTF : POR/PDR reset flag
   This bit is set by hardware when a POR/PDR occurs. It is reset by software by writing RMVF.
   0: No POR/PDR occurred
   1: POR/PDR occurred (default after power-on reset)
7. Bit 22 PINRSTF : Pin reset flag (NRST)
   This bit is set by hardware when a reset from pin occurs. It is reset by software by writing RMVF.
   0: No reset from pin occurred
   1: Reset from pin occurred (default after power-on reset)
8. Bit 21 BORRSTF : BOR reset flag
   This bit is set by hardware when a BOR occurs (pwr_bor_rst). It is reset by software by writing RMVF.
   0: No BOR occurred
   1: BOR occurred (default after power-on reset)
9. Bits 20:18 Reserved, must be kept at reset value.
10. Bit 17 LCKRSTF : CPU lockup reset flag
    This bit is set by hardware when a reset from a CPU lockup occurs. it is reset by software by writing RMVF.
    0: No reset from CPU lockup occurred
    1: Reset from CPU lockup occurred
11. Bit 16 RMVF : Remove reset flag
    This bit is write-protected by the security bit. It is security-protected by a SEC signal from RIFSC, the SYSSEC bit, a PRIV signal from RIFSC, or the SYSPRIV bit, and is publicly readable if SYSPUB = 1. This bit is written by software to clear the value of the reset flags in this register.
    0: Clear of the reset flags not activated (default after power-on reset)
    1: Clear the value of the reset flags
12. Bits 15:0 Reserved, must be kept at reset value.

14.10.9 RCC LSE configuration register (RCC_LSECFGR)

Address offset: 0x40

Reset value: 0x0000 0000

This register is used to configure the LSE oscillator. It is reset by rcc_vsw_rstn, and is in the V _BKP voltage domain.

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:18 LSEDRV[1:0] : LSE oscillator driving capability

This bitfield is write-protected by the pwr_lock_backup_n signal. It is security-protected by LSESEC or LSEPRIV, and is publicly readable if LSEPUB = 1. it is set by software to select the driving capability of the LSE oscillator.
00: Lowest drive (default after reset)
01: Medium-high drive
10: Medium-low drive
11: Highest drive

Bit 17 LSEGFON : LSE clock glitch filter enable

This bit is write-protected by the pwr_lock_backup_n signal. It is security-protected by LSESEC or LSEPRIV, and is publicly readable if LSEPUB = 1. This bit is set and cleared by software to enable the LSE clock glitch filter. it t can be written only when LSE is disabled (LSE ACT = 0).
0: LSE clock glitch filter disabled (default after reset)
1: LSE clock glitch filter enabled

Bit 16 LSEEXT : LSE clock type in bypass mode

This bit is write-protected by the pwr_lock_backup_n signal. It is security-protected by LSESEC or LSEPRIV, and is publicly readable if LSEPUB = 1. This bit is set and reset by software to select the external clock type (analog or digital).
The external clock must be enabled with the LSE enable bit to be used by the device.
This LSEEXT bit can be written only if the LSE oscillator is disabled.
0: LSE in analog mode (default after reset)
1: LSE in digital mode

Bit 15 LSEBYP : LSE clock bypass

This bit is write-protected by the pwr_lock_backup_n signal. It is security-protected by LSESEC or LSEPRIV, and is publicly readable if LSEPUB = 1. This bit is set and cleared by software to bypass the oscillator with an external clock.
The external clock must be enabled with the LSE enable bit to be used by the device.
This LSEBYP bit can be written even if the LSE oscillator is disabled.
0: LSE oscillator not bypassed (default after reset)
1: LSE oscillator bypassed with an external clock

Bits 14:10 Reserved, must be kept at reset value.

Bit 9 LSECSSD : LSE clock security system (CSS) failure detection

This bit is set by hardware to indicate when a failure has been detected by the CSS on the external LSE oscillator.

0: No failure detected on the oscillator (default after reset)

1: Failure detected on the oscillator

Bit 8 LSECSSRA : LSE clock security system (CSS) rearm function

This bit is write-protected by the pwr_lock_backup_n signal. It is security-protected by LSESEC or LSEPRIV, and is publicly readable if LSEPUB = 1. This bit is set by software.

After an LSE failure detection, the software can re-enable the LSECSS by writing this bit to 1. Reading this bit returns the written value. Prior to set this bit to 1, LSECSSON must be set to 0. Refer to CSS on LSE for details.

0: Writing 0 has no effect (default after reset).

1: Writing 1 generates a rearm pulse for the LSECSS function.

Bit 7 LSECSSON : LSE clock security system (CSS) enable

This bit is write-protected by the pwr_lock_backup_n signal. It is security-protected by LSESEC or LSEPRIV, and is publicly readable if LSEPUB = 1. This bit is set by software to enable the CSS on the LSE oscillator. Refer to LSE oscillator for details on the activation and deactivation sequences. Once this LSECSSON bit is enabled, it cannot be disabled, except after an LSE failure detection (LSECSSD = 1).

0: CSS on the LSE oscillator OFF (default after reset)

1: CSS on the LSE oscillator ON

Bits 6:0 Reserved, must be kept at reset value.

14.10.10 RCC MSI configuration register (RCC_MSICFGR)

Address offset: 0x44

Reset value: 0x0000 0000

This register is used to configure the MSI oscillator. It is reset by int_sys_rstn, and is in the V _CORE voltage domain.

Bit 31 Reserved, must be kept at reset value.

Bits 30:23 MSICAL[7:0] : MSI clock calibration

This bitfield is set by hardware by option-byte loading during a system reset. It is adjusted by software through MSITRIM bitfield. This MSICAL bitfield represents the sum of the engineering-option-byte calibration value and MSITRIM[4:0] value.

Bits 22:21 Reserved, must be kept at reset value.

Bits 20:16 MSITRIM[4:0] : MSI clock trimming

This bitfield is set by software to adjust calibration. It is added to the engineering option bytes (CAL_BSEC_Fuse[7:0]) loaded during the reset phase (bsec_msi_cal[7:0]), to form the calibration trimming value.

\( MSICAL[7:0] = MSITRIM[4:0] + CAL\_BSEC\_Fuse[7:0] \) .

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 MSIFREQSEL : MSI oscillator frequency selection

This bit is set and cleared by software.

0: MSI oscillator frequency is 4 MHz (default after backup domain reset).

1: MSI oscillator frequency is 16 MHz.

Bits 8:0 Reserved, must be kept at reset value.

14.10.11 RCC HSI configuration register (RCC_HSICFGR)

Address offset: 0x48

Reset value: 0x0000 0000

This register is used to configure the HSI oscillator. It is reset by pwr_okin_vcore_rstn, and is in the V _CORE voltage domain.

Bits 31:23 HSICAL[8:0] : HSI clock calibration

This bitfield is set by hardware by option-byte loading during a system reset. It is adjusted by software through HSITRIM bitfield. This HSICAL bitfield represents the sum of the engineering option byte calibration value and HSITRIM[6:0] value.

Bits 22:16 HSITRIM[6:0] : HSI clock trimming

This bitfield is set by software to adjust calibration. It represents a signed value, added to the engineering option bytes (bsec_hsi_cal[8:0]) loaded during the reset phase (bsec_hsi_cal), to form the calibration trimming value: \( HSICAL[8:0] = HSITRIM[6:0] + bsec\_hsi\_cal[8:0] \) .

0x1-0x3F: \( bsec\_hsi\_cal[8:0] + \{V\} \)

0x40-0x7F: \( bsec\_hsi\_cal[8:0] - 128 + \{V\} \)

0x00: \( bsec\_hsi\_cal[8:0] \) (default after reset)

Bits 15:9 Reserved, must be kept at reset value.

Bits 8:7 HSIDIV[1:0] : HSI clock divider

This bitfield is set and reset by software to control the hsi_ck frequency (see Figure 38).

00: \( hsi\_div\_ck = hsi\_ck \) (default after reset)

01: \( hsi\_div\_ck = hsi\_ck / 2 \)

10: \( hsi\_div\_ck = hsi\_ck / 4 \)

11: \( hsi\_div\_ck = hsi\_ck / 8 \)

Bits 6:0 Reserved, must be kept at reset value.

14.10.12 RCC HSI monitor control register (RCC_HSIMCR)

Address offset: 0x4C

Reset value: 0x001F 07A1

This register is used to monitor and trim of the HSI oscillator. It is reset by int_sys_rstn, and is in the \( V_{CORE} \) voltage domain.

Bit 31 HSIMONEN : HSI clock period monitor enable

This bit is set and cleared by software.

0: Writing 0 disables the HSI clock period monitoring. Reading 0 means that the HSI clock period monitoring is disabled.

1: Writing 1 enables the HSI clock period monitoring. Reading 1 means that the HSI clock period monitoring is enabled.

Bits 30:22 Reserved, must be kept at reset value.

Bits 21:16 HSIDEV[5:0] : HSI clock count deviation value

This bitfield is set and cleared by software.

Bits 15:11 Reserved, must be kept at reset value.

Bits 10:0 HSIREF[10:0] : HSI clock-cycle counter reference value.

This bit contains the number of HSI clock cycles expected between two consecutive rising edges of the LSE signal. It is set by hardware.

14.10.13 RCC HSI monitor status register (RCC_HSIMSR)

Address offset: 0x50

Reset value: 0x0000 0000

This register is used to monitor and trim of the HSI oscillator. It is reset by int_sys_rstn, and is in the \( V_{CORE} \) voltage domain.

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 HSIVAL[10:0] : HSI clock-cycle counter measured value

This bitfield contains the number of HSI clock cycles measured between consecutive rising edges of the LSE signal. It is set by hardware.

14.10.14 RCC HSE configuration register (RCC_HSECFGR)

Address offset: 0x54

Reset value: 0x0000 0800

This register is used to configure the HSE oscillator. It is reset by int_sys_rstn, and is in the V _CORE voltage domain.

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 HSEEXT : HSE clock type in bypass mode

This bit is set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSE enable bit to be used by the device. This HSEEXT bit can be written only if the HSE oscillator is disabled.

0: HSE in analog mode (default after reset)

1: HSE in digital mode

Bit 15 HSEBYP : HSE clock bypass

This bit is set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSE enable bit to be used by the device. This HSEBYP bit can be written even if the HSE oscillator is disabled.

0: HSE oscillator not bypassed (default after reset)

1: HSE oscillator bypassed with an external clock

Bits 14:11 HSECSSBPRE[3:0] : HSE CSS bypass divider

This bitfield is set and reset by software to divide the replacement internal HSI oscillator that bypasses the HSE oscillator when a failure is detected. Refer to HSE oscillator for details on the activation and deactivation sequences.

0000: HSI clock divided by 1

0001: HSI clock divided by 2

0010: HSI clock divided by 3

0011: HSI clock divided by 4

0100: HSI clock divided by 5

0101: HSI clock divided by 6

0110: HSI clock divided by 7

0111: HSI clock divided by 8

1000: HSI clock divided by 9

1001: HSI clock divided by 10

1010: HSI clock divided by 11

1011: HSI clock divided by 12

1100: HSI clock divided by 13

1101: HSI clock divided by 14

1110: HSI clock divided by 15

1111: HSI clock divided by 16

Bit 10 HSECSSBYP : HSE CSS bypass enable

This bit is set and reset by software to enable the CSS to bypass the HSE oscillator when a failure is detected, and to get a clock from the HSI oscillator. Refer to HSE oscillator for details on the activation and deactivation sequences.

0: CSS bypass of the HSE oscillator OFF (default after reset)

1: CSS bypass on the HSE oscillator ON

Bit 9 HSECSSD : HSE CSS failure detection

This bit is set by hardware to indicate when a failure has been detected by the CSS on the external HSE oscillator.

0: No failure detected on the oscillator (default after reset)

1: Failure detected on the oscillator

Bit 8 Reserved, must be kept at reset value.

Bit 7 HSECSSON : HSE CSS enable

This bit is set by software to enable the CSS on the HSE oscillator. Refer to HSE oscillator for details on the activation and deactivation sequences. Once this HSECSSON bit is enabled, it cannot be disabled, except after an HSE failure detection (HSECSSD = 1).

0: CSS on the HSE oscillator OFF (default after reset)

1: CSS on the HSE oscillator ON

Bit 6 HSEDI2SEL : HSE div2 clock source select

This bit is set and reset by software to select the source of the div2 output clock.

0: HSE: hse_div2_osc_ck = hse_osc_ck (default after reset)

1: HSE: hse_div2_osc_ck = hse_osc_ck/2

Bits 5:0 Reserved, must be kept at reset value.

14.10.15 RCC PLL1 configuration register 1 (RCC_PLL1CFGR1)

Address offset: 0x80

Reset value: 0x0820 2500

This register is used to configure the main features of PLL1. It is reset by int_sys_rst,n and is in the V _CORE voltage domain.

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 PLL1SEL[2:0] : PLL1 source selection of the reference clock

This bitfield is set and reset by software to select system clock source (sys_ck).

000: hsi_ck selected as reference clock

001: msi_ck selected as reference clock

010: hse_ck selected as reference clock

011: I2S_CKIN selected as reference clock

This bit is set and cleared by software to bypass the VCO, and to feed the output with the PLL reference clock.

0: PLL output is driven by the VCO, via the optional POSTDIV division.

1: PLL output is bypassed and driven by the PLL reference clock (default after reset).

Bit 26 Reserved, must be kept at reset value.

This bitfield is set and cleared by software.

0x00: Not applicable when the PLL is enabled

0x01: Reference clock divided by 1 (min value)

0x2-0x3F: Reference clock divided by {v}. It is recommended to configure the maximum divided reference clock frequency close to \( F_{VCO} / 16 \) .

This bitfield is set and cleared by software to control the multiplication factor of the VCO.

VCO output frequency = reference clock * DIVN / DIVM when FRACV = 0.

In integer mode, this value must be set between 0x10 (16) and 0x280 (640).

In fractional mode, this value must be set between 0x14 (20) and 0x140 (320).

Bits 7:0 Reserved, must be kept at reset value.

14.10.16 RCC PLL1 configuration register 2 (RCC_PLL1CFGR2)

Address offset: 0x84

Reset value: 0x0080 0000

This register is used to configure the optional fractional feedback division of PLL1. It is reset by int_sys_rstn, and is in the V _CORE voltage domain.

Bits 31:24 Reserved, must be kept at reset value.

This bitfield is set and cleared by software to control the VCO fractional multiplication factor.

VCO output frequency = reference clock * \( (DIVN + DIVNFRAC / 2^{24}) / DIVM \) .

14.10.17 RCC PLL1 configuration register 3 (RCC_PLL1CFGR3)

Address offset: 0x88

Reset value: 0x4900 000D

This register is used to configure the SSCG and optional inner features of PLL1. It is reset by int_sys_rstn, and is in the V _CORE voltage domain.

Bit 31 Reserved, must be kept at reset value.

Bit 30 PLL1PDIVEN : PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable

This bit is set and cleared by software to enable the post divider.

0: POSTDIV1 and POSTDIV2 powered down

1: POSTDIV1 and POSTDIV2 active (default after reset)

Bits 29:27 PLL1PDIV1[2:0] : PLL1 VCO frequency divider level 1

This bitfield is set and cleared by software to divide the VCO frequency output.

000: Not applicable

001: VCO output divided by 1 (minimum value) (default after reset)

010: VCO output divided by 2

011: VCO output divided by 3

100: VCO output divided by 4

101: VCO output divided by 5

110: VCO output divided by 6

111: VCO output divided by 7

Bits 26:24 PLL1PDIV2[2:0] : PLL1 VCO frequency divider level 2

This bitfield is set and cleared by software to divide the VCO frequency output.

000: Not applicable

001: VCO output divided by 1 (minimum value) (default after reset)

010: VCO output divided by 2

011: VCO output divided by 3

100: VCO output divided by 4

101: VCO output divided by 5

110: VCO output divided by 6

111: VCO output divided by 7

Bits 23:21 Reserved, must be kept at reset value.

Bits 20:16 PLL1MODSPR[4:0] : PLL1 modulation spread depth adjustment

This bitfield is set and cleared by software to adjust the modulation depth of the clock spreading generator.

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:8 PLL1MODDIV[3:0] : PLL1 modulation division frequency adjustment

This bitfield is set and cleared by software to adjust the modulation frequency of the clock spreading generator. Corresponds to DIVVAL in Figure 44 .

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 PLL1MODSPRDW : PLL1 modulation spread spectrum down

This bit is set and cleared by software to select the clock spreading mode of PLL1.

0: Center-spread modulation selected (default after reset)

1: Down-spread modulation selected

Bit 3 PLL1MODDSEN : PLL1 modulation spread spectrum (and fractional divide) enable

This bit is set and cleared by software to enable the delta-sigma modulator.

0: Modulation spread spectrum and fractional divide not active

1: Modulation spread spectrum and fractional divide active (default after reset)

Bit 2 PLL1MODSSDIS : PLL1 modulation spread spectrum disable

This bit is set and cleared by software to enable the clock spreading generator of PLL1.

0: Modulation spread spectrum active (and fractional divide inactive)

1: Fractional divide active (and modulation spread spectrum inactive) (default after reset)

Bit 1 PLL1DACEN : PLL1 noise canceling DAC enable in fractional mode

This bit is set and cleared by software to enable the noise cancellation in fractional mode.

0: DAC not active (default after reset)

1: DAC active

Bit 0 PLL1MODSSRST : PLL1 modulation spread spectrum reset

This bit is set and cleared by software.

0: PLL1 modulation spread spectrum reset module released

1: PLL1 modulation spread spectrum reset module asserted (default after reset)

14.10.18 RCC PLL2 configuration register 1 (RCC_PLL2CFGR1)

Address offset: 0x90

Reset value: 0x0800 0000

This register is used to configure the main features of PLL2. It is reset by int_sys_rstn , and is in the \( V_{CORE} \) voltage domain.

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 PLL2SEL[2:0] : PLL2 source selection of the reference clock

This bitfield is set and reset by software to select system clock source ( sys_ck ).

000: hsi_ck selected as reference clock

001: msi_ck selected as reference clock

010: hse_ck selected as reference clock

011: I2S_CKIN selected as reference clock

Bit 27 PLL2BYP : PLL2 bypass

This bit is set and cleared by software to bypass the VCO and to feed the output with the PLL reference clock.

0: PLL output is driven by the VCO, via the optional POSTDIV division.

1: PLL output is bypassed and driven by the PLL reference clock (default after reset).

Bit 26 Reserved, must be kept at reset value.

Bits 25:20 PLL2DIVM[5:0] : PLL2 reference input clock divide frequency ratio

This bitfield is set and cleared by software.

0x2-0x3F: Reference clock is divided by {v}. The maximum divided reference clock frequency must be close to \( F_{VCO}/16 \) .

0x00: Not applicable when PLL is enabled

0x01: Reference clock is divided by 1 (min value).

Bits 19:8 PLL2DIVN[11:0] : PLL2 integer part for the VCO multiplication factor

This bitfield is set and cleared by software to control the multiplication factor of the VCO.

VCO output frequency = reference clock * DIVN / DIVM when FRACV = 0.

In integer mode, this value must be set between 0x10 (16) and 0x280 (640).

In fractional mode, this value must be set between 0x14 (20) and 0x140 (320).

Bits 7:0 Reserved, must be kept at reset value.

14.10.19 RCC PLL2 configuration register 2 (RCC_PLL2CFGR2)

Address offset: 0x94

Reset value: 0x0000 0000

This register is used to configure the optional fractional feedback division of PLL2. It is reset by int_sys_rstn , and is in the \( V_{CORE} \) voltage domain.

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:0 PLL2DIVNFRAC[23:0] : PLL2 fractional part of the VCO multiplication factor

This bitfield is set and cleared by software to control the VCO fractional multiplication factor.

VCO output frequency = reference clock * (DIVN + DIVNFRAC / \( 2^{24} \) ) / DIVM.

14.10.20 RCC PLL2 configuration register 3 (RCC_PLL2CFGR3)

Address offset: 0x98

Reset value: 0x4900 0005

This register is used to configure the SSCG and optional inner features of PLL2. It is reset by int_sys_rstn, and is in the V _CORE voltage domain.

Bit 31 Reserved, must be kept at reset value.

Bit 30 PLL2PDIVEN : PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable

This bit is set and cleared by software to enable the post divider.

0: POSTDIV1 and POSTDIV2 powered down

1: POSTDIV1 and POSTDIV2 active (default after reset)

Bits 29:27 PLL2PDIV1[2:0] : PLL2 VCO frequency divider level 1

This bitfield is set and cleared by software to divide the VCO frequency output.

000: Not applicable

001: VCO output divided by 1 (minimum value) (default after reset)

010: VCO output divided by 2

011: VCO output divided by 3

100: VCO output divided by 4

101: VCO output divided by 5

110: VCO output divided by 6

111: VCO output divided by 7

Bits 26:24 PLL2PDIV2[2:0] : PLL2 VCO frequency divider level 2

This bitfield is set and cleared by software to divide the VCO frequency output.

000: Not applicable

001: VCO output divided by 1 (minimum value) (default after reset)

010: VCO output divided by 2

011: VCO output divided by 3

100: VCO output divided by 4

101: VCO output divided by 5

110: VCO output divided by 6

111: VCO output divided by 7

Bits 23:21 Reserved, must be kept at reset value.

Bits 20:16 PLL2MODSPR[4:0] : PLL2 modulation spread depth adjustment

This bitfield is set and cleared by software to adjust the modulation depth of the clock spreading generator.

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:8 PLL2MODDIV[3:0] : PLL2 modulation division frequency adjustment

This bitfield is set and cleared by software to adjust the modulation frequency of the clock spreading generator. It corresponds to DIVVAL in Figure 44 .

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 PLL2MODSPRDW : PLL2 modulation down spread

This bit is set and cleared by software to select the clock spreading mode of PLL2.

0: Center-spread modulation selected (default after reset)

1: Down-spread modulation selected

Bit 3 PLL2MODDSEN : PLL2 modulation spread spectrum (and fractional divide) enable

This bit is set and cleared by software to enable the delta-sigma modulator.

0: Modulation spread spectrum and fractional divide not active (default after reset)

1: Modulation spread spectrum and fractional divide active

Bit 2 PLL2MODSSDIS : PLL2 modulation spread spectrum disable

This bit is set and cleared by software to enable the clock spreading generator of PLL2.

0: Modulation spread spectrum active (and fractional divide inactive)

1: Fractional divide active (and the Modulation spread spectrum inactive) (default after reset)

Bit 1 PLL2DACEN : PLL2 noise canceling DAC enable in fractional mode

This bit is set and cleared by software to enable the noise cancellation in fractional mode.

0: DAC not active (default after reset)

1: DAC active

Bit 0 PLL2MODSSRST : PLL2 modulation spread spectrum reset

This bit is set and cleared by software.

0: PLL2 modulation spread spectrum reset module released

1: PLL2 modulation spread spectrum reset module asserted (default after reset)

14.10.21 RCC PLL3 configuration register 1 (RCC_PLL3CFGR1)

Address offset: 0xA0

Reset value: 0x0800 0000

This register is used to configure the main features of PLL3. It is reset by int_sys_rstn , and is in the \( V_{CORE} \) voltage domain.

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 PLL3SEL[2:0] : PLL3 source selection of the reference clock

This bitfield is set and reset by software to select system clock source ( sys_ck ).

000: hsi_ck selected as reference clock

001: msi_ck selected as reference clock

010: hse_ck selected as reference clock

011: I2S_CKIN selected as reference clock

Bit 27 PLL3BYP : PLL3 bypass

This bit is set and cleared by software to bypass the VCO and feed the output with the PLL reference clock.

0: PLL output is driven by the VCO, via the optional POSTDIV division.

1: PLL output is bypassed and driven by the PLL reference clock (default after reset).

Bit 26 Reserved, must be kept at reset value.

Bits 25:20 PLL3DIVM[5:0] : PLL3 reference input clock divide frequency ratio

This bitfield is set and cleared by software.

0x2-0x3F: Reference clock is divided by {v}. The maximum divided reference clock frequency must be close to \( F_{VCO}/16 \) .

0x00: Not applicable when PLL is enabled

0x01: Reference clock is divided by 1 (min value)

Bits 19:8 PLL3DIVN[11:0] : PLL3 Integer part for the VCO multiplication factor

This bitfield is set and cleared by software to control the multiplication factor of the VCO.

VCO output frequency = reference clock * DIVN / DIVM when FRACV = 0.

In integer mode, this value must be set between 0x10 (16) and 0x280 (640).

In fractional mode, this value must be set between 0x14 (20) and 0x140 (320).

Bits 7:0 Reserved, must be kept at reset value.

14.10.22 RCC PLL3 configuration register 2 (RCC_PLL3CFGR2)

Address offset: 0xA4

Reset value: 0x0000 0000

This register is used to configure the optional fractional feedback division of PLL3. It is reset by int_sys_rstn , and is in the \( V_{CORE} \) voltage domain.

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:0 PLL3DIVNFRAC[23:0] : PLL3 fractional part of the VCO multiplication factor

This bitfield is set and cleared by software to control the VCO fractional multiplication factor.

VCO output frequency = reference clock * (DIVN + DIVNFRAC / \( 2^{24} \) ) / DIVM.

14.10.23 RCC PLL3 configuration register 3 (RCC_PLL3CFGR3)

Address offset: 0xA8

Reset value: 0x4900 0005

This register is used to configure the SSCG and optional inner features of PLL3. It is reset by int_sys_rstn, and is in the V _CORE voltage domain.

Bit 31 Reserved, must be kept at reset value.

Bit 30 PLL3PDIVEN : PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable

This bit is set and cleared by software to enable the post divider.

0: POSTDIV1 and POSTDIV2 powered down

1: POSTDIV1 and POSTDIV2 active (default after reset)

Bits 29:27 PLL3PDIV1[2:0] : PLL3 VCO frequency divider level 1

This bitfield is set and cleared by software to divide the VCO frequency output.

000: Not applicable

001: VCO output divided by 1 (minimum value) (default after reset)

010: VCO output divided by 2

011: VCO output divided by 3

100: VCO output divided by 4

101: VCO output divided by 5

110: VCO output divided by 6

111: VCO output divided by 7

Bits 26:24 PLL3PDIV2[2:0] : PLL3 VCO frequency divider level 2

This bitfield is set and cleared by software to divide the VCO frequency output.

000: Not applicable

001: VCO output divided by 1 (minimum value) (default after reset)

010: VCO output divided by 2

011: VCO output divided by 3

100: VCO output divided by 4

101: VCO output divided by 5

110: VCO output divided by 6

111: VCO output divided by 7

Bits 23:21 Reserved, must be kept at reset value.

Bits 20:16 PLL3MODSPR[4:0] : PLL3 modulation spread depth adjustment

This bitfield is set and cleared by software to adjust the modulation depth of the clock spreading generator.

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:8 PLL3MODDIV[3:0] : PLL3 modulation division frequency adjustment

This bitfield is set and cleared by software to adjust the modulation frequency of the clock spreading generator. It corresponds to DIVVAL in Figure 44 .

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 PLL3MODSPRDW : PLL3 modulation down spread

This bit is set and cleared by software to select the clock spreading mode of PLL3.

0: Center-spread modulation selected (default after reset)

1: Down-spread modulation selected

Bit 3 PLL3MODDSEN : PLL3 modulation spread spectrum (and fractional divide) enable

This bit is set and cleared by software to enable the delta-sigma modulator.

0: Modulation spread spectrum and fractional divide not active (default after reset)

1: Modulation spread spectrum and fractional divide active

Bit 2 PLL3MODSSDIS : PLL3 modulation spread spectrum disable

This bit is set and cleared by software to enable the clock spreading generator of PLL3.

0: Modulation spread spectrum active (and fractional divide inactive)

1: Fractional divide active (and the modulation spread spectrum inactive) (default after reset)

Bit 1 PLL3DACEN : PLL3 noise canceling DAC enable in fractional mode

This bit is set and cleared by software to enable the noise cancellation in fractional mode.

0: DAC not active (default after reset)

1: DAC active

Bit 0 PLL3MODSSRST : PLL3 modulation spread spectrum reset

This bit is set and cleared by software.

0: PLL3 modulation spread spectrum reset module released

1: PLL3 modulation spread spectrum reset module asserted (default after reset)

14.10.24 RCC PLL4 configuration register 1 (RCC_PLL4CFGR1)

Address offset: 0xB0

Reset value: 0x0800 0000

This register is used to configure the main features of PLL4. It is reset by int_sys_rstn, and is in the V _CORE voltage domain.

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 PLL4SEL[2:0] : PLL4 source selection of the reference clock

This bitfield is set and reset by software to select system clock source (sys_ck).

000: hsi_ck selected as reference clock

001: msi_ck selected as reference clock

010: hse_ck selected as reference clock

011: I2S_CKIN selected as reference clock

Bit 27 PLL4BYP : PLL4 bypass

This bit is set and cleared by software to bypass the VCO, and to feed the output with the PLL reference clock.

0: PLL output is driven by the VCO, via the optional POSTDIV division.

1: PLL output is bypassed and driven by the PLL reference clock (default after reset).

Bit 26 Reserved, must be kept at reset value.

Bits 25:20 PLL4DIVM[5:0] : PLL4 reference input clock divide frequency ratio

This bitfield is set and cleared by software.

0x2-0x3F: Reference clock is divided by {v}. The maximum divided reference clock frequency must be close to \( F_{VCO}/16 \) .

0x00: Not applicable when PLL is enabled

0x01: Reference clock is divided by 1 (min value).

Bits 19:8 PLL4DIVN[11:0] : PLL4 integer part for the VCO multiplication factor

This bitfield is set and cleared by software to control the multiplication factor of the VCO.

VCO output frequency = reference clock * DIVN / DIVM when FRACV = 0.

In integer mode, this value must be set between 0x10 (16) and 0x280 (640).

In fractional mode, this value must be set between 0x14 (20) and 0x140 (320).

Bits 7:0 Reserved, must be kept at reset value.

14.10.25 RCC PLL4 configuration register 2 (RCC_PLL4CFGR2)

Address offset: 0xB4

Reset value: 0x0000 0000

This register is used to configure the optional fractional feedback division of PLL4. It is reset by int_sys_rstn , and is in the \( V_{CORE} \) voltage domain.

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:0 PLL4DIVNFRAC[23:0] : PLL4 fractional part of the VCO multiplication factor

This bitfield is set and cleared by software to control the VCO fractional multiplication factor.

VCO output frequency = reference clock * (DIVN + DIVNFRAC / \( 2^{24} \) ) / DIVM.

14.10.26 RCC PLL4 configuration register 3 (RCC_PLL4CFGR3)

Address offset: 0xB8

Reset value: 0x4900 0005

This register is used to configure the SSCG and optional inner features of PLL4. It is reset by int_sys_rstn , and is in the \( V_{CORE} \) voltage domain.

Bit 31 Reserved, must be kept at reset value.

Bit 30 PLL4PDIVEN : PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable

This bit is set and cleared by software to enable the post divider.

0: POSTDIV1 and POSTDIV2 powered down

1: POSTDIV1 and POSTDIV2 active (default after reset)

Bits 29:27 PLL4PDIV1[2:0] : PLL4 VCO frequency divider level 1

This bitfield is set and cleared by software to divide the VCO frequency output.

000: Not applicable

001: VCO output divided by 1 (minimum value) (default after reset)

010: VCO output divided by 2

011: VCO output divided by 3

100: VCO output divided by 4

101: VCO output divided by 5

110: VCO output divided by 6

111: VCO output divided by 7

Bits 26:24 PLL4PDIV2[2:0] : PLL4 VCO frequency divider level 2

This bitfield is set and cleared by software to divide the VCO frequency output.

000: Not applicable

001: VCO output divided by 1 (minimum value) (default after reset)

010: VCO output divided by 2

011: VCO output divided by 3

100: VCO output divided by 4

101: VCO output divided by 5

110: VCO output divided by 6

111: VCO output divided by 7

Bits 23:21 Reserved, must be kept at reset value.

Bits 20:16 PLL4MODSPR[4:0] : PLL4 modulation spread depth adjustment

This bitfield is set and cleared by software to adjust the modulation depth of the clock spreading generator.

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:8 PLL4MODDIV[3:0] : PLL4 modulation division frequency adjustment

This bitfield is set and cleared by software to adjust the modulation frequency of the clock spreading generator. It corresponds to DIVVAL in Figure 44 .

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 PLL4MODSPRDW : PLL4 modulation down spread

This bit is set and cleared by software to select the clock spreading mode of PLL4.

0: Center-spread modulation selected (default after reset)

1: Down-spread modulation selected

Bit 3 PLL4MODDSEN : PLL4 modulation spread spectrum (and fractional divide) enable

This bitfield is set and cleared by software to enable the delta-sigma modulator.

0: Modulation spread spectrum and fractional divide not active (default after reset)

1: Modulation spread spectrum and fractional divide active

Bit 2 PLL4MODSSDIS : PLL4 modulation spread spectrum disable

This bit is set and cleared by software to enable the clock spreading generator of PLL4.

0: Modulation spread spectrum active (and fractional divide inactive)

1: Fractional divide active (and modulation spread spectrum inactive) (default after reset)

Bit 1 PLL4DACEN : PLL4 noise canceling DAC enable in fractional mode

This bit is set and cleared by software to enable the noise cancellation in fractional mode.

0: DAC not active (default after reset)

1: DAC active

Bit 0 PLL4MODSSRST : PLL4 modulation spread spectrum reset

This bit is set and cleared by software.

0: PLL4 modulation spread spectrum reset module released

1: PLL4 modulation spread spectrum reset module asserted (default after reset)

14.10.27 RCC IC1 configuration register (RCC_IC1CFGR)

Address offset: 0xC4

Reset value: 0x0002 0000

This register is used to configure the IC1 divider. It is reset by int_sys_rstn , and is in the \( V_{CORE} \) voltage domain.