9. Boot modes
9.1 Boot after system reset
The ROM code is the first one executed after any system reset.
The boot mode is determined by BOOT0 and BOOT1 pins, and one OTP word.
Table 32. Boot modes
| BOOT0 | BOOT1 | Boot source #1 |
|---|---|---|
| - | 1 | Development boot |
| 0 | 0 | Flash boot |
| 1 | 0 | Serial boot |
BOOT0 is a dedicated pin latched upon reset release.
The BOOT1 is a non dedicated boot pin. The BOOT1 value comes from BOOT1 pin (default pin), or any other pin defined by BSEC_BOOTROM_CONFIG10 - OTP_WORD19[28:21] = dev_boot_port + dev_boot_pins, see Table 18: OTP fuse description (lower OTP region) .
9.1.1 Flash boot
If a flash boot is selected, the firmware is loaded from an external flash memory. The flash source selection is done through BOOTROM_CONFIG2 - OTP_WORD11[8:5] = boot_source (4 bits). The possible sources are listed below:
- • XSPI serial NOR (in SPI mode, single)
- • XSPI HyperFlash™ (8-bit)
- • e.MMC™ SDMMC1 or e.MMC™ SDMMC2 (up to JEDEC v5.1)
- • SD-Card SDMMC1 (up to SD standard v6.0)
See Table 18: OTP fuse description (lower OTP region) .
If no boot source is programmed in OTP, default source is serial NOR.
9.1.2 Serial boot
If serial boot is selected, the image is loaded from a serial interface. Serial interfaces and serial instances can be disabled by BOOTROM_CONFIG2 - OTP_WORD11[16:9] = boot_source_disable (8 bits).
Possible sources are:
- • USB boot: USB 2.0 OTG HS
- • UART boot: USART1, USART2, and UART4
See Table 18: OTP fuse description (lower OTP region) .
9.1.3 Development boot
If BOOT1 is selected, the BootROM code finishes in an endless loop after having reopened debug in a secure way.
This boot mode is available only when the device is in development.
Secure installation
The ROM code is the root-of-trust of secure firmware installation.
9.2 Boot from a low-power mode
In case of boot from a low-power mode (such as Standby mode with SRAM retention), the bootROM is not executed, and the CPU starts from the boot address defined in Section 16.1: SYSCFG registers .