5. OTP mapping (OTP)

STM32N6x5/x7xx devices have 12032 OTP (one-time programmable) bits, which can be read-accessed in 376 words: BSEC_OTP_DATAx (x = 0 to 375).

OTP bits are read or programmed by the BSEC (boot, security, and OTP control), as detailed in Section 4: Boot and security control (BSEC) . They are organized in regions:

• Lower OTP region (OTP0 to OTP127)
• Mid OTP region (OTP128 to OTP255)
• Upper OTP region (OTP256 to OTP375)

Before being programmed, the OTP bits are at 0. The OTP words are listed in Table 17 :

• Description: acronym and function. Words marked “Available to customer” have no predefined usage.
• Shadowed: loaded into a register after reset, can be read without a reload. A shadowed word may be sticky-write-locked by earlier software (such as BOOTROM). The first ten shadowed words are never writable.
• Prog-locked by ST: words locked during manufacturing.

Table 17. OTP mapping

Word	Description	Shadowed	Prog-locked by ST
Lower OTP region
OTP0	OTP_HW_WORD0	Yes	Yes
OTP1	OTP_HW_WORD1	Yes	No
OTP2	OTP_HW_WORD2	Yes	No
OTP3	OTP_HW_WORD3	Yes	No
OTP4	OTP_HW_WORD4	Yes	Yes
OTP5	ID0	Yes	Yes
OTP6	ID1	Yes	Yes
OTP7	ID2	Yes	Yes
OTP8	OTP_RPN_OPTION	Yes	Yes
OTP9	OTP_RPN_CODING	Yes	Yes
OTP10	BOOTROM_CONFIG_1	No	No
OTP11	BOOTROM_CONFIG_2	Yes	No
OTP12	BOOTROM_CONFIG_3	No	No
OTP13	BOOTROM_CONFIG_4	Yes	No
OTP14	BOOTROM_CONFIG_5	Yes	No
OTP15	BOOTROM_CONFIG_6	Yes	No
OTP16	BOOTROM_CONFIG_7	Yes	No
OTP17	BOOTROM_CONFIG_8	No	No
OTP18	BOOTROM_CONFIG_9	No	No

Table 17. OTP mapping (continued)

Word	Description	Shadowed	Prog-locked by ST
OTP19	BOOTROM_CONFIG_10	No	No
OTP20	BOOTROM_CONFIG_11	No	No
OTP21	BOOTROM_CONFIG_12	No	No
OTP22	BOOTROM_CONFIG_13	No	No
OTP23	BOOTROM_CONFIG_14	No	Yes
OTP24	BOOT_TZ_EPOCH0	No	No
OTP25	BOOT_TZ_EPOCH1	No	No
OTP26	BOOT_TZ_EPOCH2	No	No
OTP27	BOOT_TZ_EPOCH3	No	No
OTP28	BOOT_TZ_EPOCH4	No	No
OTP29	BOOT_TZ_EPOCH5	No	No
OTP30	BOOT_TZ_EPOCH6	No	No
OTP31	BOOT_TZ_EPOCH7	No	No
OTP32	BOOT_NS_EPOCH0	No	No
OTP33	BOOT_NS_EPOCH1	No	No
OTP34	BOOT_NS_EPOCH2	No	No
OTP35	BOOT_NS_EPOCH3	No	No
OTP36	BOOT_NS_EPOCH4	No	No
OTP37	BOOT_NS_EPOCH5	No	No
OTP38	BOOT_NS_EPOCH6	No	No
OTP39	BOOT_NS_EPOCH7	No	No
OTP40 to OTP55	Available to customer	No	No
OTP56	TAMP_EN	No	No
OTP57	TAMP_CFM	No	No
OTP58	TAMP_CFG	No	No
OTP59 to OTP95	Available to customer	No	No
OTP96 to OTP99	Reserved	-	-
OTP100 to OTP103	Reserved	-	-
OTP104 to OTP123	Reserved	-	-
OTP124	HCONF1	Yes	No
OTP125 to OTP127	Reserved	-	-
Mid OTP region
OTP128	STM32_CERTIF0	No	Yes
OTP129	STM32_CERTIF1	No	Yes
OTP130	STM32_CERTIF2	No	Yes

Table 17. OTP mapping (continued)

Word	Description	Shadowed	Prog-locked by ST
OTP131	STM32_CERTIF3	No	Yes
OTP132	STM32_CERTIF4	No	Yes
OTP133	STM32_CERTIF5	No	Yes
OTP134	STM32_CERTIF6	No	Yes
OTP135	STM32_CERTIF7	No	Yes
OTP136	STM32_CERTIF8	No	Yes
OTP137	STM32_CERTIF9	No	Yes
OTP138	STM32_CERTIF10	No	Yes
OTP139	STM32_CERTIF12	No	Yes
OTP140	STM32_CERTIF12	No	Yes
OTP141	STM32_CERTIF13	No	Yes
OTP142	STM32_CERTIF14	No	Yes
OTP143	STM32_CERTIF15	No	Yes
OTP144	STM32PUBKEY0	No	Yes
OTP145	STM32PUBKEY1	No	Yes
OTP146	STM32PUBKEY2	No	Yes
OTP147	STM32PUBKEY3	No	Yes
OTP148	STM32PUBKEY4	No	Yes
OTP149	STM32PUBKEY5	No	Yes
OTP150	STM32PUBKEY6	No	Yes
OTP151	STM32PUBKEY7	No	Yes
OTP152	STM32PUBKEY8	No	Yes
OTP153	STM32PUBKEY9	No	Yes
OTP154	STM32PUBKEY10	No	Yes
OTP155	STM32PUBKEY11	No	Yes
OTP156	STM32PUBKEY12	No	Yes
OTP157	STM32PUBKEY13	No	Yes
OTP158	STM32PUBKEY14	No	Yes
OTP159	STM32PUBKEY15	No	Yes
OTP160	OTP_ROT_HASH0	No	No
OTP161	OTP_ROT_HASH1	No	No
OTP162	OTP_ROT_HASH2	No	No
OTP163	OTP_ROT_HASH3	No	No
OTP164	OTP_ROT_HASH4	No	No
OTP165	OTP_ROT_HASH5	No	No

Table 17. OTP mapping (continued)

Word	Description	Shadowed	Prog-locked by ST
OTP166	OTP_ROT_HASH6	No	No
OTP167	OTP_ROT_HASH7	No	No
OTP168	ST_RSSE_EDMK_DERIV_CSTE_FUSE	No	Yes
OTP169	OTP_MAC1_ADDR_LOW	No	No
OTP170	OTP_MAC1_ADDR_HIGH	No	No
OTP171	OTP_MAC2_ADDR_LOW	No	No
OTP172	OTP_MAC2_ADDR_HIGH	No	No
OTP173 to OTP255	Available to customer	No	No
Upper OTP region
OTP256	OTP_RMA_LOCK_PSWD0	Yes	No
OTP257	OTP_RMA_LOCK_PSWD1	Yes	No
OTP258	OTP_RMA_LOCK_PSWD2	Yes	No
OTP259	OTP_RMA_LOCK_PSWD3	Yes	No
OTP260 to OTP363	OEM secrets available to customer	No	No
OTP364	OEM_SECRET_FOR_CRYPTED_BOOT0	No	No
OTP365	OEM_SECRET_FOR_CRYPTED_BOOT1	No	No
OTP366	OEM_SECRET_FOR_CRYPTED_BOOT2	No	No
OTP367	OEM_SECRET_FOR_CRYPTED_BOOT3	No	No
OTP368	STM32PRVKEY0	No	Yes
OTP369	STM32PRVKEY1	No	Yes
OTP370	STM32PRVKEY2	No	Yes
OTP371	STM32PRVKEY3	No	Yes
OTP372	STM32PRVKEY4	No	Yes
OTP373	STM32PRVKEY5	No	Yes
OTP374	STM32PRVKEY6	No	Yes
OTP375	STM32PRVKEY7	No	Yes

The following OTP words are described in detail in Table 18 or by BSEC:

• OTP0 to OTP4: used by BSEC for the security life cycle (see Section 4: Boot and security control (BSEC) )
• OTP9: used to code device part number (see Section 79: Device electronic signature )
• OTP10 to OTP22: used for the boot ROM configuration
• OTP56 to OTP58: used to record tamper configuration
• OTP96 to OTP99 and OTP104 to OTP 111: used for analog calibration parameters, set by ST
• OTP112 to OTP 119: used for engineering purposes, set by ST

• OTP120 to OTP123: used for settings such as analog trimming, set by ST
• OTP124: used for the product configuration by the user
• OTP125 to OTP 127: used for memory repair, set by ST.

Table 18. OTP fuse description (lower OTP region)

OTP word	OTP bits	Name or description	Detailed description
OTP0	-	OTP_HW_WORD0	OTP check word (virgin → non-virgin)
OTP1	-	OTP_HW_WORD1	OTP security word to close security state
OTP2	-	OTP_HW_WORD2	OTP word for reopening (close → open) via RMA password: RMA bits
OTP3	-	OTP_HW_WORD3	OTP word for reopening (close → open) via RMA password: RMA tries bits
OTP4	-	OTP_HW_WORD4	OTP word for TK retries (ECIES) and retention cell disabling
OTP5	-	ID0	96-bit unique ID for engineering purpose
OTP6	-	ID1
OTP7	-	ID2
OTP8	-	OTP_RPN_CODING	Reserved
OTP9	-	RPN_CODING	See Section 79: Device electronic signature
OTP10	-	BOOTROM_CONFIG_1	Boot source configuration word
	[0]	stkeyprov_ecies_attempted	Status of ECIES ST key provisioning when it was attempted: – 0 (failed): ECIES ST key provisioning last attempt failed – 1 (successful): ECIES ST key provisioning last attempt successful
	[1]	stkeyprov_ecies_ok	– 0 (no): HWKEY not provisioned – 1 (yes): HWKEY provisioned
	[6:2]	Reserved	Reserved
	[14:7]	security_counter	Security counter involved in product ID for chip certificate verification by HSM-OEM in SFI context
	[18:15]	st_pub_key_id	ST ECDSA public key ID (ST key instance fuse part) involved in product ID for chip certificate verification by HSM-OEM in SFI context
	[26:19]	rssefw_active_signing_key	[1-256] → [1-8]: Value of monotonic counter is X, where X is the position of the most significant bit at 1. Eight possible ST public keys (ST key revocation feature for RSSE_FW authentication)
	[31:27]	Reserved	Reserved
OTP11	-	BOOTROM_CONFIG_2	-
	[0]	no_data_cache	– 0 (enabled): DCACHE used by boot ROM – 1 (disabled): DCACHE not used by boot ROM
	[1]	no_cpu_pll	– 0 (enabled): PLLs for CPU/AXI enabled for cold boot – 1 (disabled): PLLs for CPU/AXI not enabled for cold boot

Table 18. OTP fuse description (lower OTP region) (continued)

OTP word	OTP bits	Name or description	Detailed description
OTP11	[2]	sdmmc1_not_default_af	– 0 (no): SDMMC1 uses default hard coded AFmux – 1 (yes): SDMMC1 uses AFmux defined in OTP
	[3]	sdmmc2_not_default_af	– 0 (no): SDMMC2 uses default hard coded AFmux – 1 (yes): SDMMC2 uses AFmux defined in OTP
	[4]	Reserved	Reserved
	[8:5]	flash_boot_source	If different from 0, identifies the flash memory used to boot: – 1 (sdcard): SD-Card SDMMC1 – 2 (emmc): e.MMC SDMMC1 – 3 (snor): XSPI NOR – 4 (snand): XSPI NAND – 5 (hflash): XSPI HyperFlash – 6 (pnand): FMC pNAND – 7 (sdcard): SD-Card SDMMC2 – 8 (emmc): e.MMC SDMMC2 – others: invalid
	[16:9]	boot_source_disable	Each bit disables a boot source (default to UART if all disabled): – 0x01 (usb): USB boot source disabled – 0x02 (uart): UART boot source disabled – 0x04 (fdcan): FDCAN boot source disabled – 0x08 (spi): SPI boot source disabled – 0x10 (i2c): I2C boot source disabled
	[19:17]	spi_instance_disable	– 0b001: SPI1 disabled – 0b010: SPI2 disabled – 0b100: SPI3 disabled
	[22:20]	uart_instance_disable	– 0b001: USART1 disabled – 0b010: USART2 disabled – 0b100: USART3 disabled
	[25:23]	fdcan_instance_disable	– 0b001: disable FDCAN1 disabled – 0b010: disable FDCAN2 disabled – 0b100: disable FDCAN3 disabled
	[28:26]	i2c_instance_disable	– 0b001: I2C1 disabled – 0b010: I2C2 disabled – 0b100: I2C3 disabled
	[29]	dont_boot_on_cfm_tamper	– 0: boot on confirmed tamper – 1: do not boot on confirmed tamper
	[30]	tamp_boot_cfg_glob_enable	Enable the configuration of tampers in boot ROM before boot: – 0: configuration of tampers is disabled – 1: configuration of tampers is enabled
	[31]	Reserved	Reserved

Table 18. OTP fuse description (lower OTP region) (continued)

OTP word	OTP bits	Name or description	Detailed description
OTP12	-	BOOTROM_CONFIG_3	-
OTP12	[31:0]	st_fsbl_monotonic_counter	[1-0xFFFF] → [1-32]: Value of monotonic counter is X, where X is the position of the most significant bit at 1
OTP13	-	BOOTROM_CONFIG_4	Boot source configuration word
	[3:0]	mode0	– 0 (af_nopull_ls): AF; no pull; low speed – 1 (af_nopull_ms): AF; no pull; medium speed – 2 (af_nopull_hs): AF; no pull; high speed – 3 (af_pullup_ls): AF; pull up; low speed – 4 (af_pullup_ms): AF; pull up; medium speed – 5 (af_pullup_hs): AF; pull up; high speed – 6 (af_pulldown_ls): AF; pull down; low speed – 7 (af_pulldown_ms): AF; pull down; medium speed – 8 (af_pulldown_hs): AF; pull down; high speed – 9 (gpio_out_high): GPIO output high – 10 (gpio_out_low): GPIO output low – 11 (gpio_in): GPIO input – 12 (gpio_open_nopull): GPIO open drain; No pull – 13 (gpio_open_pullup): GPIO open drain; pull up – 14 (gpio_open_pulldown): GPIO open drain; pull down – 15 (gpio_analog): GPIO analog mode
	[7:4]	afmux0	Values between 0 and 15
	[11:8]	pin0	– [0-15]: pin ID between 0 and 15 for GPIOA to GPIOG and GPIOP – [0-12]: pin ID between 0 and 12 for GPION – [0-8]: pin ID between 0 and 8 for GPIOH and GPIOQ – [0-5]: pin ID between 0 and 5 for GPIOO
	[15:12]	port0	– 0: reserved – 1 (PA): Bank A – 2 (PB): Bank B – 3 (PC): Bank C – 4 (PD): Bank D – 5 (PE): Bank E – 6 (PF): Bank F – 7 (PG): Bank G – 8 (PH): Bank H – 9 (PN): Bank N – 10 (PO): Bank O – 11 (PP): Bank P – 12 (PQ): Bank Q – 0b1111: Invalid configuration
	[19:16]	mode1	idem BOOTROM_CONFIG_4.mode0
	[23:20]	afmux1	idem BOOTROM_CONFIG_4.afmux0

Table 18. OTP fuse description (lower OTP region) (continued)

OTP word	OTP bits	Name or description	Detailed description
OTP13	[27:24]	pin1	idem BOOTROM_CONFIG_4.pin0
OTP13	[31:28]	port1	idem BOOTROM_CONFIG_4.port0
OTP14	-	BOOTROM_CONFIG_5	-
	[3:0]	mode0	idem BOOTROM_CONFIG_4.mode0
	[7:4]	afmux0	idem BOOTROM_CONFIG_4.afmux0
	[11:8]	pin0	idem BOOTROM_CONFIG_4.pin0
	[15:12]	port0	idem BOOTROM_CONFIG_4.port0
	[19:16]	mode1	idem BOOTROM_CONFIG_4.mode0
	[23:20]	afmux1	idem BOOTROM_CONFIG_4.afmux0
	[27:24]	pin1	idem BOOTROM_CONFIG_4.pin0
OTP15	[31:28]	port1	idem BOOTROM_CONFIG_4.port0
	-	BOOTROM_CONFIG_6	-
	[3:0]	mode0	idem BOOTROM_CONFIG_4.mode0
	[7:4]	afmux0	idem BOOTROM_CONFIG_4.afmux0
	[11:8]	pin0	idem BOOTROM_CONFIG_4.pin0
	[15:12]	port0	idem BOOTROM_CONFIG_4.port0
	[19:16]	mode1	idem BOOTROM_CONFIG_4.mode0
	[23:20]	afmux1	idem BOOTROM_CONFIG_4.afmux0
	[27:24]	pin1	idem BOOTROM_CONFIG_4.pin0
	[31:28]	port1	idem BOOTROM_CONFIG_4.port0
OTP16	-	BOOTROM_CONFIG_7	-
	[0]	disable_traces	– 0 (no): boot ROM traces disabled – 1 (yes): boot ROM traces enabled
	[1]	disable_hse_freq_detect	– 0 (no): HSE frequency auto-detection disabled – 1 (yes): HSE frequency auto-detection enabled
	[2]	disable_hse_bypass_detect	– 0 (no): HSE bypass detection disabled – 1 (yes): HSE bypass detection enabled
	[4:3]	Reserved	Reserved
	[5]	fmc_force_sw_reset	-
	[6]	emergency_debug_req	– 0 (no): emergency debug not requested – 1 (yes): emergency debug requested
	[7]	emmc_128k_boot_partition	– 0 (no): BootROM does not support e.MMC with 128-Kbyte boot partition – 1 (yes): BootROM supports e.MMC with 128-Kbyte boot partition

Table 18. OTP fuse description (lower OTP region) (continued)

OTP word	OTP bits	Name or description	Detailed description
OTP16	[8]	Reserved	Reserved
	[9]	iomgr_port	Reserved
	[10]	iomgr_muxen	Reserved
	[13:11]	HSE_value	– 0b000 (auto): HSE value is auto-detected among 10, 12, 14, 16, 20, 24, 28, 32, 36, 40, and 48 MHz. – 0b001: HSE = 19.2 MHz – 0b010: HSE = 20 MHz – 0b011: HSE = 24 MHz – 0b100: HSE = 38.4 MHz – 0b101: HSE = 40 MHz – 0b110: HSE = 48 MHz – 0b111: Reserved
	[14]	snand_need_plane_select_1	– 0 (no): serial NAND plane select not needed – 1 (yes): serial NAND plane select needed
	[17:15]	pnand_number_of_ecc_bits_1	– 0 (unset): ECC unset – 1 (hamming): ECC 1 bit (Hamming) – 2 (bch4): ECC 4 bits (BCH4) – 3 (bch8): ECC 8 bits (BCH8) – 4 (ondie): on-die ECC
	[18]	pnand_bus_width_1	– 0 (8 bits): data width is 8 bits – 1 (16 bits): data width is 16 bits
	[26:19]	nand_nb_of_blocks_1	[1-256]: number of block = 256 × value
	[28:27]	nand_block_size_1	[1-4]: block size in number of pages
	[30:29]	nand_page_size_1	– 0 (64): 64 pages per block – 1 (128): 128 pages per block – 2 (256): 256 pages per block
	[31]	pnand_param_stored_in_otp	– 0 (no): BootROM uses ONFI parameter table to get parallel NAND parameters – 1 (yes): parallel NAND parameters are defined in bank1 or bank2, depending on nand_config_distribution value
OTP17	-	BOOTROM_CONFIG_8	-
	[7:0]	oem_ecdsa_active_key	[1-256] → [1-8]: Value of monotonic counter is X, where X is the position of the most significant bit at 1. Eight possible OEM public keys (OEM key revocation feature for OEM-FSBL authentication)
	[31:8]	Reserved	Reserved

Table 18. OTP fuse description (lower OTP region) (continued)

OTP word	OTP bits	Name or description	Detailed description
OTP18	-	BOOTROM_CONFIG_9	-
	[3:0]	secure_boot	– 0 (closed_unlocked): device in CLOSED_UNLOCKED state. Secure boot is not enforced (OEM FSBL authentication is not mandatory). – 1 (closed_locked): device in CLOSED_LOCKED state. Secure boot is enforced (OEM FSBL authentication is mandatory).
	[4]	fsbl_decrypt_prio	– 0 (cryp): BootROM uses CRYPT to decrypt FSBL – 1 (saes): BootROM uses SAES to decrypt FSBL
	[8:5]	prov_done	– 0 (no): provisioning not done or not finished successfully. Device is CLOSED_LOCKED_UNPROVD and accepts only ST-BootExtension FSBL. – 1 (yes): provisioning successfully completed. Device is CLOSED_LOCKED_PROVD and accepts only OEM FSBL.
	[12:9]	enable_fingerprint	– 0x0: fingerprint feature is disabled – others: fingerprint feature is enabled
	[15:13]	Reserved	Reserved
	[21:16]	nb_added_secrets	Number of OTP words located in upper area [360 - nb_added_stsecrets ... 359] provisioned (in encrypted mode) with ST secrets. These will be decoded and used by RSSE fw. Coding up to 64 ST secrets to provision in EWS (with DEV_BOOT)
	[25:22]	debug_lock	– 0: do not lock debug enabling – [1-64]: lock debug enabling
	[26]	ns_epoch_enable	– 0: the BootROM only sets bsec_epoch0 – 1: the BootROM set both bsec_epoch0 and bsec_epoch1
	[31:27]	Reserved	Reserved

Table 18. OTP fuse description (lower OTP region) (continued)

OTP word	OTP bits	Name or description	Detailed description
OTP19	-	BOOTROM_CONFIG_10	-
	[17:0]	Reserved	Reserved
	[20:18]	rng_htcr_value	- 1: 0xA2B3 - 2: 0xAA74 - 3: 0xA6BA - 4: 0x9AAE - 5: 0x72AC - 6: 0xAAC7 - others: RNG HTCR not modified
	[24:21]	dev_boot_port	- 0: reserved - 1 (PA): Bank A - 2 (PB): Bank B - 3 (PC): Bank C - 4 (PD): Bank D - 5 (PE): Bank E - 6 (PF): Bank F - 7 (PG): Bank G - 8 (PH): Bank H - 9 (PN): Bank N - 10 (PO): Bank O - 11 (PP): Bank P - 12 (PQ): Bank Q
	[28:25]	dev_boot_pin	- [0-15]: pin ID between 0 and 15 for GPIOA to GPIOG, and GPIOP - [0-12]: pin ID between 0 and 12 for GPION - [0-8]: pin ID between 0 and 8 for GPIOH and GPIOQ - [0-5]: pin ID between 0 and 5 for GPIOO
	[31:29]	Reserved	Reserved
OTP20	-	BOOTROM_CONFIG_11	-
OTP20	[31:0]	oem_fsbl_monotonic_counter	[1-0xFFFF] → [1-32]: Value of monotonic counter is X, where X is the position of the most significant bit at 1
OTP21	-	BOOTROM_CONFIG_12	-
OTP21	[31:0]	oem_fsbl_monotonic_counter	[1-0xFFFF] → [33-64]: Value of monotonic counter is 32 + X, where X is the position of the most significant bit at 1
OTP22	-	BOOTROM_CONFIG_13	Reserved
OTP23	-	BOOTROM_CONFIG_14	Reserved

Table 18. OTP fuse description (lower OTP region) (continued)

OTP word	OTP bits	Name or description	Detailed description
OTP24	-	BOOTROM_TZ_EPOCH0	If the highest blown bit is the nth of these 256 bits, the boot ROM sets BSEC3_EPOCH_TZ = n
OTP25	-	BOOTROM_TZ_EPOCH1
OTP26	-	BOOTROM_TZ_EPOCH2
OTP27	-	BOOTROM_TZ_EPOCH3
OTP28	-	BOOTROM_TZ_EPOCH4
OTP29	-	BOOTROM_TZ_EPOCH5
OTP30	-	BOOTROM_TZ_EPOCH6
OTP31	-	BOOTROM_TZ_EPOCH7
OTP32	-	BOOTROM_NS_EPOCH0	If the highest blown bit is the nth of these 256 bits, the boot ROM sets BSEC3_EPOCH_NS = n
OTP33	-	BOOTROM_NS_EPOCH1
OTP34	-	BOOTROM_NS_EPOCH2
OTP35	-	BOOTROM_NS_EPOCH3
OTP36	-	BOOTROM_NS_EPOCH4
OTP37	-	BOOTROM_NS_EPOCH5
OTP38	-	BOOTROM_NS_EPOCH6
OTP39	-	BOOTROM_NS_EPOCH7
OTP40 to OTP55	-	Customer zone	Customer values

Table 18. OTP fuse description (lower OTP region) (continued)

OTP word	OTP bits	Name or description	Detailed description
OTP56	-	TAMP_EN	-
	[0]	tamp1_enable	0: disabled, 1: enabled
	[1]	tamp2_enable	0: disabled, 1: enabled
	[2]	tamp3_enable	0: disabled, 1: enabled
	[3]	tamp4_enable	0: disabled, 1: enabled
	[4]	tamp5_enable	0: disabled, 1: enabled
	[5]	tamp6_enable	0: disabled, 1: enabled
	[6]	tamp7_enable	0: disabled, 1: enabled
	[7]	tamp8_enable	0: disabled, 1: enabled
	[8]	itamp1_enable	0: disabled, 1: enabled
	[9]	itamp2_enable	0: disabled, 1: enabled
	[10]	itamp3_enable	0: disabled, 1: enabled
	[11]	itamp4_enable	0: disabled, 1: enabled
	[12]	itamp5_enable	0: disabled, 1: enabled
	[13]	itamp6_enable	0: disabled, 1: enabled
	[14]	itamp7_enable	0: disabled, 1: enabled
	[15]	itamp8_enable	0: disabled, 1: enabled
	[16]	itamp9_enable	0: disabled, 1: enabled
	[17]	Reserved	Reserved
	[18]	itamp11_enable	0: disabled, 1: enabled
	[31:19]	Reserved	Reserved

Table 18. OTP fuse description (lower OTP region) (continued)

OTP word	OTP bits	Name or description	Detailed description
OTP57	-	TAMP_CFM	-
	[0]	tamp1_confirmed	0: potential tamper, 1: confirmed tamper
	[1]	tamp2_confirmed	0: potential tamper, 1: confirmed tamper
	[2]	tamp3_confirmed	0: potential tamper, 1: confirmed tamper
	[3]	tamp4_confirmed	0: potential tamper, 1: confirmed tamper
	[4]	tamp5_confirmed	0: potential tamper, 1: confirmed tamper
	[5]	tamp6_confirmed	0: potential tamper, 1: confirmed tamper
	[6]	tamp7_confirmed	0: potential tamper, 1: confirmed tamper
	[7]	tamp8_confirmed	0: potential tamper, 1: confirmed tamper
	[8]	itamp1_confirmed	0: potential tamper, 1: confirmed tamper
	[9]	itamp2_confirmed	0: potential tamper, 1: confirmed tamper
	[10]	itamp3_confirmed	0: potential tamper, 1: confirmed tamper
	[11]	itamp4_confirmed	0: potential tamper, 1: confirmed tamper
	[12]	itamp5_confirmed	0: potential tamper, 1: confirmed tamper
	[13]	itamp6_confirmed	0: potential tamper, 1: confirmed tamper
	[14]	itamp7_confirmed	0: potential tamper, 1: confirmed tamper
	[15]	itamp8_confirmed	0: potential tamper, 1: confirmed tamper
	[16]	itamp9_confirmed	0: potential tamper, 1: confirmed tamper
	[17]	Reserved	Reserved
	[18]	itamp11_confirmed	0: potential tamper, 1: confirmed tamper
	[31:19]	Reserved	Reserved
OTP58	-	TAMP_CFG	-
	[1:0]	tamp1_cfg	00: level low, 01: level high, 10: edge falling, 11: edge rising
	[3:2]	tamp2_cfg	00: level low, 01: level high, 10: edge falling, 11: edge rising
	[5:4]	tamp3_cfg	00: level low, 01: level high, 10: edge falling, 11: edge rising
	[7:6]	tamp4_cfg	00: level low, 01: level high, 10: edge falling, 11: edge rising
	[9:8]	tamp5_cfg	00: level low, 01: level high, 10: edge falling, 11: edge rising
	[11:10]	tamp6_cfg	00: level low, 01: level high, 10: edge falling, 11: edge rising
	[13:12]	tamp7_cfg	00: level low, 01: level high, 10: edge falling, 11: edge rising
	[15:14]	tamp8_cfg	00: level low, 01: level high, 10: edge falling, 11: edge rising
	[31:16]	Reserved	Reserved
OTP59 to OTP95	-	Reserved	Reserved

Table 18. OTP fuse description (lower OTP region) (continued)

OTP word	OTP bits	Name or description	Detailed description
OTP96 to OTP99	-	Reserved	Reserved
OTP100 to OTP102	-	Reserved	Reserved
OTP103	-	Reserved	Reserved
OTP104 to OTP123	-	Reserved	Reserved
OTP124	-	HCONF1	-
	[0]	IWDG1_HW	IWDG1 start on reset
	[1]	IWDG1_FZ_STOP	IWDG1 freeze in Stop mode
	[2]	IWDG1_FZ_STANDBY	IWDG1 freeze in Standby mode
	[9:3]	Reserved	Reserved
	[10]	RST_STOP	Reset caused if the device is put in Stop mode
	[11]	RST_STDBY	Reset caused if the device is put in Standby mode
	[12]	SELINBORH	– 0: BOR disabled – 1: BOR = 2.7 V
	[13]	HSLV_VDDIO5	VDDIO5 I/O segment below 2.5 V for I/O mode. The I/O segment is used by SDMMC2 port.
	[14]	HSLV_VDDIO4	VDDIO4 I/O segment below 2.5 V for I/O mode (I/O segment used by SDMMC1 port)
	[15]	HSLV_VDDIO3	VDDIO3 I/O segment below 2.5 V for I/O mode (I/O segment used by XSPIM port 2)
	[16]	HSLV_VDDIO2	VDDIO2 I/O segment below 2.5 V for I/O mode (I/O segment used by XSPIM port 1)
	[17]	HSLV_VDD	Main I/O segment below 2.5 V for I/O mode
	[19:18]	Reserved	Reserved
	[20]	DFT_DISABLE	– 0: scan and bist available – 1: scan and bist only available on an OPEN part
	[31:21]	Reserved	Reserved
OTP125 to OTP127	-	Reserved	Reserved

Table 19. OTP fuse description (mid OTP region)

OTP words	Name or description	Detailed description
OTP128	STM32CERTIF0	STM32 device certificate (signature of the public key)
OTP129	STM32CERTIF1
OTP130	STM32CERTIF2
OTP131	STM32CERTIF3
OTP132	STM32CERTIF4
OTP133	STM32CERTIF5
OTP134	STM32CERTIF6
OTP135	STM32CERTIF7
OTP136	STM32CERTIF8
OTP137	STM32CERTIF9
OTP138	STM32CERTIF10
OTP139	STM32CERTIF11
OTP140	STM32CERTIF12
OTP141	STM32CERTIF13
OTP142	STM32CERTIF14
OTP143	STM32CERTIF15
OTP144	STM32PUBKEY0	STM32 device public key
OTP145	STM32PUBKEY1
OTP146	STM32PUBKEY2
OTP147	STM32PUBKEY3
OTP148	STM32PUBKEY4
OTP149	STM32PUBKEY5
OTP150	STM32PUBKEY6
OTP151	STM32PUBKEY7
OTP152	STM32PUBKEY8
OTP153	STM32PUBKEY9
OTP154	STM32PUBKEY10
OTP155	STM32PUBKEY11
OTP156	STM32PUBKEY12
OTP157	STM32PUBKEY13
OTP158	STM32PUBKEY14
OTP159	STM32PUBKEY15

Table 19. OTP fuse description (mid OTP region) (continued)

OTP words	Name or description	Detailed description
OTP160	OTP_ROT_HASH0	Hash of Table of hashes of OEM public keys
OTP161	OTP_ROT_HASH1
OTP162	OTP_ROT_HASH2
OTP163	OTP_ROT_HASH3
OTP164	OTP_ROT_HASH4
OTP165	OTP_ROT_HASH5
OTP166	OTP_ROT_HASH6
OTP167	OTP_ROT_HASH7
OTP168	ST_RSSE_EDMK_DERIV_CSTE_FUSE	ST Encryption Decryption Master Key Derivation constant
OTP169	OTP_MAC1_ADDR_LOW	MAC_ADDR1
OTP170	OTP_MAC1_ADDR_HIGH	MAC_ADDR1
OTP171	OTP_MAC2_ADDR_LOW	MAC_ADDR2
OTP172	OTP_MAC2_ADDR_HIGH	MAC_ADDR2
OTP173 to OTP255	Available to customer	-
OTP256	OTP_RMA_LOCK_PSWD	RMA password
OTP257	OTP_RMA_LOCK_PSWD
OTP258	OTP_RMA_LOCK_PSWD
OTP259	OTP_RMA_LOCK_PSWD
OTP260 to OTP363	OEM secrets available to customer	-
OTP364	OEM_SECRET_FOR_CRYPTED_BOOT0	OEM secret used to derive FSBL decryption key
OTP365	OEM_SECRET_FOR_CRYPTED_BOOT1
OTP366	OEM_SECRET_FOR_CRYPTED_BOOT2
OTP367	OEM_SECRET_FOR_CRYPTED_BOOT3
OTP368	STM32PRVKEY0	STM32 device private key (ST)
OTP369	STM32PRVKEY1
OTP370	STM32PRVKEY2
OTP371	STM32PRVKEY3
OTP372	STM32PRVKEY4
OTP373	STM32PRVKEY5
OTP374	STM32PRVKEY6
OTP375	STM32PRVKEY7