2. Memory and bus architecture

2.1 System architecture

2.1.1 Introduction

The STM32N6x5 and STM32N6x7 device architecture relies on an Arm Cortex-M55 core optimized for execution:

• • Main masters:
  • – Cortex-M55 with Arm TrustZone mainline with two master ports:
    • > M-AXI provides access to the memory and to peripherals
    • > P-AHB provides access to peripherals
  • – NPU (neural processor unit), which includes two master AXI ports (STM32N6x7 devices only)
• • Memories:
  • – AHB and APB peripherals
  • – 4.2 Mbytes of SRAM
  • – 64 Kbytes I-TCM RAM with ECC for critical real-time routines, and 128 Kbytes of D-TCM RAM with ECC for critical real-time data
  • – 8 Kbytes of backup SRAM (BKPSRAM) active in \( V_{BAT} \) mode
  • – 2 x 16-Kbyte AHB RAMs
  • – Flexible external memory controller (FLEXMEM) with cypher engine supporting up to 32-bit data bus: SRAM, PSRAM, SDRAM, LPSDR SDRAM, NOR/NAND flash memories
  • – XSPIM port2 8-bit configuration with cypher engine
  • – XSPIM port1 16-bit configuration with cypher engine

2.1.2 Bus architecture

The bus architecture is divided in two domains, high- and low-performance (see Figure 1 and Figure 2 ).

High-speed, multi-frequency domain, AXI compliant interconnect

This high-performance interconnect is mainly used by the CPU, the NPU (STM32N6x7 devices only), and by the high-bandwidth masters (GPU, DMA2D, GFXMMU, VENC, DCMIPP, LTDC, ETH1, OTG1/2, SDMMC1/2, HPDMA1 AXI port).

This domain manages accesses to:

• • external flash memories and SRAMs (through the FMC and the XSPI manager)
• • main system internal memories AXISRAM1/2/3/4/5/6, boot ROM, VENCRAM (when the VENC is off), and CACHEAXI RAM (STM32N6x7 devices when NPU is off) or SRAM7 (STM32N6x5 devices)
• • the CPU internal memory (TCM) when accessed by the HPDMA1 AXI and the NPU
  Note: The CPU has internally access to the TCM.
• • the GFXMMU
• • the STM (system trace macrocell)

The CPU uses its M-AXI master port to access the above-described targets.

The NPU uses a local interconnect (NPU_NIC) to have a direct access to AXISRAM3/4/5/6 and to the CPU TCM. This results in a high-performance and low-latency bus when accessing these targets.

In addition, data interleaving can be enabled on AXISRAM3/4/5/6 to balance the traffic and to improve access performance.

The CPU and high-bandwidth masters use another local interconnect called CPU_NOC to have high-performance access on AXISRAM1/2 and external flash memories.

Note: The boot ROM is accessible only by the CPU through an intermediate interconnect called CPU_NIC.

Multi-layer AHB interconnect

This interconnect is used to access AHBSRAM1/2, BKPSRAM, and peripherals.

The CPU can reach peripherals mapped in the peripheral region (address range from 0x4000 0000 to 0x5FFF FFFF), using the following masters ports:

• • the CPU P-AHB master port for data accesses
• • the CPU M-AXI master port for instruction accesses

When P-AHB is disabled, data accesses are performed on M-AXI.

The CPU accesses AHBSRAM1/2 and BKPSRAM through its M-AXI master port. The CPU memory accesses start on the high-performance interconnect before reaching the AHB interconnect.

GPDMA1 and HPDMA1 AHB ports are the other masters on this interconnect.

The GPDMA1_P has a dedicated access to APB1/2/4 peripherals.

Figure 1. Interconnect top view - STM32N6x7 devices

1. 1. The high-performance domain is shown in pink. The low-performance domain is shown in blue.

Figure 2. Interconnect top view - STM32N6x5 devices

1. The high-performance domain is shown in pink. The low-performance domain is shown in blue.

2.2 Bus network-on-chip (NoC)

2.2.1 STNoC AXI

The STNoC AXI interconnect is built out of the ST in-house network-on-chip. Its main features are:

• • Source routed, packet based, wormhole switching forwarding scheme for simultaneous and parallel/pipelined accesses from master to slave
• • Independent read and write input/output points to cope with AXI independent channels
• • Size and frequency conversion, asynchronism management
• • Fine grain automatic clock gating shutting down the clocks to unused network parts at any point in time, with zero delay clock resume
• • Internal packets buffering for improved traffic efficiency
• • Independent request and response network
• • Software accessible registers to observe and report traffic statistics, performance, blocking sources (if any) over the network.

2.2.2 NPU_NIC network interconnect

The NPU_NIC interconnect is based on Arm NIC-400 Network Interconnect. Its main features are:

• • High-performance and low-latency interconnect
• • Independent read/write request/response channel as defined in AXI protocol
• • Asynchronism management
• • Address interleaving to AXISRAM3/4/5/6/7 (can be disabled by software)
• • CACHEAXI / SRAM7:
  • – for STM32N6x7, when CACHEAXI is disabled, 256 KB SRAM7 can be accessible
  • – for STM32N6x5, no CACHEAXI feature, only 256 KB accessible
• • Static QoS assigned by software used at any arbitration node. The highest value has the highest priority. Arbitration with same QoS value uses an LRU (least recently used) algorithm.

2.2.3 Multi-layer AHB interconnect (AHBM)

The multi-layer AHB main features are:

• • 32-bit bus matrix running at 200 MHz using a master clock from the RCC
• • Simultaneous accesses from different masters to the slaves connected to separated layers
• • Five master ports: CPU P-AHB, HPDMA1, GPDMA1_P /M, and CPU_NOC
• • Nine slave ports: memories (AHB SRAM1/2 and BKPSRAM), peripherals for AHBx/APBx targets, and CPU_NOC target to reach AXI.

Note: The GPDMA1_P has a direct path to APB1, APB2, and APB4 targets. It bypasses this multi-layer AHB.

2.3 Memory organization

2.3.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

2.3.2 Memory map and register boundary addresses

Program memory, data memory, registers, and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in little-endian format. The lowest numbered byte in a word is considered the word least significant byte, and the highest numbered byte the most significant.

All memory map areas that are not allocated to on-chip memories and peripherals are considered reserved.

The IDAU mapping indicates if a particular memory address is secure or nonsecure.

Table 1. Memory map based on IDAU mapping

Table 1. Memory map based on IDAU mapping (continued)

Table 1. Memory map based on IDAU mapping (continued)

Table 1. Memory map based on IDAU mapping (continued)

Table 2. Memory map and peripheral register boundary addresses (continued)

Table 2. Memory map and peripheral register boundary addresses (continued)

Table 2. Memory map and peripheral register boundary addresses (continued)

Table 2. Memory map and peripheral register boundary addresses (continued)

Table 3. Peripheral register boundary addresses

Table 3. Peripheral register boundary addresses (continued)

Table 3. Peripheral register boundary addresses (continued)

Table 3. Peripheral register boundary addresses (continued)