RM0486-STM32N6x5-x7

This document is addressed to application developers. It provides complete information on how to use the STM32N645xx, STM32N647xx, STM32N655xx, and STM32N657xx (referred to as STM32N6x5/x7xx) microcontrollers memory and peripherals.

For ordering information, mechanical and electrical device characteristics, refer to the datasheet.

For information on the Arm ® Cortex ® -M55 core, refer to the corresponding Arm ® Technical Reference Manual available on http://infocenter.arm.com .

STM32N6x5/x7xx microcontrollers include ST state-of-the-art patented technology.

Contents

3.6Secure storage . . . . .193
3.6.1Battery backup registers . . . . .193
3.6.2Secure RAM and registers . . . . .193
3.6.3Fuse secrets . . . . .193
3.6.4Hardware key management . . . . .193
3.6.5Unique ID . . . . .195
3.7Tamper detection and response . . . . .195
3.8Crypto engines . . . . .197
3.8.1Accelerators . . . . .197
3.8.2Memory cipher engine (MCE) . . . . .199
3.8.3NPU encryption . . . . .199
3.9Access controlled debug . . . . .200
4Boot and security control (BSEC) . . . . .201
4.1Introduction . . . . .201
4.2BSEC main features . . . . .201
4.3BSEC functional description . . . . .202
4.3.1BSEC block diagram . . . . .202
4.3.2BSEC internal signals . . . . .202
4.3.3BSEC reset and clocks . . . . .203
4.3.4Organization and use of fuses . . . . .204
4.3.5Operations on fuses . . . . .205
4.3.6BSEC read and programming status reporting . . . . .207
4.3.7Lifecycle management . . . . .208
4.3.8Epoch registers . . . . .209
4.3.9BSEC local access control . . . . .210
4.3.10Temporal isolation in BSEC . . . . .210
4.3.11BSEC debug and trace control . . . . .211
4.3.12Device features control . . . . .212
4.3.13Scratch registers . . . . .212
4.3.14JTAG registers . . . . .212
4.3.15STM32 root hardware unique key (RHUK) . . . . .212
4.3.16BSEC error management . . . . .213
4.3.17BSEC tamper response mechanisms . . . . .213
4.4BSEC interrupts . . . . .213
4.5BSEC registers . . . . .213
6.4RIFSC registers . . . . .251
6.4.1RIFSC RISC slave configuration register x (RIFSC_RISC_CR) . . . . .251
6.4.2RIFSC RISC slave security configuration register x
(RIFSC_RISC_SECCFGRx) . . . . .		252
6.4.3RIFSC RISC slave privileged register x
(RIFSC_RISC_PRIVCFG Rx) . . . . .		252
6.4.4RIFSC RISC slave resource configuration lock register x
(RIFSC_RISC_RCFGLOCK Rx) . . . . .		253
6.4.5RIFSC RIMC master configuration register (RIFSC_RIMC_CR) . . . . .253
6.4.6RIFSC RIMC master attribute register x (RIFSC_RIMC_ATTR Rx) . . . . .254
6.4.7RIFSC peripheral protection status register 0 (RIFSC_PPSR0) . . . . .254
6.4.8RIFSC peripheral protection status register 1 (RIFSC_PPSR1) . . . . .255
6.4.9RIFSC peripheral protection status register 2 (RIFSC_PPSR2) . . . . .255
6.4.10RIFSC peripheral protection status register 3 (RIFSC_PPSR3) . . . . .255
6.4.11RIFSC peripheral protection status register 4 (RIFSC_PPSR4) . . . . .256
6.4.12RIFSC peripheral protection status register 5 (RIFSC_PPSR5) . . . . .256
6.4.13RIFSC register map . . . . .257
7Resource isolation slave unit for address space
protection (full version) (RISAF) . . . . .		258
7.1RISAF introduction . . . . .258
7.2RISAF main features . . . . .258
7.3RISAF implementation . . . . .259
7.4RISAF functional description . . . . .260
7.4.1RISAF block diagram . . . . .260
7.4.2RISAF internal signals . . . . .260
7.4.3RISAF reset and clocks . . . . .261
7.4.4RISAF address space management . . . . .261
7.4.5RISAF programming . . . . .262
7.4.6RISAF runtime modification of region or subregion configuration . . . . .263
7.4.7Managing illegal accesses . . . . .264
7.5RISAF registers . . . . .265
7.5.1RISAF configuration register (RISAF_CR) . . . . .265
7.5.2RISAF illegal access status register (RISAF_IASR) . . . . .265
7.5.3RISAF illegal access clear register (RISAF_IACR) . . . . .266
7.5.4RISAF illegal access error status register (RISAF_IAESR) . . . . .266
7.5.5RISAF illegal address register (RISAF_IADDR) . . . . .267
7.5.6RISAF region x configuration register (RISAF_REGx_CFGR) . . . . .267

8        Illegal access controller (IAC) . . . . . 280

9Boot modes .....286
9.1Boot after system reset .....286
9.1.1Flash boot .....286
9.1.2Serial boot .....286
9.1.3Development boot .....286
9.2Boot from a low-power mode .....287
10SRAM configuration controller (RAMCFG) .....288
10.1RAMCFG introduction .....288
10.2RAMCFG main features .....288
10.3RAMCFG functional description .....288
10.3.1Internal SRAM features .....288
10.3.2FLEXRAM control .....289
10.3.3ECC (BKPSRAM) .....292
10.4RAMCFG low-power modes .....293
10.5RAMCFG interrupts .....294
10.6RAMCFG registers .....295
10.6.1RAMCFG AXISRAM1 control register (RAMCFG_AXISRAM1CR) . . .295
10.6.2RAMCFG AXISRAMx interrupt status register
(RAMCFG_AXISRAMxISR) .....		295
10.6.3RAMCFG AXISRAMx erase key register
(RAMCFG_AXISRAMxERKEYR) .....		296
10.6.4RAMCFG AXISRAMx control register (RAMCFG_AXISRAMxCR) . . .296
10.6.5RAMCFG AHBSRAMx control register (RAMCFG_AHBSRAMxCR) . . .297
10.6.6RAMCFG AHBSRAMx interrupt status register
(RAMCFG_AHBSRAMxISR) .....		297
10.6.7RAMCFG AHBSRAMx erase key register
(RAMCFG_AHBSRAMxERKEYR) .....		298
10.6.8RAMCFG VENCRAM control register (RAMCFG_VENCRAMCR) . . .298
10.6.9RAMCFG VENCRAM interrupt status register
(RAMCFG_VENCRAMISR) .....		299
10.6.10RAMCFG VENCRAM erase key register
(RAMCFG_VENCRAMERKEYR) .....		299
10.6.11RAMCFG BKPSRAM control register (RAMCFG_BKPSRAMCR) . . .300
10.6.12RAMCFG BKPSRAM interrupt enable register
(RAMCFG_BKPSRAMIER) .....		301
10.6.13RAMCFG BKPSRAM interrupt status register
(RAMCFG_BKPSRAMISR) .....		301

11.7.4ICACHE flag clear register (ICACHE_FCR) .....318
11.7.5ICACHE hit monitor register (ICACHE_HMONR) .....319
11.7.6ICACHE miss monitor register (ICACHE_MMONR) .....319
11.7.7ICACHE register map .....319
12AXI cache (CACHEAXI) .....321
12.1CACHEAXI introduction .....321
12.2CACHEAXI main features .....322
12.3CACHEAXI implementation .....323
12.4CACHEAXI functional description .....324
12.4.1CACHEAXI block diagram .....325
12.4.2CACHEAXI reset and clocks .....325
12.4.3CACHEAXI TAG memory .....326
12.4.4CACHEAXI enable .....329
12.4.5Cacheable and noncacheable AXI traffic to slave cache port .....329
12.4.6Cacheable accesses .....330
12.4.7AXI traffic to master port .....331
12.4.8AXI traffic to slave SRAM port .....332
12.4.9CACHEAXI security .....332
12.4.10CACHEAXI maintenance .....332
12.4.11CACHEAXI performance monitoring .....334
12.4.12CACHEAXI boot .....335
12.5CACHEAXI low-power modes .....335
12.6CACHEAXI error management and interrupts .....335
12.7CACHEAXI registers .....337
12.7.1CACHEAXI control register 1 (CACHEAXI_CR1) .....337
12.7.2CACHEAXI status register (CACHEAXI_SR) .....338
12.7.3CACHEAXI interrupt enable register (CACHEAXI_IER) .....339
12.7.4CACHEAXI flag clear register (CACHEAXI_FCR) .....340
12.7.5CACHEAXI read-hit monitor register (CACHEAXI_RHMONR) .....341
12.7.6CACHEAXI read-miss monitor register (CACHEAXI_RMMONR) .....341
12.7.7CACHEAXI read-allocate miss monitor register
(CACHEAXI_RAMMONR) .....		341
12.7.8CACHEAXI eviction monitor register (CACHEAXI_EVIMONR) .....342
12.7.9CACHEAXI write-hit monitor register (CACHEAXI_WHMONR) .....342
12.7.10CACHEAXI write-miss monitor register (CACHEAXI_WMMONR) .....342

12.7.11 CACHEAXI write-allocate miss monitor register (CACHEAXI_WAMMONR) . . . . . 343

12.7.12 CACHEAXI write-through monitor register (CACHEAXI_WTMONR) . . . . . 343

12.7.13 CACHEAXI control register 2 (CACHEAXI_CR2) . . . . . 343

12.7.14 CACHEAXI command range start address register (CACHEAXI_CMDRSADDDRR) . . . . . 344

12.7.15 CACHEAXI command range end address register (CACHEAXI_CMDREADDRR) . . . . . 345

12.7.16 CACHEAXI register map . . . . . 345

13 Power control (PWR) . . . . . 347

13.1 PWR introduction . . . . . 347

13.2 PWR main features . . . . . 347

13.3 PWR block diagram . . . . . 348

13.3.1 PWR pins and internal signals . . . . . 348

13.4 Power supplies . . . . . 350

13.4.1 System supply startup . . . . . 353

13.4.2 Core domain . . . . . 355

13.4.3 PWR external supply . . . . . 356

13.4.4 Backup domain . . . . . 357

13.4.5 Retention domain . . . . . 358

13.4.6 Analog supply . . . . . 360

13.5 Power supply supervision . . . . . 360

13.5.1 Power-on reset (POR)/power-down reset (PDR) . . . . . 361

13.5.2 Brownout reset (BOR) . . . . . 361

13.5.3 Vdda18pmu_ok reset . . . . . 362

13.5.4 Vddcore_ok reset . . . . . 363

13.5.5 V DDCORE monitoring . . . . . 363

13.5.6 Programmable voltage detector (PVD) . . . . . 364

13.5.7 Peripheral voltage monitoring (PVM) . . . . . 365

13.5.8 Battery voltage thresholds . . . . . 366

13.5.9 Temperature thresholds . . . . . 367

13.6 Power management . . . . . 368

13.6.1 Operating modes . . . . . 368

13.6.2 Voltage scaling . . . . . 373

13.6.3 Power management examples . . . . . 374

13.7 Low-power modes . . . . . 376

13.7.1Slowing down system clocks . . . . .377
13.7.2Controlling peripheral clocks . . . . .377
13.7.3Entering low-power modes . . . . .377
13.7.4Exiting low-power modes . . . . .377
13.7.5Sleep mode . . . . .378
13.7.6Stop mode . . . . .379
13.7.7Standby mode . . . . .381
13.7.8Power mode output pins . . . . .383
13.8PWR security and privileged protection . . . . .383
13.8.1Secure/nonsecure access filtering . . . . .384
13.8.2Privileged/unprivileged access filtering . . . . .385
13.9PWR registers . . . . .385
13.9.1PWR control register 1 (PWR_CR1) . . . . .385
13.9.2PWR control register 2 (PWR_CR2) . . . . .386
13.9.3PWR control register 3 (PWR_CR3) . . . . .387
13.9.4PWR control register 4 (PWR_CR4) . . . . .387
13.9.5PWR voltage scaling control register (PWR_VOSCR) . . . . .388
13.9.6PWR backup domain control register 1 (PWR_BDCR1) . . . . .389
13.9.7PWR backup domain control register 2 (PWR_BDCR2) . . . . .390
13.9.8PWR disable backup protection control register (PWR_DBPCR) . . . . .391
13.9.9PWR CPU control register (PWR_CPUCR) . . . . .391
13.9.10PWR supply voltage monitoring control register 1 (PWR_SVMCR1) . . . . .392
13.9.11PWR supply voltage monitoring control register 2 (PWR_SVMCR2) . . . . .394
13.9.12PWR supply voltage monitoring control register 3 (PWR_SVMCR3) . . . . .395
13.9.13PWR wake-up clear register (PWR_WKUPCR) . . . . .397
13.9.14PWR wake-up status register (PWR_WKUPSR) . . . . .398
13.9.15PWR wake-up enable and polarity register (PWR_WKUPEPR) . . . . .399
13.9.16PWR security configuration register (PWR_SECCFGR) . . . . .401
13.9.17PWR privilege configuration register (PWR_PRIVCFGR) . . . . .402
13.9.18PWR debug control register 1 (PWR_CRCFG1) . . . . .405
13.9.19PWR debug control register 2 (PWR_CRCFG2) . . . . .406
13.9.20PWR Debug control register 3 (PWR_CRCFG3) . . . . .406
13.9.21PWR register map . . . . .408
14Reset and clock control (RCC) . . . . .411
14.1RCC main features . . . . .411
14.2RCC power domains . . . . .411
14.3RCC block diagram . . . . .412
14.4RCC pins and internal signals . . . . .412
14.5Functional description of RCC reset . . . . .414
14.5.1Reset from the PWR . . . . .414
14.5.2System and application resets (sys_rst, nreset_rstn) . . . . .415
14.5.3NRST reset . . . . .416
14.5.4Low-power mode security reset (lpwr_rst) . . . . .416
14.5.5Backup domain reset . . . . .417
14.5.6CoreSight debug reset . . . . .417
14.5.7Option-byte loading . . . . .417
14.5.8Reset of peripherals . . . . .418
14.5.9Reset pulse control (RPCTL) . . . . .418
14.5.10Reset coverage summary . . . . .419
14.5.11Reset source identification . . . . .420
14.5.12Power-on and wake-up sequences . . . . .420
14.6Functional description of RCC clocks . . . . .421
14.6.1Clock naming convention . . . . .424
14.6.2Oscillator description . . . . .424
14.6.3Clock security system (CSS) . . . . .432
14.6.4Clock output generation (MCO1/MCO2) . . . . .435
14.6.5PLL description . . . . .435
14.6.6System clocks . . . . .440
14.6.7Clock generation in Stop and Standby modes . . . . .443
14.6.8Peripheral clock distribution . . . . .444
14.6.9General clock concept overview . . . . .468
14.6.10Peripheral allocation . . . . .469
14.6.11Peripheral clock-gating control . . . . .470
14.6.12CPU and bus matrix clock-gating control . . . . .472
14.6.13Low-power emulation modes . . . . .473
14.7RCC interrupts . . . . .474
14.8RCC application information . . . . .474
14.8.1HSE crystal auto-detection . . . . .474
14.8.2Calibration and clock frequency measurement using TIMx . . . . .475
14.8.3Clock monitoring . . . . .476
14.8.4Clock frequency limits . . . . .476
14.9RCC security . . . . .477
14.9.1Internal register protection . . . . .478
14.9.2Internal register write-protection . . . . .479
14.10RCC registers . . . . .479
14.10.1RCC control register (RCC_CR) . . . . .479
14.10.2RCC status register (RCC_SR) . . . . .481
14.10.3RCC Stop mode control register (RCC_STOPCR) . . . . .482
14.10.4RCC configuration register 1 (RCC_CFGR1) . . . . .483
14.10.5RCC configuration register 2 (RCC_CFGR2) . . . . .484
14.10.6RCC backup domain protection register (RCC_BDCR) . . . . .486
14.10.7RCC reset status register for hardware (RCC_HWRCSR) . . . . .487
14.10.8RCC reset register (RCC_RSR) . . . . .488
14.10.9RCC LSE configuration register (RCC_LSECFGR) . . . . .490
14.10.10RCC MSI configuration register (RCC_MSICFGR) . . . . .491
14.10.11RCC HSI configuration register (RCC_HSI CFGR) . . . . .492
14.10.12RCC HSI monitor control register (RCC_HSIMCR) . . . . .493
14.10.13RCC HSI monitor status register (RCC_HSIMSR) . . . . .493
14.10.14RCC HSE configuration register (RCC_HSECFGR) . . . . .494
14.10.15RCC PLL1 configuration register 1 (RCC_PLL1CFGR1) . . . . .495
14.10.16RCC PLL1 configuration register 2 (RCC_PLL1CFGR2) . . . . .496
14.10.17RCC PLL1 configuration register 3 (RCC_PLL1CFGR3) . . . . .497
14.10.18RCC PLL2 configuration register 1 (RCC_PLL2CFGR1) . . . . .498
14.10.19RCC PLL2 configuration register 2 (RCC_PLL2CFGR2) . . . . .499
14.10.20RCC PLL2 configuration register 3 (RCC_PLL2CFGR3) . . . . .500
14.10.21RCC PLL3 configuration register 1 (RCC_PLL3CFGR1) . . . . .501
14.10.22RCC PLL3 configuration register 2 (RCC_PLL3CFGR2) . . . . .502
14.10.23RCC PLL3 configuration register 3 (RCC_PLL3CFGR3) . . . . .503
14.10.24RCC PLL4 configuration register 1 (RCC_PLL4CFGR1) . . . . .504
14.10.25RCC PLL4 configuration register 2 (RCC_PLL4CFGR2) . . . . .505
14.10.26RCC PLL4 configuration register 3 (RCC_PLL4CFGR3) . . . . .505
14.10.27RCC IC1 configuration register (RCC_IC1CFGR) . . . . .507
14.10.28RCC IC2 configuration register (RCC_IC2CFGR) . . . . .508
14.10.29RCC IC3 configuration register (RCC_IC3CFGR) . . . . .509
14.10.30RCC IC4 configuration register (RCC_IC4CFGR) . . . . .509
14.10.31RCC IC5 configuration register (RCC_IC5CFGR) . . . . .510
14.10.32RCC IC6 configuration register (RCC_IC6CFGR) . . . . .511
14.10.33RCC IC7 configuration register (RCC_IC7CFGR) . . . . .512
14.10.34RCC IC8 configuration register (RCC_IC8CFGR) . . . . .512
14.10.35 RCC IC9 configuration register (RCC_IC9CFGR) . . . . .513
14.10.36 RCC IC10 configuration register (RCC_IC10CFGR) . . . . .514
14.10.37 RCC IC11 configuration register (RCC_IC11CFGR) . . . . .514
14.10.38 RCC IC12 configuration register (RCC_IC12CFGR) . . . . .515
14.10.39 RCC IC13 configuration register (RCC_IC13CFGR) . . . . .516
14.10.40 RCC IC14 configuration register (RCC_IC14CFGR) . . . . .517
14.10.41 RCC IC15 configuration register (RCC_IC15CFGR) . . . . .518
14.10.42 RCC IC16 configuration register (RCC_IC16CFGR) . . . . .518
14.10.43 RCC IC17 configuration register (RCC_IC17CFGR) . . . . .519
14.10.44 RCC IC18 configuration register (RCC_IC18CFGR) . . . . .520
14.10.45 RCC IC19 configuration register (RCC_IC19CFGR) . . . . .520
14.10.46 RCC IC20 configuration register (RCC_IC20CFGR) . . . . .521
14.10.47 RCC clock-source interrupt enable register (RCC_CIER) . . . . .522
14.10.48 RCC clock-source interrupt flag register (RCC_CIFR) . . . . .523
14.10.49 RCC clock-source interrupt clear register (RCC_CICR) . . . . .525
14.10.50 RCC clock configuration for independent peripheral register 1
(RCC_CCIPR1) . . . . .		527
14.10.51 RCC clock configuration for independent peripheral register 2
(RCC_CCIPR2) . . . . .		528
14.10.52 RCC clock configuration for independent peripheral register 3
(RCC_CCIPR3) . . . . .		530
14.10.53 RCC clock configuration for independent peripheral register 4
(RCC_CCIPR4) . . . . .		530
14.10.54 RCC clock configuration for independent peripheral register 5
(RCC_CCIPR5) . . . . .		532
14.10.55 RCC clock configuration for independent peripheral register 6
(RCC_CCIPR6) . . . . .		534
14.10.56 RCC clock configuration for independent peripheral register 7
(RCC_CCIPR7) . . . . .		536
14.10.57 RCC clock configuration for independent peripheral register 8
(RCC_CCIPR8) . . . . .		537
14.10.58 RCC clock configuration for independent peripheral register 9
(RCC_CCIPR9) . . . . .		538
14.10.59 RCC clock configuration for independent peripheral register 12
(RCC_CCIPR12) . . . . .		540
14.10.60 RCC clock configuration for independent peripheral register 13
(RCC_CCIPR13) . . . . .		542
14.10.61 RCC clock configuration for independent peripheral register 14
(RCC_CCIPR14) . . . . .		544
14.10.62 RCC miscellaneous configurations reset register
(RCC_MISCSTR) . . . . .		545
14.10.63RCC embedded memories reset register (RCC_MEMRSTR)546
14.10.64RCC AHB1 reset register (RCC_AHB1RSTR)548
14.10.65RCC AHB2 reset register (RCC_AHB2RSTR)549
14.10.66RCC AHB3 reset register (RCC_AHB3RSTR)550
14.10.67RCC AHB4 reset register (RCC_AHB4RSTR)551
14.10.68RCC AHB5 reset register (RCC_AHB5RSTR)553
14.10.69RCC APB1L reset register (RCC_APB1LRSTR)556
14.10.70RCC APB1H reset register (RCC_APB1HRSTR)560
14.10.71RCC APB2 reset register (RCC_APB2RSTR)561
14.10.72RCC APB4L reset register (RCC_APB4LRSTR)563
14.10.73RCC APB4H reset register (RCC_APB4HRSTR)565
14.10.74RCC APB5 reset register (RCC_APB5RSTR)566
14.10.75RCC IC dividers enable register (RCC_DIVENR)567
14.10.76RCC embedded buses enable register (RCC_BUSENR)570
14.10.77RCC miscellaneous configurations enable register
(RCC_MISCENR)		572
14.10.78RCC embedded memories enable register (RCC_MEMENR)573
14.10.79RCC AHB1 enable register (RCC_AHB1ENR)575
14.10.80RCC AHB2 enable register (RCC_AHB2ENR)575
14.10.81RCC AHB3 enable register (RCC_AHB3ENR)576
14.10.82RCC AHB4 enable register (RCC_AHB4ENR)577
14.10.83RCC AHB5 enable register (RCC_AHB5ENR)580
14.10.84RCC APB1L enable register (RCC_APB1LENR)584
14.10.85RCC APB1H enable register (RCC_APB1HENR)587
14.10.86RCC APB2 enable register (RCC_APB2ENR)588
14.10.87RCC APB3 enable register (RCC_APB3ENR)591
14.10.88RCC APB4L enable register (RCC_APB4LENR)591
14.10.89RCC APB4H enable register (RCC_APB4HENR)593
14.10.90RCC APB5 enable register (RCC_APB5ENR)594
14.10.91RCC embedded buses sleep enable register (RCC_BUSLPENR)595
14.10.92RCC miscellaneous configurations sleep enable register
(RCC_MISCLPENR)		596
14.10.93RCC embedded memories sleep enable register
(RCC_MEMLPENR)		597
14.10.94RCC AHB1 sleep enable register (RCC_AHB1LPENR)599
14.10.95RCC AHB2 sleep enable register (RCC_AHB2LPENR)599
14.10.96RCC AHB3 sleep enable register (RCC_AHB3LPENR)600
14.10.97RCC AHB4 sleep enable register (RCC_AHB4LPENR)601
14.10.98RCC AHB5 sleep enable register (RCC_AHB5LPENR) . . . . .604
14.10.99RCC APB1L sleep enable register (RCC_APB1LLPENR) . . . . .607
14.10.100RCC APB1H sleep enable register (RCC_APB1HLPENR) . . . . .611
14.10.101RCC APB2 sleep enable register (RCC_APB2LPENR) . . . . .612
14.10.102RCC APB3 sleep enable register (RCC_APB3LPENR) . . . . .614
14.10.103RCC APB4L sleep enable register (RCC_APB4LLPENR) . . . . .615
14.10.104RCC APB4H sleep enable register (RCC_APB4HLPENR) . . . . .617
14.10.105RCC APB5 sleep enable register (RCC_APB5LPENR) . . . . .618
14.10.106RCC reset duration control register (RCC_RDCR) . . . . .619
14.10.107RCC oscillator secure configuration register 0 (RCC_SECCFGR0) . .620
14.10.108RCC oscillator privilege configuration register 0
(RCC_PRIVCFGR0) . . . . .		620
14.10.109RCC oscillator lock configuration register 0 (RCC_LOCKCFGR0) . . .621
14.10.110RCC oscillator public configuration register 0 (RCC_PUBCFGR0) . . .622
14.10.111RCC PLL secure configuration register 1 (RCC_SECCFGR1) . . . . .623
14.10.112RCC PLL privilege configuration register 1 (RCC_PRIVCFGR1) . . . .624
14.10.113RCC PLL lock configuration register 1 (RCC_LOCKCFGR1) . . . . .624
14.10.114RCC PLL public configuration register 1 (RCC_PUBCFGR1) . . . . .625
14.10.115RCC divider secure configuration register 2 (RCC_SECCFGR2) . . . .626
14.10.116RCC divider privilege configuration register 2 (RCC_PRIVCFGR2) . . .628
14.10.117RCC divider lock configuration register 2 (RCC_LOCKCFGR2) . . . . .630
14.10.118RCC divider public configuration register 2 (RCC_PUBCFGR2) . . . .633
14.10.119RCC system secure configuration register 3 (RCC_SECCFGR3) . . . .635
14.10.120RCC system privilege configuration register 3 (RCC_PRIVCFGR3) . . .636
14.10.121RCC system lock configuration register 3 (RCC_LOCKCFGR3) . . . . .637
14.10.122RCC system public configuration register 3 (RCC_PUBCFGR3) . . . .638
14.10.123RCC bus secure configuration register 4 (RCC_SECCFGR4) . . . . .638
14.10.124RCC bus privilege configuration register 4 (RCC_PRIVCFGR4) . . . .640
14.10.125RCC bus lock configuration register 4 (RCC_LOCKCFGR4) . . . . .642
14.10.126RCC bus public configuration register 4 (RCC_PUBCFGR4) . . . . .643
14.10.127RCC bus public configuration register 4 (RCC_PUBCFGR5) . . . . .645
14.10.128RCC control set register (RCC_CSR) . . . . .647
14.10.129RCC Stop mode configuration set register (RCC_STOPCSR) . . . . .648
14.10.130RCC miscellaneous reset register (RCC_MISCIRSTSR) . . . . .648
14.10.131RCC memory reset register (RCC_MEMIRSTSR) . . . . .649
14.10.132RCC AHB1 reset register (RCC_AHB1RSTSR) . . . . .650
14.10.133RCC AHB2 reset register (RCC_AHB2RSTSR) . . . . .650
14.10.134RCC AHB3 reset register (RCC_AHB3RSTSR) . . . . .651
14.10.135RCC AHB4 reset register (RCC_AHB4RSTSR) . . . . .652
14.10.136RCC AHB5 reset register (RCC_AHB5RSTSR) . . . . .653
14.10.137RCC APB1L reset register (RCC_APB1LRSTSR) . . . . .654
14.10.138RCC APB1H reset register (RCC_APB1HRSTSR) . . . . .656
14.10.139RCC APB2 reset register (RCC_APB2RSTSR) . . . . .657
14.10.140RCC APB4L reset register (RCC_APB4LRSTSR) . . . . .658
14.10.141RCC APB4H reset register (RCC_APB4HRSTSR) . . . . .659
14.10.142RCC APB5 reset register (RCC_APB5RSTSR) . . . . .659
14.10.143RCC divider enable register (RCC_DIVENSR) . . . . .660
14.10.144RCC bus enable register (RCC_BUSENSR) . . . . .661
14.10.145RCC miscellaneous enable register (RCC_MISCENSR) . . . . .662
14.10.146RCC memory enable register (RCC_MEMENSR) . . . . .663
14.10.147RCC AHB1 enable register (RCC_AHB1ENSR) . . . . .664
14.10.148RCC AHB2 enable register (RCC_AHB2ENSR) . . . . .664
14.10.149RCC AHB3 enable register (RCC_AHB3ENSR) . . . . .665
14.10.150RCC AHB4 enable register (RCC_AHB4ENSR) . . . . .666
14.10.151RCC AHB5 enable register (RCC_AHB5ENSR) . . . . .667
14.10.152RCC APB1L enable register (RCC_APB1LENSR) . . . . .668
14.10.153RCC APB1H enable register (RCC_APB1HENSR) . . . . .670
14.10.154RCC APB2 enable register (RCC_APB2ENSR) . . . . .671
14.10.155RCC APB3 enable register (RCC_APB3ENSR) . . . . .672
14.10.156RCC APB4L enable register (RCC_APB4LENSR) . . . . .672
14.10.157RCC APB4H enable register (RCC_APB4HENSR) . . . . .674
14.10.158RCC APB5 enable register (RCC_APB5ENSR) . . . . .674
14.10.159RCC bus sleep enable register (RCC_BUSLPENSR) . . . . .675
14.10.160RCC miscellaneous sleep enable register (RCC_MISCLPENSR) . . . . .675
14.10.161RCC memory sleep enable register (RCC_MEMLPENSR) . . . . .676
14.10.162RCC AHB1 sleep enable register (RCC_AHB1LPENSR) . . . . .677
14.10.163RCC AHB2 sleep enable register (RCC_AHB2LPENSR) . . . . .677
14.10.164RCC AHB3 sleep enable register (RCC_AHB3LPENSR) . . . . .678
14.10.165RCC AHB4 sleep enable register (RCC_AHB4LPENSR) . . . . .679
14.10.166RCC AHB5 sleep enable register (RCC_AHB5LPENSR) . . . . .680
14.10.167RCC APB1L sleep enable register (RCC_APB1LLPENSR) . . . . .681
14.10.168RCC APB1H sleep enable register (RCC_APB1HLPENSR) . . . . .683
14.10.169RCC APB2 sleep enable register (RCC_APB2LPENSR) . . . . .684
14.10.170RCC APB3 sleep enable register (RCC_APB3LPENSR) . . . . .685
14.10.171RCC APB4L sleep enable register (RCC_APB4LLPENSR) . . . . .685
14.10.172RCC APB4H sleep enable register (RCC_APB4HLPENSR) . . . . .687
14.10.173RCC APB5 sleep enable register (RCC_APB5LPENSR) . . . . .687
14.10.174RCC oscillator privilege configuration set register 0
(RCC_PRIVCFGSR0) . . . . .		688
14.10.175RCC oscillator public configuration set register 0
(RCC_PUBCFGSR0) . . . . .		688
14.10.176RCC PLL privilege configuration set register 1 (RCC_PRIVCFGSR1)689
14.10.177RCC PLL public configuration set register 1 (RCC_PUBCFGSR1) . .690
14.10.178RCC divider privilege configuration set register 2
(RCC_PRIVCFGSR2) . . . . .		691
14.10.179RCC divider public configuration set register 2
(RCC_PUBCFGSR2) . . . . .		692
14.10.180RCC system privilege configuration set register 3
(RCC_PRIVCFGSR3) . . . . .		694
14.10.181RCC system public configuration set register 3 (RCC_PUBCFGSR3)695
14.10.182RCC privilege configuration set register 4 (RCC_PRIVCFGSR4) . . .696
14.10.183RCC public configuration set register 4 (RCC_PUBCFGSR4) . . . . .697
14.10.184RCC public configuration set register 5 (RCC_PUBCFGSR5) . . . . .698
14.10.185RCC control clear register (RCC_CCR) . . . . .700
14.10.186RCC Stop mode configuration clear register (RCC_STOPCCR) . . . .700
14.10.187RCC miscellaneous reset clear register (RCC_MISCIRSTCR) . . . . .701
14.10.188RCC memory reset clear register (RCC_MEMIRSTCR) . . . . .702
14.10.189RCC AHB1 reset clear register (RCC_AHB1RSTCR) . . . . .703
14.10.190RCC AHB2 reset clear register (RCC_AHB2RSTCR) . . . . .703
14.10.191RCC AHB3 reset clear register (RCC_AHB3RSTCR) . . . . .704
14.10.192RCC AHB4 reset clear register (RCC_AHB4RSTCR) . . . . .704
14.10.193RCC AHB5 reset clear register (RCC_AHB5RSTCR) . . . . .705
14.10.194RCC APB1L reset clear register (RCC_APB1LRSTCR) . . . . .707
14.10.195RCC APB1H reset clear register (RCC_APB1HRSTCR) . . . . .709
14.10.196RCC APB2 reset clear register (RCC_APB2RSTCR) . . . . .709
14.10.197RCC APB4L reset clear register (RCC_APB4LRSTCR) . . . . .711
14.10.198RCC APB4H reset clear register (RCC_APB4HRSTCR) . . . . .712
14.10.199RCC APB5 reset clear register (RCC_APB5RSTCR) . . . . .712
14.10.200RCC divider enable clear register (RCC_DIVENCR) . . . . .713
14.10.201RCC bus enable clear register (RCC_BUSENCR) . . . . .714
14.10.202RCC miscellaneous enable clear register (RCC_MISCENCR) . . . . .715
14.10.203RCC memory enable clear register (RCC_MEMENCR) . . . . .715
14.10.204RCC AHB1 enable clear register (RCC_AHB1ENCR) . . . . .716
14.10.205RCC AHB2 enable clear register (RCC_AHB2ENCR) . . . . .717
14.10.206RCC AHB3 enable clear register (RCC_AHB3ENCR) . . . . .717
14.10.207RCC AHB4 enable clear register (RCC_AHB4ENCR) . . . . .718
14.10.208RCC AHB5 enable clear register (RCC_AHB5ENCR) . . . . .719
14.10.209RCC APB1L enable clear register (RCC_APB1LENCR) . . . . .721
14.10.210RCC APB1H enable clear register (RCC_APB1HENCR) . . . . .723
14.10.211RCC APB2 enable clear register (RCC_APB2ENCR) . . . . .724
14.10.212RCC APB3 enable clear register (RCC_APB3ENCR) . . . . .725
14.10.213RCC APB4L enable clear register (RCC_APB4LENCR) . . . . .725
14.10.214RCC APB4H enable clear register (RCC_APB4HENCR) . . . . .726
14.10.215RCC APB5 enable clear register (RCC_APB5ENCR) . . . . .727
14.10.216RCC bus sleep enable clear register (RCC_BUSLPENCR) . . . . .728
14.10.217RCC miscellaneous sleep enable clear register
(RCC_MISCLPENCR) . . . . .		728
14.10.218RCC memory sleep enable clear register (RCC_MEMLPENCR) . . . . .729
14.10.219RCC AHB1 sleep enable clear register (RCC_AHB1LPENCR) . . . . .730
14.10.220RCC AHB2 sleep enable clear register (RCC_AHB2LPENCR) . . . . .730
14.10.221RCC AHB3 sleep enable clear register (RCC_AHB3LPENCR) . . . . .731
14.10.222RCC AHB4 sleep enable clear register (RCC_AHB4LPENCR) . . . . .732
14.10.223RCC AHB5 sleep enable clear register (RCC_AHB5LPENCR) . . . . .733
14.10.224RCC APB1L sleep enable clear register (RCC_APB1LLPENCR) . . . . .735
14.10.225RCC APB1H sleep enable clear register (RCC_APB1HLPENCR) . . . . .736
14.10.226RCC APB2 sleep enable clear register (RCC_APB2LPENCR) . . . . .737
14.10.227RCC APB3 sleep enable clear register (RCC_APB3LPENCR) . . . . .738
14.10.228RCC APB4L sleep enable clear register (RCC_APB4LLPENCR) . . . . .739
14.10.229RCC APB4H sleep enable clear register (RCC_APB4HLPENCR) . . . . .740
14.10.230RCC APB5 sleep enable clear register (RCC_APB5LPENCR) . . . . .740
14.10.231RCC oscillator privilege configuration clear register 0
(RCC_PRIVCFGCR0) . . . . .		741
14.10.232RCC oscillator public configuration clear register 0
(RCC_PUBCFGCR0) . . . . .		742
14.10.233RCC PLL privilege configuration clear register 1
(RCC_PRIVCFGCR1) . . . . .		742
14.10.234RCC PLL public configuration clear register 1 (RCC_PUBCFGCR1) . . . . .743
14.10.235RCC divider privilege configuration clear register 2
(RCC_PRIVCFGCR2) . . . . .		744
14.10.236RCC divider public configuration clear register 2
(RCC_PUBCFGCR2) . . . . .		745
14.10.237RCC system privilege configuration clear register 3 (RCC_PRIVCFGCR3) . . . . .747
14.10.238RCC system public configuration clear register 3 (RCC_PUBCFGCR3) . . . . .748
14.10.239RCC privilege configuration clear register 4 (RCC_PRIVCFGCR4) . . . . .749
14.10.240RCC public configuration clear register 4 (RCC_PUBCFGCR4) . . . . .751
14.10.241RCC public configuration clear register 4 (RCC_PUBCFGCR5) . . . . .752
14.10.242RCC register map . . . . .754
15General-purpose I/Os (GPIO) . . . . .783
15.1Introduction . . . . .783
15.2GPIO main features . . . . .783
15.3GPIO functional description . . . . .783
15.3.1General-purpose I/O (GPIO) . . . . .785
15.3.2I/O pin AF multiplexer and mapping . . . . .786
15.3.3I/O port control registers . . . . .786
15.3.4I/O port data registers . . . . .787
15.3.5I/O data bitwise handling . . . . .787
15.3.6GPIO locking mechanism . . . . .787
15.3.7I/O AF input/output . . . . .788
15.3.8External interrupt/wake-up lines . . . . .788
15.3.9Input configuration . . . . .788
15.3.10Output configuration . . . . .788
15.3.11AF configuration . . . . .789
15.3.12Analog configuration . . . . .790
15.3.13Using HSE or LSE oscillator pins as GPIOs . . . . .791
15.3.14Using GPIO pins in V SW supply domain . . . . .791
15.3.15Advanced I/O configurations . . . . .791
15.3.16I/O pin isolation using TrustZone . . . . .791
15.3.17I/O pin isolation using privilege . . . . .793
15.4GPIO registers . . . . .794
15.4.1GPIO port x mode register (GPIOx_MODER) (x = A to H, N to Q) . . . . .794
15.4.2GPIO port x output type register (GPIOx_OTYPER) (x = A to H, N to Q) . . . . .794
15.4.3GPIO port x output speed register (GPIOx_OSPEEDR) (x = A to H, N to Q) . . . . .795
15.4.4GPIO port x pull-up/pull-down register (GPIOx_PUPDR) (x = A to H, N to Q) . . . . .795
15.4.5GPIO port x input data register (GPIOx_IDR) (x = A to H, N to Q) . . .796
15.4.6GPIO port x output data register (GPIOx_ODR) (x = A to H, N to Q) . . .796
15.4.7GPIO port x bit set/reset register (GPIOx_BSRR) (x = A to H, N to Q) . . .797
15.4.8GPIO port x configuration lock register (GPIOx_LCKR)
(x = A to H, N to Q) . . . . .		798
15.4.9GPIO port x AF low register (GPIOx_AFRL) (x = A to H, N to Q) . . . .799
15.4.10GPIO port x AF high register (GPIOx_AFRH) (x = A to H, N to Q) . . .799
15.4.11GPIO port x bit reset register (GPIOx_BRR) (x = A to H, N to Q) . . . .800
15.4.12GPIO port x secure configuration register (GPIOx_SECCFGR)
(x = A to H, N to Q) . . . . .		800
15.4.13GPIO port x privileged configuration register (GPIOx_PRIVCFGR)
(x = A to H, N to Q) . . . . .		801
15.4.14GPIO port x resource configuration lock register
(GPIOx_RCFGLOCKR) (x = A to H, N to Q) . . . . .		802
15.4.15GPIO port x delay low register (GPIOx_DELAYRL)
(x = A to H, N to Q) . . . . .		802
15.4.16GPIO port x delay high register (GPIOx_DELAYRH)
(x = A to H, N to Q) . . . . .		803
15.4.17GPIO port x advanced configuration low register (GPIOx_ADVCFGRL)
(x = A to H, N to Q) . . . . .		803
15.4.18GPIO port x advanced configuration high register (GPIOx_ADVCFGHR)
(x = A to H, N to Q) . . . . .		804
15.4.19GPIO register map . . . . .806
16System configuration controller (SYSCFG) . . . . .809
16.0.1I/O compensation cell . . . . .809
16.1SYSCFG registers . . . . .810
16.1.1SYSCFG boot pin control register (SYSCFG_BOOTCR) . . . . .810
16.1.2SYSCFG Cortex-M55 control register (SYSCFG_CM55CR) . . . . .811
16.1.3SYSCFG Cortex-M55 TCM control register
(SYSCFG_CM55TCMCR) . . . . .		811
16.1.4SYSCFG Cortex-M55 memory RW margin register
(SYSCFG_CM55RWMCR) . . . . .		812
16.1.5SYSCFG Cortex-M55 SVTOR control register
(SYSCFG_INITSVTORCR) . . . . .		813
16.1.6SYSCFG Cortex-M55 NSVTOR control register
(SYSCFG_INITNSVTORCR) . . . . .		813
16.1.7SYSCFG Cortex-M55 reset type control register
(SYSCFG_CM55RSTCR) . . . . .		814
16.1.8SYSCFG Cortex-M55 P-AHB write posting control register
(SYSCFG_CM55PAHBWPR) . . . . .		814
16.1.9SYSCFG VENCRAM control register (SYSCFG_VENCRAMCR) . . . .815
16.1.10SYSCFG potential tamper reset register
(SYSCFG_POTTAMPRSTCR) . . . . .		815
16.1.11SYSCFG NPUNIC QoS control register (SYSCFG_NPUNICQOSCR)816
16.1.12SYSCFG AHB-AXI bridge early write response control register
(SYSCFG_ICNEWRCR) . . . . .		816
16.1.13SYSCFG ICN clock gating control register (SYSCFG_ICNCGCR) . . .817
16.1.14SYSCFG VDDIO4 compensation cell control register
(SYSCFG_VDDIO4CCCR) . . . . .		818
16.1.15SYSCFG VDDIO4 compensation cell status register
(SYSCFG_VDDIO4CCSR) . . . . .		818
16.1.16SYSCFG VDDIO5 compensation cell control register
(SYSCFG_VDDIO5CCCR) . . . . .		819
16.1.17SYSCFG VDDIO5 compensation cell status register
(SYSCFG_VDDIO5CCSR) . . . . .		820
16.1.18SYSCFG VDDIO2 compensation cell control register
(SYSCFG_VDDIO2CCCR) . . . . .		820
16.1.19SYSCFG VDDIO2 compensation cell status register
(SYSCFG_VDDIO2CCSR) . . . . .		821
16.1.20SYSCFG VDDIO3 compensation cell control register
(SYSCFG_VDDIO3CCCR) . . . . .		822
16.1.21SYSCFG VDDIO3 compensation cell status register
(SYSCFG_VDDIO3CCSR) . . . . .		822
16.1.22SYSCFG VDD compensation cell control register
(SYSCFG_VDDCCCR) . . . . .		823
16.1.23SYSCFG VDD compensation cell status register
(SYSCFG_VDDCCSR) . . . . .		824
16.1.24SYSCFG control timer break register (SYSCFG_CBR) . . . . .824
16.1.25SYSCFG DMA CID secure control register (SYSCFG_SEC_AIDCR) .825
16.1.26SYSCFG FMC retiming logic control register
(SYSCFG_FMC_RETIMECR) . . . . .		826
16.1.27SYSCFG NPU RAM interleaving control register
(SYSCFG_NPU_ICNCR) . . . . .		826
16.1.28SYSCFG boot pin status register (SYSCFG_BOOTSR) . . . . .827
16.1.29SYSCFG AHB write posting address error register
(SYSCFG_AHBWP_ERROR_SR) . . . . .		827
16.1.30SYSCFG SMPS observable signals through HDP selection
configuration register (SYSCFG_SMPSHDPCCR) . . . . .		828
16.1.31SYSCFG DMA CID nonsecure control register
(SYSCFG_SECPRIV_AIDCR) . . . . .		828
16.1.32SYSCFG device ID register (SYSCFG_DEVICEID) . . . . .829
16.1.33SYSCFG register map . . . . .829
17Peripherals interconnect matrix . . . . .833
17.1Introduction . . . . .833
17.2Connection summary . . . . .833
18High-performance direct memory access controller (HPDMA) . . . . .834
18.1HPDMA introduction . . . . .834
18.2HPDMA main features . . . . .834
18.3HPDMA implementation . . . . .835
18.3.1HPDMA channels . . . . .835
18.3.2HPDMA allowed AXI maximum burst length . . . . .836
18.3.3HPDMA in low-power modes . . . . .836
18.3.4HPDMA requests . . . . .836
18.3.5HPDMA block requests . . . . .841
18.3.6HPDMA channels with peripheral early termination . . . . .841
18.3.7HPDMA triggers . . . . .842
18.4HPDMA functional description . . . . .845
18.4.1HPDMA block diagram . . . . .845
18.4.2HPDMA channel state and direct programming without
any linked-list . . . . .		846
18.4.3HPDMA channel suspend and resume . . . . .847
18.4.4HPDMA channel abort and restart . . . . .848
18.4.5HPDMA linked-list data structure . . . . .849
18.4.6Linked-list item transfer execution . . . . .852
18.4.7HPDMA channel state and linked-list programming
in run-to-completion mode . . . . .		852
18.4.8HPDMA channel state and linked-list programming
in link step mode . . . . .		856
18.4.9HPDMA channel state and linked-list programming . . . . .863
18.4.10HPDMA FIFO-based transfers . . . . .865
18.4.11HPDMA transfer request and arbitration . . . . .881
18.4.12HPDMA triggered transfer . . . . .885
18.4.13HPDMA circular buffering with linked-list programming . . . . .886
18.4.14HPDMA transfer in peripheral flow-control mode . . . . .888
18.4.15HPDMA secure/nonsecure channel . . . . .889
18.4.16HPDMA privileged/unprivileged channel . . . . .890
18.4.17HPDMA error management . . . . .890
18.5HPDMA in debug mode . . . . .892
18.6HPDMA in low-power modes . . . . .892
18.7HPDMA interrupts . . . . .893
18.8HPDMA registers . . . . .894
18.8.1HPDMA secure configuration register (HPDMA_SECCFGR) . . . . .894
18.8.2HPDMA privileged configuration register (HPDMA_PRIVCFGR) . . . . .895
18.8.3HPDMA configuration lock register (HPDMA_RCFGLOCKR) . . . . .896
18.8.4HPDMA nonsecure masked interrupt status register
(HPDMA_MISR) . . . . .		896
18.8.5HPDMA secure masked interrupt status register (HPDMA_SMISR) . . . . .897
18.8.6HPDMA channel x linked-list base address register
(HPDMA_CxLBAR) . . . . .		898
18.8.7HPDMA channel x CID register (HPDMA_CxCIDCFGR) . . . . .899
18.8.8HPDMA channel x semaphore control register
(HPDMA_CxSEMCR) . . . . .		900
18.8.9HPDMA channel x flag clear register (HPDMA_CxFCR) . . . . .902
18.8.10HPDMA channel x status register (HPDMA_CxSR) . . . . .903
18.8.11HPDMA channel x control register (HPDMA_CxCR) . . . . .904
18.8.12HPDMA channel x transfer register 1 (HPDMA_CxTR1) . . . . .907
18.8.13HPDMA channel x transfer register 2 (HPDMA_CxTR2) . . . . .911
18.8.14HPDMA channel x block register 1 (HPDMA_CxBR1) . . . . .915
18.8.15HPDMA channel x alternate block register 1 (HPDMA_CxBR1) . . . . .916
18.8.16HPDMA channel x source address register (HPDMA_CxSAR) . . . . .919
18.8.17HPDMA channel x destination address register (HPDMA_CxDAR) . . . . .921
18.8.18HPDMA channel x transfer register 3 (HPDMA_CxTR3) . . . . .923
18.8.19HPDMA channel x block register 2 (HPDMA_CxBR2) . . . . .924
18.8.20HPDMA channel x linked-list address register (HPDMA_CxLLR) . . . . .925
18.8.21HPDMA channel x alternate linked-list address register
(HPDMA_CxLLR) . . . . .		927
18.8.22HPDMA register map . . . . .929
19General purpose direct memory access controller (GPDMA) . . . . .931
19.1GPDMA introduction . . . . .931
19.2GPDMA main features . . . . .931
19.3GPDMA implementation . . . . .932
19.3.1GPDMA channels . . . . .932
19.3.2GPDMA in low-power modes . . . . .933
19.3.3GPDMA requests . . . . .933
19.3.4GPDMA block requests . . . . .938
19.3.5GPDMA channels with peripheral early termination . . . . .938
19.3.6GPDMA triggers . . . . .938
19.4GPDMA functional description . . . . .942
19.4.1GPDMA block diagram . . . . .942
19.4.2GPDMA channel state and direct programming without any linked-list942
19.4.3GPDMA channel suspend and resume . . . . .943
19.4.4GPDMA channel abort and restart . . . . .944
19.4.5GPDMA linked-list data structure . . . . .945
19.4.6Linked-list item transfer execution . . . . .948
19.4.7GPDMA channel state and linked-list programming
in run-to-completion mode . . . . .		948
19.4.8GPDMA channel state and linked-list programming in link step mode952
19.4.9GPDMA channel state and linked-list programming . . . . .959
19.4.10GPDMA FIFO-based transfers . . . . .961
19.4.11GPDMA transfer request and arbitration . . . . .968
19.4.12GPDMA triggered transfer . . . . .972
19.4.13GPDMA circular buffering with linked-list programming . . . . .973
19.4.14GPDMA transfer in peripheral flow-control mode . . . . .975
19.4.15GPDMA secure/nonsecure channel . . . . .976
19.4.16GPDMA privileged/unprivileged channel . . . . .977
19.4.17GPDMA error management . . . . .977
19.5GPDMA in debug mode . . . . .979
19.6GPDMA in low-power modes . . . . .979
19.7GPDMA interrupts . . . . .980
19.8GPDMA registers . . . . .981
19.8.1GPDMA secure configuration register (GPDMA_SECCFGR) . . . . .981
19.8.2GPDMA privileged configuration register (GPDMA_PRIVCFGR) . . . . .982
19.8.3GPDMA configuration lock register (GPDMA_RCFGLOCKR) . . . . .982
19.8.4GPDMA nonsecure masked interrupt status register
(GPDMA_MISR) . . . . .		983
19.8.5GPDMA secure masked interrupt status register (GPDMA_SMISR) . . . . .984
19.8.6GPDMA channel x linked-list base address register
(GPDMA_CxLBAR) . . . . .		984
19.8.7GPDMA channel x flag clear register (GPDMA_CxFGR) . . . . .985
19.8.8GPDMA channel x status register (GPDMA_CxSR) . . . . .986
19.8.9GPDMA channel x control register (GPDMA_CxCR) . . . . .987
19.8.10GPDMA channel x transfer register 1 (GPDMA_CxTR1) . . . . .989

20 Neural-ART accelerator™ (NPU) . . . . . 1012

20.4.5Chained convolutions . . . . .1027
20.4.6Split convolutions . . . . .1027
20.5Address space . . . . .1028
20.6System integration . . . . .1029
20.6.1System considerations . . . . .1029
20.6.2Architecture intent . . . . .1029
21Chrom-ART Accelerator controller (DMA2D) . . . . .1032
21.1DMA2D introduction . . . . .1032
21.2DMA2D main features . . . . .1032
21.3DMA2D functional description . . . . .1033
21.3.1General description . . . . .1033
21.3.2DMA2D internal signals . . . . .1034
21.3.3DMA2D control . . . . .1035
21.3.4DMA2D foreground and background FIFOs . . . . .1035
21.3.5DMA2D foreground and background PFC . . . . .1035
21.3.6DMA2D foreground and background CLUT interface . . . . .1037
21.3.7DMA2D blender . . . . .1039
21.3.8DMA2D output PFC . . . . .1039
21.3.9DMA2D output FIFO . . . . .1039
21.3.10DMA2D output FIFO byte reordering . . . . .1040
21.3.11DMA2D AXI master port timer . . . . .1042
21.3.12DMA2D transactions . . . . .1042
21.3.13DMA2D configuration . . . . .1042
21.3.14YCbCr support . . . . .1046
21.3.15DMA2D transfer control (start, suspend, abort, and completion) . . . . .1046
21.3.16Watermark . . . . .1047
21.3.17Error management . . . . .1047
21.3.18AXI dead time . . . . .1047
21.4DMA2D interrupts . . . . .1047
21.5DMA2D registers . . . . .1048
21.5.1DMA2D control register (DMA2D_CR) . . . . .1048
21.5.2DMA2D interrupt status register (DMA2D_ISR) . . . . .1050
21.5.3DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . .1050
21.5.4DMA2D foreground memory address register (DMA2D_FGMAR) . . . . .1051
21.5.5DMA2D foreground offset register (DMA2D_FGOR) . . . . .1051

21.5.6 DMA2D background memory address register (DMA2D_BGMAR) . 1052

21.5.7 DMA2D background offset register (DMA2D_BGOR) . . . . . 1052

21.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . 1053

21.5.9 DMA2D foreground color register (DMA2D_FGCOLR) . . . . . 1055

21.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR) . . . 1055

21.5.11 DMA2D background color register (DMA2D_BGCOLR) . . . . . 1057

21.5.12 DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . . 1057

21.5.13 DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . . 1058

21.5.14 DMA2D output PFC control register (DMA2D_OPFCCR) . . . . . 1058

21.5.15 DMA2D output color register (DMA2D_OCOLR) . . . . . 1059

21.5.16 DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . . 1060

21.5.17 DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . . 1060

21.5.18 DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . . 1061

21.5.19 DMA2D output memory address register (DMA2D_OMAR) . . . . . 1061

21.5.20 DMA2D output offset register (DMA2D_OOR) . . . . . 1062

21.5.21 DMA2D number of line register (DMA2D_NLR) . . . . . 1062

21.5.22 DMA2D line watermark register (DMA2D_LWR) . . . . . 1063

21.5.23 DMA2D AXI master timer configuration register (DMA2D_AMTCR) . 1063

21.5.24 DMA2D foreground CLUT (DMA2D_FGCLUTx) . . . . . 1064

21.5.25 DMA2D background CLUT (DMA2D_BGCLUTx) . . . . . 1064

21.5.26 DMA2D register map . . . . . 1065

22 Chrom-GRC (GFXMMU) . . . . . 1067

22.1 GFXMMU introduction . . . . . 1067

22.2 GFXMMU main features . . . . . 1067

22.3 GFXMMU functional and architectural description . . . . . 1067

22.3.1 GFXMMU block diagram . . . . . 1067

22.3.2 GFXMMU internal signals . . . . . 1068

22.3.3 Virtual memory . . . . . 1068

22.3.4 Packing and unpacking . . . . . 1070

22.3.5 MMU architecture . . . . . 1071

22.4 GTZC TZIC GFXMMU interrupts . . . . . 1074

22.5 GFXMMU registers . . . . . 1075

22.5.1 GFXMMU configuration register (GFXMMU_CR) . . . . . 1075

22.5.2 GFXMMU status register (GFXMMU_SR) . . . . . 1077

22.5.3GFXMMU flag clear register (GFXMMU_FCR) . . . . .1077
22.5.4GFXMMU default value register (GFXMMU_DVR) . . . . .1078
22.5.5GFXMMU default alpha register (GFXMMU_DAR) . . . . .1078
22.5.6GFXMMU buffer x configuration register (GFXMMU_BxCR) . . . . .1079
22.5.7GFXMMU LUT entry x low (GFXMMU_LUTxL) . . . . .1079
22.5.8GFXMMU LUT entry x high (GFXMMU_LUTxH) . . . . .1080
22.5.9GFXMMU register map . . . . .1080
23Graphic timer (GFXTIM) . . . . .1082
23.1GFXTIM introduction . . . . .1082
23.2GFXTIM main features . . . . .1082
23.3GFXTIM functional description . . . . .1082
23.3.1Block diagram . . . . .1082
23.3.2GFXTIM pins and internal signals . . . . .1083
23.3.3Clock generator . . . . .1084
23.3.4Example of clock generator configuration . . . . .1086
23.3.5Absolute timers . . . . .1090
23.3.6Relative timers . . . . .1091
23.3.7Tearing-effect detection . . . . .1092
23.3.8Event generator . . . . .1092
23.3.9Watchdog timer . . . . .1093
23.4GFXTIM interrupts . . . . .1094
23.5GFXTIM registers . . . . .1095
23.5.1GFXTIM configuration register (GFXTIM_CR) . . . . .1095
23.5.2GFXTIM clock generator configuration register (GFXTIM_CGCR) . . . . .1096
23.5.3GFXTIM timers configuration register (GFXTIM_TCR) . . . . .1098
23.5.4GFXTIM timers disable register (GFXTIM_TDR) . . . . .1099
23.5.5GFXTIM events control register (GFXTIM_EVCR) . . . . .1100
23.5.6GFXTIM events selection register (GFXTIM_EVSR) . . . . .1100
23.5.7GFXTIM watchdog timer configuration register
(GFXTIM_WDGTCR) . . . . .		1102
23.5.8GFXTIM interrupt status register (GFXTIM_ISR) . . . . .1104
23.5.9GFXTIM interrupt clear register (GFXTIM_ICR) . . . . .1105
23.5.10GFXTIM interrupt enable register (GFXTIM_IER) . . . . .1107
23.5.11GFXTIM timers status register (GFXTIM_TSR) . . . . .1109
23.5.12GFXTIM line-clock counter reload register (GFXTIM_LCCRR) . . . . .1110
23.5.13GFXTIM frame-clock counter reload register (GFXTIM_FCCRR) . . . . .1110
23.5.14GFXTIM absolute time register (GFXTIM_ATR) . . . . .1110
23.5.15GFXTIM absolute frame counter register (GFXTIM_AFCR) . . . . .1111
23.5.16GFXTIM absolute line counter register (GFXTIM_ALCR) . . . . .1111
23.5.17GFXTIM absolute frame counter compare 1 register
(GFXTIM_AFCC1R) . . . . .		1112
23.5.18GFXTIM absolute line counter compare 1 register
(GFXTIM_ALCC1R) . . . . .		1112
23.5.19GFXTIM absolute line counter compare 2 register
(GFXTIM_ALCC2R) . . . . .		1112
23.5.20GFXTIM relative frame counter 1 register (GFXTIM_RFC1R) . . . . .1113
23.5.21GFXTIM relative frame counter 1 reload register
(GFXTIM_RFC1RR) . . . . .		1113
23.5.22GFXTIM relative frame counter 2 register (GFXTIM_RFC2R) . . . . .1114
23.5.23GFXTIM relative frame counter 2 reload register
(GFXTIM_RFC2RR) . . . . .		1114
23.5.24GFXTIM watchdog counter register (GFXTIM_WDGCR) . . . . .1114
23.5.25GFXTIM watchdog reload register (GFXTIM_WDGRR) . . . . .1115
23.5.26GFXTIM watchdog pre-alarm register (GFXTIM_WDGPAR) . . . . .1115
23.5.27GFXTIM register map . . . . .1115
24Nested vectored interrupt controller (NVIC) . . . . .1118
24.1NVIC features . . . . .1118
24.1.1SysTick calibration value register . . . . .1118
24.1.2Interrupt and exception vectors . . . . .1118
25Extended interrupts and event controller (EXTI) . . . . .1126
25.1EXTI main features . . . . .1126
25.2EXTI implementation . . . . .1127
25.3EXTI block diagram . . . . .1127
25.3.1EXTI connections between peripherals and CPU . . . . .1128
25.3.2EXTI wake-up interrupt list . . . . .1129
25.4EXTI functional description . . . . .1131
25.4.1EXTI configurable event input wake-up . . . . .1131
25.4.2EXTI direct event input wake-up . . . . .1132
25.4.3EXTI multiplexer selection . . . . .1132
25.5EXTI functional behavior . . . . .1133
25.6EXTI event protection . . . . .1134
25.6.1EXTI register security protection . . . . .1134
25.6.2EXTI register privilege protection . . . . .1135
25.7EXTI registers . . . . .1135
25.7.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .1135
25.7.2EXTI falling trigger selection register (EXTI_FTSR1) . . . . .1136
25.7.3EXTI software interrupt event register (EXTI_SWIER1) . . . . .1137
25.7.4EXTI rising edge pending register (EXTI_RPR1) . . . . .1138
25.7.5EXTI falling edge pending register (EXTI_FPR1) . . . . .1138
25.7.6EXTI security configuration register (EXTI_SECCFGR1) . . . . .1139
25.7.7EXTI privilege configuration register (EXTI_PRIVCFGR1) . . . . .1139
25.7.8EXTI rising trigger selection register (EXTI_RTSR2) . . . . .1140
25.7.9EXTI falling trigger selection register (EXTI_FTSR2) . . . . .1141
25.7.10EXTI software interrupt event register (EXTI_SWIER2) . . . . .1142
25.7.11EXTI rising edge pending register (EXTI_RPR2) . . . . .1143
25.7.12EXTI falling edge pending register (EXTI_FPR2) . . . . .1144
25.7.13EXTI security enable register (EXTI_SECCFGR2) . . . . .1145
25.7.14EXTI privilege enable register (EXTI_PRIVCFGR2) . . . . .1146
25.7.15EXTI rising trigger selection register (EXTI_RTSR3) . . . . .1146
25.7.16EXTI falling trigger selection register (EXTI_FTSR3) . . . . .1147
25.7.17EXTI software interrupt event register (EXTI_SWIER3) . . . . .1148
25.7.18EXTI rising edge pending register (EXTI_RPR3) . . . . .1149
25.7.19EXTI falling edge pending register (EXTI_FPR3) . . . . .1149
25.7.20EXTI security enable register (EXTI_SECCFGR3) . . . . .1150
25.7.21EXTI privilege enable register (EXTI_PRIVCFGR3) . . . . .1151
25.7.22EXTI external interrupt selection register 1 (EXTI_EXTICR1) . . . . .1151
25.7.23EXTI external interrupt selection register 2 (EXTI_EXTICR2) . . . . .1154
25.7.24EXTI external interrupt selection register 3 (EXTI_EXTICR3) . . . . .1157
25.7.25EXTI external interrupt selection register 4 (EXTI_EXTICR4) . . . . .1159
25.7.26EXTI lock register (EXTI_LOCKR) . . . . .1162
25.7.27EXTI CPU wake-up with interrupt mask register 1 (EXTI_IMR1) . . . . .1162
25.7.28EXTI CPU wake-up with event mask register 1 (EXTI_EMR1) . . . . .1163
25.7.29EXTI CPU wake-up with interrupt mask register 2 (EXTI_IMR2) . . . . .1163
25.7.30EXTI CPU wake-up with event mask register 2 (EXTI_EMR2) . . . . .1164
25.7.31EXTI CPU wake-up with interrupt mask register 3 (EXTI_IMR3) . . . . .1164
25.7.32EXTI CPU wake-up with event mask register 3 (EXTI_EMR3) . . . . .1165
25.7.33EXTI register map . . . . .1167
26Cyclic redundancy check calculation unit (CRC) . . . . .1170
26.1CRC introduction . . . . .1170
26.2CRC main features . . . . .1170
26.3CRC functional description . . . . .1171
26.3.1CRC block diagram . . . . .1171
26.3.2CRC internal signals . . . . .1171
26.3.3CRC operation . . . . .1171
26.4CRC registers . . . . .1173
26.4.1CRC data register (CRC_DR) . . . . .1173
26.4.2CRC independent data register (CRC_IDR) . . . . .1173
26.4.3CRC control register (CRC_CR) . . . . .1174
26.4.4CRC initial value (CRC_INIT) . . . . .1175
26.4.5CRC polynomial (CRC_POL) . . . . .1175
26.4.6CRC register map . . . . .1176
27Flexible memory controller (FMC) . . . . .1177
27.1FMC main features . . . . .1177
27.2FMC implementation . . . . .1178
27.3FMC block diagram . . . . .1179
27.4FMC internal signals . . . . .1180
27.5AHB interface . . . . .1180
27.6AXI interface . . . . .1180
27.6.1Supported memories and transactions . . . . .1181
27.7External device address mapping . . . . .1182
27.7.1NOR/PSRAM address mapping . . . . .1183
27.7.2NAND flash memory address mapping . . . . .1183
27.7.3SDRAM address mapping . . . . .1184
27.8NOR flash/PSRAM controller . . . . .1187
27.8.1External memory interface signals . . . . .1189
27.8.2Supported memories and transactions . . . . .1191
27.8.3General timing rules . . . . .1193
27.8.4NOR flash/PSRAM controller asynchronous transactions . . . . .1193
27.8.5Synchronous transactions . . . . .1212
27.8.6NOR/PSRAM controller registers . . . . .1217
27.9NAND flash controller . . . . .1226
27.9.1External memory interface signals . . . . .1227
27.9.2NAND flash supported memories and transactions . . . . .1228
27.9.3Timing diagrams for NAND flash memory . . . . .1229
27.9.4NAND flash operations . . . . .1230
27.9.5NAND flash prewait function . . . . .1231
27.9.6NAND ECC controller . . . . .1232
27.9.7FMC command sequencer . . . . .1235
27.9.8NAND flash controller interrupt . . . . .1242
27.9.9NAND flash controller registers . . . . .1243
27.10SDRAM controller . . . . .1267
27.10.1SDRAM controller main features . . . . .1267
27.10.2SDRAM External memory interface signals . . . . .1267
27.10.3SDRAM controller functional description . . . . .1268
27.10.4Low-power modes . . . . .1274
27.10.5SDRAM controller registers . . . . .1276
27.11FMC register map . . . . .1284
28Extended-SPI interface (XSPI) . . . . .1289
28.1XSPI introduction . . . . .1289
28.2XSPI main features . . . . .1289
28.3XSPI implementation . . . . .1290
28.4XSPI functional description . . . . .1291
28.4.1XSPI block diagram . . . . .1291
28.4.2XSPI pins and internal signals . . . . .1295
28.4.3Clock constraints . . . . .1296
28.4.4XSPI interface to memory modes . . . . .1296
28.4.5XSPI regular-command protocol . . . . .1296
28.4.6XSPI regular-command protocol signal interface . . . . .1300
28.4.7HyperBus protocol . . . . .1305
28.4.8Specific features . . . . .1310
28.4.9XSPI operating modes introduction . . . . .1312
28.4.10XSPI indirect mode . . . . .1312
28.4.11XSPI automatic status-polling mode . . . . .1314
28.4.12XSPI memory-mapped mode . . . . .1314
28.4.13XSPI configuration introduction . . . . .1315
28.4.14XSPI system configuration . . . . .1315
28.4.15XSPI device configuration . . . . .1316
28.4.16XSPI regular-command mode configuration . . . . .1318
28.4.17XSPI HyperBus protocol configuration . . . . .1321
28.4.18XSPI error management . . . . .1321
28.4.19XSPI high-speed interface and calibration . . . . .1322
28.4.20XSPI BUSY and ABORT . . . . .1323
28.4.21XSPI reconfiguration or deactivation . . . . .1323
28.4.22NCS behavior . . . . .1324
28.4.23Software control of two external memories . . . . .1324
28.4.24Hardware-controlled extended memory support . . . . .1325
28.5Address alignment and data number . . . . .1326
28.6XSPI interrupts . . . . .1328
28.7XSPI registers . . . . .1328
28.7.1XSPI control register (XSPI_CR) . . . . .1328
28.7.2XSPI device configuration register 1 (XSPI_DCR1) . . . . .1332
28.7.3XSPI device configuration register 2 (XSPI_DCR2) . . . . .1333
28.7.4XSPI device configuration register 3 (XSPI_DCR3) . . . . .1334
28.7.5XSPI device configuration register 4 (XSPI_DCR4) . . . . .1335
28.7.6XSPI status register (XSPI_SR) . . . . .1335
28.7.7XSPI flag clear register (XSPI_FCR) . . . . .1336
28.7.8XSPI data length register (XSPI_DLR) . . . . .1337
28.7.9XSPI address register (XSPI_AR) . . . . .1337
28.7.10XSPI data register (XSPI_DR) . . . . .1338
28.7.11XSPI polling status mask register (XSPI_PSMKR) . . . . .1339
28.7.12XSPI polling status match register (XSPI_PSMAR) . . . . .1339
28.7.13XSPI polling interval register (XSPI_PIR) . . . . .1340
28.7.14XSPI communication configuration register (XSPI_CCR) . . . . .1340
28.7.15XSPI timing configuration register (XSPI_TCR) . . . . .1342
28.7.16XSPI instruction register (XSPI_IR) . . . . .1343
28.7.17XSPI alternate bytes register (XSPI_ABR) . . . . .1343
28.7.18XSPI low-power timeout register (XSPI_LPTR) . . . . .1343
28.7.19XSPI wrap communication configuration register
(XSPI_WPCCR) . . . . .		1344
28.7.20XSPI wrap timing configuration register (XSPI_WPTCR) . . . . .1346
28.7.21XSPI wrap instruction register (XSPI_WPIR) . . . . .1347
28.7.22XSPI wrap alternate byte register (XSPI_WPABR) . . . . .1347
28.7.23XSPI write communication configuration register
(XSPI_WCCR) . . . . .		1347
28.7.24XSPI write timing configuration register (XSPI_WTCR) . . . . .1349
28.7.25XSPI write instruction register (XSPI_WIR) . . . . .1350
28.7.26XSPI write alternate byte register (XSPI_WABR) . . . . .1350
28.7.27XSPI HyperBus latency configuration register (XSPI_HLCR) . . . . .1351
28.7.28XSPI full-cycle calibration configuration (XSPI_CALFCR) . . . . .1351
28.7.29XSPI DLL master calibration configuration (XSPI_CALMR) . . . . .1352
28.7.30XSPI DLL slave output calibration configuration
(XSPI_CALSOR) . . . . .		1353
28.7.31XSPI DLL slave input calibration configuration (XSPI_CALSIR) . . . . .1354
28.7.32XSPI register map . . . . .1354
29XSPI I/O manager (XSPIM) . . . . .1358
29.1XSPIM introduction . . . . .1358
29.2XSPIM main features . . . . .1358
29.3XSPIM implementation . . . . .1358
29.4XSPIM functional description . . . . .1358
29.4.1XSPIM block diagram . . . . .1358
29.4.2XSPIM input/output pins . . . . .1359
29.4.3XSPIM matrix . . . . .1360
29.4.4XSPIM multiplexed mode . . . . .1360
29.5Use cases description . . . . .1361
29.5.1XSPIs direct octal mode . . . . .1361
29.5.2XSPI direct 16-bit mode . . . . .1362
29.5.3XSPI dual-octal mode . . . . .1363
29.5.4XSPI swapped mode . . . . .1364
29.5.5Two XSPIs multiplexed mode to Port 1 accessing two external
memories, and the third XSPI accessing Port 2 . . . . .		1365
29.5.6Two XSPIs multiplexed mode to Port 2 accessing two external
memories, and the third XSPI accessing Port 1 . . . . .		1366
29.5.7XSPI1 and XSPI2 drive a single external memory . . . . .1367
29.5.8A single XSPI drives two external memories . . . . .1368
29.6XSPIM registers . . . . .1370
29.6.1XSPIM control register (XSPIM_CR) . . . . .1370
29.6.2XSPIM register map . . . . .1371
30Secure digital input/output MultiMediaCard interface (SDMMC) . . . . .1372
30.1SDMMC main features . . . . .1372
30.2SDMMC implementation . . . . .1372
30.3SDMMC bus topology . . . . .1373
30.4SDMMC operation modes . . . . .1375
30.5SDMMC functional description . . . . .1376
30.5.1SDMMC block diagram . . . . .1376
30.5.2SDMMC pins and internal signals . . . . .1376
30.5.3General description . . . . .1377
30.5.4SDMMC adapter . . . . .1379
30.5.5SDMMC AHB slave interface . . . . .1401
30.5.6SDMMC AHB master interface . . . . .1402
30.5.7AHB and SDMMC_CK clock relation . . . . .1405
30.6Card functional description . . . . .1406
30.6.1SD I/O mode . . . . .1406
30.6.2CMD12 send timing . . . . .1414
30.6.3Sleep (CMD5) . . . . .1418
30.6.4Interrupt mode (Wait-IRQ) . . . . .1419
30.6.5Boot operation . . . . .1420
30.6.6Response R1b handling . . . . .1423
30.6.7Reset and card cycle power . . . . .1424
30.7Hardware flow control . . . . .1425
30.7.1Hardware flow control during data transfer . . . . .1425
30.7.2Block gap hardware flow control . . . . .1426
30.8Ultra-high-speed phase I (UHS-I) voltage switch . . . . .1427
30.9SDMMC interrupts . . . . .1431
30.10SDMMC registers . . . . .1432
30.10.1SDMMC power control register (SDMMC_POWER) . . . . .1432
30.10.2SDMMC clock control register (SDMMC_CLKCR) . . . . .1433
30.10.3SDMMC argument register (SDMMC_ARGR) . . . . .1435
30.10.4SDMMC command register (SDMMC_CMDR) . . . . .1435
30.10.5SDMMC command response register (SDMMC_RESPCMDR) . . . . .1437
30.10.6SDMMC response x register (SDMMC_RESPxR) . . . . .1438
30.10.7SDMMC data timer register (SDMMC_DTIMER) . . . . .1438
30.10.8SDMMC data length register (SDMMC_DLENR) . . . . .1439
30.10.9SDMMC data control register (SDMMC_DCTRL) . . . . .1440
30.10.10SDMMC data counter register (SDMMC_DCNTR) . . . . .1441
30.10.11SDMMC status register (SDMMC_STAR) . . . . .1442
30.10.12SDMMC interrupt clear register (SDMMC_ICR) . . . . .1445
30.10.13SDMMC mask register (SDMMC_MASKR) . . . . .1447
30.10.14SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . .1450
30.10.15SDMMC data FIFO threshold register (SDMMC_FIFOTHRR) . . . . .1450
30.10.16SDMMC DMA control register (SDMMC_IDMACTLRLR) . . . . .1451
30.10.17SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . .1451
30.10.18SDMMC IDMA buffer base address register
(SDMMC_IDMABASER) . . . . .		1452
30.10.19SDMMC IDMA linked list address register (SDMMC_IDMALAR) . . .1452
30.10.20SDMMC IDMA linked list memory base register
(SDMMC_IDMABAR) . . . . .		1453
30.10.21SDMMC data FIFO registers x (SDMMC_FIFORx) . . . . .1454
30.10.22SDMMC register map . . . . .1454
31Delay block (DLYB) . . . . .1457
31.1DLYB introduction . . . . .1457
31.2DLYB main features . . . . .1457
31.3DLYB implementation . . . . .1457
31.4DLYB functional description . . . . .1457
31.4.1DLYB diagram . . . . .1457
31.4.2DLYB internal signals . . . . .1459
31.4.3General description . . . . .1461
31.4.4Lock mode procedure . . . . .1462
31.4.5Bypass mode procedure . . . . .1462
31.5DLYB SDMMC registers description . . . . .1463
31.5.1Delay block SDMMC DLL configuration (DLYBSD_CFG) . . . . .1463
31.5.2Delay block SDMMC DLL status (DLYBSD_STATUS) . . . . .1464
31.5.3DLYB register map . . . . .1464
32Analog-to-digital converters (ADC) . . . . .1466
32.1ADC introduction . . . . .1466
32.2ADC main features . . . . .1466
32.3ADC implementation . . . . .1468
32.4ADC functional description . . . . .1469
32.4.1ADC block diagram . . . . .1469
32.4.2ADC pins and internal signals . . . . .1470
32.4.3ADC clocks . . . . .1473
32.4.4ADC connectivity . . . . .1475
32.4.5Slave AHB interface . . . . .1477
32.4.6ADC Deep-power-down mode (DEEPPWD) . . . . .1477
32.4.7Single-ended and differential input channels . . . . .1477
32.4.8Calibration (ADCAL, CALADDOS, ADC_CALFACT) . . . . .1478
32.4.9ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .1480
32.4.10Constraints when writing the ADC control bits . . . . .1481
32.4.11Channel selection (ADC_SQRY, ADC_JSQR) . . . . .1482
32.4.12Channel preselection register (ADC_PCSEL) . . . . .1482
32.4.13Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .1483
32.4.14Single conversion mode . . . . .1484
32.4.15Continuous conversion mode (CONT = 1) . . . . .1485
32.4.16Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .1486
32.4.17Starting conversions (ADSTART, JADSTART) . . . . .1487
32.4.18Timing . . . . .1488
32.4.19Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .1489
32.4.20Conversion on external trigger and trigger polarity
(EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .		1491
32.4.21Injected channel management . . . . .1492
32.4.22Programmable resolution (RES) - fast conversion mode . . . . .1493
32.4.23End of conversion and end of sampling phase
(EOC, JEOC, EOSMP) . . . . .		1494
32.4.24End of conversion sequence (EOS, JEOS) . . . . .1494
32.4.25Timing diagram examples (single/continuous modes,
hardware/software triggers) . . . . .		1495
32.4.26Data management . . . . .1497
32.4.27Managing conversions using the MDF . . . . .1505
32.4.28Dynamic low-power features . . . . .1506
32.4.29Analog window watchdog (AWD1EN, JAWD1EN,
AWD1SGL, AWD1CH, AWDCH of ADC_AWD2CR and
ADC_AWD3CR, HTR, LTR, AWDFILT) . . . . .		1509
32.4.30Oversampler . . . . .1514
32.4.31Dual ADC modes . . . . .1520
32.4.32VBAT supply monitoring . . . . .1536
32.4.33Monitoring the internal voltage reference . . . . .1537
32.4.34Monitoring the supply voltage . . . . .1539
32.5ADC interrupts . . . . .1539
32.6ADC registers (for each ADC) . . . . .1540
32.6.1ADC interrupt and status register (ADC_ISR) . . . . .1540
32.6.2ADC interrupt enable register (ADC_IER) . . . . .1542
32.6.3ADC control register (ADC_CR) . . . . .1544
32.6.4ADC configuration register (ADC_CFGR1) . . . . .1547
32.6.5ADC configuration register 2 (ADC_CFGR2) . . . . .1550
32.6.6ADC sample time register 1 (ADC_SMPR1) . . . . .1553
32.6.7ADC sample time register 2 (ADC_SMPR2) . . . . .1554
32.6.8ADC channel preselection register (ADC_PCSEL) . . . . .1555
32.6.9ADC regular sequence register 1 (ADC_SQR1) . . . . .1555
32.6.10ADC regular sequence register 2 (ADC_SQR2) . . . . .1556
32.6.11ADC regular sequence register 3 (ADC_SQR3) . . . . .1557
32.6.12ADC regular sequence register 4 (ADC_SQR4) . . . . .1558
32.6.13ADC regular data register (ADC_DR) . . . . .1559
32.6.14ADC injected sequence register (ADC_JSQR) . . . . .1559
32.6.15ADC offset y configuration register (ADC_OFCFGry) . . . . .1561
32.6.16ADC offset y register (ADC_OFry) . . . . .1562
32.6.17ADC gain compensation register (ADC_GCOMP) . . . . .1563
32.6.18ADC injected channel y data register (ADC_JDry) . . . . .1564
32.6.19ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .1564
32.6.20ADC analog watchdog 3 configuration register (ADC_AWD3CR) . . . . .1565
32.6.21ADC analog watchdog 1 lower threshold register (ADC_AWD1LTR) . . . . .1565
32.6.22ADC analog watchdog 1 higher threshold register
(ADC_AWD1HTR) . . . . .		1566
32.6.23ADC analog watchdog 2 lower threshold register (ADC_AWD2LTR) . . . . .1566
32.6.24ADC analog watchdog 2 higher threshold register
(ADC_AWD2HTR) . . . . .		1567
32.6.25ADC analog watchdog 3 lower threshold register (ADC_AWD3LTR) . . . . .1567
32.6.26ADC analog watchdog 3 higher threshold register
(ADC_AWD3HTR) . . . . .		1567
32.6.27ADC differential mode selection register (ADC_DIFSEL) . . . . .1568
32.6.28ADC calibration factors (ADC_CALFACT) . . . . .1568
32.6.29ADC option register (ADC_OR) . . . . .1570
32.7ADC common registers . . . . .1571
32.7.1ADC common status register (ADCC_CSR) . . . . .1571
32.7.2ADC common control register (ADCC_CCR) . . . . .1572
32.7.3ADC common regular data register for dual mode
(ADCC_CDR) . . . . .		1574
32.7.4ADC common regular data register for dual mode
(ADCC_CDR2) . . . . .		1574

32.8 ADC register map . . . . . 1575

33 Digital temperature sensor (DTS) . . . . . 1579

33.1 Introduction . . . . . 1579

33.2 DTS main features . . . . . 1579

33.3 DTS functional description . . . . . 1580

33.3.1 DTS block diagram . . . . . 1580

33.3.2 DTS pins and internal signals . . . . . 1580

33.3.3 DTS reset and clocks . . . . . 1581

33.3.4 DTS serial data adapter (SDA) . . . . . 1583

33.3.5 Alarms . . . . . 1589

33.3.6 Main APB programming routines . . . . . 1590

33.3.7 Temperature sensor configuration . . . . . 1593

33.4 DTS interrupts . . . . . 1595

33.5 DTS registers . . . . . 1596

33.5.1 DTS PVT common registers . . . . . 1596

33.5.2 PVT IRQ registers . . . . . 1598

33.5.3 TS common registers . . . . . 1602

33.5.4 TS individual registers . . . . . 1609

33.5.5 DTS register map . . . . . 1616

34 Voltage reference buffer (VREFBUF) . . . . . 1621

34.1 VREFBUF introduction . . . . . 1621

34.2 VREFBUF implementation . . . . . 1621

34.3 VREFBUF functional description . . . . . 1621

34.4 VREFBUF trimming . . . . . 1622

34.5 VREFBUF power sequence . . . . . 1623

34.6 VREFBUF registers . . . . . 1624

34.6.1 VREFBUF control and status register (VREFBUF_CSR) . . . . . 1624

34.6.2 VREFBUF calibration control register (VREFBUF_CCR) . . . . . 1625

34.6.3 VREFBUF register map . . . . . 1625

35 Multi-function digital filter (MDF) . . . . . 1626

35.1 MDF introduction . . . . . 1626

35.2 MDF main features . . . . . 1627

35.3 MDF implementation . . . . . 1627

35.4MDF functional description . . . . .1629
35.4.1MDF block diagram . . . . .1629
35.4.2MDF pins and internal signals . . . . .1630
35.4.3Serial input interfaces (SITF) . . . . .1631
35.4.4ADC slave interface (ADCITF) . . . . .1636
35.4.5Clock generator (CKGEN) . . . . .1637
35.4.6Bitstream matrix (BSMX) . . . . .1639
35.4.7Short-circuit detectors (SCD) . . . . .1640
35.4.8Digital filter processing (DFLT) . . . . .1642
35.4.9Out-of-limit detector (OLD) . . . . .1652
35.4.10Digital filter acquisition modes . . . . .1655
35.4.11Start-up sequence examples . . . . .1665
35.4.12Break interface . . . . .1666
35.4.13Data transfer to memory . . . . .1667
35.4.14Autonomous mode . . . . .1672
35.4.15Register protection . . . . .1673
35.5MDF low-power modes . . . . .1674
35.6MDF interrupts . . . . .1674
35.7MDF application informations . . . . .1676
35.7.1MDF configuration examples for audio capture . . . . .1676
35.7.2Programming examples . . . . .1677
35.7.3Connection examples . . . . .1679
35.7.4Global frequency response . . . . .1680
35.7.5Total MDF gain . . . . .1681
35.8MDF registers . . . . .1685
35.8.1MDF global control register (MDF_GCR) . . . . .1685
35.8.2MDF clock generator control register (MDF_CKGCR) . . . . .1686
35.8.3MDF serial interface control register x (MDF_SITFxCr) . . . . .1688
35.8.4MDF bitstream matrix control register x (MDF_BSMXxCr) . . . . .1689
35.8.5MDF digital filter control register x (MDF_DFLTxCr) . . . . .1690
35.8.6MDF digital filter configuration register x (MDF_DFLTxCICR) . . . . .1692
35.8.7MDF reshape filter configuration register x (MDF_DFLTxRSFR) . . . . .1694
35.8.8MDF integrator configuration register x (MDF_DFLTxINTR) . . . . .1695
35.8.9MDF out-of limit detector control register x (MDF_OLDxCr) . . . . .1695
35.8.10MDF OLDx low threshold register x (MDF_OLDxTHLR) . . . . .1697
35.8.11MDF OLDx high threshold register x (MDF_OLDxTHHR) . . . . .1697
35.8.12MDF delay control register x (MDF_DLYxCR) . . . . .1698
35.8.13MDF short circuit detector control register x (MDF_SCDxCR) . . . . .1698
35.8.14MDF DFLT0 interrupt enable register 0 (MDF_DFLT0IER) . . . . .1699
35.8.15MDF DFLTx interrupt enable register x (MDF_DFLTxIER) . . . . .1701
35.8.16MDF DFLT0 interrupt status register 0 (MDF_DFLT0ISR) . . . . .1702
35.8.17MDF DFLTx interrupt status register x (MDF_DFLTxISR) . . . . .1704
35.8.18MDF offset error compensation control register x (MDF_OECxCR) . . . . .1705
35.8.19MDF snapshot data register x (MDF_SNPSxDR) . . . . .1706
35.8.20MDF digital filter data register x (MDF_DFLTxDR) . . . . .1706
35.8.21MDF register map . . . . .1707
36Audio digital filter (ADF) . . . . .1709
36.1ADF introduction . . . . .1709
36.2ADF main features . . . . .1709
36.3ADF implementation . . . . .1710
36.4ADF functional description . . . . .1711
36.4.1ADF block diagram . . . . .1711
36.4.2ADF pins and internal signals . . . . .1711
36.4.3Serial input interface (SITF) . . . . .1712
36.4.4ADC slave interface (ADCITF) . . . . .1717
36.4.5Clock generator (CKGEN) . . . . .1717
36.4.6Bitstream matrix (BSMX) . . . . .1719
36.4.7Digital filter processing (DFLT) . . . . .1720
36.4.8Digital filter acquisition modes . . . . .1730
36.4.9Start-up sequence examples . . . . .1738
36.4.10Sound activity detection (SAD) . . . . .1739
36.4.11Data transfer to memory . . . . .1747
36.4.12Autonomous mode . . . . .1750
36.4.13Register protection . . . . .1750
36.5ADF low-power modes . . . . .1751
36.6ADF interrupts . . . . .1751
36.7ADF application information . . . . .1753
36.7.1ADF configuration examples for audio capture . . . . .1753
36.7.2Programming examples . . . . .1754
36.7.3Connection examples . . . . .1756
36.7.4Global frequency response . . . . .1757
36.7.5Total ADF gain . . . . .1758
36.7.6How to compute SAD thresholds . . . . .1761
36.8ADF registers . . . . .1765
36.8.1ADF global control register (ADF_GCR) . . . . .1765
36.8.2ADF clock generator control register (ADF_CKGCR) . . . . .1765
36.8.3ADF serial interface control register 0 (ADF_SITF0CR) . . . . .1767
36.8.4ADF bitstream matrix control register 0 (ADF_BSMX0CR) . . . . .1769
36.8.5ADF digital filter control register 0 (ADF_DFLT0CR) . . . . .1769
36.8.6ADF digital filter configuration register 0 (ADF_DFLT0CICR) . . . . .1771
36.8.7ADF reshape filter configuration register 0 (ADF_DFLT0RSFR) . . . . .1772
36.8.8ADF delay control register 0 (ADF_DLY0CR) . . . . .1773
36.8.9ADF DFLT0 interrupt enable register (ADF_DFLT0IER) . . . . .1774
36.8.10ADF DFLT0 interrupt status register 0 (ADF_DFLT0ISR) . . . . .1775
36.8.11ADF SAD control register (ADF_SADCR) . . . . .1776
36.8.12ADF SAD configuration register (ADF_SADCFGR) . . . . .1778
36.8.13ADF SAD sound level register (ADF_SADSDLVR) . . . . .1779
36.8.14ADF SAD ambient noise level register (ADF_SADANLVR) . . . . .1780
36.8.15ADF digital filter data register 0 (ADF_DFLT0DR) . . . . .1780
36.8.16ADF register map . . . . .1780
37Camera subsystem . . . . .1783
37.1Introduction . . . . .1783
37.2Camera path main features . . . . .1783
37.2.1DCMI path main features . . . . .1783
37.2.2DCMIPP path main features . . . . .1784
37.3Camera subsystem implementation . . . . .1785
37.3.1Hardware settings . . . . .1785
37.4Camera subsystem functional description . . . . .1786
37.4.1Camera subsystem block diagram . . . . .1786
37.4.2Camera subsystem pins and external signal interface . . . . .1786
37.4.3Camera subsystem reset and clocks . . . . .1787
37.4.4Streaming from the camera subsystem to slave peripherals . . . . .1787
37.4.5Camera subsystem security . . . . .1788
37.5Camera subsystem programmable parameters . . . . .1789
37.5.1Low-resolution parallel camera and DCMI . . . . .1790
37.5.2High-resolution parallel camera and DCMIPP . . . . .1790
37.5.3High-resolution CSI2 camera and DCMIPP . . . . .1791
37.5.4Sensors over target resolution . . . . .1792
37.5.5Sensors over target pixel rate . . . . .1792
37.5.6Double sensors . . . . .1792
37.6Camera subsystem interrupts . . . . .1793
37.7Camera subsystem registers . . . . .1793
38Digital camera interface (DCMI) . . . . .1794
38.1DCMI introduction . . . . .1794
38.2DCMI main features . . . . .1794
38.3DCMI functional description . . . . .1794
38.3.1DCMI block diagram . . . . .1795
38.3.2DCMI pins and internal signals . . . . .1795
38.3.3DCMI clocks . . . . .1796
38.3.4DCMI DMA interface . . . . .1796
38.3.5DCMI physical interface . . . . .1796
38.3.6DCMI synchronization . . . . .1798
38.3.7DCMI capture modes . . . . .1800
38.3.8DCMI crop feature . . . . .1801
38.3.9DCMI JPEG format . . . . .1802
38.3.10DCMI FIFO . . . . .1802
38.3.11DCMI data format description . . . . .1803
38.4DCMI interrupts . . . . .1805
38.5DCMI registers . . . . .1805
38.5.1DCMI control register (DCMI_CR) . . . . .1805
38.5.2DCMI status register (DCMI_SR) . . . . .1808
38.5.3DCMI raw interrupt status register (DCMI_RIS) . . . . .1808
38.5.4DCMI interrupt enable register (DCMI_IER) . . . . .1809
38.5.5DCMI masked interrupt status register (DCMI_MIS) . . . . .1810
38.5.6DCMI interrupt clear register (DCMI_ICR) . . . . .1811
38.5.7DCMI embedded synchronization code register (DCMI_ESCR) . . . . .1812
38.5.8DCMI embedded synchronization unmask register (DCMI_ESUR) . . . . .1812
38.5.9DCMI crop window start (DCMI_CWSTRT) . . . . .1813
38.5.10DCMI crop window size (DCMI_CWSIZE) . . . . .1814
38.5.11DCMI data register (DCMI_DR) . . . . .1814
38.5.12DCMI register map . . . . .1815
39Digital camera interface pixel pipeline (DCMIPP) . . . . .1816
39.1DCMIPP introduction . . . . .1816
39.2DCMIPP main features . . . . .1819
39.3DCMIPP functional description . . . . .1821
39.3.1DCMIPP block diagram . . . . .1821
39.3.2DCMIPP pads and internal signals . . . . .1822
39.3.3DCMIPP reset and clocks . . . . .1822
39.3.4DCMIPP maximum resolution . . . . .1825
39.3.5DCMIPP minimum requirements for frame structure . . . . .1826
39.3.6Description of DCMIPP pixel format support . . . . .1826
39.4DCMIPP input and flow control . . . . .1827
39.4.1DCMIPP common configuration . . . . .1828
39.4.2Parallel input interface . . . . .1828
39.4.3Interface from CSI-2 host . . . . .1832
39.4.4Input selection . . . . .1832
39.4.5Flow selection . . . . .1832
39.4.6Frame counter . . . . .1834
39.4.7Frame control . . . . .1835
39.4.8Pipe deactivation . . . . .1840
39.5Pipe0 (dump pipe) . . . . .1841
39.5.1Overview . . . . .1841
39.5.2Decimation . . . . .1842
39.5.3Crop/statistics selection/suppression . . . . .1842
39.5.4Header insertion . . . . .1843
39.5.5Dump counter . . . . .1844
39.5.6Double buffer mode . . . . .1845
39.6Pipe1 (ISP part) . . . . .1846
39.6.1Overview . . . . .1846
39.6.2Byte-to-pixel conversion . . . . .1846
39.6.3Statistics removal . . . . .1847
39.6.4Bad pixel removal . . . . .1848
39.6.5Input decimation . . . . .1849
39.6.6Black level calibration . . . . .1850
39.6.7Exposure compensation and white-balance calibration . . . . .1851
39.6.8Demosaicing . . . . .1852
39.6.9Color conversion . . . . .1854
39.6.10Contrast enhancement . . . . .1857
39.6.11Statistics extraction . . . . .1858
39.7Pipe1 (post-processing part) . . . . .1863
39.7.1Overview . . . . .1863
39.7.2Pixel 2D cropping . . . . .1863
39.7.3Decimation pre-downsize . . . . .1864
39.7.4Downsize . . . . .1865
39.7.5Regions of interest (ROIs) . . . . .1867
39.7.6Gamma conversion . . . . .1868
39.7.7YUV conversion . . . . .1868
39.7.8Chroma down-sampling . . . . .1868
39.7.9Pixel packing . . . . .1869
39.7.10Overrun detection . . . . .1871
39.8Pipe2 (post-processing) . . . . .1872
39.8.1Overview . . . . .1872
39.8.2Pipe1 and Pipe2 sharing image processing functions . . . . .1873
39.9Application use cases . . . . .1873
39.9.1Parallel interface camera sensor module . . . . .1873
39.9.2CSI2 camera sensor module . . . . .1874
39.9.3Force data type format from CSI-2 data flow (pixel pipes only) . . . . .1881
39.10Pixel format description . . . . .1884
39.10.1Parallel interface formats . . . . .1884
39.10.2Pixel pipe formats . . . . .1886
39.10.3Dump pipe formats . . . . .1887
39.10.4AXI IP-Plug . . . . .1889
39.11Shadow registers . . . . .1895
39.12DCMIPP low power modes . . . . .1897
39.13DCMIPP interrupts . . . . .1898
39.13.1Free-running DCMIPP . . . . .1898
39.13.2Interrupts . . . . .1898
39.13.3Event pins . . . . .1901
39.14DCMIPP registers . . . . .1902
39.14.1DCMIPP IP-Plug global register 1 (DCMIPP_IPGR1) . . . . .1902
39.14.2DCMIPP IP-Plug global register 2 (DCMIPP_IPGR2) . . . . .1903
39.14.3DCMIPP IP-Plug global register 3 (DCMIPP_IPGR3) . . . . .1903
39.14.4DCMIPP IP-Plug identification register (DCMIPP_IPGR8) . . . . .1904
39.14.5DCMIPP IP-Plug Clientx register 1 (DCMIPP_IPCxR1) . . . . .1904
39.14.6DCMIPP IP-Plug Clientx register 2 (DCMIPP_IPCxR2) . . . . .1905
39.14.7DCMIPP IP-Plug Clientx register 3 (DCMIPP_IPCxR3) . . . . .1905
39.14.8DCMIPP parallel interface control register (DCMIPP_PRCR) . . . . .1906
39.14.9DCMIPP parallel interface embedded synchronization code register
(DCMIPP_PRESCR) . . . . .		1907
39.14.10DCMIPP parallel interface embedded synchronization unmask register
(DCMIPP_PRESUR) . . . . .		1908
39.14.11DCMIPP parallel interface interrupt enable register
(DCMIPP_PRIER) . . . . .		1909
39.14.12DCMIPP parallel interface status register (DCMIPP_PRSR) . . . . .1909
39.14.13DCMIPP parallel interface interrupt clear register
(DCMIPP_PRFCR) . . . . .		1910
39.14.14DCMIPP common configuration register (DCMIPP_CMCR) . . . . .1911
39.14.15DCMIPP common frame counter register (DCMIPP_CMFRCR) . . . . .1912
39.14.16DCMIPP common interrupt enable register (DCMIPP_CMIER) . . . . .1912
39.14.17DCMIPP common status register 1 (DCMIPP_CMSR1) . . . . .1913
39.14.18DCMIPP common status register 2 (DCMIPP_CMSR2) . . . . .1915
39.14.19DCMIPP common interrupt clear register (DCMIPP_CMFCR) . . . . .1917
39.14.20DCMIPP Pipe0 flow selection configuration register
(DCMIPP_P0FSCR) . . . . .		1919
39.14.21DCMIPP Pipe0 flow control configuration register
(DCMIPP_P0FCTCR) . . . . .		1919
39.14.22DCMIPP Pipe0 statistic/crop start register (DCMIPP_P0SCSTR) . . . . .1920
39.14.23DCMIPP Pipe0 statistic/crop size register (DCMIPP_P0SCSZR) . . . . .1921
39.14.24DCMIPP Pipe0 dump counter register (DCMIPP_P0DCCNTR) . . . . .1921
39.14.25DCMIPP Pipe0 dump limit register (DCMIPP_P0DCLMTR) . . . . .1922
39.14.26DCMIPP Pipe0 pixel packer configuration register
(DCMIPP_P0PPCR) . . . . .		1922
39.14.27DCMIPP Pipe0 pixel packer Memory0 address register 1
(DCMIPP_P0PPM0AR1) . . . . .		1924
39.14.28DCMIPP Pipe0 pixel packer Memory0 address register 2
(DCMIPP_P0PPM0AR2) . . . . .		1924
39.14.29DCMIPP Pipe0 status Memory0 address register
(DCMIPP_P0STM0AR) . . . . .		1924
39.14.30DCMIPP Pipe0 interrupt enable register (DCMIPP_P0IER) . . . . .1925
39.14.31DCMIPP Pipe0 status register (DCMIPP_P0SR) . . . . .1926
39.14.32DCMIPP Pipe0 interrupt clear register (DCMIPP_P0FCR) . . . . .1927
39.14.33DCMIPP Pipe0 current flow selection configuration register
(DCMIPP_P0CFSCR) . . . . .		1927
39.14.34DCMIPP Pipe0 current flow control configuration register
(DCMIPP_P0CFCTCR) . . . . .		1928
39.14.35DCMIPP Pipe0 current statistic/crop start register
(DCMIPP_P0CSCSTR) . . . . .		1929
39.14.36DCMIPP Pipe0 current statistic/crop size register
(DCMIPP_P0CSCSZR) . . . . .		1929
39.14.37DCMIPP Pipe0 current pixel packer configuration register
(DCMIPP_P0CPPCR) . . . . .		1930
39.14.38DCMIPP Pipe0 current pixel packer Memory0 address register 1
(DCMIPP_P0CPPM0AR1) . . . . .		1932
39.14.39DCMIPP Pipe0 current pixel packer Memory0 address register 2
(DCMIPP_P0CPPM0AR2) . . . . .		1932
39.14.40DCMIPP Pipe1 flow selection configuration register
(DCMIPP_P1FSCR) . . . . .		1933
39.14.41DCMIPP Pipe1 stat removal configuration register
(DCMIPP_P1SRCR) . . . . .		1934
39.14.42DCMIPP Pipe1 bad pixel removal control register
(DCMIPP_P1BPRCR) . . . . .		1935
39.14.43DCMIPP Pipe1 bad pixel removal status register
(DCMIPP_P1BPRSR) . . . . .		1935
39.14.44DCMIPP Pipe1 decimation register (DCMIPP_P1DECR) . . . . .1936
39.14.45DCMIPP Pipe1 black level calibration control register
(DCMIPP_P1BLCCR) . . . . .		1936
39.14.46DCMIPP Pipe1 exposure control register 1 (DCMIPP_P1EXCR1) . . .1937
39.14.47DCMIPP Pipe1 exposure control register 2 (DCMIPP_P1EXCR2) . . .1937
39.14.48DCMIPP Pipe1 statistics1 control register (DCMIPP_P1ST1CR) . . .1938
39.14.49DCMIPP Pipe1 statistics 2 control register (DCMIPP_P1ST2CR) . . .1939
39.14.50DCMIPP Pipe1 statistics 3 control register (DCMIPP_P1ST3CR) . . .1940
39.14.51DCMIPP Pipe1 statistics window start register
(DCMIPP_P1STSTR) . . . . .		1941
39.14.52DCMIPP Pipe1 statistics window size register
(DCMIPP_P1STSZR) . . . . .		1941
39.14.53DCMIPP Pipe1 statistics 1 status register (DCMIPP_P1ST1SR) . . .1942
39.14.54DCMIPP Pipe1 statistics 2 status register (DCMIPP_P1ST2SR) . . .1943
39.14.55DCMIPP Pipe1 statistics 3 status register (DCMIPP_P1ST3SR) . . .1943
39.14.56DCMIPP Pipe1 demosaicing configuration register
(DCMIPP_P1DMCR) . . . . .		1943
39.14.57DCMIPP Pipe1 ColorConv configuration register
(DCMIPP_P1CCCR) . . . . .		1944
39.14.58DCMIPP Pipe1 ColorConv red coefficient register 1
(DCMIPP_P1CCRR1) . . . . .		1945
39.14.59DCMIPP Pipe1 ColorConv red coefficient register 2
(DCMIPP_P1CCRR2)		1945
39.14.60DCMIPP Pipe1 ColorConv green coefficient register 1
(DCMIPP_P1CCGR1)		1946
39.14.61DCMIPP Pipe1 ColorConv green coefficient register 2
(DCMIPP_P1CCGR2)		1946
39.14.62DCMIPP Pipex ColorConv blue coefficient register 1
(DCMIPP_P1CCBR1)		1947
39.14.63DCMIPP Pipe1 ColorConv blue coefficient register 2
(DCMIPP_P1CCBR2)		1947
39.14.64DCMIPP Pipe1 contrast control register 1 (DCMIPP_P1CTCR1)1948
39.14.65DCMIPP Pipe1 contrast control register 2 (DCMIPP_P1CTCR2)1948
39.14.66DCMIPP Pipe1 contrast control register 3 (DCMIPP_P1CTCR3)1949
39.14.67DCMIPP Pipex flow control configuration register
(DCMIPP_PxFCTCR)		1949
39.14.68DCMIPP Pipex crop window start register (DCMIPP_PxCSTR)1950
39.14.69DCMIPP Pipex crop window size register (DCMIPP_PxCRSZR)1951
39.14.70DCMIPP Pipex decimation register (DCMIPP_PxDCCR)1951
39.14.71DCMIPP Pipex downsize configuration register
(DCMIPP_PxDSCR)		1952
39.14.72DCMIPP Pipex downsize ratio register (DCMIPP_PxDSRTIOR)1952
39.14.73DCMIPP Pipex downsize destination size register
(DCMIPP_PxDSSZR)		1953
39.14.74DCMIPP Pipex common ROI configuration register
(DCMIPP_PxCMRICR)		1953
39.14.75DCMIPP Pipe1 ROIx configuration register 1 (DCMIPP_P1RIxCR1)1955
39.14.76DCMIPP Pipe1 ROIx configuration register 2 (DCMIPP_P1RIxCR2)1955
39.14.77DCMIPP Pipex gamma configuration register (DCMIPP_PxGMCR)1956
39.14.78DCMIPP Pipe1 YUVConv configuration register
(DCMIPP_P1YUVCR)		1956
39.14.79DCMIPP Pipe1 YUVConv red coefficient register 1
(DCMIPP_P1YUVR1)		1956
39.14.80DCMIPP Pipe1 YUVConv red coefficient register 2
(DCMIPP_P1YUVR2)		1957
39.14.81DCMIPP Pipe1 YUVConv green coefficient register 1
(DCMIPP_P1YUVGR1)		1957
39.14.82DCMIPP Pipe1 YUVConv green coefficient register 2
(DCMIPP_P1YUVGR2)		1958
39.14.83DCMIPP Pipe1 YUVConv blue coefficient register 1
(DCMIPP_P1YUVBR1)		1958
39.14.84DCMIPP Pipe1 YUV blue coefficient register 2
(DCMIPP_P1YUVBR2)		1958

39.14.85 DCMIPP Pipe1 pixel packer configuration register
(DCMIPP_P1PPCR) . . . . . 1959

39.14.86 DCMIPP Pipe1 pixel packer Memory0 address register 1
(DCMIPP_P1PPM0AR1) . . . . . 1960

39.14.87 DCMIPP Pipe1 pixel packer Memory0 address register 2
(DCMIPP_P1PPM0AR2) . . . . . 1961

39.14.88 DCMIPP Pipex pixel packer Memory0 pitch register
(DCMIPP_PxPPM0PR) . . . . . 1961

39.14.89 DCMIPP Pipex status Memory0 address register
(DCMIPP_PxSTM0AR) . . . . . 1962

39.14.90 DCMIPP Pipex pixel packer Memory1 address register 1
(DCMIPP_PxPPM1AR1) . . . . . 1962

39.14.91 DCMIPP Pipex pixel packer Memory1 address register 2
(DCMIPP_PxPPM1AR2) . . . . . 1962

39.14.92 DCMIPP Pipex pixel packer Memory1 pitch register
(DCMIPP_PxPPM1PR) . . . . . 1963

39.14.93 DCMIPP Pipex status Memory1 address register
(DCMIPP_PxSTM1AR) . . . . . 1963

39.14.94 DCMIPP Pipex pixel packer memory2 address register 1
(DCMIPP_PxPPM2AR1) . . . . . 1964

39.14.95 DCMIPP Pipex pixel packer memory2 address register 2
(DCMIPP_PxPPM2AR2) . . . . . 1964

39.14.96 DCMIPP Pipex status Memory2 address register
(DCMIPP_PxSTM2AR) . . . . . 1964

39.14.97 DCMIPP Pipe1 interrupt enable register (DCMIPP_P1IER) . . . . . 1965

39.14.98 DCMIPP Pipe1 status register (DCMIPP_P1SR) . . . . . 1966

39.14.99 DCMIPP Pipe1 interrupt clear register (DCMIPP_P1FCR) . . . . . 1967

39.14.100DCMIPP Pipe1 current flow selection configuration register
(DCMIPP_P1CFSCR) . . . . . 1967

39.14.101DCMIPP Pipe1 current bad pixel removal register
(DCMIPP_P1CBPRCR) . . . . . 1968

39.14.102DCMIPP Pipe1 current black level calibration control register
(DCMIPP_P1CBLCCR) . . . . . 1969

39.14.103DCMIPP Pipe1 current exposure control register 1
(DCMIPP_P1CEXCR1) . . . . . 1969

39.14.104DCMIPP Pipe1 current exposure control register 2
(DCMIPP_P1CEXCR2) . . . . . 1970

39.14.105DCMIPP Pipe1 current statistics 1 control register
(DCMIPP_P1CST1CR) . . . . . 1971

39.14.106DCMIPP Pipe1 current statistics 2 control register
(DCMIPP_P1CST2CR) . . . . . 1972

39.14.107DCMIPP Pipe1 current statistics 3 control register
(DCMIPP_P1CST3CR) . . . . . 1973

39.14.108DCMIPP Pipe1 current statistics window start register
(DCMIPP_P1CSTSTR) . . . . .		1974
39.14.109DCMIPP Pipe1 current statistics window size register
(DCMIPP_P1CSTSZR) . . . . .		1974
39.14.110DCMIPP Pipe1 current ColorConv configuration register
(DCMIPP_P1CCCCR) . . . . .		1975
39.14.111DCMIPP Pipe1 current ColorConv red coefficient register 1
(DCMIPP_P1CCRR1) . . . . .		1975
39.14.112DCMIPP Pipe1 current ColorConv red coefficient register 2
(DCMIPP_P1CCRR2) . . . . .		1976
39.14.113DCMIPP Pipe1 current ColorConv green coefficient register 1
(DCMIPP_P1CCGR1) . . . . .		1976
39.14.114DCMIPP Pipe1 current ColorConv green coefficient register 2
(DCMIPP_P1CCGR2) . . . . .		1977
39.14.115DCMIPP Pipex current ColorConv blue coefficient register 1
(DCMIPP_P1CCBR1) . . . . .		1977
39.14.116DCMIPP Pipe1 current ColorConv blue coefficient register 2
(DCMIPP_P1CCBR2) . . . . .		1978
39.14.117DCMIPP Pipe1 current contrast control register 1
(DCMIPP_P1CCTCR1) . . . . .		1978
39.14.118DCMIPP Pipe1 current contrast control register 2
(DCMIPP_P1CCTCR2) . . . . .		1979
39.14.119DCMIPP Pipe1 current contrast control register 3
(DCMIPP_P1CCTCR3) . . . . .		1979
39.14.120DCMIPP Pipex current flow control configuration register
(DCMIPP_PxCFCTCR) . . . . .		1980
39.14.121DCMIPP Pipex current crop window start register
(DCMIPP_PxCcRSTR) . . . . .		1981
39.14.122DCMIPP Pipex current crop window size register
(DCMIPP_PxCcRSZR) . . . . .		1981
39.14.123DCMIPP Pipex current decimation register (DCMIPP_PxCDCR) . . . . .1982
39.14.124DCMIPP Pipex current downsize configuration register
(DCMIPP_PxCDSR) . . . . .		1982
39.14.125DCMIPP Pipex current downsize ratio register
(DCMIPP_PxCDSRTIOR) . . . . .		1983
39.14.126DCMIPP Pipex current downsize destination size register
(DCMIPP_PxCDSZR) . . . . .		1983
39.14.127DCMIPP Pipex current common ROI configuration register
(DCMIPP_PxCcMRICR) . . . . .		1984
39.14.128DCMIPP Pipe1 current ROIx configuration register 1
(DCMIPP_P1CRICR1) . . . . .		1985
39.14.129DCMIPP Pipe1 current ROIx configuration register 2
(DCMIPP_P1CRICR2) . . . . .		1985

39.14.130 DCMIPP Pipe1 current pixel packer configuration register
(DCMIPP_P1CPPCR) . . . . . 1986

39.14.131 DCMIPP Pipe1 current pixel packer Memory0 address register 1
(DCMIPP_P1CPPM0AR1) . . . . . 1987

39.14.132 DCMIPP Pipe1 current pixel packer Memory0 address register 2
(DCMIPP_P1CPPM0AR2) . . . . . 1988

39.14.133 DCMIPP Pipex current pixel packer Memory0 pitch register
(DCMIPP_PxCPPM0PR) . . . . . 1988

39.14.134 DCMIPP Pipex current pixel packer Memory1 address register 1
(DCMIPP_PxCPPM1AR1) . . . . . 1988

39.14.135 DCMIPP Pipex current pixel packer Memory1 address register 2
(DCMIPP_PxCPPM1AR2) . . . . . 1989

39.14.136 DCMIPP Pipex current pixel packer Memory1 pitch register
(DCMIPP_PxCPPM1PR) . . . . . 1989

39.14.137 DCMIPP Pipex current pixel packer Memory2 address register 1
(DCMIPP_PxCPPM2AR1) . . . . . 1990

39.14.138 DCMIPP Pipex current pixel packer Memory2 address register 2
(DCMIPP_PxCPPM2AR2) . . . . . 1990

39.14.139 DCMIPP Pipe2 flow selection configuration register
(DCMIPP_P2FSCR) . . . . . 1990

39.14.140 DCMIPP Pipe2 ROIx configuration register 1 (DCMIPP_P2RIxCR1) 1991

39.14.141 DCMIPP Pipe2 ROIx configuration register 2 (DCMIPP_P2RIxCR2) 1992

39.14.142 DCMIPP Pipe2 pixel packer configuration register
(DCMIPP_P2PPCR) . . . . . 1992

39.14.143 DCMIPP Pipe2 pixel packer Memory0 address register 1
(DCMIPP_P2PPM0AR1) . . . . . 1994

39.14.144 DCMIPP Pipe2 pixel packer Memory0 address register 2
(DCMIPP_P2PPM0AR2) . . . . . 1994

39.14.145 DCMIPP Pipe2 interrupt enable register (DCMIPP_P2IER) . . . . . 1994

39.14.146 DCMIPP Pipe2 status register (DCMIPP_P2SR) . . . . . 1995

39.14.147 DCMIPP Pipe2 interrupt clear register (DCMIPP_P2FCR) . . . . . 1996

39.14.148 DCMIPP Pipe2 current flow selection configuration register
(DCMIPP_P2CFSCR) . . . . . 1997

39.14.149 DCMIPP Pipe2 current ROIx configuration register 1
(DCMIPP_P2CR1xCR1) . . . . . 1998

39.14.150 DCMIPP Pipe2 current ROIx configuration register 2
(DCMIPP_P2CR2xCR2) . . . . . 1998

39.14.151 DCMIPP Pipe2 current pixel packer configuration register
(DCMIPP_P2CPPCR) . . . . . 1999

39.14.152 DCMIPP Pipe2 current pixel packer Memory0 address register 1
(DCMIPP_P2CPPM0AR1) . . . . . 2000

39.14.153 DCMIPP Pipe2 current pixel packer Memory0 address register 2
(DCMIPP_P2CPPM0AR2) . . . . . 2000

39.15DCMIPP register map . . . . .2001
40CSI-2 Host (CSI) . . . . .2016
40.1CSI introduction . . . . .2016
40.2Standard and references . . . . .2016
40.3Glossary . . . . .2016
40.4CSI-2 Host main features . . . . .2017
40.5CSI-2 Host functional description . . . . .2017
40.5.1General description . . . . .2017
40.5.2System level architecture . . . . .2019
40.5.3CSI-2 Host reset and clocks . . . . .2020
40.5.4Lane merger . . . . .2021
40.5.5Clock changer . . . . .2022
40.5.6Low-level protocol (LLP) . . . . .2023
40.5.7CSI-2 Host protocol output . . . . .2033
40.6CSI-2 Host programming guide . . . . .2033
40.6.1CSI-2 PHY setup . . . . .2033
40.6.2CSI-2 Host controller setup and data reception start . . . . .2034
40.6.3Data reception stop . . . . .2035
40.7CSI-2 Host low-power modes . . . . .2035
40.8CSI-2 Host interrupts and errors . . . . .2035
40.8.1Error handling . . . . .2037
40.8.2Interrupt handling . . . . .2039
40.9CSI-2 Host registers . . . . .2040
40.9.1CSI-2 Host control register (CSI_CR) . . . . .2040
40.9.2CSI-2 Host DPHY_RX control register (CSI_PCR) . . . . .2042
40.9.3CSI-2 Host virtual channel x configuration register 1
(CSI_VCxCFGR1) . . . . .		2043
40.9.4CSI-2 Host virtual channel x configuration register 2
(CSI_VCxCFGR2) . . . . .		2045
40.9.5CSI-2 Host virtual channel x configuration register 3
(CSI_VCxCFGR3) . . . . .		2046
40.9.6CSI-2 Host virtual channel x configuration register 4
(CSI_VCxCFGR4) . . . . .		2047
40.9.7CSI-2 Host line byte x configuration register (CSI_LBxCFGR) . . . . .2048
40.9.8CSI-2 Host timer x configuration register (CSI_TIMxCFGR) . . . . .2049
40.9.9CSI-2 Host lane merger configuration register (CSI_LMCFGR) . . . . .2049
40.9.10CSI-2 Host program interrupt register (CSI_PRGITR) . . . . .2050
40.9.11CSI-2 Host watchdog register (CSI_WDR) . . . . .2054
40.9.12CSI-2 Host interrupt enable register 0 (CSI_IER0) . . . . .2054
40.9.13CSI-2 Host interrupt enable register 1 (CSI_IER1) . . . . .2057
40.9.14CSI-2 Host status register 0 (CSI_SR0) . . . . .2059
40.9.15CSI-2 Host status register 1 (CSI_SR1) . . . . .2061
40.9.16CSI-2 Host flag clear register 0 (CSI_FCR0) . . . . .2063
40.9.17CSI-2 Host flag clear register 1 (CSI_FCR1) . . . . .2064
40.9.18CSI-2 Host short packet data field register (CSI_SPDFR) . . . . .2065
40.9.19CSI-2 Host error register 1 (CSI_ERR1) . . . . .2066
40.9.20CSI-2 Host error register 2 (CSI_ERR2) . . . . .2067
40.10CSI PHY registers . . . . .2067
40.10.1CSI PHY reset control register (CSI_PRCR) . . . . .2067
40.10.2CSI PHY mode control register (CSI_PMCR) . . . . .2068
40.10.3CSI PHY frequency control register (CSI_PFCR) . . . . .2069
40.10.4CSI PHY test control register 0 (CSI_PTCR0) . . . . .2069
40.10.5CSI PHY test control register 1 (CSI_PTCR1) . . . . .2070
40.10.6CSI PHY test status register (CSI_PTSR) . . . . .2070
40.10.7CSI-2 Host and PHY register map . . . . .2070
41Parallel synchronous slave interface (PSSI) . . . . .2074
41.1PSSI introduction . . . . .2074
41.2PSSI main features . . . . .2074
41.3PSSI functional description . . . . .2074
41.3.1PSSI block diagram . . . . .2075
41.3.2PSSI pins and internal signals . . . . .2075
41.3.3PSSI clock . . . . .2076
41.3.4PSSI data management . . . . .2076
41.3.5PSSI optional control signals . . . . .2078
41.4PSSI interrupts . . . . .2081
41.5PSSI registers . . . . .2082
41.5.1PSSI control register (PSSI_CR) . . . . .2082
41.5.2PSSI status register (PSSI_SR) . . . . .2083
41.5.3PSSI raw interrupt status register (PSSI_RIS) . . . . .2084
41.5.4PSSI interrupt enable register (PSSI_IER) . . . . .2085
41.5.5PSSI masked interrupt status register (PSSI_MIS) . . . . .2085
41.5.6PSSI interrupt clear register (PSSI_ICR) . . . . .2086
41.5.7PSSI data register (PSSI_DR) . . . . .2086
41.5.8PSSI register map . . . . .2087
42Display subsystem . . . . .2088
42.1Introduction . . . . .2088
42.2Display subsystem main features . . . . .2088
42.3Display subsystem implementation . . . . .2088
42.4Display subsystem functional description . . . . .2088
42.4.1Display subsystem block diagram . . . . .2088
42.4.2Display subsystem pins and external signal interface . . . . .2089
42.4.3Display subsystem clocks . . . . .2089
42.4.4Display subsystem security . . . . .2089
42.5Display subsystem programmable parameters . . . . .2092
42.6Display subsystem interrupts . . . . .2093
42.7Display subsystem registers . . . . .2093
43LCD-TFT display controller (LTDC) . . . . .2094
43.1LTDC introduction . . . . .2094
43.2LTDC main features . . . . .2094
43.3LTDC functional description . . . . .2095
43.3.1LTDC block diagram . . . . .2095
43.3.2LTDC pins and internal signals . . . . .2095
43.3.3LTDC reset and clocks . . . . .2096
43.4LTDC configuration parameters . . . . .2098
43.4.1AXI master . . . . .2098
43.4.2Input layer definition and cropping . . . . .2099
43.4.3Input pixel format . . . . .2100
43.4.4YUV planar . . . . .2102
43.4.5YUV-to-RGB color conversion . . . . .2103
43.4.6Horizontal or vertical mirroring . . . . .2104
43.4.7Default layer color . . . . .2105
43.4.8Color look-up table (CLUT) . . . . .2105
43.4.9Transparency color keying . . . . .2106
43.4.10Display composition - windowing . . . . .2106
43.4.11Display composition - blending . . . . .2107
43.4.12Gamma correction . . . . .2109
43.4.13YUV output conversion . . . . .2109
43.4.14Dithering . . . . .2110
43.4.15CRC hashing . . . . .2111
43.4.16Display timing . . . . .2111
43.4.17Output interface polarity . . . . .2113
43.4.18Shadow registers . . . . .2114
43.4.19General control . . . . .2115
43.4.20Hardware trigger generation . . . . .2115
43.4.21Provision for a secure layer . . . . .2116
43.5LTDC interrupts . . . . .2117
43.6LTDC programming procedure . . . . .2118
43.7LTDC registers . . . . .2119
43.7.1LTDC synchronization size configuration register (LTDC_SSCR) . . . . .2119
43.7.2LTDC back porch configuration register (LTDC_BPCR) . . . . .2119
43.7.3LTDC active width configuration register (LTDC_AWCR) . . . . .2120
43.7.4LTDC total width configuration register (LTDC_TWCR) . . . . .2121
43.7.5LTDC global control register (LTDC_GCR) . . . . .2121
43.7.6LTDC shadow reload configuration register (LTDC_SRCR) . . . . .2123
43.7.7LTDC gamma correction configuration register (LTDC_GCCR) . . . . .2123
43.7.8LTDC background color configuration register (LTDC_BCCR) . . . . .2124
43.7.9LTDC interrupt enable register (LTDC_IER) . . . . .2125
43.7.10LTDC interrupt status register (LTDC_ISR) . . . . .2126
43.7.11LTDC interrupt clear register (LTDC_ICR) . . . . .2126
43.7.12LTDC line interrupt position configuration register (LTDC_LIPCR) . . . . .2127
43.7.13LTDC current position status register (LTDC_CPSR) . . . . .2128
43.7.14LTDC current display status register (LTDC_CDSR) . . . . .2128
43.7.15LTDC external display control register (LTDC_EDCR) . . . . .2129
43.7.16LTDC interrupt enable register 2 (LTDC_IER2) . . . . .2129
43.7.17LTDC interrupt status register 2 (LTDC_ISR2) . . . . .2130
43.7.18LTDC interrupt clear register 2 (LTDC_ICR2) . . . . .2131
43.7.19LTDC line interrupt position configuration register 2 (LTDC_LIPCR2) . . . . .2132
43.7.20LTDC expected CRC register (LTDC_ECRCR) . . . . .2132
43.7.21LTDC computed CRC register (LTDC_CCCRCR) . . . . .2133
43.7.22LTDC FIFO underrun threshold register (LTDC_FUTR) . . . . .2133
43.7.23LTDC layer x configuration 0 register (LTDC_LxC0R) . . . . .2134
43.7.24LTDC layer x configuration 1 register (LTDC_LxC1R) . . . . .2135
43.7.25LTDC layer x reload control register (LTDC_LxRCR) . . . . .2135
43.7.26LTDC layer x control register (LTDC_LxCR) . . . . .2136
43.7.27LTDC layer x window horizontal position configuration register
(LTDC_LxWHPER) . . . . .		2137
43.7.28LTDC layer x window vertical position configuration register
(LTDC_LxWVPER) . . . . .		2138
43.7.29LTDC layer x color keying configuration register
(LTDC_LxCKCR) . . . . .		2138
43.7.30LTDC layer x pixel format configuration register
(LTDC_LxPFCR) . . . . .		2139
43.7.31LTDC layer x constant alpha configuration register
(LTDC_LxCACR) . . . . .		2139
43.7.32LTDC layer x default color configuration register
(LTDC_LxDCCR) . . . . .		2140
43.7.33LTDC layer x blending factors configuration register
(LTDC_LxBFCR) . . . . .		2140
43.7.34LTDC layer x burst length configuration register
(LTDC_LxBLER) . . . . .		2141
43.7.35LTDC layer x planar configuration register
(LTDC_LxPCR) . . . . .		2142
43.7.36LTDC layer x color frame buffer address register
(LTDC_LxCFBAR) . . . . .		2143
43.7.37LTDC layer x color frame buffer length register
(LTDC_LxCFBLER) . . . . .		2143
43.7.38LTDC layer x color frame buffer line number register
(LTDC_LxCFBLNR) . . . . .		2144
43.7.39LTDC layer 1 auxiliary frame buffer address 0 register
(LTDC_L1AFBA0R) . . . . .		2144
43.7.40LTDC layer 1 auxiliary frame buffer address 1 register
(LTDC_L1AFBA1R) . . . . .		2145
43.7.41LTDC layer 1 auxiliary frame buffer length register
(LTDC_L1AFBLER) . . . . .		2145
43.7.42LTDC layer 1 auxiliary frame buffer line number register
(LTDC_L1AFBLNR) . . . . .		2146
43.7.43LTDC layer x CLUT write register (LTDC_LxCLUTWR) . . . . .2146
43.7.44LTDC layer x conversion YCbCr RGB 0 register (LTDC_LxCYR0R) . . . . .2147
43.7.45LTDC layer x conversion YCbCr RGB 1 register (LTDC_LxCYR1R) . . . . .2147
43.7.46LTDC layer x flexible pixel format 0 register (LTDC_LxFPF0R) . . . . .2148
43.7.47LTDC layer x flexible pixel format 1 register (LTDC_LxFPF1R) . . . . .2148
43.7.48LTDC register map . . . . .2149
44Neo-Chrom graphic processor (GPU2D) . . . . .2154
44.1GPU2D introduction . . . . .2154
44.2GPU2D main features . . . . .2154
44.3GPU2D general description . . . . .2155
44.3.1GPU2D block diagram . . . . .2155
44.3.2GPU2D pins and internal signals . . . . .2155
45Video encoder (VENC) . . . . .2157
45.1VENC introduction . . . . .2157
45.2VENC main features . . . . .2157
45.3VENC implementation . . . . .2157
45.4VENC functional description . . . . .2158
45.4.1VENC block diagram . . . . .2158
45.4.2VENC pins and internal signals . . . . .2158
45.4.3VENC reset and clocks . . . . .2159
45.4.4VENC pre-processor . . . . .2159
45.4.5VENC H264 encoder . . . . .2159
45.4.6VENC JPEG encoder . . . . .2160
45.4.7VENC synchronization . . . . .2160
45.4.8VENC security . . . . .2161
45.4.9VENC power-on sequence . . . . .2161
45.4.10VENCRAM power-on sequence for AXI access . . . . .2162
45.5VENC low power modes . . . . .2162
45.6VENC interrupts . . . . .2162
45.7VENC registers . . . . .2162
45.7.1VENC ID register (VENC_SWREG0) . . . . .2162
45.7.2VENC interrupt register (VENC_SWREG1) . . . . .2163
45.7.3VENC bus interface configuration register (VENC_SWREG2) . . . . .2163
45.7.4VENC device configuration register (VENC_SWREG3) . . . . .2163
45.7.5VENC base address for output stream data register
(VENC_SWREG5) . . . . .		2164
45.7.6VENC base address for output control data register
(VENC_SWREG6) . . . . .		2164
45.7.7VENC base address for reference luma register
(VENC_SWREG7) . . . . .		2164
45.7.8VENC base address for reference chroma register
(VENC_SWREG8) . . . . .		2165
45.7.9VENC base address for reconstructed luma register (VENC_SWREG9) . . . . .2165
45.7.10VENC base address for reconstructed chroma register (VENC_SWREG10) . . . . .2165
45.7.11VENC base address for input picture luma register (VENC_SWREG11) . . . . .2166
45.7.12VENC base address for input picture cb register (VENC_SWREG12) . . . . .2166
45.7.13VENC base address for input picture cr register (VENC_SWREG13) . . . . .2166
45.7.14VENC encoder control register 0 (VENC_SWREG14) . . . . .2167
45.7.15VENC encoder control register 1 (VENC_SWREG15) . . . . .2167
45.7.16VENC encoder control register 2 (VENC_SWREG16) . . . . .2167
45.7.17VENC encoder control register 3 (VENC_SWREG17) . . . . .2168
45.7.18VENC encoder control register 4 (VENC_SWREG18) . . . . .2168
45.7.19VENC encoder control register 5 (VENC_SWREG19) . . . . .2168
45.7.20VENC encoder control register 6 (VENC_SWREG20) . . . . .2169
45.7.21VENC encoder control register 7 (VENC_SWREG21) . . . . .2169
45.7.22VENC stream header remainder MSB bits register (VENC_SWREG22) . . . . .2169
45.7.23VENC stream header remainder LSB bits register (VENC_SWREG23) . . . . .2170
45.7.24VENC stream buffer limit/output stream size register (VENC_SWREG24) . . . . .2170
45.7.25VENC encoder control register 8 (VENC_SWREG25) . . . . .2170
45.7.26VENC intra-slice bitmap register (VENC_SWREG26) . . . . .2171
45.7.27VENC encoder control register 9 (VENC_SWREG27) . . . . .2171
45.7.28VENC encoder control register 10 (VENC_SWREG28) . . . . .2171
45.7.29VENC encoder control register 11 (VENC_SWREG29) . . . . .2172
45.7.30VENC encoder control register 12 (VENC_SWREG30) . . . . .2172
45.7.31VENC encoder control register 13 (VENC_SWREG31) . . . . .2172
45.7.32VENC encoder control register 14 (VENC_SWREG32) . . . . .2173
45.7.33VENC encoder control register 15 (VENC_SWREG33) . . . . .2173
45.7.34VENC encoder control register 16 (VENC_SWREG34) . . . . .2173
45.7.35VENC H.264 checkpoint word error 5-6/encoder control register 17 (VENC_SWREG35) . . . . .2174
45.7.36VENC H.264 checkpoint delta QP 1-8/encoder control register 18 (VENC_SWREG36) . . . . .2174
45.7.37VENC encoder control register 19, stream start offset (VENC_SWREG37) . . . . .2174
45.7.38VENC macroblock count output register (VENC_SWREG38) . . . . .2175
45.7.39VENC base address for next pic luminance register
(VENC_SWREG39) . . . . .		2175
45.7.40VENC stabilization mode control register (VENC_SWREG40) . . . . .2175
45.7.41VENC stabilization motion sum div8 output register
(VENC_SWREG41) . . . . .		2176
45.7.42VENC stabilization GMV output, matrix 1, up-left position
output register (VENC_SWREG42) . . . . .		2176
45.7.43VENC stabilization GMV output, matrix 2, up position
output register (VENC_SWREG43) . . . . .		2176
45.7.44VENC stabilization matrix 3, up-right position
output register (VENC_SWREG44) . . . . .		2177
45.7.45VENC stabilization matrix 4, left position
output register (VENC_SWREG45) . . . . .		2177
45.7.46VENC stabilization matrix 5, GMV position
output register (VENC_SWREG46) . . . . .		2177
45.7.47VENC stabilization matrix 6, right position
output register (VENC_SWREG47) . . . . .		2178
45.7.48VENC stabilization matrix 7, down-left position
output register (VENC_SWREG48) . . . . .		2178
45.7.49VENC stabilization matrix 8, down position
output register (VENC_SWREG49) . . . . .		2178
45.7.50VENC stabilization matrix 9, down-right position
output register (VENC_SWREG50) . . . . .		2179
45.7.51VENC base address for cabac context tables H264
register (VENC_SWREG51) . . . . .		2179
45.7.52VENC base address for MV output writing
register (VENC_SWREG52) . . . . .		2179
45.7.53VENC RGB to YUV conversion coefficient A - B
register (VENC_SWREG53) . . . . .		2180
45.7.54VENC RGB to YUV conversion coefficient C - E
register (VENC_SWREG54) . . . . .		2180
45.7.55VENC RGB to YUV conversion coefficient F, RGB mask
MSB bit position register (VENC_SWREG55) . . . . .		2180
45.7.56VENC intra area register (VENC_SWREG56) . . . . .2181
45.7.57VENC CIR intra mb position register (VENC_SWREG57) . . . . .2181
45.7.58VENC intra slice bitmap for slices 0..31/base address for
1st DCT partition register (VENC_SWREG58) . . . . .		2181
45.7.59VENC intra slice bitmap for slices 32..63/base address for
2nd DCT partition register (VENC_SWREG59) . . . . .		2182
45.7.60VENC 1st ROI area register (VENC_SWREG60) . . . . .2182
45.7.61VENC 2nd ROI area register (VENC_SWREG61) . . . . .2182
45.7.62VENC ROI area delta QP, MV register (VENC_SWREG62) . . . . .2183
45.7.63VENC synthesis configuration register encoder 0 register (VENC_SWREG63) . . . . .2183
45.7.64VENC JPEG luma quantization 1/intra 16x16 mode 0-1 penalty register (VENC_SWREG64) . . . . .2183
45.7.65VENC JPEG luma quantization 2/intra 16x16 mode 2-3 penalty register (VENC_SWREG65) . . . . .2184
45.7.66VENC JPEG luma quantization 3/intra 4x4 mode 0-1 penalty register (VENC_SWREG66) . . . . .2184
45.7.67VENC JPEG luma quantization 4/intra 4x4 mode 2-3 penalty register (VENC_SWREG67) . . . . .2184
45.7.68VENC JPEG luma quantization 5/intra 4x4 mode 4-5 penalty register (VENC_SWREG68) . . . . .2185
45.7.69VENC JPEG luma quantization 6/intra 4x4 mode 6-7 penalty register (VENC_SWREG69) . . . . .2185
45.7.70VENC JPEG luma quantization 7/intra 4x4 mode 8-9 penalty register (VENC_SWREG70) . . . . .2185
45.7.71VENC JPEG luma quantization 8/base address for segmentation map register (VENC_SWREG71) . . . . .2186
45.7.72VENC JPEG luma quantization 9/segment1 parameter register (VENC_SWREG72) . . . . .2186
45.7.73VENC JPEG luma quantization 10/segment1 parameter register (VENC_SWREG73) . . . . .2186
45.7.74VENC JPEG luma quantization 11/segment1 parameter register (VENC_SWREG74) . . . . .2187
45.7.75VENC JPEG luma quantization 12/segment1 parameter register (VENC_SWREG75) . . . . .2187
45.7.76VENC JPEG luma quantization 13/segment1 parameter register (VENC_SWREG76) . . . . .2187
45.7.77VENC JPEG luma quantization 14/segment1 parameter register (VENC_SWREG77) . . . . .2188
45.7.78VENC JPEG luma quantization 15/segment1 parameter register (VENC_SWREG78) . . . . .2188
45.7.79VENC JPEG luma quantization 16/segment2 parameter register (VENC_SWREG79) . . . . .2188
45.7.80VENC JPEG chroma quantization 1/segment2 parameter register (VENC_SWREG80) . . . . .2189
45.7.81VENC JPEG chroma quantization 2/segment2 parameter register (VENC_SWREG81) . . . . .2189
45.7.82VENC JPEG chroma quantization 3/segment2 parameter register (VENC_SWREG82) . . . . .2189
45.7.83VENC JPEG chroma quantization 4/segment2 parameter register (VENC_SWREG83) . . . . .2190
45.7.84VENC JPEG chroma quantization 5/segment2 parameter register (VENC_SWREG84) .....2190
45.7.85VENC JPEG chroma quantization 6/segment2 parameter register (VENC_SWREG85) .....2190
45.7.86VENC JPEG chroma quantization 7/segment2 parameter register (VENC_SWREG86) .....2191
45.7.87VENC JPEG chroma quantization 8/segment2 parameter register (VENC_SWREG87) .....2191
45.7.88VENC JPEG chroma quantization 9/segment3 parameter register (VENC_SWREG88) .....2191
45.7.89VENC JPEG chroma quantization 10/segment3 parameter register (VENC_SWREG89) .....2192
45.7.90VENC JPEG chroma quantization 11/segment3 parameter register (VENC_SWREG90) .....2192
45.7.91VENC JPEG chroma quantization 12/segment3 parameter register (VENC_SWREG91) .....2192
45.7.92VENC JPEG chroma quantization 13/segment3 parameter register (VENC_SWREG92) .....2193
45.7.93VENC JPEG chroma quantization 14/segment3 parameter register (VENC_SWREG93) .....2193
45.7.94VENC JPEG chroma quantization 15/segment3 parameter register (VENC_SWREG94) .....2193
45.7.95VENC JPEG chroma quantization 16/segment3 parameter register (VENC_SWREG95) .....2194
45.7.96VENC DMV 4p/1p penalty values 0-3 register (VENC_SWREG96) .2194
45.7.97VENC DMV 4p/1p penalty values 4-7 register (VENC_SWREG97) .2194
45.7.98VENC DMV 4p/1p penalty values register (VENC_SWREGx) . . . .2195
45.7.99VENC DMV 4p/1p penalty values 124-127 register (VENC_SWREG127) .....2195
45.7.100VENC DMV qpel penalty values 0-3 register (VENC_SWREG128) .....2195
45.7.101VENC DMV qpel penalty values 4-7 register (VENC_SWREG129) .....2196
45.7.102VENC DMV qpel penalty values register (VENC_SWREGx) . . . .2196
45.7.103VENC DMV qpel penalty values 124-127 register (VENC_SWREG159) .....2196
45.7.104VENC base address for output of down-scaled encoder image in YUYV 4:2:2 format register (VENC_SWREG231) .....2197
45.7.105VENC scaling control register (VENC_SWREGx) .....2197
45.7.106VENC squared error output calculated for 13x13 pixels per macroblock register (VENC_SWREG236) .....2197
45.7.107VENC MAD 2 control and output register (VENC_SWREG237) . . . .2198
45.7.108VENC MAD 3 control and output register (VENC_SWREG238) . . . .2198
45.7.109VENC segment 1: intra 16x16 mode 0-2 penalty register (VENC_SWREG256) . . . . .2198
45.7.110VENC segment 1: intra 16x16 mode 3, intra 4x4 0-1 penalty register (VENC_SWREG257) . . . . .2199
45.7.111VENC segment 1: intra 4x4 mode 2-4 penalty register (VENC_SWREG258) . . . . .2199
45.7.112VENC segment 1: intra 4x4 mode 5-7 penalty register (VENC_SWREG259) . . . . .2199
45.7.113VENC segment 1: intra 4x4 mode 8-9 penalty, previous mode favor for H.264 register (VENC_SWREG260) . . . . .2200
45.7.114VENC segment 1: bit cost of inter type, intra 16x16 mode favor register (VENC_SWREG261) . . . . .2200
45.7.115VENC segment 1: inter MB mode favor, skip mode penalty, penalty value for 2nd reference frame register (VENC_SWREG262)2200
45.7.116VENC segment 1: penalty value register (VENC_SWREGx) . . . . .2201
45.7.117VENC segment 1: deadzone rate multiplier for plane 0-1 register (VENC_SWREG265) . . . . .2201
45.7.118VENC segment 1: deadzone rate multiplier for plane 2-3 register (VENC_SWREG266) . . . . .2201
45.7.119VENC segment 1: deadzone rate for macroblock skip token 0-1, dmv penalty coefficient register (VENC_SWREG267) . . . . .2202
45.7.120VENC segment 2: intra 16x16 mode 0-2 penalty register (VENC_SWREG268) . . . . .2202
45.7.121VENC segment 2: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1 penalty register (VENC_SWREG269) . . . . .2202
45.7.122VENC segment 2: intra 4x4 mode 2-4 penalty register (VENC_SWREG270) . . . . .2203
45.7.123VENC segment 2: intra 4x4 mode 5-7 penalty register (VENC_SWREG271) . . . . .2203
45.7.124VENC segment 2: intra 4x4 mode 8-9 penalty, intra 4x4 previous mode favor for H.264 register (VENC_SWREG272) . . . . .2203
45.7.125VENC segment 2: bit cost of inter type, intra 16x16 mode favor register (VENC_SWREG273) . . . . .2204
45.7.126VENC segment 2: inter MB mode favor, skip mode penalty, penalty value register (VENC_SWREG274) . . . . .2204
45.7.127VENC segment 2: penalty value register (VENC_SWREGx) . . . . .2204
45.7.128VENC segment 2: deadzone rate multiplier for plane 0-1 register (VENC_SWREG277) . . . . .2205
45.7.129VENC segment 2: deadzone rate multiplier for plane 2-3 register (VENC_SWREG278) . . . . .2205
45.7.130VENC segment 2: deadzone rate for macroblock skip token 0-1, dmv penalty coefficient register (VENC_SWREG279) . . . . .2205
45.7.131VENC segment 3: intra 16x16 mode 0-2 penalty register (VENC_SWREG280) . . . . .2206
45.7.132VENC segment 3: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1 penalty register (VENC_SWREG281) . . . . .2206
45.7.133VENC segment 3: intra 4x4 mode 2-4 penalty register (VENC_SWREG282) . . . . .2206
45.7.134VENC segment 3: intra 4x4 mode 5-7 penalty register (VENC_SWREG283) . . . . .2207
45.7.135VENC segment 3: intra 4x4 mode 8-9 penalty, intra 4x4 previous mode favor for H.264 register (VENC_SWREG284) . . . . .2207
45.7.136VENC segment 3: bit cost of inter type, intra 16x16 mode favor register (VENC_SWREG285) . . . . .2207
45.7.137VENC segment 3: inter MB mode favor in intra/inter selection, inter MB mode favor, penalty value for second reference frame register (VENC_SWREG286) . . . . .2208
45.7.138VENC segment 3: penalty value register (VENC_SWREGx) . . . . .2208
45.7.139VENC segment 3: deadzone rate multiplier for plane 0-1 register (VENC_SWREG289) . . . . .2208
45.7.140VENC segment 3: deadzone rate multiplier for plane 2-3 register (VENC_SWREG290) . . . . .2209
45.7.141VENC segment 3: deadzone rate for macroblock skip token 0-1, dmv penalty coefficient register (VENC_SWREG291) . . . . .2209
45.7.142VENC Mb boost register (VENC_SWREG294) . . . . .2209
45.7.143VENC variance control, Pskop condoning mode register (VENC_SWREG295) . . . . .2210
45.7.144VENC synthesis configuration register encoder 1 read only register (VENC_SWREG296) . . . . .2210
45.7.145VENC MBRC control register (VENC_SWREG297) . . . . .2210
45.7.146VENC segment 4: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG298) . . . . .2211
45.7.147VENC segment 4: skip mode penalty, inter MB mode favor register (VENC_SWREG299) . . . . .2211
45.7.148VENC segment 4: penalty value register (VENC_SWREGx) . . . . .2211
45.7.149VENC segment 5: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG302) . . . . .2212
45.7.150VENC segment 5: skip mode penalty, inter MB mode favor register (VENC_SWREG303) . . . . .2212
45.7.151VENC segment 5: penalty value register (VENC_SWREGx) . . . . .2212
45.7.152VENC segment 6: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG306) . . . . .2213
45.7.153 VENC segment 6: skip mode penalty, inter MB mode favor register (VENC_SWREG307) .....2213
45.7.154 VENC segment 6: penalty value register (VENC_SWREGx) .....2213
45.7.155 VENC segment 7: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG310) .....2214
45.7.156 VENC segment 7: skip mode penalty, inter MB mode favor register (VENC_SWREG311) .....2214
45.7.157 VENC segment 7: penalty value register (VENC_SWREGx) .....2214
45.7.158 VENC segment 8: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG314) .....2215
45.7.159 VENC segment 8: skip mode penalty, inter MB mode favor register (VENC_SWREG315) .....2215
45.7.160 VENC segment 8: penalty value register (VENC_SWREGx) .....2215
45.7.161 VENC segment 9: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG318) .....2216
45.7.162 VENC segment 9: skip mode penalty, inter MB mode favor register (VENC_SWREG319) .....2216
45.7.163 VENC segment 9: penalty value register (VENC_SWREGx) .....2216
45.7.164 VENC segment 10: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG322) .....2217
45.7.165 VENC segment 10: skip mode penalty, inter MB mode favor register (VENC_SWREG323) .....2217
45.7.166 VENC segment 10: penalty value register (VENC_SWREGx) .....2217
45.7.167 VENC segment 11: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG326) .....2218
45.7.168 VENC segment 11: skip mode penalty, inter MB mode favor register (VENC_SWREG327) .....2218
45.7.169 VENC segment 11: penalty value register (VENC_SWREGx) .....2218
45.7.170 VENC segment 12: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG330) .....2219
45.7.171 VENC segment 12: skip mode penalty, inter MB mode favor register (VENC_SWREG331) .....2219
45.7.172 VENC segment 12: penalty value register (VENC_SWREGx) .....2219
45.7.173 VENC segment 13: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG334) .....2220
45.7.174VENC segment 13: skip mode penalty, inter MB mode favor register (VENC_SWREG335) . . . . .2220
45.7.175VENC segment 13: penalty value register (VENC_SWREGx) . . . . .2220
45.7.176VENC segment 14: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG338) . . . . .2221
45.7.177VENC segment 14: skip mode penalty, inter MB mode favor register (VENC_SWREG339) . . . . .2221
45.7.178VENC segment 14: penalty value register (VENC_SWREGx) . . . . .2221
45.7.179VENC segment 15: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG342) . . . . .2222
45.7.180VENC segment 15: skip mode penalty, inter MB mode favor register (VENC_SWREG343) . . . . .2222
45.7.181VENC segment 15: penalty value register (VENC_SWREGx) . . . . .2222
45.7.182VENC segment 16: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG346) . . . . .2223
45.7.183VENC segment 16: skip mode penalty, inter MB mode favor register (VENC_SWREG347) . . . . .2223
45.7.184VENC segment 16: penalty value register (VENC_SWREGx) . . . . .2223
45.7.185VENC segment 17: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG350) . . . . .2224
45.7.186VENC segment 17: skip mode penalty, inter MB mode favor register (VENC_SWREG351) . . . . .2224
45.7.187VENC segment 17: penalty value register (VENC_SWREGx) . . . . .2224
45.7.188VENC segment 18: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG354) . . . . .2225
45.7.189VENC segment 18: skip mode penalty, inter MB mode favor register (VENC_SWREG355) . . . . .2225
45.7.190VENC segment 18: penalty value register (VENC_SWREGx) . . . . .2225
45.7.191VENC segment 19: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG358) . . . . .2226
45.7.192VENC segment 19: skip mode penalty, inter MB mode favor register (VENC_SWREG359) . . . . .2226
45.7.193VENC segment 19: penalty value register (VENC_SWREGx) . . . . .2226
45.7.194VENC segment 20: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG362) . . . . .2227
45.7.195VENC segment 20: skip mode penalty, inter MB mode favor register (VENC_SWREG363) . . . . .2227
45.7.196VENC segment 20: penalty value register (VENC_SWREGx) . . . . .2227
45.7.197VENC segment 21: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG366) . . . . .2228
45.7.198VENC segment 21: skip mode penalty, inter MB mode favor register (VENC_SWREG367) . . . . .2228
45.7.199VENC segment 21: penalty value register (VENC_SWREGx) . . . . .2228
45.7.200VENC segment 22: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG370) . . . . .2229
45.7.201VENC segment 22: skip mode penalty, inter MB mode favor register (VENC_SWREG371) . . . . .2229
45.7.202VENC segment 22: penalty value register (VENC_SWREGx) . . . . .2229
45.7.203VENC segment 23: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG374) . . . . .2230
45.7.204VENC segment 23: skip mode penalty, inter MB mode favor register (VENC_SWREG375) . . . . .2230
45.7.205VENC segment 23: penalty value register (VENC_SWREGx) . . . . .2230
45.7.206VENC segment 24: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG378) . . . . .2231
45.7.207VENC segment 24: skip mode penalty, inter MB mode favor register (VENC_SWREG379) . . . . .2231
45.7.208VENC segment 24: penalty value register (VENC_SWREGx) . . . . .2231
45.7.209VENC segment 25: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG382) . . . . .2232
45.7.210VENC segment 25: skip mode penalty, inter MB mode favor register (VENC_SWREG383) . . . . .2232
45.7.211VENC segment 25: penalty value register (VENC_SWREGx) . . . . .2232
45.7.212VENC segment 26: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG386) . . . . .2233
45.7.213VENC segment 26: skip mode penalty, inter MB mode favor register (VENC_SWREG387) . . . . .2233
45.7.214VENC segment 26: penalty value register (VENC_SWREGx) . . . . .2233
45.7.215VENC segment 27: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG390) . . . . .2234
45.7.216VENC segment 27: skip mode penalty, inter MB mode favor register (VENC_SWREG391) . . . . .2234
45.7.217VENC segment 27: penalty value register (VENC_SWREGx) . . . . .2234
45.7.218VENC segment 28: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG394) . . . . .2235
45.7.219VENC segment 28: skip mode penalty, inter MB mode favor register (VENC_SWREG395) . . . . .2235
45.7.220VENC segment 28: penalty value register (VENC_SWREGx) . . . . .2235
45.7.221VENC segment 29: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG398) . . . . .2236
45.7.222VENC segment 29: skip mode penalty, inter MB mode favor register (VENC_SWREG399) . . . . .2236
45.7.223VENC segment 29: penalty value register (VENC_SWREGx) . . . . .2236
45.7.224VENC segment 30: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG402) . . . . .2237
45.7.225VENC segment 30: skip mode penalty, inter MB mode favor register (VENC_SWREG403) . . . . .2237
45.7.226VENC segment 30: penalty value register (VENC_SWREGx) . . . . .2237
45.7.227VENC segment 31: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register (VENC_SWREG406) . . . . .2238
45.7.228VENC segment 31: skip mode penalty, inter MB mode favor register (VENC_SWREG407) . . . . .2238
45.7.229VENC segment 31: penalty value register (VENC_SWREGx) . . . . .2238
45.7.230VENC MBRC control, QP, offset, enable register (VENC_SWREG410) . . . . .2239
45.7.231VENC gain of MB QP delta. 8.8 format register (VENC_SWREG411) . . . . .2239
45.7.232VENC average of MB complexity register (VENC_SWREG412) . . . . .2239
45.7.233VENC reference compression control register (VENC_SWREG413) . . . . .2240
45.7.234VENC base address for reference luma register (VENC_SWREG414) . . . . .2240
45.7.235VENC base address for reference chroma register (VENC_SWREG415) . . . . .2240
45.7.236VENC base address for reconstructed luma register (VENC_SWREG416) . . . . .2241
45.7.237VENC base address for reconstructed chroma register (VENC_SWREG417) . . . . .2241
45.7.238 VENC base address for second reference luma register (VENC_SWREG418) . . . . .2241
45.7.239 VENC base address for second reference chroma register (VENC_SWREG419) . . . . .2242
45.7.240 VENC limit of chroma RFC buffer register (VENC_SWREG420) . . . . .2242
45.7.241 VENC reorder control register (VENC_SWREG421) . . . . .2242
45.7.242 VENC AXI read ID register (VENC_SWREG422) . . . . .2243
45.7.243 VENC base address MSB for reference luma compression table register (VENC_SWREG423) . . . . .2243
45.7.244 VENC base address MSB for reference chroma compression table register (VENC_SWREG424) . . . . .2243
45.7.245 VENC base address MSB for reconstructed luma compression table register (VENC_SWREG425) . . . . .2244
45.7.246 VENC base address for reconstructed chroma compression table register (VENC_SWREG426) . . . . .2244
45.7.247 VENC base address MSB for second reference luma compression table register (VENC_SWREG427) . . . . .2244
45.7.248 VENC base address MSB for second reference chroma compression table register (VENC_SWREG428) . . . . .2245
45.7.249 VENC high 32 bits of base address for output stream data register (VENC_SWREG429) . . . . .2245
45.7.250 VENC high 32 bits of base address for output control data register (VENC_SWREG430) . . . . .2245
45.7.251 VENC high 32 bits of base address for reference luma register (VENC_SWREG431) . . . . .2246
45.7.252 VENC high 32 bits of base address for reference chroma register (VENC_SWREG432) . . . . .2246
45.7.253 VENC high 32 bits of base address for reconstructed luma register (VENC_SWREG433) . . . . .2246
45.7.254 VENC high 32 bits of base address for reconstructed chroma register (VENC_SWREG434) . . . . .2247
45.7.255 VENC high 32 bits of base address for input picture luma register (VENC_SWREG435) . . . . .2247
45.7.256 VENC high 32 bits of base address for input picture cb register (VENC_SWREG436) . . . . .2247
45.7.257 VENC high 32 bits of base address for input picture cr register (VENC_SWREG437) . . . . .2248
45.7.258 VENC high 32 bits of base address for second reference luma register (VENC_SWREG438) . . . . .2248
45.7.259 VENC high 32 bits of base address for second reference chroma register (VENC_SWREG439) . . . . .2248
45.7.260VENC high 32 bits of H264 secondary ref pic base register (VENC_SWREGx) . . . . .2249
45.7.261VENC high 32 bits of base address for next pic luminance register (VENC_SWREG442) . . . . .2249
45.7.262VENC high 32 bits of base address for cabac context tables H264 register (VENC_SWREG443) . . . . .2249
45.7.263VENC high 32 bits of base address for MV output writing register (VENC_SWREG444) . . . . .2250
45.7.264VENC high 32 bits of base address for output of down-scaled encoder image in YUYV 4:2:2 format register (VENC_SWREG449)2250
45.7.265VENC low-latency control register (VENC_SWREG497) . . . . .2250
45.7.266VENC encoder line buffer offset register (VENC_SWREG498) . . . . .2251
45.7.267VENC register map . . . . .2251
46JPEG codec (JPEG) . . . . .2265
46.1JPEG introduction . . . . .2265
46.2JPEG codec main features . . . . .2265
46.3JPEG codec block functional description . . . . .2266
46.3.1General description . . . . .2266
46.3.2JPEG internal signals . . . . .2266
46.3.3JPEG decoding procedure . . . . .2267
46.3.4JPEG encoding procedure . . . . .2269
46.4JPEG codec interrupts . . . . .2272
46.5JPEG codec registers . . . . .2272
46.5.1JPEG codec control register (JPEG_CONF0) . . . . .2272
46.5.2JPEG codec configuration register 1 (JPEG_CONF1) . . . . .2273
46.5.3JPEG codec configuration register 2 (JPEG_CONF2) . . . . .2274
46.5.4JPEG codec configuration register 3 (JPEG_CONF3) . . . . .2274
46.5.5JPEG codec configuration register x (JPEG_CONFx) . . . . .2275
46.5.6JPEG control register (JPEG_CR) . . . . .2276
46.5.7JPEG status register (JPEG_SR) . . . . .2277
46.5.8JPEG clear flag register (JPEG_CFR) . . . . .2278
46.5.9JPEG data input register (JPEG_DIR) . . . . .2279
46.5.10JPEG data output register (JPEG_DOR) . . . . .2279
46.5.11JPEG quantization memory x (JPEG_QMEMx_y) . . . . .2280
46.5.12JPEG Huffman min (JPEG_HUFFMINx_y) . . . . .2280
46.5.13JPEG Huffman min x (JPEG_HUFFMINx_y) . . . . .2281
46.5.14JPEG Huffman base (JPEG_HUFFBASEx)2281
46.5.15JPEG Huffman symbol (JPEG_HUFFSYMBx)2282
46.5.16JPEG DHT memory (JPEG_DHTMEMx)2283
46.5.17JPEG Huffman encoder ACx (JPEG_HUFFENC_ACx_y)2283
46.5.18JPEG Huffman encoder DCx (JPEG_HUFFENC_DCx_y)2284
46.5.19JPEG codec register map2285
47True random number generator (RNG)2287
47.1RNG introduction2287
47.2RNG main features2287
47.3RNG functional description2288
47.3.1RNG block diagram2288
47.3.2RNG internal signals2288
47.3.3Random number generation2288
47.3.4RNG initialization2291
47.3.5RNG operation2292
47.3.6RNG clocking2294
47.3.7Error management2294
47.3.8RNG low-power use2295
47.4RNG interrupts2296
47.5RNG processing time2296
47.6RNG entropy source validation2297
47.6.1Introduction2297
47.6.2Validation conditions2297
47.7RNG registers2298
47.7.1RNG control register (RNG_CR)2298
47.7.2RNG status register (RNG_SR)2300
47.7.3RNG data register (RNG_DR)2301
47.7.4RNG noise source control register (RNG_NSCR)2302
47.7.5RNG health test control register (RNG_HTCR)2303
47.7.6RNG register map2303
48Secure AES coprocessor (SAES)2304
48.1SAES introduction2304
48.2SAES main features2304
48.3SAES implementation2305
48.4SAES functional description . . . . .2305
48.4.1SAES block diagram . . . . .2305
48.4.2SAES internal signals . . . . .2306
48.4.3SAES reset and clocks . . . . .2307
48.4.4SAES symmetric cipher implementation . . . . .2307
48.4.5SAES encryption or decryption typical usage . . . . .2308
48.4.6SAES authenticated encryption, decryption, and cipher-based message authentication . . . . .2310
48.4.7SAES ciphertext stealing and data padding . . . . .2311
48.4.8SAES suspend and resume operations . . . . .2311
48.4.9SAES basic chaining modes (ECB, CBC) . . . . .2312
48.4.10SAES counter (CTR) mode . . . . .2316
48.4.11SAES Galois/counter mode (GCM) . . . . .2318
48.4.12SAES Galois message authentication code (GMAC) . . . . .2322
48.4.13SAES counter with CBC-MAC (CCM) . . . . .2324
48.4.14SAES operation with wrapped keys . . . . .2329
48.4.15SAES operation with shared keys . . . . .2333
48.4.16SAES data registers and data swapping . . . . .2334
48.4.17SAES key registers . . . . .2337
48.4.18SAES initialization vector registers . . . . .2338
48.4.19SAES error management . . . . .2339
48.5SAES interrupts . . . . .2341
48.6SAES DMA requests . . . . .2341
48.7SAES processing latency . . . . .2342
48.8SAES registers . . . . .2344
48.8.1SAES control register (SAES_CR) . . . . .2344
48.8.2SAES status register (SAES_SR) . . . . .2347
48.8.3SAES data input register (SAES_DINR) . . . . .2348
48.8.4SAES data output register (SAES_DOUTr) . . . . .2349
48.8.5SAES key register 0 (SAES_KEYR0) . . . . .2349
48.8.6SAES key register 1 (SAES_KEYR1) . . . . .2350
48.8.7SAES key register 2 (SAES_KEYR2) . . . . .2350
48.8.8SAES key register 3 (SAES_KEYR3) . . . . .2350
48.8.9SAES initialization vector register 0 (SAES_IVR0) . . . . .2351
48.8.10SAES initialization vector register 1 (SAES_IVR1) . . . . .2351
48.8.11SAES initialization vector register 2 (SAES_IVR2) . . . . .2351
48.8.12SAES initialization vector register 3 (SAES_IVR3) . . . . .2352
48.8.13SAES key register 4 (SAES_KEYR4) . . . . .2352
48.8.14SAES key register 5 (SAES_KEYR5) . . . . .2352
48.8.15SAES key register 6 (SAES_KEYR6) . . . . .2353
48.8.16SAES key register 7 (SAES_KEYR7) . . . . .2353
48.8.17SAES suspend registers (SAES_SUSPRx) . . . . .2353
48.8.18SAES interrupt enable register (SAES_IER) . . . . .2354
48.8.19SAES interrupt status register (SAES_ISR) . . . . .2355
48.8.20SAES interrupt clear register (SAES_ICR) . . . . .2356
48.8.21SAES register map . . . . .2357
49Cryptographic processor (CRYP) . . . . .2359
49.1CRYP introduction . . . . .2359
49.2CRYP main features . . . . .2359
49.3CRYP implementation . . . . .2360
49.4CRYP functional description . . . . .2361
49.4.1CRYP block diagram . . . . .2361
49.4.2CRYP internal signals . . . . .2362
49.4.3CRYP reset and clocks . . . . .2362
49.4.4CRYP symmetric cipher implementation . . . . .2362
49.4.5CRYP encryption/ decryption typical usage . . . . .2363
49.4.6CRYP authenticated encryption, decryption, and cipher-based message authentication . . . . .2366
49.4.7CRYP ciphertext stealing and data padding . . . . .2366
49.4.8CRYP suspend and resume operations . . . . .2367
49.4.9CRYP basic chaining modes (ECB, CBC) . . . . .2367
49.4.10CRYP counter mode (CTR) . . . . .2372
49.4.11CRYP AES Galois/counter mode (GCM) . . . . .2374
49.4.12CRYP AES Galois message authentication code (GMAC) . . . . .2380
49.4.13CRYP AES Counter with CBC-MAC (CCM) . . . . .2381
49.4.14AES key sharing with secure AES co-processor . . . . .2386
49.4.15CRYP data registers and data swapping . . . . .2387
49.4.16CRYP key registers . . . . .2390
49.4.17CRYP initialization vector registers . . . . .2390
49.4.18CRYP error management . . . . .2391
49.5CRYP interrupts . . . . .2391
49.6CRYP DMA requests . . . . .2392
49.7CRYP processing time . . . . .2393
49.8CRYP registers . . . . .2394
49.8.1CRYP control register (CRYP_CR) . . . . .2394
49.8.2CRYP status register (CRYP_SR) . . . . .2396
49.8.3CRYP data input register (CRYP_DINR) . . . . .2398
49.8.4CRYP data output register (CRYP_DOUTR) . . . . .2398
49.8.5CRYP DMA control register (CRYP_DMACR) . . . . .2399
49.8.6CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . .2399
49.8.7CRYP raw interrupt status register (CRYP_RISR) . . . . .2400
49.8.8CRYP masked interrupt status register (CRYP_MISR) . . . . .2400
49.8.9CRYP key register 0L (CRYP_K0LR) . . . . .2401
49.8.10CRYP key register 0R (CRYP_K0RR) . . . . .2402
49.8.11CRYP key register 1L (CRYP_K1LR) . . . . .2402
49.8.12CRYP key register 1R (CRYP_K1RR) . . . . .2402
49.8.13CRYP key register 2L (CRYP_K2LR) . . . . .2403
49.8.14CRYP key register 2R (CRYP_K2RR) . . . . .2403
49.8.15CRYP key register 3L (CRYP_K3LR) . . . . .2404
49.8.16CRYP key register 3R (CRYP_K3RR) . . . . .2404
49.8.17CRYP initialization vector register 0L (CRYP_IV0LR) . . . . .2404
49.8.18CRYP initialization vector register 0R (CRYP_IV0RR) . . . . .2405
49.8.19CRYP initialization vector register 1L (CRYP_IV1LR) . . . . .2405
49.8.20CRYP initialization vector register 1R (CRYP_IV1RR) . . . . .2406
49.8.21CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) . . . . .2406
49.8.22CRYP context swap GCM registers (CRYP_CSGCMxR) . . . . .2407
49.8.23CRYP register map . . . . .2407
50Hash processor (HASH) . . . . .2409
50.1HASH introduction . . . . .2409
50.2HASH main features . . . . .2409
50.3HASH implementation . . . . .2410
50.4HASH functional description . . . . .2410
50.4.1HASH block diagram . . . . .2410
50.4.2HASH internal signals . . . . .2410
50.4.3About secure hash algorithms . . . . .2411
50.4.4Message data feeding . . . . .2411
50.4.5Message digest computing . . . . .2412
50.4.6Message padding . . . . .2414
50.4.7HMAC operation . . . . .2416
50.4.8HASH suspend/resume operations . . . . .2417
50.4.9HASH DMA interface . . . . .2419
50.4.10HASH error management . . . . .2420
50.4.11HASH processing time . . . . .2420
50.5HASH interrupts . . . . .2421
50.6HASH registers . . . . .2421
50.6.1HASH control register (HASH_CR) . . . . .2421
50.6.2HASH data input register (HASH_DIN) . . . . .2423
50.6.3HASH start register (HASH_STR) . . . . .2424
50.6.4HASH digest registers . . . . .2425
50.6.5HASH interrupt enable register (HASH_IMR) . . . . .2427
50.6.6HASH status register (HASH_SR) . . . . .2427
50.6.7HASH context swap registers . . . . .2428
50.6.8HASH register map . . . . .2429
51Memory cipher engine (MCE) . . . . .2431
51.1MCE introduction . . . . .2431
51.2MCE main features . . . . .2431
51.3MCE implementation . . . . .2432
51.4MCE functional description . . . . .2432
51.4.1MCE block diagram . . . . .2432
51.4.2MCE internal signals . . . . .2432
51.4.3MCE programming . . . . .2433
51.4.4MCE reset and clocks . . . . .2434
51.4.5MCE block cipher encryption mode . . . . .2434
51.4.6MCE stream cipher encryption mode . . . . .2436
51.4.7MCE AXI traffic management . . . . .2437
51.4.8MCE encryption disable options . . . . .2437
51.4.9MCE error management . . . . .2438
51.5MCE interrupts . . . . .2438
51.6MCE registers . . . . .2439
51.6.1MCE configuration register (MCE_CR) . . . . .2439
51.6.2MCE status register (MCE_SR) . . . . .2440
51.6.3MCE illegal access status register (MCE_IASR) . . . . .2441
51.6.4MCE illegal access clear register (MCE_IACR) . . . . .2441
51.6.5MCE illegal access interrupt enable register (MCE_IAIER) . . . . .2441
51.6.6MCE illegal address register (MCE_IADDR) . . . . .2442
51.6.7MCE region x configuration register (MCE_REGCRx) . . . . .2442
51.6.8MCE start address for region x register
(MCE_SADDRx) . . . . .		2444
51.6.9MCE end address for region x register
(MCE_EADDRx) . . . . .		2444
51.6.10MCE master key x (MCE_MKEYRx) . . . . .2445
51.6.11MCE fast master key x (MCE_FMKEYRx) . . . . .2445
51.6.12MCE cipher context z configuration register (MCE_CCzCFGR) . . . . .2446
51.6.13MCE cipher context z nonce register 0 (MCE_CCzNR0) . . . . .2447
51.6.14MCE cipher context z nonce register 1 (MCE_CCzNR1) . . . . .2448
51.6.15MCE cipher context z key register 0 (MCE_CCzKEYR0) . . . . .2448
51.6.16MCE cipher context z key register 1 (MCE_CCzKEYR1) . . . . .2449
51.6.17MCE cipher context z key register 2 (MCE_CCzKEYR2) . . . . .2449
51.6.18MCE cipher context z key register 3 (MCE_CCzKEYR3) . . . . .2449
51.6.19MCE register map . . . . .2450
52Public key accelerator (PKA) . . . . .2452
52.1PKA introduction . . . . .2452
52.2PKA main features . . . . .2452
52.3PKA functional description . . . . .2453
52.3.1PKA block diagram . . . . .2453
52.3.2PKA internal signals . . . . .2453
52.3.3PKA reset and clocks . . . . .2453
52.3.4PKA public key acceleration . . . . .2454
52.3.5Typical applications for PKA . . . . .2456
52.3.6PKA procedure to perform an operation . . . . .2458
52.3.7PKA error management . . . . .2459
52.4PKA operating modes . . . . .2460
52.4.1Introduction . . . . .2460
52.4.2Montgomery parameter computation . . . . .2461
52.4.3Modular addition . . . . .2461
52.4.4Modular subtraction . . . . .2462
52.4.5Modular and Montgomery multiplication . . . . .2462
52.4.6Modular exponentiation . . . . .2463
52.4.7Modular inversion . . . . .2465
52.4.8Modular reduction . . . . .2465
52.4.9Arithmetic addition . . . . .2466
52.4.10Arithmetic subtraction . . . . .2466
52.4.11Arithmetic multiplication . . . . .2467
52.4.12Arithmetic comparison . . . . .2467
52.4.13RSA CRT exponentiation . . . . .2467
52.4.14Point on elliptic curve Fp check . . . . .2468
52.4.15ECC Fp scalar multiplication . . . . .2469
52.4.16ECDSA sign . . . . .2470
52.4.17ECDSA verification . . . . .2472
52.4.18ECC complete addition . . . . .2473
52.4.19ECC double base ladder . . . . .2473
52.4.20ECC projective to affine . . . . .2474
52.5Example of configurations and processing times . . . . .2475
52.5.1Supported elliptic curves . . . . .2475
52.5.2Computation times . . . . .2477
52.6PKA interrupts . . . . .2479
52.7PKA registers . . . . .2480
52.7.1PKA control register (PKA_CR) . . . . .2480
52.7.2PKA status register (PKA_SR) . . . . .2482
52.7.3PKA clear flag register (PKA_CLRFR) . . . . .2483
52.7.4PKA RAM . . . . .2483
52.7.5PKA register map . . . . .2484
53Advanced-control timers (TIM1/TIM8) . . . . .2485
53.1TIM1/TIM8 introduction . . . . .2485
53.2TIM1/TIM8 main features . . . . .2485
53.3TIM1/TIM8 functional description . . . . .2486
53.3.1Block diagram . . . . .2486
53.3.2TIM1/TIM8 pins and internal signals . . . . .2487
53.3.3Time-base unit . . . . .2491
53.3.4Counter modes . . . . .2493
53.3.5Repetition counter . . . . .2505
53.3.6External trigger input . . . . .2506
53.3.7Clock selection . . . . .2507
53.3.8Capture/compare channels . . . . .2511
53.3.9Input capture mode . . . . .2513
53.3.10PWM input mode . . . . .2514
53.3.11Forced output mode . . . . .2515
53.3.12Output compare mode . . . . .2516
53.3.13PWM mode . . . . .2517
53.3.14Asymmetric PWM mode . . . . .2525
53.3.15Combined PWM mode . . . . .2526
53.3.16Combined 3-phase PWM mode . . . . .2527
53.3.17Complementary outputs and dead-time insertion . . . . .2528
53.3.18Using the break function . . . . .2531
53.3.19Bidirectional break inputs . . . . .2537
53.3.20Clearing the tim_ocxref signal on an external event . . . . .2538
53.3.216-step PWM generation . . . . .2539
53.3.22One-pulse mode . . . . .2540
53.3.23Retriggerable One-pulse mode . . . . .2542
53.3.24Pulse on compare mode . . . . .2543
53.3.25Encoder interface mode . . . . .2545
53.3.26Direction bit output . . . . .2562
53.3.27UIF bit remapping . . . . .2563
53.3.28Timer input XOR function . . . . .2563
53.3.29Interfacing with Hall sensors . . . . .2563
53.3.30Timer synchronization . . . . .2565
53.3.31ADC triggers . . . . .2570
53.3.32ADC synchronization . . . . .2570
53.3.33DMA burst mode . . . . .2571
53.3.34TIM1/TIM8 DMA requests . . . . .2572
53.3.35Debug mode . . . . .2572
53.4TIM1/TIM8 low-power modes . . . . .2573
53.5TIM1/TIM8 interrupts . . . . .2573
53.6TIM1/TIM8 registers . . . . .2574
53.6.1TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . .2574
53.6.2TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . .2575
53.6.3TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) . . . . .2579
53.6.4TIMx DMA/interrupt enable register (TIMx_DIER)(x = 1, 8) . . . . .2583
53.6.5TIMx status register (TIMx_SR)(x = 1, 8) . . . . .2584
53.6.6TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . .2587
53.6.7TIMx capture/compare mode register 1 (TIMx_CCMR1)
(x = 1, 8) . . . . .		2588
53.6.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . .		2590
53.6.9TIMx capture/compare mode register 2 (TIMx_CCMR2)
(x = 1, 8) . . . . .		2593
53.6.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . .		2594
53.6.11TIMx capture/compare enable register (TIMx_CCER)(x = 1, 8) . . . . .2597
53.6.12TIMx counter (TIMx_CNT)(x = 1, 8) . . . . .2601
53.6.13TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . .2601
53.6.14TIMx autoreload register (TIMx_ARR)(x = 1, 8) . . . . .2602
53.6.15TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . .2602
53.6.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 1, 8) . . . . .2603
53.6.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 1, 8) . . . . .2603
53.6.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 1, 8) . . . . .2604
53.6.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 1, 8) . . . . .2605
53.6.20TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) . . . . .2606
53.6.21TIMx capture/compare register 5 (TIMx_CCR5)(x = 1, 8) . . . . .2610
53.6.22TIMx capture/compare register 6 (TIMx_CCR6)(x = 1, 8) . . . . .2611
53.6.23TIMx capture/compare mode register 3 (TIMx_CCMR3)
(x = 1, 8) . . . . .		2612
53.6.24TIMx timer deadtime register 2 (TIMx_DTR2)(x = 1, 8) . . . . .2613
53.6.25TIMx timer encoder control register (TIMx_ECR)(x = 1, 8) . . . . .2614
53.6.26TIMx timer input selection register (TIMx_TISEL)(x = 1, 8) . . . . .2615
53.6.27TIMx alternate function option register 1 (TIMx_AF1)(x = 1, 8) . . . . .2616
53.6.28TIMx alternate function register 2 (TIMx_AF2)(x = 1, 8) . . . . .2619
53.6.29TIMx DMA control register (TIMx_DCR)(x = 1, 8) . . . . .2621
53.6.30TIMx DMA address for full transfer (TIMx_DMAR)(x = 1, 8) . . . . .2623
53.6.31TIMx register map . . . . .2623
54General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . .2626
54.1TIM2/TIM3/TIM4/TIM5 introduction . . . . .2626
54.2TIM2/TIM3/TIM4/TIM5 main features . . . . .2626
54.3TIM2/TIM3/TIM4/TIM5 implementation . . . . .2627
54.4TIM2/TIM3/TIM4/TIM5 functional description . . . . .2628
54.4.1Block diagram . . . . .2628
54.4.2TIM2/TIM3/TIM4/TIM5 pins and internal signals . . . . .2629
54.4.3Time-base unit . . . . .2632
54.4.4Counter modes . . . . .2634
54.4.5Clock selection . . . . .2646
54.4.6Capture/compare channels . . . . .2650
54.4.7Input capture mode . . . . .2652
54.4.8PWM input mode . . . . .2653
54.4.9Forced output mode . . . . .2654
54.4.10Output compare mode . . . . .2654
54.4.11PWM mode . . . . .2656
54.4.12Asymmetric PWM mode . . . . .2664
54.4.13Combined PWM mode . . . . .2665
54.4.14Clearing the tim_ocxref signal on an external event . . . . .2666
54.4.15One-pulse mode . . . . .2668
54.4.16Retriggerable one-pulse mode . . . . .2669
54.4.17Pulse on compare mode . . . . .2670
54.4.18Encoder interface mode . . . . .2672
54.4.19Direction bit output . . . . .2690
54.4.20UIF bit remapping . . . . .2691
54.4.21Timer input XOR function . . . . .2691
54.4.22Timers and external trigger synchronization . . . . .2691
54.4.23Timer synchronization . . . . .2695
54.4.24ADC triggers . . . . .2700
54.4.25ADC synchronization . . . . .2701
54.4.26DMA burst mode . . . . .2702
54.4.27TIM2/TIM3/TIM4/TIM5 DMA requests . . . . .2703
54.4.28Debug mode . . . . .2703
54.4.29TIM2/TIM3/TIM4/TIM5 low-power modes . . . . .2703
54.4.30TIM2/TIM3/TIM4/TIM5 interrupts . . . . .2704
54.5TIM2/TIM3/TIM4/TIM5 registers . . . . .2705
54.5.1TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . .2705
54.5.2TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . .2706
54.5.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . .2708
54.5.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . .2712
54.5.5TIMx status register (TIMx_SR)(x = 2 to 5) . . . . .2713
54.5.6TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . .2715
54.5.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) . . . . .2716
54.5.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 2 to 5) . . . . .		2718
54.5.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) . . . . .2720
54.5.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 2 to 5) . . . . .		2721
54.5.11TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5) . . . . .2724
54.5.12TIMx counter (TIMx_CNT)(x = 2 to 5) . . . . .2726
54.5.13TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . .2726
54.5.14TIMx autoreload register (TIMx_ARR)(x = 2 to 5) . . . . .2727
54.5.15TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) . . . . .2727
54.5.16TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) . . . . .2728
54.5.17TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) . . . . .2729
54.5.18TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) . . . . .2730
54.5.19TIMx timer encoder control register (TIMx_ECR)(x = 2 to 5) . . . . .2731
54.5.20TIMx timer input selection register (TIMx_TISEL)(x = 2 to 5) . . . . .2732
54.5.21TIMx alternate function register 1 (TIMx_AF1)(x = 2 to 5) . . . . .2733
54.5.22TIMx alternate function register 2 (TIMx_AF2)(x = 2 to 5) . . . . .2734
54.5.23TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . .2735
54.5.24TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . .2736
54.5.25TIMx register map . . . . .2737
55Basic timers (TIM6/TIM7/TIM18) . . . . .2740
55.1TIM6/TIM7/TIM18 introduction . . . . .2740
55.2TIM6/TIM7/TIM18 main features . . . . .2740
55.3TIM6/TIM7/TIM18 functional description . . . . .2740
55.3.1TIM6/TIM7/TIM18 block diagram . . . . .2740
55.3.2TIM6/TIM7/TIM18 internal signals . . . . .2741
55.3.3TIM6/TIM7/TIM18 clocks . . . . .2741
55.3.4Time-base unit . . . . .2742
55.3.5Counting mode . . . . .2744
55.3.6UIF bit remapping . . . . .2750
55.3.7ADC triggers . . . . .2751
55.3.8ADC synchronization . . . . .2751
55.3.9TIM6/TIM7/TIM18 DMA requests . . . . .2752
55.3.10Debug mode . . . . .2752
55.3.11TIM6/TIM7/TIM18 low-power modes . . . . .2752
55.3.12TIM6/TIM7/TIM18 interrupts . . . . .2752
55.4TIM6/TIM7/TIM18 registers . . . . .2753
55.4.1TIMx control register 1 (TIMx_CR1)(x = 6, 7, 18) . . . . .2753
55.4.2TIMx control register 2 (TIMx_CR2)(x = 6, 7, 18) . . . . .2755
55.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6, 7, 18) . . . .2755
55.4.4TIMx status register (TIMx_SR)(x = 6, 7, 18) . . . . .2756
55.4.5TIMx event generation register (TIMx_EGR)(x = 6, 7, 18) . . . . .2756
55.4.6TIMx counter (TIMx_CNT)(x = 6, 7, 18) . . . . .2757
55.4.7TIMx prescaler (TIMx_PSC)(x = 6, 7, 18) . . . . .2757
55.4.8TIMx autoreload register (TIMx_ARR)(x = 6, 7, 18) . . . . .2758
55.4.9TIMx register map . . . . .2759
56General-purpose timers (TIM9/TIM10/TIM11/TIM12/TIM13/TIM14) .2760
56.1TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 introduction . . . . .2760
56.2TIM9/TIM12 main features . . . . .2760
56.3TIM10/TIM11/TIM13/TIM14 main features . . . . .2761
56.4TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 functional description . . . . .2762
56.4.1Block diagram . . . . .2762
56.4.2TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 pins and internal signals . .2763
56.4.3Time-base unit . . . . .2765
56.4.4Counter modes . . . . .2767
56.4.5Clock selection . . . . .2770
56.4.6Capture/compare channels . . . . .2772
56.4.7Input capture mode . . . . .2774
56.4.8PWM input mode (TIM9/TIM12 only) . . . . .2775
56.4.9Forced output mode . . . . .2776
56.4.10Output compare mode . . . . .2777
56.4.11PWM mode . . . . .2778
56.4.12Combined PWM mode (TIM9/TIM12 only) . . . . .2783
56.4.13One-pulse mode . . . . .2784
56.4.14Retriggerable one pulse mode (TIM9/TIM12 only) . . . . .2786
56.4.15UIF bit remapping . . . . .2787
56.4.16Timer input XOR function . . . . .2787
56.4.17TIM9/TIM12 external trigger synchronization . . . . .2787
56.4.18Slave mode – combined reset + trigger mode . . . . .2790
56.4.19Slave mode – combined reset + gated mode . . . . .2790
56.4.20Timer synchronization (TIM9/TIM12 only) . . . . .2790
56.4.21Using timer output as trigger for other timers
(TIM10/TIM11/TIM13/TIM14 only) . . . . .		2790
56.4.22ADC triggers (TIM9/TIM12 only) . . . . .2790
56.4.23ADC synchronization (TIM9/TIM12 only) . . . . .2791
56.4.24Debug mode .....2792
56.5TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 low-power modes .....2792
56.6TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 interrupts .....2792
56.7TIM9/TIM12 registers .....2792
56.7.1TIMx control register 1 (TIMx_CR1)(x = 9, 12) .....2793
56.7.2TIM12 control register 2 (TIMx_CR2)(x = 9, 12) .....2794
56.7.3TIMx slave mode control register (TIMx_SMCR)(x = 9, 12) .....2795
56.7.4TIMx interrupt enable register (TIMx_DIER)(x = 9, 12) .....2797
56.7.5TIMx status register (TIMx_SR)(x = 9, 12) .....2798
56.7.6TIMx event generation register (TIMx_EGR)(x = 9, 12) .....2799
56.7.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 9, 12) .2800
56.7.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 9, 12) .....		2801
56.7.9TIMx capture/compare enable register (TIMx_CCER)(x = 9, 12) . . .2804
56.7.10TIMx counter (TIMx_CNT)(x = 9, 12) .....2805
56.7.11TIMx prescaler (TIMx_PSC)(x = 9, 12) .....2806
56.7.12TIMx autoreload register (TIMx_ARR)(x = 9, 12) .....2806
56.7.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 9, 12) .....2807
56.7.14TIMx capture/compare register 2 (TIMx_CCR2)(x = 9, 12) .....2807
56.7.15TIMx timer input selection register (TIMx_TISEL)(x = 9, 12) .....2808
56.7.16TIM9/TIM12 register map .....2809
56.8TIM10/TIM11/TIM13/TIM14 registers .....2811
56.8.1TIMx control register 1 (TIMx_CR1)(x = 10, 11, 13, 14) .....2811
56.8.2TIMx interrupt enable register (TIMx_DIER)(x = 10, 11, 13, 14) . . .2812
56.8.3TIMx status register (TIMx_SR)(x = 10, 11, 13, 14) .....2812
56.8.4TIMx event generation register (TIMx_EGR)(x = 10, 11, 13, 14) . . .2813
56.8.5TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 10, 11, 13, 14) .....		2814
56.8.6TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 10, 11, 13, 14) .....		2815
56.8.7TIMx capture/compare enable register
(TIMx_CCER)(x = 10, 11, 13, 14) .....		2817
56.8.8TIMx counter (TIMx_CNT)(x = 10, 11, 13, 14) .....2818
56.8.9TIMx prescaler (TIMx_PSC)(x = 10, 11, 13, 14) .....2819
56.8.10TIMx autoreload register (TIMx_ARR)(x = 10, 11, 13, 14) .....2819
56.8.11TIMx capture/compare register 1 (TIMx_CCR1)(x = 10, 11, 13, 14) .2820
56.8.12TIMx timer input selection register (TIMx_TISEL)(x = 10, 11, 13, 14)2820
56.8.13TIM10/TIM11/TIM13/TIM14 register map .....2821
57General purpose timers (TIM15/TIM16/TIM17) . . . . .2823
57.1TIM15/TIM16/TIM17 introduction . . . . .2823
57.2TIM15 main features . . . . .2823
57.3TIM16/TIM17 main features . . . . .2824
57.4TIM15/TIM16/TIM17 functional description . . . . .2825
57.4.1Block diagram . . . . .2825
57.4.2TIM15/TIM16/TIM17 pins and internal signals . . . . .2826
57.4.3Time-base unit . . . . .2829
57.4.4Counter modes . . . . .2831
57.4.5Repetition counter . . . . .2835
57.4.6Clock selection . . . . .2836
57.4.7Capture/compare channels . . . . .2838
57.4.8Input capture mode . . . . .2840
57.4.9PWM input mode (only for TIM15) . . . . .2842
57.4.10Forced output mode . . . . .2843
57.4.11Output compare mode . . . . .2843
57.4.12PWM mode . . . . .2845
57.4.13Combined PWM mode (TIM15 only) . . . . .2850
57.4.14Complementary outputs and dead-time insertion . . . . .2851
57.4.15Using the break function . . . . .2854
57.4.16Bidirectional break input . . . . .2858
57.4.17Clearing the tim_ocxref signal on an external event . . . . .2859
57.4.186-step PWM generation . . . . .2860
57.4.19One-pulse mode . . . . .2862
57.4.20Retriggerable one pulse mode (TIM15 only) . . . . .2863
57.4.21UIF bit remapping . . . . .2864
57.4.22Timer input XOR function (TIM15 only) . . . . .2864
57.4.23External trigger synchronization (TIM15 only) . . . . .2864
57.4.24Slave mode – combined reset + trigger mode (TIM15 only) . . . . .2867
57.4.25Slave mode – combined reset + gated mode (TIM15 only) . . . . .2867
57.4.26Timer synchronization (TIM15 only) . . . . .2868
57.4.27Using timer output as trigger for other timers (TIM16/TIM17 only) . . . . .2868
57.4.28ADC triggers (TIM15 only) . . . . .2868
57.4.29ADC synchronization (TIM15 only) . . . . .2869
57.4.30DMA burst mode . . . . .2869
57.4.31TIM15/TIM16/TIM17 DMA requests . . . . .2870
57.4.32Debug mode . . . . .2871
57.5TIM15/TIM16/TIM17 low-power modes . . . . .2871
57.6TIM15/TIM16/TIM17 interrupts . . . . .2871
57.7TIM15 registers . . . . .2872
57.7.1TIM15 control register 1 (TIM15_CR1) . . . . .2872
57.7.2TIM15 control register 2 (TIM15_CR2) . . . . .2873
57.7.3TIM15 slave mode control register (TIM15_SMCR) . . . . .2875
57.7.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .2877
57.7.5TIM15 status register (TIM15_SR) . . . . .2878
57.7.6TIM15 event generation register (TIM15_EGR) . . . . .2880
57.7.7TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .2881
57.7.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		2883
57.7.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .2885
57.7.10TIM15 counter (TIM15_CNT) . . . . .2888
57.7.11TIM15 prescaler (TIM15_PSC) . . . . .2888
57.7.12TIM15 autoreload register (TIM15_ARR) . . . . .2889
57.7.13TIM15 repetition counter register (TIM15_RCR) . . . . .2889
57.7.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .2890
57.7.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .2891
57.7.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .2891
57.7.17TIM15 timer deadtime register 2 (TIM15_DTR2) . . . . .2894
57.7.18TIM15 input selection register (TIM15_TISEL) . . . . .2895
57.7.19TIM15 alternate function register 1 (TIM15_AF1) . . . . .2896
57.7.20TIM15 alternate function register 2 (TIM15_AF2) . . . . .2898
57.7.21TIM15 DMA control register (TIM15_DCR) . . . . .2899
57.7.22TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .2900
57.7.23TIM15 register map . . . . .2900
57.8TIM16/TIM17 registers . . . . .2903
57.8.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .2903
57.8.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .2904
57.8.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .2905
57.8.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .2906
57.8.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .2907
57.8.6TIMx capture/compare mode register 1 (TIMx_CCMR1)
(x = 16 to 17) . . . . .		2908

57.8.7 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . . 2909

57.8.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . 2911

57.8.9 TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . . 2914

57.8.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . . 2914

57.8.11 TIMx auto-reautoreload register (TIMx_ARR)(x = 16 to 17) . . . . . 2915

57.8.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . . 2915

57.8.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . . 2916

57.8.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . . 2917

57.8.15 TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16 to 17) . . . . . 2920

57.8.16 TIMx input selection register (TIMx_TISEL)(x = 16 to 17) . . . . . 2921

57.8.17 TIMx alternate function register 1 (TIMx_AF1)(x = 16 to 17) . . . . . 2921

57.8.18 TIMx alternate function register 2 (TIMx_AF2)(x = 16 to 17) . . . . . 2924

57.8.19 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . . 2924

57.8.20 TIM16/TIM17 DMA address for full transfer
(TIMx_DMAR)(x = 16 to 17) . . . . . 2925

57.8.21 TIM16/TIM17 register map . . . . . 2927

58 Low-power timer (LPTIM) . . . . . 2929

58.1 LPTIM introduction . . . . . 2929

58.2 LPTIM main features . . . . . 2929

58.3 LPTIM implementation . . . . . 2930

58.4 LPTIM functional description . . . . . 2931

58.4.1 LPTIM block diagram . . . . . 2931

58.4.2 LPTIM pins and internal signals . . . . . 2932

58.4.3 LPTIM input and trigger mapping . . . . . 2934

58.4.4 LPTIM reset and clocks . . . . . 2935

58.4.5 Glitch filter . . . . . 2936

58.4.6 Prescaler . . . . . 2937

58.4.7 Trigger multiplexer . . . . . 2937

58.4.8 Operating mode . . . . . 2938

58.4.9 Timeout function . . . . . 2940

58.4.10 Waveform generation . . . . . 2940

58.4.11 Register update . . . . . 2941

58.4.12 Counter mode . . . . . 2942

58.4.13 Timer enable . . . . . 2942

58.4.14 Timer counter reset . . . . . 2943

58.4.15Encoder mode . . . . .2943
58.4.16Repetition counter . . . . .2945
58.4.17Capture/compare channels . . . . .2946
58.4.18Input capture mode . . . . .2947
58.4.19PWM mode . . . . .2949
58.4.20DMA requests . . . . .2951
58.4.21Debug mode . . . . .2952
58.5LPTIM low-power modes . . . . .2952
58.6LPTIM interrupts . . . . .2952
58.7LPTIM registers . . . . .2953
58.7.1LPTIMx interrupt and status register (LPTIMx_ISR)(x = 4 to 5) . . . . .2954
58.7.2LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1 to 3) . . . . .		2955
58.7.3LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1 to 3) . . . . .		2957
58.7.4LPTIMx interrupt clear register (LPTIMx_ICR)(x = 4 to 5) . . . . .2959
58.7.5LPTIMx interrupt clear register [alternate] (LPTIMx_ICR)
(x = 1 to 3) . . . . .		2960
58.7.6LPTIMx interrupt clear register [alternate] (LPTIMx_ICR)
(x = 1 to 3) . . . . .		2961
58.7.7LPTIMx interrupt enable register (LPTIMx_DIER)(x = 4 to 5) . . . . .2962
58.7.8LPTIMx interrupt enable register [alternate] (LPTIMx_DIER)
(x = 1 to 3) . . . . .		2964
58.7.9LPTIMx interrupt enable register [alternate] (LPTIMx_DIER)
(x = 1 to 3) . . . . .		2965
58.7.10LPTIM configuration register (LPTIM_CFGGR) . . . . .2967
58.7.11LPTIM control register (LPTIM_CR) . . . . .2970
58.7.12LPTIM compare register 1 (LPTIM_CCR1) . . . . .2971
58.7.13LPTIM autoreload register (LPTIM_ARR) . . . . .2972
58.7.14LPTIM counter register (LPTIM_CNT) . . . . .2972
58.7.15LPTIM configuration register 2 (LPTIM_CFGGR2) . . . . .2973
58.7.16LPTIM repetition register (LPTIM_RCR) . . . . .2974
58.7.17LPTIM capture/compare mode register 1 (LPTIM_CCMR1) . . . . .2974
58.7.18LPTIM compare register 2 (LPTIM_CCR2) . . . . .2977
58.7.19LPTIM register map . . . . .2977
59Independent watchdog (IWDG) . . . . .2980
59.1IWDG introduction . . . . .2980
60.6.3WWDG status register (WWDG_SR) .....3002
60.6.4WWDG register map .....3002
61Real-time clock (RTC) .....3003
61.1RTC introduction .....3003
61.2RTC main features .....3003
61.3RTC functional description .....3004
61.3.1RTC block diagram .....3004
61.3.2RTC pins and internal signals .....3006
61.3.3GPIOs controlled by the RTC and TAMP .....3007
61.3.4RTC secure protection modes .....3010
61.3.5RTC privilege protection modes .....3011
61.3.6Clock and prescalers .....3012
61.3.7Real-time clock and calendar .....3013
61.3.8Calendar ultra-low power mode .....3014
61.3.9Programmable alarms .....3014
61.3.10Periodic auto-wake-up .....3014
61.3.11RTC initialization and configuration .....3015
61.3.12Reading the calendar .....3018
61.3.13Resetting the RTC .....3019
61.3.14RTC synchronization .....3020
61.3.15RTC reference clock detection .....3020
61.3.16RTC smooth digital calibration .....3021
61.3.17Timestamp function .....3023
61.3.18Calibration clock output .....3024
61.3.19Tamper and alarm output .....3024
61.4RTC low-power modes .....3025
61.5RTC interrupts .....3025
61.6RTC registers .....3027
61.6.1RTC time register (RTC_TR) .....3027
61.6.2RTC date register (RTC_DR) .....3028
61.6.3RTC subsecond register (RTC_SSR) .....3029
61.6.4RTC initialization control and status register (RTC_ICSR) .....3030
61.6.5RTC prescaler register (RTC_PRER) .....3032
61.6.6RTC wake-up timer register (RTC_WUTR) .....3033
61.6.7RTC control register (RTC_CR) .....3033

62 Tamper and backup registers (TAMP) . . . . . 3058

62.6TAMP registers . . . . .3076
62.6.1TAMP control register 1 (TAMP_CR1) . . . . .3076
62.6.2TAMP control register 2 (TAMP_CR2) . . . . .3077
62.6.3TAMP control register 3 (TAMP_CR3) . . . . .3080
62.6.4TAMP filter control register (TAMP_FLTCR) . . . . .3081
62.6.5TAMP active tamper control register 1 (TAMP_ATCR1) . . . . .3083
62.6.6TAMP active tamper seed register (TAMP_ATSEEDR) . . . . .3085
62.6.7TAMP active tamper output register (TAMP_ATOR) . . . . .3085
62.6.8TAMP active tamper control register 2 (TAMP_ATCR2) . . . . .3086
62.6.9TAMP secure configuration register (TAMP_SECCFGR) . . . . .3089
62.6.10TAMP privilege configuration register (TAMP_PRIVCFGR) . . . . .3090
62.6.11TAMP interrupt enable register (TAMP_IER) . . . . .3091
62.6.12TAMP status register (TAMP_SR) . . . . .3093
62.6.13TAMP nonsecure masked interrupt status register (TAMP_MISR) . . . . .3095
62.6.14TAMP secure masked interrupt status register (TAMP_SMISR) . . . . .3097
62.6.15TAMP status clear register (TAMP_SCR) . . . . .3098
62.6.16TAMP monotonic counter 1 register (TAMP_COUNT1R) . . . . .3100
62.6.17TAMP option register (TAMP_OR) . . . . .3100
62.6.18TAMP resources protection configuration register (TAMP_RPCFGR) . . . . .3101
62.6.19TAMP backup x register (TAMP_BKPxR) . . . . .3102
62.6.20TAMP register map . . . . .3103
63Inter-integrated circuit interface (I2C) . . . . .3105
63.1I2C introduction . . . . .3105
63.2I2C main features . . . . .3105
63.3I2C implementation . . . . .3106
63.4I2C functional description . . . . .3106
63.4.1I2C block diagram . . . . .3107
63.4.2I2C pins and internal signals . . . . .3107
63.4.3I2C clock requirements . . . . .3108
63.4.4I2C mode selection . . . . .3108
63.4.5I2C initialization . . . . .3109
63.4.6I2C reset . . . . .3113
63.4.7I2C data transfer . . . . .3114
63.4.8I2C target mode . . . . .3116
63.4.9I2C controller mode . . . . .3125
63.4.10I2C_TIMINGR register configuration examples . . . . .3136
63.4.11SMBus specific features . . . . .3138
63.4.12SMBus initialization . . . . .3140
63.4.13SMBus I2C_TIMEOUTR register configuration examples . . . . .3142
63.4.14SMBus target mode . . . . .3143
63.4.15SMBus controller mode . . . . .3146
63.4.16Wake-up from Stop mode on address match . . . . .3149
63.4.17Error conditions . . . . .3150
63.5I2C in low-power modes . . . . .3152
63.6I2C interrupts . . . . .3152
63.7I2C DMA requests . . . . .3153
63.7.1Transmission using DMA . . . . .3153
63.7.2Reception using DMA . . . . .3153
63.8I2C debug modes . . . . .3154
63.9I2C registers . . . . .3154
63.9.1I2C control register 1 (I2C_CR1) . . . . .3154
63.9.2I2C control register 2 (I2C_CR2) . . . . .3157
63.9.3I2C own address 1 register (I2C_OAR1) . . . . .3159
63.9.4I2C own address 2 register (I2C_OAR2) . . . . .3159
63.9.5I2C timing register (I2C_TIMINGR) . . . . .3160
63.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .3161
63.9.7I2C interrupt and status register (I2C_ISR) . . . . .3162
63.9.8I2C interrupt clear register (I2C_ICR) . . . . .3165
63.9.9I2C PEC register (I2C_PECR) . . . . .3166
63.9.10I2C receive data register (I2C_RXDR) . . . . .3166
63.9.11I2C transmit data register (I2C_TXDR) . . . . .3167
63.9.12I2C register map . . . . .3168
64Improved inter-integrated circuit (I3C) . . . . .3169
64.1I3C introduction . . . . .3169
64.2I3C main features . . . . .3169
64.3I3C implementation . . . . .3171
64.3.1I3C instantiation . . . . .3171
64.3.2I3C wake-up from low-power mode(s) . . . . .3171
64.3.3I3C FIFOs . . . . .3171
64.3.4I3C triggers . . . . .3171
64.3.5I3C interrupt(s) . . . . .3171
64.3.6I3C MIPI ® support . . . . .3173
64.4I3C block diagram . . . . .3174
64.5I3C pins and internal signals . . . . .3174
64.6I3C reset and clocks . . . . .3175
64.6.1I3C reset . . . . .3175
64.6.2I3C clocks and requirements . . . . .3175
64.7I3C peripheral state and programming . . . . .3177
64.7.1I3C peripheral state . . . . .3177
64.7.2I3C controller state and programming sequence . . . . .3178
64.7.3I3C target state and programming sequence . . . . .3182
64.8I3C registers and programming . . . . .3186
64.8.1I3C register set, as controller/target . . . . .3186
64.8.2I3C registers and fields use versus peripheral state, as controller . . . . .3187
64.8.3I3C registers and fields usage versus peripheral state, as target . . . . .3190
64.9I3C bus transfers and programming . . . . .3192
64.9.1I3C command set (CCC), as controller/target . . . . .3192
64.9.2I3C broadcast/direct CCC transfer (except ENTDAA, RSTACT),
as controller . . . . .		3196
64.9.3I3C broadcast ENTDAA CCC transfer, as controller . . . . .3198
64.9.4I3C broadcast/direct RSTACT CCC transfer, as controller . . . . .3198
64.9.5I3C broadcast/direct CCC transfer
(except ENTDAA, DEFTGTS, DEFGRPA), as target . . . . .		3200
64.9.6I3C broadcast ENTDAA CCC transfer, as target . . . . .3202
64.9.7I3C broadcast DEFTGTS CCC transfer, as target . . . . .3203
64.9.8I3C broadcast DEFGRPA CCC transfer, as target . . . . .3204
64.9.9I3C direct GETSTATUS CCC response, as target . . . . .3205
64.9.10I3C private read/write transfer, as controller . . . . .3206
64.9.11I3C private read/write transfer, as target . . . . .3207
64.9.12Legacy I2C read/write transfer, as controller . . . . .3208
64.9.13I3C IBI transfer, as controller/target . . . . .3209
64.9.14I3C hot-join request transfer, as controller/target . . . . .3211
64.9.15I3C controller-role request transfer, as controller/target . . . . .3212
64.10I3C FIFOs management, as controller . . . . .3213
64.10.1C-FIFO management, as controller . . . . .3213
64.10.2TX-FIFO management, as controller . . . . .3214
64.10.3RX-FIFO management, as controller . . . . .3217
64.10.4S-FIFO management, as controller . . . . .3219
64.11I3C FIFOs management, as target . . . . .3221
64.11.1RX-FIFO management, as target . . . . .3221
64.11.2TX-FIFO management, as target . . . . .3222
64.12I3C error management . . . . .3225
64.12.1Controller error management . . . . .3225
64.12.2Target error management . . . . .3227
64.13I3C wake-up from low-power mode(s) . . . . .3228
64.13.1Wake-up from Stop . . . . .3228
64.14I3C in low-power modes . . . . .3231
64.15I3C interrupts . . . . .3232
64.16I3C registers . . . . .3233
64.16.1I3C message control register (I3C_CR) . . . . .3233
64.16.2I3C message control register [alternate] (I3C_CR) . . . . .3235
64.16.3I3C configuration register (I3C_CFGGR) . . . . .3237
64.16.4I3C receive data byte register (I3C_RDR) . . . . .3242
64.16.5I3C receive data word register (I3C_RDWR) . . . . .3242
64.16.6I3C transmit data byte register (I3C_TDR) . . . . .3243
64.16.7I3C transmit data word register (I3C_TDWR) . . . . .3244
64.16.8I3C IBI payload data register (I3C_IBIDR) . . . . .3246
64.16.9I3C target transmit configuration register (I3C_TGTTDR) . . . . .3247
64.16.10I3C status register (I3C_SR) . . . . .3248
64.16.11I3C status error register (I3C_SER) . . . . .3249
64.16.12I3C received message register (I3C_RMR) . . . . .3251
64.16.13I3C event register (I3C_EVR) . . . . .3252
64.16.14I3C interrupt enable register (I3C_IER) . . . . .3256
64.16.15I3C clear event register (I3C_CEVR) . . . . .3258
64.16.16I3C own device characteristics register (I3C_DEVR0) . . . . .3260
64.16.17I3C device x characteristics register (I3C_DEVRx) . . . . .3262
64.16.18I3C maximum read length register (I3C_MAXRLR) . . . . .3264
64.16.19I3C maximum write length register (I3C_MAXWLR) . . . . .3265
64.16.20I3C timing register 0 (I3C_TIMINGR0) . . . . .3266
64.16.21I3C timing register 1 (I3C_TIMINGR1) . . . . .3267
64.16.22I3C timing register 2 (I3C_TIMINGR2) . . . . .3269
64.16.23I3C bus characteristics register (I3C_BCR) . . . . .3270
64.16.24I3C device characteristics register (I3C_DCR) . . . . .3271
64.16.25I3C get capability register (I3C_GETCAPR) . . . . .3272
64.16.26I3C controller-role capability register (I3C_CRCAPR) . . . . .3273
64.16.27I3C get max data speed register (I3C_GETMXDSR) . . . . .3274
64.16.28I3C extended provisioned ID register (I3C_EPIDR) . . . . .3276
64.16.29I3C register map . . . . .3277
65Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .3280
65.1USART introduction . . . . .3280
65.2USART main features . . . . .3280
65.3USART extended features . . . . .3281
65.4USART implementation . . . . .3281
65.5USART functional description . . . . .3283
65.5.1USART block diagram . . . . .3283
65.5.2USART pins and internal signals . . . . .3283
65.5.3USART clocks . . . . .3285
65.5.4USART character description . . . . .3285
65.5.5USART FIFOs and thresholds . . . . .3288
65.5.6USART transmitter . . . . .3288
65.5.7USART receiver . . . . .3291
65.5.8USART baud rate generation . . . . .3298
65.5.9Tolerance of the USART receiver to clock deviation . . . . .3300
65.5.10USART auto baud rate detection . . . . .3301
65.5.11USART multiprocessor communication . . . . .3303
65.5.12USART Modbus communication . . . . .3305
65.5.13USART parity control . . . . .3306
65.5.14USART LIN (local interconnection network) mode . . . . .3307
65.5.15USART synchronous mode . . . . .3309
65.5.16USART single-wire half-duplex communication . . . . .3313
65.5.17USART receiver timeout . . . . .3313
65.5.18USART smartcard mode . . . . .3314
65.5.19USART IrDA SIR ENDEC block . . . . .3318
65.5.20Continuous communication using USART and DMA . . . . .3321
65.5.21RS232 hardware flow control and RS485 driver enable . . . . .3323
65.5.22USART low-power management . . . . .3326
65.6USART in low-power modes . . . . .3329
65.7USART interrupts . . . . .3329
65.8USART registers . . . . .3332
65.8.1USART control register 1 (USART_CR1) . . . . .3332
65.8.2USART control register 1 [alternate] (USART_CR1) . . . . .3336
65.8.3USART control register 2 (USART_CR2) . . . . .3339
65.8.4USART control register 3 (USART_CR3) . . . . .3343
65.8.5USART control register 3 [alternate] (USART_CR3) . . . . .3347
65.8.6USART baud rate register (USART_BRR) . . . . .3350
65.8.7USART guard time and prescaler register (USART_GTPR) . . . . .3351
65.8.8USART receiver timeout register (USART_RTOR) . . . . .3352
65.8.9USART request register (USART_RQR) . . . . .3353
65.8.10USART interrupt and status register (USART_ISR) . . . . .3354
65.8.11USART interrupt and status register [alternate] (USART_ISR) . . . . .3360
65.8.12USART interrupt flag clear register (USART_ICR) . . . . .3365
65.8.13USART receive data register (USART_RDR) . . . . .3366
65.8.14USART transmit data register (USART_TDR) . . . . .3367
65.8.15USART prescaler register (USART_PRESC) . . . . .3367
65.8.16USART register map . . . . .3368
66Low-power universal asynchronous receiver transmitter (LPUART) . . . . .3370
66.1LPUART introduction . . . . .3370
66.2LPUART main features . . . . .3370
66.3LPUART implementation . . . . .3371
66.4LPUART functional description . . . . .3373
66.4.1LPUART block diagram . . . . .3373
66.4.2LPUART pins and internal signals . . . . .3374
66.4.3LPUART clocks . . . . .3375
66.4.4LPUART character description . . . . .3375
66.4.5LPUART FIFOs and thresholds . . . . .3377
66.4.6LPUART transmitter . . . . .3377
66.4.7LPUART receiver . . . . .3381
66.4.8LPUART baud rate generation . . . . .3385
66.4.9Tolerance of the LPUART receiver to clock deviation . . . . .3386
66.4.10LPUART multiprocessor communication . . . . .3387
66.4.11LPUART parity control . . . . .3389
66.4.12LPUART single-wire half-duplex communication . . . . .3390
66.4.13Continuous communication using DMA and LPUART . . . . .3390
66.4.14RS232 hardware flow control and RS485 driver enable . . . . .3393
66.4.15LPUART low-power management . . . . .3395
66.5LPUART in low-power modes . . . . .3398
66.6LPUART interrupts . . . . .3399
66.7LPUART registers . . . . .3400
66.7.1LPUART control register 1 (LPUART_CR1) . . . . .3400
66.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .3403
66.7.3LPUART control register 2 (LPUART_CR2) . . . . .3406
66.7.4LPUART control register 3 (LPUART_CR3) . . . . .3408
66.7.5LPUART control register 3 [alternate] (LPUART_CR3) . . . . .3411
66.7.6LPUART baud rate register (LPUART_BRR) . . . . .3413
66.7.7LPUART request register (LPUART_RQR) . . . . .3413
66.7.8LPUART interrupt and status register (LPUART_ISR) . . . . .3414
66.7.9LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .3419
66.7.10LPUART interrupt flag clear register (LPUART_ICR) . . . . .3422
66.7.11LPUART receive data register (LPUART_RDR) . . . . .3423
66.7.12LPUART transmit data register (LPUART_TDR) . . . . .3423
66.7.13LPUART prescaler register (LPUART_PRESC) . . . . .3424
66.7.14LPUART register map . . . . .3425
67Serial peripheral interface (SPI) . . . . .3427
67.1SPI introduction . . . . .3427
67.2SPI main features . . . . .3427
67.3SPI implementation . . . . .3428
67.4SPI functional description . . . . .3429
67.4.1SPI block diagram . . . . .3429
67.4.2SPI pins and internal signals . . . . .3430
67.4.3SPI communication general aspects . . . . .3431
67.4.4Communications between one master and one slave . . . . .3431
67.4.5Standard multislave communication . . . . .3434
67.4.6Multimaster communication . . . . .3437
67.4.7Slave select (NSS pin) management . . . . .3438
67.4.8Ready pin (RDY) management . . . . .3442
67.4.9Communication formats . . . . .3442
67.4.10Configuring the SPI . . . . .3444
67.4.11Enabling the SPI . . . . .3445
67.4.12SPI data transmission and reception procedures . . . . .3446
67.4.13Disabling the SPI . . . . .3450
67.4.14Communication using DMA (direct memory addressing) . . . . .3451
67.5SPI specific modes and control . . . . .3453
67.5.1TI mode . . . . .3453
67.5.2SPI error flags . . . . .3453
67.5.3CRC computation . . . . .3457
67.6SPI in low-power modes . . . . .3458
67.7SPI interrupts . . . . .3458
67.8I2S main features . . . . .3460
67.9I2S functional description . . . . .3460
67.9.1I2S general description . . . . .3460
67.9.2Pin sharing with SPI function . . . . .3461
67.9.3Bitfields usable in I2S/PCM mode . . . . .3461
67.9.4Slave and master modes . . . . .3462
67.9.5Supported audio protocols . . . . .3462
67.9.6Additional serial interface flexibility . . . . .3468
67.9.7Startup sequence . . . . .3470
67.9.8Stop sequence . . . . .3472
67.9.9Clock generator . . . . .3473
67.9.10Internal FIFOs . . . . .3475
67.9.11FIFO status flags . . . . .3476
67.9.12Handling of underrun situation . . . . .3476
67.9.13Handling of overrun situation . . . . .3477
67.9.14Frame error detection . . . . .3478
67.9.15DMA interface . . . . .3480
67.9.16Programing examples . . . . .3480
67.10I2S interrupts . . . . .3482
67.11SPI/I2S registers . . . . .3483
67.11.1SPI/I2S control register 1 (SPI_CR1) . . . . .3483
67.11.2SPI/I2S control register 2 (SPI_CR2) . . . . .3485
67.11.3SPI/I2S configuration register 1 (SPI_CFG1) . . . . .3485
67.11.4SPI/I2S configuration register 2 (SPI_CFG2) . . . . .3488
67.11.5SPI/I2S interrupt enable register (SPI_IER) . . . . .3490
67.11.6SPI/I2S status register (SPI_SR) . . . . .3491
67.11.7SPI/I2S interrupt/status flags clear register (SPI_IFCR) . . . . .3494
67.11.8SPI/I2S transmit data register (SPI_TXDR) . . . . .3495
67.11.9SPI/I2S receive data register (SPI_RXDR) . . . . .3495
67.11.10SPI/I2S polynomial register (SPI_CRCPOLY) . . . . .3496
67.11.11SPI/I2S transmitter CRC register (SPI_TXCRC) . . . . .3496
67.11.12SPI/I2S receiver CRC register (SPI_RXCRC) . . . . .3497
67.11.13SPI/I2S underrun data register (SPI_UDRDR) . . . . .3498
67.11.14SPI/I2S configuration register (SPI_I2SCFGGR) . . . . .3498
67.11.15SPI/I2S register map . . . . .3500
68Serial audio interface (SAI) . . . . .3502
68.1SAI introduction . . . . .3502
68.2SAI main features . . . . .3502
68.3SAI implementation . . . . .3503
68.4SAI functional description . . . . .3504
68.4.1SAI block diagram . . . . .3504
68.4.2SAI pins and internal signals . . . . .3505
68.4.3Main SAI modes . . . . .3506
68.4.4SAI synchronization mode . . . . .3507
68.4.5Audio data size . . . . .3508
68.4.6Frame synchronization . . . . .3508
68.4.7Slot configuration . . . . .3511
68.4.8SAI clock generator . . . . .3513
68.4.9Internal FIFOs . . . . .3516
68.4.10PDM interface . . . . .3518
68.4.11AC'97 link controller . . . . .3526
68.4.12SPDIF output . . . . .3528
68.4.13Specific features . . . . .3531
68.4.14Error flags . . . . .3535
68.4.15Disabling the SAI . . . . .3538
68.4.16SAI DMA interface . . . . .3538
68.5SAI interrupts . . . . .3539
68.6SAI registers . . . . .3541
68.6.1SAI global configuration register (SAI_GCR) . . . . .3541
68.6.2SAI configuration register 1 (SAI_ACR1) . . . . .3541
68.6.3SAI configuration register 2 (SAI_ACR2) . . . . .3544
68.6.4SAI frame configuration register (SAI_AFRCR) . . . . .3546

68.6.5 SAI slot register (SAI_ASLOTR) . . . . . 3547

68.6.6 SAI interrupt mask register (SAI_AIM) . . . . . 3548

68.6.7 SAI status register (SAI_ASR) . . . . . 3550

68.6.8 SAI clear flag register (SAI_ACLRFR) . . . . . 3552

68.6.9 SAI data register (SAI_ADR) . . . . . 3553

68.6.10 SAI configuration register 1 (SAI_BCR1) . . . . . 3553

68.6.11 SAI configuration register 2 (SAI_BCR2) . . . . . 3556

68.6.12 SAI frame configuration register (SAI_BFRCR) . . . . . 3558

68.6.13 SAI slot register (SAI_BSLOTR) . . . . . 3559

68.6.14 SAI interrupt mask register (SAI_BIM) . . . . . 3560

68.6.15 SAI status register (SAI_BSR) . . . . . 3561

68.6.16 SAI clear flag register (SAI_BCLRFR) . . . . . 3563

68.6.17 SAI data register (SAI_BDR) . . . . . 3564

68.6.18 SAI PDM control register (SAI_PDMCR) . . . . . 3565

68.6.19 SAI PDM delay register (SAI_PDMPLY) . . . . . 3566

68.6.20 SAI register map . . . . . 3568

69 SPDIF receiver interface (SPDIFRX) . . . . . 3570

69.1 SPDIFRX interface introduction . . . . . 3570

69.2 SPDIFRX main features . . . . . 3570

69.3 SPDIFRX functional description . . . . . 3570

69.3.1 SPDIFRX pins and internal signals . . . . . 3571

69.3.2 S/PDIF protocol (IEC-60958) . . . . . 3572

69.3.3 SPDIFRX decoder (SPDIFRX_DC) . . . . . 3574

69.3.4 SPDIFRX tolerance to clock deviation . . . . . 3578

69.3.5 SPDIFRX synchronization . . . . . 3578

69.3.6 SPDIFRX handling . . . . . 3580

69.3.7 Data reception management . . . . . 3582

69.3.8 Dedicated control flow . . . . . 3584

69.3.9 Reception errors . . . . . 3585

69.3.10 Clocking strategy . . . . . 3587

69.3.11 Symbol clock generation . . . . . 3587

69.3.12 DMA interface . . . . . 3589

69.3.13 Interrupt generation . . . . . 3590

69.3.14 Register protection . . . . . 3591

69.4 Programming procedures . . . . . 3591

69.4.1 Initialization phase . . . . . 3592

69.4.2Handling of interrupts coming from SPDIFRX3593
69.4.3Handling of interrupts coming from DMA3593
69.5SPDIFRX interface registers3594
69.5.1SPDIFRX control register (SPDIFRX_CR)3594
69.5.2SPDIFRX interrupt mask register (SPDIFRX_IMR)3596
69.5.3SPDIFRX status register (SPDIFRX_SR)3597
69.5.4SPDIFRX interrupt flag clear register (SPDIFRX_IFCR)3599
69.5.5SPDIFRX data input register (SPDIFRX_FMT0_DR)3600
69.5.6SPDIFRX data input register (SPDIFRX_FMT1_DR)3600
69.5.7SPDIFRX data input register (SPDIFRX_FMT2_DR)3601
69.5.8SPDIFRX channel status register (SPDIFRX_CSR)3602
69.5.9SPDIFRX debug information register (SPDIFRX_DIR)3602
69.5.10SPDIFRX interface register map3603
70Management data input/output (MDIOS)3604
70.1MDIOS introduction3604
70.2MDIOS main features3604
70.3MDIOS functional description3605
70.3.1MDIOS block diagram3605
70.3.2MDIOS pins and internal signals3605
70.3.3MDIOS protocol3605
70.3.4MDIOS enabling and disabling3606
70.3.5MDIOS data3607
70.3.6MDIOS APB frequency3608
70.3.7Write/read flags and interrupts3608
70.3.8MDIOS error management3609
70.3.9MDIOS in Stop mode3610
70.3.10MDIOS interrupts3610
70.4MDIOS registers3610
70.4.1MDIOS configuration register (MDIOS_CR)3610
70.4.2MDIOS write flag register (MDIOS_WRFR)3611
70.4.3MDIOS clear write flag register (MDIOS_CWRFR)3612
70.4.4MDIOS read flag register (MDIOS_RDFR)3612
70.4.5MDIOS clear read flag register (MDIOS_CRDFR)3613
70.4.6MDIOS status register (MDIOS_SR)3613
70.4.7MDIOS clear flag register (MDIOS_CLRFR)3614
70.4.8MDIOS input data register x (MDIOS_DINRx)3614
71.5.4FDCAN test register (FDCAN_TEST) . . . . .3683
71.5.5FDCAN RAM watchdog register (FDCAN_RWD) . . . . .3684
71.5.6FDCAN CC control register (FDCAN_CCCR) . . . . .3685
71.5.7FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . . .3687
71.5.8FDCAN timestamp counter configuration register (FDCAN_TSCC) . .3688
71.5.9FDCAN timestamp counter value register (FDCAN_TSCV) . . . . .3688
71.5.10FDCAN timeout counter configuration register (FDCAN_TOCC) . . .3689
71.5.11FDCAN timeout counter value register (FDCAN_TOCV) . . . . .3690
71.5.12FDCAN error counter register (FDCAN_ECR) . . . . .3690
71.5.13FDCAN protocol status register (FDCAN_PSR) . . . . .3691
71.5.14FDCAN transmitter delay compensation register (FDCAN_TDCR) . .3693
71.5.15FDCAN interrupt register (FDCAN_IR) . . . . .3693
71.5.16FDCAN interrupt enable register (FDCAN_IE) . . . . .3696
71.5.17FDCAN interrupt line select register (FDCAN_ILS) . . . . .3698
71.5.18FDCAN interrupt line enable register (FDCAN_ILE) . . . . .3699
71.5.19FDCAN global filter configuration register (FDCAN_GFC) . . . . .3700
71.5.20FDCAN standard ID filter configuration register (FDCAN_SIDFC) . .3701
71.5.21FDCAN extended ID filter configuration register (FDCAN_XIDFC) . .3701
71.5.22FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . .3702
71.5.23FDCAN high priority message status register (FDCAN_HPMS) . . . .3703
71.5.24FDCAN new data 1 register (FDCAN_NDAT1) . . . . .3703
71.5.25FDCAN new data 2 register (FDCAN_NDAT2) . . . . .3704
71.5.26FDCAN Rx FIFO 0 configuration register (FDCAN_RXF0C) . . . . .3704
71.5.27FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . .3705
71.5.28FDCAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . .3706
71.5.29FDCAN Rx buffer configuration register (FDCAN_RXBC) . . . . .3706
71.5.30FDCAN Rx FIFO 1 configuration register (FDCAN_RXF1C) . . . . .3707
71.5.31FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . .3708
71.5.32FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . .3709
71.5.33FDCAN Rx buffer element size configuration register
(FDCAN_RXESC) . . . . .		3709
71.5.34FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . .3710
71.5.35FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . .3711
71.5.36FDCAN Tx buffer element size configuration register
(FDCAN_TXESC) . . . . .		3712
71.5.37FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . .3712
71.5.38FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . .3713
71.5.39FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . .3714
71.5.40FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO)3714
71.5.41FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . . .3715
71.5.42FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . .		3715
71.5.43FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_TXBCIE) . . . . .		3716
71.5.44FDCAN Tx event FIFO configuration register (FDCAN_TXEFC) . . .3716
71.5.45FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . .3717
71.5.46FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . .3718
71.5.47FDCAN register map . . . . .3718
71.6TT CAN registers . . . . .3722
71.6.1FDCAN TT trigger memory configuration register
(FDCAN_TTTMC) . . . . .		3722
71.6.2FDCAN TT reference message configuration register
(FDCAN_TTRMC) . . . . .		3722
71.6.3FDCAN TT operation configuration register (FDCAN_TTOCF) . . . . .3723
71.6.4FDCAN TT matrix limits register (FDCAN_TTMLM) . . . . .3725
71.6.5FDCAN TUR configuration register (FDCAN_TURCF) . . . . .3726
71.6.6FDCAN TT operation control register (FDCAN_TTOCN) . . . . .3727
71.6.7FDCAN TT global time preset register (FDCAN_TTGTP) . . . . .3729
71.6.8FDCAN TT time mark register (FDCAN_TTTMK) . . . . .3729
71.6.9FDCAN TT interrupt register (FDCAN_TTIR) . . . . .3730
71.6.10FDCAN TT interrupt enable register (FDCAN_TTIE) . . . . .3732
71.6.11FDCAN TT interrupt line select register (FDCAN_TTILS) . . . . .3734
71.6.12FDCAN TT operation status register (FDCAN_TTOST) . . . . .3735
71.6.13FDCAN TUR numerator actual register (FDCAN_TURNA) . . . . .3737
71.6.14FDCAN TT local and global time register (FDCAN_TTLGT) . . . . .3738
71.6.15FDCAN TT cycle time and count register (FDCAN_TTCTC) . . . . .3738
71.6.16FDCAN TT capture time register (FDCAN_TTCPT) . . . . .3739
71.6.17FDCAN TT cycle sync mark register (FDCAN_TTCSM) . . . . .3739
71.6.18FDCAN TT trigger select register (FDCAN_TTTS) . . . . .3740
71.6.19FDCAN TT register map . . . . .3740
71.7CCU registers . . . . .3742
71.7.1Clock calibration unit core release register (FDCAN_CCU_CREL) . . .3742
71.7.2Calibration configuration register (FDCAN_CCU_CCFG) . . . . .3742
71.7.3Calibration status register (FDCAN_CCU_CSTAT) . . . . .3744
71.7.4Calibration watchdog register (FDCAN_CCU_CWD) . . . . .3744
71.7.5Clock calibration unit interrupt register (FDCAN_CCU_IR) . . . . .3745
71.7.6Clock calibration unit interrupt enable register (FDCAN_CCU_IE) ..3746
71.7.7CCU register map .....3746
72USB subsystem (USBSS) .....3748
72.1Overview .....3748
72.2USB2 OTG high-speed Port 1 .....3748
72.2.1USB2 OTG high-speed Port 1 main features .....3748
72.2.2USB2 OTG high-speed Port 1 functional description .....3749
72.2.3USB2 OTG high-speed Port 1 interrupts .....3751
72.2.4Battery charging .....3751
72.2.5ID management .....3752
72.2.6VBUS detection .....3752
72.3USB2 OTG high-speed Port 2 .....3752
72.3.1USB2 OTG high-speed Port 2 main features .....3752
72.3.2USB2 OTG high-speed Port 2 functional description .....3753
72.3.3USB2 OTG high-speed Port 2 interrupts .....3755
72.3.4Battery charging .....3755
72.3.5ID management .....3755
72.3.6VBUS management .....3755
72.4USB Type-C and power delivery interface .....3756
72.4.1USB Type-C and power delivery interface main features .....3756
72.4.2USB Type-C and power delivery interface implementation .....3756
72.4.3USB Type-C and power delivery interface functional description ..3758
72.4.4USB Type-C and power delivery interrupts .....3759
72.5Debug signals .....3760
73USB on-the-go high-speed (OTG) .....3761
73.1OTG introduction .....3761
73.2OTG main features .....3762
73.2.1General features .....3762
73.2.2Host-mode features .....3763
73.2.3Peripheral-mode features .....3763
73.3OTG implementation .....3763
73.4OTG functional description .....3764
73.4.1OTG block diagram .....3764
73.4.2OTG pin and internal signals .....3764
73.4.3OTG core . . . . .3765
73.4.4OTG detections . . . . .3765
73.4.5High-speed OTG PHY connected to OTG . . . . .3765
73.4.6Battery charging detection . . . . .3765
73.5OTG dual role device (DRD) . . . . .3766
73.5.1ID line detection . . . . .3766
73.6OTG as a USB peripheral . . . . .3766
73.6.1Peripheral states . . . . .3767
73.6.2Peripheral endpoints . . . . .3768
73.7OTG as a USB host . . . . .3770
73.7.1USB host states . . . . .3771
73.7.2Host channels . . . . .3772
73.7.3Host scheduler . . . . .3773
73.8OTG SOF trigger . . . . .3774
73.8.1Host SOFs . . . . .3775
73.8.2Peripheral SOFs . . . . .3775
73.9OTG low-power modes . . . . .3775
73.10OTG Dynamic update of the OTG_HFIR register . . . . .3776
73.11OTG data FIFOs . . . . .3777
73.11.1Peripheral FIFO architecture . . . . .3777
73.11.2Host FIFO architecture . . . . .3778
73.11.3FIFO RAM allocation . . . . .3780
73.12OTG interrupts . . . . .3781
73.13OTG control and status registers . . . . .3783
73.13.1CSR memory map . . . . .3783
73.14OTG registers . . . . .3788
73.14.1OTG control and status register (OTG_GOTGCTL) . . . . .3788
73.14.2OTG interrupt register (OTG_GOTGINT) . . . . .3790
73.14.3OTG AHB configuration register (OTG_GAHBCFG) . . . . .3791
73.14.4OTG USB configuration register (OTG_GUSBCFG) . . . . .3792
73.14.5OTG reset register (OTG_GRSTCTL) . . . . .3794
73.14.6OTG core interrupt register [alternate] (OTG_GINTSTS) . . . . .3797
73.14.7OTG core interrupt register [alternate] (OTG_GINTSTS) . . . . .3801
73.14.8OTG interrupt mask register [alternate] (OTG_GINTMSK) . . . . .3806
73.14.9OTG interrupt mask register [alternate] (OTG_GINTMSK) . . . . .3807
73.14.10OTG receive status debug read register [alternate] (OTG_GRXSTSR) .....3809
73.14.11OTG receive status debug read register [alternate] (OTG_GRXSTSR) .....3810
73.14.12OTG status read and pop registers (OTG_GRXSTSP) .....3811
73.14.13OTG status read and pop registers [alternate] (OTG_GRXSTSP) ..3812
73.14.14OTG receive FIFO size register (OTG_GRXFSIZ) .....3813
73.14.15OTG host non-periodic transmit FIFO size register [alternate] (OTG_HNPTXFSIZ) .....3814
73.14.16Endpoint 0 transmit FIFO size [alternate] (OTG_DIEPTXF0) .....3814
73.14.17OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS) .....3815
73.14.18OTG general core configuration register (OTG_GCCFG) .....3816
73.14.19OTG core ID register (OTG_CID) .....3817
73.14.20OTG core LPM configuration register (OTG_GLPMCFG) .....3818
73.14.21OTG host periodic transmit FIFO size register (OTG_HPTXFSIZ) .....3822
73.14.22OTG device IN endpoint transmit FIFO x size register (OTG_DIEPTXFx) .....3822
73.14.23Host-mode registers .....3822
73.14.24OTG host configuration register (OTG_HCFG) .....3823
73.14.25OTG host frame interval register (OTG_HFIR) .....3823
73.14.26OTG host frame number/frame time remaining register (OTG_HFNUM) .....3824
73.14.27OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS) .....3825
73.14.28OTG host all channels interrupt register (OTG_HAINT) .....3826
73.14.29OTG host all channels interrupt mask register (OTG_HAINTMSK) .....3826
73.14.30OTG host port control and status register (OTG_HPRT) .....3827
73.14.31OTG host channel x characteristics register (OTG_HCCHARx) .....3829
73.14.32OTG host channel x split control register (OTG_HCSPLTx) .....3830
73.14.33OTG host channel x interrupt register (OTG_HCINTx) .....3831
73.14.34OTG host channel x interrupt mask register (OTG_HCINTMSKx) ..3832
73.14.35OTG host channel x transfer size register (OTG_HCTSIZx) .....3833
73.14.36OTG host channel x DMA address register(OTG_HCDMAx) .....3834
73.14.37Device-mode registers .....3834
73.14.38OTG device configuration register (OTG_DCFG) .....3834
73.14.39OTG device control register (OTG_DCTL) .....3836
73.14.40OTG device status register (OTG_DSTS) .....3838
73.14.41OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) . . . . .3839
73.14.42OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) . . . . .3840
73.14.43OTG device all endpoints interrupt register (OTG_DAININT) . . . . .3841
73.14.44OTG all endpoints interrupt mask register (OTG_DAININTMSK) . . . . .3842
73.14.45OTG device threshold control register (OTG_DTHRCTL) . . . . .3842
73.14.46OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK) . . . . .3843
73.14.47OTG device IN endpoint x control register [alternate] (OTG_DIEPCTLx) . . . . .3844
73.14.48OTG device IN endpoint x control register [alternate] (OTG_DIEPCTLx) . . . . .3846
73.14.49OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . . .3848
73.14.50OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0) . . . . .3849
73.14.51OTG device IN endpoint x DMA address register (OTG_DIEPDMAx) . . . . .3850
73.14.52OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) . . . . .3850
73.14.53OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) . . . . .3851
73.14.54OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0) . . . . .3851
73.14.55OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . . . .3853
73.14.56OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0) . . . . .3855
73.14.57OTG device OUT endpoint x DMA address register (OTG_DOEPDMAx) . . . . .3856
73.14.58OTG device OUT endpoint x control register [alternate] (OTG_DOEPCTLx) . . . . .3856
73.14.59OTG device OUT endpoint x control register [alternate] (OTG_DOEPCTLx) . . . . .3858
73.14.60OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx) . . . . .3860
73.14.61OTG power and clock gating control register (OTG_PCGCCTL) . . . . .3861
73.14.62OTG power and clock gating control register 1 (OTG_PCGCCTL1) . . . . .3862
73.14.63OTG register map . . . . .3863
73.15OTG programming model . . . . .3870
73.15.1Core initialization . . . . .3870
73.15.2Host initialization . . . . .3871
73.15.3Device initialization .....3872
73.15.4DMA mode .....3872
73.15.5Host programming model .....3872
73.15.6Device programming model .....3905
73.15.7Worst case response time .....3925
73.15.8OTG programming model .....3927
74USB HS PHY controller (USBPHYC) .....3928
74.1Introduction .....3928
74.2USBPHYC main features .....3928
74.3USBPHYC implementation .....3928
74.4USBPHYC functional description .....3928
74.4.1USBPHYC block diagram .....3928
74.4.2USBPHYC reset and clocks .....3928
74.4.3USBPHYC programmable parameters .....3929
74.4.4USBPHYC trimming of electrical parameters .....3929
74.5USBPHYC registers .....3929
74.5.1USBPHYC control register (USBPHYC_CR) .....3929
74.5.2USBPHYC trimming 1 register (USBPHYC_TRIM1CR) .....3931
74.5.3USBPHYC trimming 2 register (USBPHYC_TRIM2CR) .....3935
74.5.4USBPHYC register map .....3936
75USB Type-C ® /USB Power Delivery interface (UCPD) .....3937
75.1UCPD introduction .....3937
75.2UCPD main features .....3937
75.3UCPD implementation .....3938
75.4UCPD functional description .....3938
75.4.1UCPD block diagram .....3939
75.4.2UCPD reset and clocks .....3940
75.4.3Physical layer protocol .....3940
75.4.4UCPD BMC transmitter .....3947
75.4.5UCPD BMC receiver .....3948
75.4.6UCPD Type-C pull-ups (Rp) and pull-downs (Rd) .....3950
75.4.7UCPD Type-C voltage monitoring and de-bouncing .....3950
75.4.8UCPD fast role swap (FRS) .....3951
75.4.9UCPD DMA Interface .....3951
75.4.10Wake-up from Stop mode . . . . .3951
75.5UCPD programming sequences . . . . .3951
75.5.1Initialization phase . . . . .3951
75.5.2Type-C state machine handling . . . . .3952
75.5.3USB PD transmit . . . . .3953
75.5.4USB PD receive . . . . .3954
75.6UCPD low-power modes . . . . .3955
75.7UCPD interrupts . . . . .3956
75.8UCPD registers . . . . .3957
75.8.1UCPD configuration register 1 (UCPD_CFGR1) . . . . .3957
75.8.2UCPD configuration register 2 (UCPD_CFGR2) . . . . .3959
75.8.3UCPD control register (UCPD_CR) . . . . .3959
75.8.4UCPD interrupt mask register (UCPD_IMR) . . . . .3962
75.8.5UCPD status register (UCPD_SR) . . . . .3963
75.8.6UCPD interrupt clear register (UCPD_ICR) . . . . .3966
75.8.7UCPD Tx ordered set type register (UCPD_TX_ORDSETR) . . . . .3967
75.8.8UCPD Tx payload size register (UCPD_TX_PAYSZR) . . . . .3967
75.8.9UCPD Tx data register (UCPD_TXDR) . . . . .3968
75.8.10UCPD Rx ordered set register (UCPD_RX_ORDSETR) . . . . .3968
75.8.11UCPD Rx payload size register (UCPD_RX_PAYSZR) . . . . .3969
75.8.12UCPD receive data register (UCPD_RXDR) . . . . .3969
75.8.13UCPD Rx ordered set extension register 1
(UCPD_RX_ORDEXTR1) . . . . .		3970
75.8.14UCPD Rx ordered set extension register 2
(UCPD_RX_ORDEXTR2) . . . . .		3970
75.8.15UCPD register map . . . . .3971
76Ethernet (ETH): gigabit media access control
(GMAC) with DMA controller . . . . .		3973
76.1Ethernet introduction . . . . .3973
76.2Ethernet main features . . . . .3973
76.2.1Standard compliance . . . . .3973
76.2.2MAC features . . . . .3973
76.2.3Transaction layer (MTL) features . . . . .3975
76.2.4DMA block features . . . . .3976
76.2.5Bus interface features . . . . .3977
76.2.6Audio and video features . . . . .3978
76.2.7Time sensitive networking features . . . . .3978
76.2.8Generic queuing features . . . . .3978
76.3Ethernet pins and internal signals . . . . .3978
76.4Ethernet architecture . . . . .3980
76.4.1DMA controller . . . . .3981
76.4.2MTL . . . . .3988
76.4.3MAC . . . . .3988
76.4.4Multiple channels and queues support . . . . .3993
76.5Ethernet functional description: MAC . . . . .4005
76.5.1Double VLAN processing . . . . .4005
76.5.2Source address and VLAN insertion, replacement, or deletion . . . . .4006
76.5.3Queue/channel-based VLAN tag insertion on Tx . . . . .4007
76.5.4Packet filtering . . . . .4008
76.5.5IEEE 1588 timestamp support . . . . .4020
76.5.6Time sensitive networking (TSN) . . . . .4046
76.5.7Checksum offload engine . . . . .4075
76.5.8TCP segmentation offload . . . . .4081
76.5.9IPv4 ARP offload . . . . .4087
76.5.10Loopback . . . . .4088
76.5.11Flow control . . . . .4089
76.5.12MAC management counters . . . . .4092
76.5.13Interrupts generated by the MAC . . . . .4094
76.5.14MAC and MMC register descriptions . . . . .4094
76.6Ethernet functional description: PHY interfaces . . . . .4095
76.6.1Station management agent (SMA) . . . . .4095
76.6.2Media independent interface (MII) . . . . .4102
76.6.3Reduced media independent interface (RMII) . . . . .4103
76.6.4Reduced gigabit media independent interface (RGMII) . . . . .4106
76.7Ethernet low-power modes . . . . .4108
76.7.1Low-power management . . . . .4108
76.7.2Energy-efficient Ethernet (EEE) . . . . .4114
76.8Ethernet interrupts . . . . .4121
76.8.1DMA interrupts . . . . .4121
76.8.2MTL interrupts . . . . .4123
76.8.3MAC interrupts . . . . .4123
76.9Ethernet programming model . . . . .4124

77            Hardware debug port (HDP) . . . . . 4368

77.1HDP introduction . . . . .4368
77.2HDP functional description . . . . .4368
77.3HDP block diagram . . . . .4370
77.4HDP register description . . . . .4370
77.4.1HDP control register (HDP_CTRL) . . . . .4370
77.4.2HDP multiplexer control register (HDP_MUX) . . . . .4371
77.4.3HDP read back value register (HDP_VAL) . . . . .4371
77.4.4HDP general-purpose output set register (HDP_GPOSET) . . . . .4371
77.4.5HDP general purpose output clear register (HDP_GPOCLR) . . . . .4372
77.4.6HDP general purpose output value register (HDP_GPOVAL) . . . . .4372
77.4.7HDP register map . . . . .4372
78Debug support (DBG) . . . . .4374
78.1DBG introduction . . . . .4374
78.2DBG functional description . . . . .4375
78.3DBG block diagram . . . . .4377
78.4DBG pins . . . . .4377
78.5DBG power, clock, and reset . . . . .4378
78.5.1DBG power domains . . . . .4378
78.5.2DBG clocks . . . . .4378
78.5.3Debug reset . . . . .4379
78.6Security . . . . .4379
78.6.1BSEC control over debug . . . . .4380
78.6.2Authentication signals . . . . .4380
78.7Debug authentication . . . . .4381
78.7.1Main characteristics . . . . .4381
78.7.2Debug authentication protocol . . . . .4381
78.8Chip-level TAP controller (CLTAPC) . . . . .4382
78.9Serial-wire and JTAG debug port (SWJ-DP) . . . . .4382
78.9.1JTAG debug port . . . . .4383
78.9.2SWD debug port . . . . .4386
78.9.3Debug port registers . . . . .4388
78.10Access ports . . . . .4396
78.10.1AP0 registers . . . . .4398
78.10.2AP1 registers . . . . .4401
78.10.3AP2 registers . . . . .4405

78.12.21 DBGMCU registers . . . . . 4650

78.13 References . . . . . 4661

79 Device electronic signature . . . . . 4662

79.1 Unique device ID register (96 bits) (UID) . . . . . 4662

79.2 Device part number (RPN) . . . . . 4663

79.3 Package data register (PKG) . . . . . 4664

79.4 Device version . . . . . 4664

79.5 Boot ROM version . . . . . 4665

80 Important security notice . . . . . 4666

81 Revision history . . . . . 4667

List of tables

Table 1. Memory map based on IDAU mapping. . . . . 164

Table 2. Memory map and peripheral register boundary addresses . . . . . 169

Table 3. Peripheral register boundary addresses. . . . . 175

Table 4. Aliasing . . . . . 185

Table 5. Nonsecure peripheral functions that can be connected to secure I/Os . . . . . 192

Table 6. Internal tampers in TAMP. . . . . 195

Table 7. Effect of low-power modes on TAMP . . . . . 197

Table 8. Accelerated cryptographic operations . . . . . 198

Table 9. BSEC internal input/output signals . . . . . 202

Table 10. BSEC initial status reporting structure . . . . . 207

Table 11. BSEC ad-hoc error/status reporting structure. . . . . 207

Table 12. BSEC states definition . . . . . 208

Table 13. Current HDPL coding . . . . . 210

Table 14. BSEC Next HDPL register usage . . . . . 211

Table 15. BSEC debug register legal values . . . . . 211

Table 16. BSEC register map and reset values . . . . . 228

Table 17. OTP mapping . . . . . 231

Table 18. OTP fuse description (lower OTP region). . . . . 235

Table 19. OTP fuse description (mid OTP region) . . . . . 246

Table 20. RISUP indexes . . . . . 249

Table 21. RISC indexes purely for RCC security control . . . . . 250

Table 22. RIMU resource assignment . . . . . 250

Table 23. RIFSC register map and reset values. . . . . 257

Table 24. RISAF resource assignment. . . . . 259

Table 25. RISAF internal input/output signals . . . . . 260

Table 26. RISAF subregion security setup matrix . . . . . 262

Table 27. RISAF register map and reset values. . . . . 278

Table 28. Peripheral indexes in IAC . . . . . 280

Table 29. IAC internal signals. . . . . 282

Table 30. IAC interrupt request. . . . . 283

Table 31. IAC register map and reset values . . . . . 285

Table 32. Boot modes. . . . . 286

Table 33. Internal SRAM features . . . . . 289

Table 34. Hardware-erase conditions for internal SRAMs . . . . . 289

Table 35. FLEXRAM supported configurations . . . . . 290

Table 36. FLEXMEM versus retention . . . . . 290

Table 37. RAMCFG interrupt requests . . . . . 294

Table 38. RAMCFG register map and reset values . . . . . 306

Table 39. ICACHE features . . . . . 309

Table 40. TAG memory dimensioning parameters
for n-way set associative operating mode (default) . . . . . 311

Table 41. TAG memory dimensioning parameters for direct-mapped cache mode . . . . . 312

Table 42. ICACHE cacheability for AHB transaction . . . . . 313

Table 43. ICACHE interrupts . . . . . 316

Table 44. ICACHE register map and reset values . . . . . 319

Table 45. CACHEAXI features . . . . . 323

Table 46. TAG memory dimensioning parameters. . . . . 328

Table 47. CACHEAXI supported AXI 4-bit memory/cache attribute . . . . . 329

Table 48.CACHEAXI interrupts . . . . .336
Table 49.CACHEAXI register map and reset values . . . . .345
Table 50.PWR input/output signals connected to package pins or balls . . . . .349
Table 51.PWR internal input/output signals . . . . .349
Table 52.Wake-up source selection . . . . .350
Table 53.Supply configuration control . . . . .353
Table 54.Operating mode summary . . . . .369
Table 55.Functionalities depending on system operating mode . . . . .370
Table 56.Sleep mode . . . . .378
Table 57.Stop mode SVOS high . . . . .380
Table 58.Stop mode SVOS low . . . . .380
Table 59.Standby and Stop flags . . . . .382
Table 60.Standby mode . . . . .382
Table 61.Power mode output states versus MCU power modes . . . . .383
Table 62.PWR register security overview . . . . .384
Table 63.PWR register map and reset values . . . . .408
Table 64.RCC input/output signals connected to package pins or balls . . . . .412
Table 65.RCC internal input/output signals . . . . .413
Table 66.Reset coverage summary . . . . .419
Table 67.Reset source identification . . . . .420
Table 68.Oscillator states versus system modes . . . . .424
Table 69.Clock output selection . . . . .435
Table 70.STOPWUCK description . . . . .443
Table 71.HSISTOPEN and MSISTOPEN behavior . . . . .444
Table 72.Peripheral clock distribution summary . . . . .445
Table 73.SDMMC interface clock constraints . . . . .464
Table 74.Peripheral clock enabling . . . . .471
Table 75.Interrupt sources and control . . . . .474
Table 76.Maximum peripheral clock frequencies . . . . .476
Table 77.RCC register map and reset values . . . . .754
Table 78.Port x bit configurations . . . . .784
Table 79.Secure AF between peripherals and allocated I/Os . . . . .792
Table 80.GPIO secured bits . . . . .792
Table 81.GPIO register map and reset values . . . . .806
Table 82.SYSCFG register map and reset values . . . . .829
Table 83.Connectivity matrix . . . . .833
Table 84.Implementation of HPDMA1 channels . . . . .836
Table 85.HPDMA1 in low-power modes . . . . .836
Table 86.Programmed HPDMA1 request . . . . .837
Table 87.Programmed HPDMA1 request as a block request . . . . .841
Table 88.HPDMA1 channel with peripheral early termination . . . . .841
Table 89.Programmed HPDMA1 request with peripheral early termination . . . . .841
Table 90.Programmed HPDMA1 trigger . . . . .842
Table 91.Programmed HPDMA source/destination burst . . . . .865
Table 92.Programmed data handling . . . . .870
Table 93.Effect of low-power modes on HPDMA . . . . .892
Table 94.HPDMA interrupt requests . . . . .893
Table 95.HPDMA register map and reset values . . . . .929
Table 96.GPDMA1 channel implementation . . . . .933
Table 97.GPDMA1 wake-up in low-power modes . . . . .933
Table 98.Programmed GPDMA1 request . . . . .933
Table 99.Programmed GPDMA1 request as a block request . . . . .938
Table 100.GPDMA1 channel with peripheral early termination . . . . .938
Table 101.Programmed GPDMA1 request with peripheral early termination . . . . .938
Table 102.Programmed GPDMA1 trigger . . . . .938
Table 103.Programmed GPDMA source/destination burst . . . . .961
Table 104.Programmed data handling . . . . .966
Table 105.Effect of low-power modes on GPDMA . . . . .979
Table 106.GPDMA interrupt requests . . . . .980
Table 107.GPDMA register map and reset values . . . . .1009
Table 108.Neural-ART 14 NPU configuration . . . . .1013
Table 109.Neural-ART 14 NPU signals . . . . .1015
Table 110.Activation functions example . . . . .1021
Table 111.Neural-ART 14 functional units memory base addresses. . . . .1028
Table 112.DMA2D internal signals . . . . .1034
Table 113.DMA2D trigger interconnections . . . . .1034
Table 114.Supported color mode in input . . . . .1035
Table 115.Data order in memory . . . . .1036
Table 116.Alpha mode configuration . . . . .1037
Table 117.Supported CLUT color mode . . . . .1038
Table 118.CLUT data order in memory . . . . .1038
Table 119.Supported color mode in output . . . . .1039
Table 120.Data order in memory . . . . .1040
Table 121.Standard data order in memory . . . . .1040
Table 122.Output FIFO byte reordering steps . . . . .1041
Table 123.MCU order in memory . . . . .1046
Table 124.DMA2D interrupt requests . . . . .1047
Table 125.DMA2D register map and reset values . . . . .1065
Table 126.GFXMMU internal input/output signals . . . . .1068
Table 127.GFXMMU interrupt requests . . . . .1074
Table 128.GFXMMU register map and reset values . . . . .1080
Table 129.GFXTIM input/output pins . . . . .1083
Table 130.GFXTIM internal signals . . . . .1083
Table 131.GFXTIM trigger interconnections . . . . .1084
Table 132.Graphic timer interrupt requests . . . . .1094
Table 133.GFXTIM register map and reset values . . . . .1115
Table 134.STM32N6x5/x7xx vector table . . . . .1118
Table 135.EXTI implementation . . . . .1127
Table 136.EXTI signals . . . . .1127
Table 137.EVG signals . . . . .1128
Table 138.EXTI line connection . . . . .1129
Table 139.EXTI event input configurations and register control . . . . .1131
Table 140.Masking functionality . . . . .1133
Table 141.Register protection overview . . . . .1134
Table 142.EXTI register map sections. . . . .1135
Table 143.EXTI register map and reset values . . . . .1167
Table 144.CRC internal input/output signals . . . . .1171
Table 145.CRC register map and reset values . . . . .1176
Table 146.FMC features . . . . .1178
Table 147.FMC internal signals . . . . .1180
Table 148.FMC memory regions (default mapping) . . . . .1182
Table 149.FMC memory region remap using BMAP[1:0] . . . . .1182
Table 150.NOR/PSRAM subregion selection . . . . .1183
Table 151.NOR/PSRAM External memory address . . . . .1183
Table 152.NAND access memory map . . . . .1183
Table 153.SDRAM device selection . . . . .1184
Table 154.SDRAM address mapping . . . . .1184
Table 155.SDRAM address mapping with 8-bit data bus width. . . . .1185
Table 156.SDRAM address mapping with 16-bit data bus width. . . . .1186
Table 157.SDRAM address mapping with 32-bit data bus width. . . . .1186
Table 158.Programmable NOR/PSRAM access parameters . . . . .1188
Table 159.Non-multiplexed I/O NOR flash memory. . . . .1189
Table 160.16-bit multiplexed I/O NOR flash memory . . . . .1189
Table 161.Non-multiplexed I/Os PSRAM/SRAM . . . . .1190
Table 162.16-bit multiplexed I/O PSRAM . . . . .1190
Table 163.NOR flash/PSRAM: Example of supported memories and transactions . . . . .1191
Table 164.FMC_BCRx bitfields (mode 1) . . . . .1195
Table 165.FMC_BTRx bitfields (mode 1) . . . . .1195
Table 166.FMC_BCRx bitfields (mode A) . . . . .1197
Table 167.FMC_BTRx bitfields (mode A) . . . . .1198
Table 168.FMC_BWTRx bitfields (mode A). . . . .1198
Table 169.FMC_BCRx bitfields (mode 2/B). . . . .1200
Table 170.FMC_BTRx bitfields (mode 2/B). . . . .1201
Table 171.FMC_BWTRx bitfields (mode 2/B) . . . . .1201
Table 172.FMC_BCRx bitfields (mode C) . . . . .1203
Table 173.FMC_BTRx bitfields (mode C) . . . . .1203
Table 174.FMC_BWTRx bitfields (mode C). . . . .1204
Table 175.FMC_BCRx bitfields (mode D) . . . . .1205
Table 176.FMC_BTRx bitfields (mode D) . . . . .1206
Table 177.FMC_BWTRx bitfields (mode D). . . . .1206
Table 178.FMC_BCRx bitfields (muxed mode) . . . . .1208
Table 179.FMC_BTRx bitfields (muxed mode) . . . . .1209
Table 180.FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .1214
Table 181.FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .1215
Table 182.FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .1216
Table 183.FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .1217
Table 184.Programmable NAND flash access parameters . . . . .1227
Table 185.8-bit NAND flash memory . . . . .1227
Table 186.16-bit NAND flash memory . . . . .1228
Table 187.Supported memories and transactions . . . . .1228
Table 188.Number of ECC parity bytes per sector . . . . .1233
Table 189.FMC NAND controller Interrupt request . . . . .1242
Table 190.HPR relevant bits . . . . .1248
Table 191.ECC result relevant bits . . . . .1249
Table 192.SDRAM signals. . . . .1267
Table 193.FMC register map . . . . .1284
Table 194.XSPI implementation . . . . .1290
Table 195.XSPI input/output pins . . . . .1295
Table 196.XSPI internal signals. . . . .1295
Table 197.Command/address phase description . . . . .1306
Table 198.OctaRAM command address bit assignment
(based on 64 Mb OctaRAM) . . . . .		1318
Table 199.Address alignment cases . . . . .1326
Table 200.XSPI interrupt requests. . . . .1328
Table 201.XSPI register map and reset values . . . . .1354
Table 202.XSPIM implementation . . . . .1358
Table 203.XSPIM input/output pins . . . . .1359
Table 204.Use cases . . . . .1361
Table 205.XSPIM register map and reset values . . . . .1371
Table 206.SDMMC features . . . . .1372
Table 207.SDMMC operation modes SD and SDIO . . . . .1375
Table 208.SDMMC operation modes e•MMC . . . . .1375
Table 209.SDMMC internal input/output signals . . . . .1376
Table 210.SDMMC pins . . . . .1377
Table 211.SDMMC Command and data phase selection . . . . .1378
Table 212.Command token format . . . . .1384
Table 213.Short response with CRC token format . . . . .1385
Table 214.Short response without CRC token format . . . . .1385
Table 215.Long response with CRC token format . . . . .1385
Table 216.Specific Commands overview . . . . .1386
Table 217.Command path status flags . . . . .1387
Table 218.Command path error handling . . . . .1387
Table 219.Data token format . . . . .1395
Table 220.Data path status flags and clear bits . . . . .1395
Table 221.Data path error handling . . . . .1397
Table 222.Data FIFO access . . . . .1398
Table 223.Transmit FIFO status flags . . . . .1399
Table 224.Receive FIFO status flags . . . . .1401
Table 225.AHB and SDMMC_CK clock frequency relation . . . . .1405
Table 226.SDIO special operation control . . . . .1406
Table 227.4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . .1410
Table 228.CMD12 use cases . . . . .1415
Table 229.Data block gap hardware flow control behavior . . . . .1427
Table 230.Hardware flow control selection . . . . .1427
Table 231.SDMMC interrupts . . . . .1431
Table 232.Response type and SDMMC_RESPxR registers . . . . .1438
Table 233.SDMMC register map . . . . .1454
Table 234.STM32N6x5/x7xx features . . . . .1457
Table 235.DLYB functional signals . . . . .1459
Table 236.DLYB interconnection . . . . .1460
Table 237.DLYB register map and reset values . . . . .1464
Table 238.ADC features . . . . .1468
Table 239.ADC input/output pins . . . . .1470
Table 240.ADC internal input/output signals . . . . .1470
Table 241.ADC1/2 interconnection . . . . .1470
Table 242.Configuring the trigger polarity for regular external triggers . . . . .1491
Table 243.Configuring the trigger polarity for injected external triggers . . . . .1491
Table 244.TSAR timings depending on resolution . . . . .1494
Table 245.Offset computation versus data resolution . . . . .1498
Table 246.12-bit data formats . . . . .1500
Table 247.Numerical examples for 32-bit or 16-bit format (POSSPFF = 0) . . . . .1501
Table 248.Analog window watchdog features . . . . .1509
Table 249.Analog watchdog 1 channel selection . . . . .1510
Table 250.Analog watchdog 1, 2, 3 comparison . . . . .1511
Table 251.Maximum output results versus N and M . . . . .1516
Table 252.Oversampler operating mode summary . . . . .1520
Table 253.DELAY bits versus ADC resolution . . . . .1526
Table 254.ADC interrupts . . . . .1539
Table 255.ADC register map and reset values for each ADC . . . . .1575
Table 256.ADC register map and reset values (master and slave ADC common registers) . . . . .1578
Table 257.DTS internal input/output signals . . . . .1580
Table 258.DTS interconnection . . . . .1581
Table 259.SDA slave registers . . . . .1586
Table 260.SDA TS control register (SDATS_CR) . . . . .1586
Table 261.SDA TS configuration register (SDATS_CFGGR) . . . . .1587
Table 262.SDA TS data register (SDATS_DR) . . . . .1588
Table 263.SDA TS timer register (SDATS_TIMER) . . . . .1589
Table 264.Output resolution configuration . . . . .1594
Table 265.DTS interrupts . . . . .1595
Table 266.DTS register memory map . . . . .1596
Table 267.PVT common register map and reset values . . . . .1616
Table 268.PVT IRQ register map and reset values . . . . .1616
Table 269.DTS TSC clock synthesizer register map and reset values . . . . .1617
Table 270.DTS TS individual register map and reset values . . . . .1619
Table 271.VREFBUF typical values . . . . .1621
Table 272.VREF buffer modes . . . . .1622
Table 273.VREFBUF register map and reset values . . . . .1625
Table 274.MDF features . . . . .1627
Table 275.MDF external pins . . . . .1630
Table 276.MDF internal signals . . . . .1630
Table 277.MDF trigger connections . . . . .1630
Table 278.MDF break connections . . . . .1631
Table 279.Control of the common clock generation . . . . .1638
Table 280.Clock constraints with respect to the incoming stream . . . . .1639
Table 281.Data size according to CIC order and CIC decimation values . . . . .1646
Table 282.Maximum decimation ratio versus order and input data size . . . . .1647
Table 283.Possible gain values . . . . .1648
Table 284.Recommended maximum gain values versus CIC decimation ratios . . . . .1650
Table 285.Most common microphone settings . . . . .1650
Table 286.HPF 3 dB cut-off frequencies examples . . . . .1652
Table 287.Register protection summary . . . . .1673
Table 288.Effect of low-power modes on MDF . . . . .1674
Table 289.MDF interrupt requests . . . . .1676
Table 290.Examples of MDF settings for microphone capture . . . . .1677
Table 291.Programming sequence . . . . .1677
Table 292.Output signal levels . . . . .1684
Table 293.MDF register map and reset values . . . . .1707
Table 294.ADF features . . . . .1710
Table 295.ADF external pins . . . . .1711
Table 296.ADF internal signals . . . . .1712
Table 297.ADF trigger connections . . . . .1712
Table 298.Control of the common clock generation . . . . .1718
Table 299.Clock constraints with respect to the incoming stream . . . . .1719
Table 300.Data size according to CIC order and CIC decimation values . . . . .1724
Table 301.Possible gain values . . . . .1725
Table 302.Recommended maximum gain values versus CIC decimation ratios . . . . .1727
Table 303.Most common microphone settings . . . . .1728
Table 304.HPF 3 dB cut-off frequency examples . . . . .1730
Table 305.ANSLP values versus FRFSIZE and sampling rates . . . . .1743
Table 306.Threshold values according SNTHR . . . . .1744
Table 307.Register protection summary . . . . .1750
Table 308.Effect of low-power modes on ADF . . . . .1751
Table 309.ADF interrupt requests . . . . .1752
Table 310.Examples of ADF settings for microphone capture . . . . .1753
Table 311.Programming sequence (CIC4) . . . . .1754
Table 312.Programming sequence (CIC5) . . . . .1755
Table 313.Output signal levels . . . . .1760
Table 314.ADF register map and reset values . . . . .1780
Table 315.Camera subsystem RIF peripheral ID . . . . .1789
Table 316.DCMI input/output pins . . . . .1795
Table 317.DCMI internal input/output signals . . . . .1795
Table 318.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .1797
Table 319.Positioning of captured data bytes in 32-bit words (10-bit width) . . . . .1797
Table 320.Positioning of captured data bytes in 32-bit words (12-bit width) . . . . .1797
Table 321.Positioning of captured data bytes in 32-bit words (14-bit width) . . . . .1798
Table 322.Data storage in monochrome progressive video format . . . . .1803
Table 323.Data storage in RGB progressive video format . . . . .1804
Table 324.Data storage in YCbCr progressive video format . . . . .1804
Table 325.Data storage in YCbCr progressive video format - Y extraction mode . . . . .1804
Table 326.DCMI interrupts . . . . .1805
Table 327.DCMI register map and reset values . . . . .1815
Table 328.Available pipelines . . . . .1816
Table 329.Glossary . . . . .1817
Table 330.DCMIPP input/output pads . . . . .1822
Table 331.DCMIPP input/output pins . . . . .1822
Table 332.DCMIPP clocks . . . . .1822
Table 333.DCMIPP resets . . . . .1823
Table 334.Parallel interface maximum resolution (80 MHz) . . . . .1824
Table 335.Supported pixel formats . . . . .1826
Table 336.DCMIPP_CMCR bit function . . . . .1828
Table 337.DCMIPP_PRCR bit function . . . . .1831
Table 338.DCMIPP_PRESR and DCMIPP_PRESUR bit function . . . . .1831
Table 339.DCMIPP_PxFCTCR bit function . . . . .1839
Table 340.DCMIPP_P0PPCR bit function . . . . .1842
Table 341.DCMIPP_P0DCCNTR and DCMIPP_P0DCLMTR bit function . . . . .1845
Table 342.DCMIPP_P1SRCR bit function . . . . .1848
Table 343.DCMIPP_P1BPRCR and DCMIPP_P1BPRSR bit function . . . . .1848
Table 344.DCMIPP_P1DECR bit function . . . . .1850
Table 345.DCMIPP_P1BLCCR bit function . . . . .1850
Table 346.DCMIPP_P1EXCR1 and DCMIPP_P1EXCR2 bit function . . . . .1851
Table 347.DCMIPP_P1DMCR bit function . . . . .1853
Table 348.DCMIPP_PxCCyy (yy = R0, R1, G0, G1, B0, B1) bit function . . . . .1854
Table 349.Color conversion: examples of coefficients . . . . .1855
Table 350.DCMIPP_P1CTCR1,2,3 bit function . . . . .1857
Table 351.DCMIPP_P1STyCR (y = 1, 2, 3), DCMIPP_P1STySR (y = 1, 2, 3),
DCMIPP_P1STSTR and DCMIPP_P1STSZR bit function . . . . .		1859
Table 352.Statistics extraction: collected data vs. modes . . . . .1860
Table 353.DCMIPP_PxCRSTR and DCMIPP_PxCRSZR bit function . . . . .1864
Table 354.DCMIPP_PxDCCR bit function . . . . .1865
Table 355.DCMIPP_PxDSCR, DCMIPP_PxDSRTIOR, DCMIPP_PxDSSZR . . . . .1866
Table 356.DCMIPP_PxPPCR bit function . . . . .1869
Table 357.Parallel interface input pixel formats . . . . .1884
Table 358.Correspondence between index and DCMIPP_PRCR register values. . . . .1885
Table 359.Parallel interface input pixel formats . . . . .1886
Table 360.Pixel pipe output pixel format . . . . .1886
Table 361.Dump pipe OUTPUT pixel formats . . . . .1888
Table 362.Shadow and physical registers . . . . .1895
Table 363.DCMIPP low power modes . . . . .1897
Table 364.DCMIPP interrupts . . . . .1900
Table 365.Event connection . . . . .1901
Table 366.DCMIPP registers organization . . . . .1902
Table 367.DCMIPP register map and reset values . . . . .2001
Table 368.Glossary of terms . . . . .2016
Table 369.Effect of low-power modes on CSI-2 Host controller . . . . .2035
Table 370.List of errors detected by the CSI-2 Host controller . . . . .2035
Table 371.List of events that trigger an interrupt . . . . .2036
Table 372.CSI-2 Host and PHY register map and reset values . . . . .2070
Table 373.PSSI input/output pins . . . . .2076
Table 374.PSSI internal input/output signals . . . . .2076
Table 375.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .2077
Table 376.Positioning of captured data bytes in 32-bit words (16-bit width) . . . . .2078
Table 377.PSSI interrupt requests . . . . .2081
Table 378.PSSI register map and reset values . . . . .2087
Table 379.Display subsystem RIF peripheral ID . . . . .2092
Table 380.LTDC pins . . . . .2095
Table 381.LTDC trigger interconnections . . . . .2096
Table 382.Clock domain for each register . . . . .2096
Table 383.LTDC register access and updated durations . . . . .2098
Table 384.Pixel data mapping versus color format . . . . .2101
Table 385.LTDC hardware triggers . . . . .2116
Table 386.LTDC interrupt requests . . . . .2118
Table 387.LTDC register map and reset values . . . . .2149
Table 388.GPU2D internal input/output signals . . . . .2155
Table 389.GPU2D trigger connections . . . . .2156
Table 390.VENC register map and reset values . . . . .2251
Table 391.JPEG internal signals . . . . .2266
Table 392.JPEG trigger connections . . . . .2267
Table 393.JPEG codec interrupt requests . . . . .2272
Table 394.JPEG codec register map and reset values . . . . .2285
Table 395.RNG internal input/output signals . . . . .2288
Table 396.RNG interrupt requests . . . . .2296
Table 397.RNG initialization times . . . . .2297
Table 398.RNG configurations . . . . .2297
Table 399.Configuration selection . . . . .2298
Table 400.RNG register map and reset map . . . . .2303
Table 401.CRYP versus SAES features . . . . .2305
Table 402.SAES internal input/output signals . . . . .2306
Table 403.SAES approved symmetric key functions . . . . .2307
Table 404.Counter mode initialization vector definition . . . . .2317
Table 405.Initialization of IV registers in GCM mode . . . . .2320
Table 406.GCM last block definition . . . . .2320
Table 407.Initialization of IV registers in CCM mode . . . . .2326
Table 408.AES data swapping example . . . . .2335
Table 409.Key endianness in SAES_KEYRx registers (128/256-bit keys) . . . . .2337
Table 410.IVI bitfield spread over SAES_IVRx registers . . . . .2339
Table 411.SAES interrupt requests . . . . .2341
Table 412.Processing latency for ECB, CBC and CTR . . . . .2342
Table 413.Processing latency for GCM and CCM (in SAES kernel clock cycles) . . . . .2342
Table 414.SAES register map and reset values . . . . .2357
Table 415.CRYP versus SAES features . . . . .2360
Table 416.CRYP internal input/output signals . . . . .2362
Table 417.CRYP approved AES symmetric key functions . . . . .2362
Table 418.Counter mode initialization vector definition . . . . .2373
Table 419.GCM mode IVI registers initialization . . . . .2376
Table 420.GCM last block definition . . . . .2376
Table 421.CCM mode IVI registers initialization . . . . .2383
Table 422.AES data swapping example . . . . .2388
Table 423.Key endianness in CRYP_KxR/LR registers (128/192/256-bit keys) . . . . .2390
Table 424.Initialization vector endianness in CRYP_IVxR registers (AES) . . . . .2390
Table 425.CRYP interrupt requests . . . . .2392
Table 426.Processing latency for ECB, CBC and CTR . . . . .2393
Table 427.Processing latency for GCM and CCM (in clock cycles) . . . . .2394
Table 428.CRYP register map and reset values . . . . .2407
Table 429.HASH internal input/output signals . . . . .2410
Table 430.Information on supported hash algorithms . . . . .2411
Table 431.Hash processor outputs . . . . .2414
Table 432.Processing time (in clock cycle) . . . . .2420
Table 433.HASH interrupt requests . . . . .2421
Table 434.HASH1 register map and reset values . . . . .2429
Table 435.MCE internal input/output signals . . . . .2432
Table 436.MCE block cipher latencies . . . . .2436
Table 437.MCE stream cipher latencies . . . . .2437
Table 438.MCE interrupt requests . . . . .2438
Table 439.MCE register map and reset values . . . . .2450
Table 440.Internal input/output signals . . . . .2453
Table 441.PKA integer arithmetic functions list . . . . .2454
Table 442.PKA prime field (Fp) elliptic curve functions list . . . . .2455
Table 443.Example of 'a' curve coefficient for ECC Fp scalar . . . . .2461
Table 444.Montgomery parameter computation . . . . .2461
Table 445.Modular addition . . . . .2462
Table 446.Modular subtraction . . . . .2462
Table 447.Montgomery multiplication . . . . .2463
Table 448.Modular exponentiation (normal mode) . . . . .2464
Table 449.Modular exponentiation (fast mode) . . . . .2464
Table 450.Modular exponentiation (protected mode) . . . . .2465
Table 451.Modular inversion . . . . .2465
Table 452.Modular reduction . . . . .2466
Table 453.Arithmetic addition . . . . .2466
Table 454.Arithmetic subtraction . . . . .2466
Table 455.Arithmetic multiplication . . . . .2467
Table 456.Arithmetic comparison . . . . .2467
Table 457.CRT exponentiation . . . . .2468
Table 458.Point on elliptic curve Fp check . . . . .2469
Table 459.ECC Fp scalar multiplication . . . . .2469
Table 460.ECDSA sign - Inputs . . . . .2471
Table 461.ECDSA sign - Outputs . . . . .2471
Table 462.Extended ECDSA sign - additional outputs . . . . .2472
Table 463.ECDSA verification - inputs . . . . .2472
Table 464.ECDSA verification - outputs . . . . .2473
Table 465.ECC complete addition . . . . .2473
Table 466.ECC double base ladder . . . . .2474
Table 467.ECC projective to affine . . . . .2475
Table 468.Family of supported curves for ECC operations . . . . .2476
Table 469.Modular exponentiation . . . . .2477
Table 470.ECC scalar multiplication . . . . .2477
Table 471.ECDSA signature average computation time . . . . .2478
Table 472.ECDSA verification average computation times . . . . .2478
Table 473.ECC double base ladder average computation times . . . . .2478
Table 474.ECC projective to affine average computation times . . . . .2478
Table 475.ECC complete addition average computation times . . . . .2478
Table 476.Point on elliptic curve Fp check average computation times . . . . .2478
Table 477.Montgomery parameters average computation times . . . . .2479
Table 478.PKA interrupt requests . . . . .2479
Table 479.PKA register map and reset values . . . . .2484
Table 480.TIM input/output pins . . . . .2487
Table 481.TIM internal input/output signals . . . . .2487
Table 482.Interconnect to the tim_ti1 input multiplexer . . . . .2488
Table 483.Interconnect to the tim_ti2 input multiplexer . . . . .2488
Table 484.Interconnect to the tim_ti3 input multiplexer . . . . .2489
Table 485.Interconnect to the tim_ti4 input multiplexer . . . . .2489
Table 486.Internal trigger connection . . . . .2489
Table 487.Interconnect to the tim_etr input multiplexer . . . . .2490
Table 488.Timer break interconnect . . . . .2490
Table 489.Timer break2 interconnect . . . . .2490
Table 490.System break interconnect . . . . .2490
Table 491.CCR and ARR register change dithering pattern . . . . .2523
Table 492.CCR register change dithering pattern in center-aligned PWM mode . . . . .2524
Table 493.Behavior of timer outputs versus tim_brk/tim_brk2 inputs . . . . .2536
Table 494.Break protection disarming conditions . . . . .2538
Table 495.Counting direction versus encoder signals (CC1P = CC2P = 0) . . . . .2546
Table 496.Counting direction versus encoder signals and polarity settings . . . . .2550
Table 497.DMA request . . . . .2572
Table 498.Effect of low-power modes on TIM1/TIM8 . . . . .2573
Table 499.Interrupt requests . . . . .2573
Table 500.Output control bits for complementary tim_ocx and tim_ocxn channels
with break feature . . . . .		2600
Table 501.TIMx register map and reset values . . . . .2623
Table 502.STM32N6x5/x7xx general purpose timers . . . . .2627
Table 503.TIM input/output pins . . . . .2629
Table 504.TIM internal input/output signals . . . . .2629
Table 505.Interconnect to the tim_ti1 input multiplexer . . . . .2630
Table 506.Interconnect to the tim_ti2 input multiplexer . . . . .2630
Table 507.Interconnect to the tim_ti3 input multiplexer . . . . .2630
Table 508.Interconnect to the tim_ti4 input multiplexer . . . . .2631
Table 509.TIMx internal trigger connection . . . . .2631
Table 510.Interconnect to the tim_etr input multiplexer . . . . .2631
Table 511.CCR and ARR register change dithering pattern . . . . .2663
Table 512.CCR register change dithering pattern in center-aligned PWM mode . . . . .2664
Table 513.Counting direction versus encoder signals(CC1P = CC2P = 0) . . . . .2673
Table 514.Counting direction versus encoder signals and polarity settings . . . . .2678
Table 515.DMA request . . . . .2703
Table 516.Effect of low-power modes on TIM2/TIM3/TIM4/TIM5 . . . . .2703
Table 517.Interrupt requests . . . . .2704
Table 518.Output control bit for standard tim_ocx channels . . . . .2725
Table 519.TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . .2737
Table 520.TIM internal input/output signals . . . . .2741
Table 521.TIMx_ARR register change dithering pattern . . . . .2750
Table 522.DMA request . . . . .2752
Table 523.Effect of low-power modes on TIM6/TIM7/TIM18 . . . . .2752
Table 524.Interrupt request . . . . .2752
Table 525.TIMx register map and reset values . . . . .2759
Table 526.TIM input/output pins . . . . .2763
Table 527.TIM internal input/output signals . . . . .2763
Table 528.Interconnect to the tim_ti1 input multiplexer . . . . .2764
Table 529.Interconnect to the tim_ti2 input multiplexer . . . . .2764
Table 530.TIMx internal trigger connection . . . . .2764
Table 531.CCR and ARR register change dithering pattern . . . . .2782
Table 532.Effect of low-power modes on TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 . . . . .2792
Table 533.Interrupt requests . . . . .2792
Table 534.Output control bit for standard tim_ocx channels . . . . .2805
Table 535.TIMx register map and reset values (x = 9, 12) . . . . .2809
Table 536.Output control bit for standard tim_ocx channels . . . . .2818
Table 537.TIM10/TIM11/TIM13/TIM14 register map and reset values . . . . .2821
Table 538.TIM input/output pins . . . . .2826
Table 539.TIM internal input/output signals . . . . .2827
Table 540.Interconnect to the tim_ti1 input multiplexer . . . . .2828
Table 541.Interconnect to the tim_ti2 input multiplexer . . . . .2828
Table 542.TIMx internal trigger connection . . . . .2828
Table 543.Timer break interconnect . . . . .2829
Table 544.System break interconnect . . . . .2829
Table 545.CCR and ARR register change dithering pattern . . . . .2849
Table 546.Break protection disarming conditions . . . . .2858
Table 547.DMA request . . . . .2871
Table 548.Effect of low-power modes on TIM15/TIM16/TIM17 . . . . .2871
Table 549.Interrupt requests . . . . .2872
Table 550.Output control bits for complementary tim_ocx and tim_ocxn channels with break feature (TIM15) . . . . .2887
Table 551.TIM15 register map and reset values . . . . .2900
Table 552.Output control bits for complementary tim_oc1 and tim_oc1n channels with break feature (TIM16/TIM17) . . . . .2913
Table 553.TIM16/TIM17 register map and reset values . . . . .2927
Table 554.STM32N6x5/x7xx LPTIM features . . . . .2930
Table 555.LPTIM1/2/3 input/output pins . . . . .2932
Table 556.LPTIM4/5 input/output pins . . . . .2932
Table 557.LPTIM1/2/3 internal signals . . . . .2933
Table 558.LPTIM4/5 internal signals . . . . .2933
Table 559.LPTIM1/2/3/4/5 external trigger connections . . . . .2934
Table 560.LPTIM1/2/3 input 1 connections . . . . .2934
Table 561.LPTIM1/2/3 input 2 connections . . . . .2934
Table 562.LPTIM1/2/3 input capture 1 connections . . . . .2934
Table 563.LPTIM1 input capture 2 connections . . . . .2935
Table 564.LPTIM2 input capture 2 connections . . . . .2935
Table 565.LPTIM3 input capture 2 connections . . . . .2935
Table 566.Prescaler division ratios . . . . .2937
Table 567.Encoder counting scenarios . . . . .2944
Table 568.Input capture Glitch filter latency (in counter step unit). . . . .2948
Table 569.Effect of low-power modes on the LPTIM. . . . .2952
Table 570.Interrupt events. . . . .2953
Table 571.LPTIM register map and reset values. . . . .2977
Table 572.IWDG features . . . . .2980
Table 573.IWDG delays versus actions . . . . .2981
Table 574.IWDG internal input/output signals . . . . .2982
Table 575.Effect of low power modes on IWDG . . . . .2987
Table 576.IWDG interrupt request. . . . .2989
Table 577.IWDG register map and reset values . . . . .2995
Table 578.WWDG features . . . . .2996
Table 579.WWDG internal input/output signals. . . . .2997
Table 580.WWDG interrupt requests. . . . .3000
Table 581.WWDG register map and reset values . . . . .3002
Table 582.RTC input/output pins . . . . .3006
Table 583.RTC internal input/output signals . . . . .3006
Table 584.RTC interconnection . . . . .3007
Table 585.RTC pin PC13 configuration . . . . .3007
Table 586.RTC_OUT mapping . . . . .3009
Table 587.Effect of low-power modes on RTC . . . . .3025
Table 588.RTC pins functionality over modes. . . . .3025
Table 589.Nonsecure interrupt requests . . . . .3026
Table 590.Secure interrupt requests . . . . .3026
Table 591.RTC register map and reset values . . . . .3056
Table 592.TAMP input/output pins . . . . .3061
Table 593.TAMP internal input/output signals. . . . .3061
Table 594.TAMP interconnection . . . . .3062
Table 595.Device resource x tamper protection . . . . .3067
Table 596.Active tamper output change period . . . . .3071
Table 597.Minimum ATPER value. . . . .3072
Table 598.Active tamper filtered pulse duration . . . . .3073
Table 599.Effect of low-power modes on TAMP . . . . .3075
Table 600.TAMP pins functionality over modes . . . . .3075
Table 601.Interrupt requests . . . . .3075
Table 602.TAMP register map and reset values . . . . .3103
Table 603.I2C implementation. . . . .3106
Table 604.I2C input/output pins. . . . .3107
Table 605.I2C internal input/output signals . . . . .3108
Table 606.Comparison of analog and digital filters . . . . .3110
Table 607.I 2 C-bus and SMBus specification data setup and hold times . . . . .3112
Table 608.I2C configuration. . . . .3116
Table 609.I 2 C-bus and SMBus specification clock timings . . . . .3127
Table 610.Timing settings for f I2CCLK of 8 MHz. . . . .3137
Table 611.Timing settings for f I2CCLK of 16 MHz. . . . .3137
Table 612.SMBus timeout specifications . . . . .3139
Table 613.SMBus with PEC configuration . . . . .3141
Table 614.TIMEOUTA[11:0] for maximum \( t_{TIMEOUT} \) of 25 ms. . . . .3142
Table 615.TIMEOUTB[11:0] for maximum \( t_{LOW:SEXT} \) and \( t_{LOW:MEXT} \) of 8 ms . . . . .3142
Table 616.TIMEOUTA[11:0] for maximum \( t_{IDLE} \) of 50 \( \mu s \) . . . . .3142
Table 617.Effect of low-power modes to I2C. . . . .3152
Table 618.I2C interrupt requests . . . . .3152
Table 619.I2C register map and reset values . . . . .3168
Table 620.I3C instantiation . . . . .3171
Table 621.I3C wake-up . . . . .3171
Table 622.I3C FIFOs implementation . . . . .3171
Table 623.I3C interrupt(s) . . . . .3172
Table 624.I3C peripheral controller/target features versus MIPI v1.1 . . . . .3173
Table 625.I3C input/output pins. . . . .3174
Table 626.I3C internal input/output signals . . . . .3174
Table 627.I3C register usage . . . . .3186
Table 628.I3C registers/fields usage versus controller state . . . . .3187
Table 629.I3C registers/fields usage versus target state. . . . .3190
Table 630.List of supported I3C CCCs, as controller/target . . . . .3193
Table 631.I3C controller error management . . . . .3225
Table 632.I3C target error management . . . . .3227
Table 633.Effect of low-power modes . . . . .3231
Table 634.I3C interrupt requests . . . . .3232
Table 635.I3C register map and reset values . . . . .3277
Table 636.Instance implementation on STM32N6x5/x7xx . . . . .3281
Table 637.USART/LPUART features . . . . .3282
Table 638.USART/UART input/output pins . . . . .3284
Table 639.USART internal input/output signals. . . . .3285
Table 640.Noise detection from sampled data . . . . .3297
Table 641.Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .3301
Table 642.Tolerance of the USART receiver when BRR[3:0] is different from 0000. . . . .3301
Table 643.USART frame formats . . . . .3306
Table 644.Effect of low-power modes on the USART . . . . .3329
Table 645.USART interrupt requests. . . . .3330
Table 646.USART register map and reset values . . . . .3368
Table 647.Instance implementation on STM32N6x5/x7xx . . . . .3371
Table 648.USART/LPUART features . . . . .3371
Table 649.LPUART input/output pins . . . . .3374
Table 650.LPUART internal input/output signals. . . . .3374
Table 651.Error calculation for programmed baud rates at lpuart_ker_ck_pres= 32.768 kHz . . . . .3385
Table 652.Tolerance of the LPUART receiver. . . . .3386
Table 654.Effect of low-power modes on the LPUART . . . . .3398
Table 655.LPUART interrupt requests. . . . .3399
Table 656.LPUART register map and reset values . . . . .3425
Table 657.SPI features . . . . .3428
Table 658.SPI/I2S input/output pins . . . . .3431
Table 659.SPI internal input/output signals . . . . .3431
Table 660.Effect of low-power modes on the SPI . . . . .3458
Table 661.SPI wake-up and interrupt requests . . . . .3459
Table 662.Bitfields usable in PCM/I2S mode . . . . .3461
Table 663.WS and CK level before SPI/I2S is enabled when AFCNTR = 1 . . . . .3470
Table 664.Serial data line swapping . . . . .3470
Table 665.CLKGEN programming examples for usual I2S frequencies . . . . .3474
Table 666.I2S interrupt requests . . . . .3483
Table 667.SPI register map and reset values . . . . .3500
Table 668.SAI features . . . . .3503
Table 669.SAI internal input/output signals . . . . .3505
Table 670.SAI input/output pins. . . . .3505
Table 671.External synchronization selection . . . . .3508
Table 672.MCLK_x activation conditions. . . . .3513
Table 673.Clock generator programming examples . . . . .3516
Table 674.SAI_A configuration for TDM mode . . . . .3523
Table 675.TDM frame configuration examples . . . . .3525
Table 676.SOPD pattern . . . . .3529
Table 677.Parity bit calculation . . . . .3529
Table 678.Audio sampling frequency versus symbol rates . . . . .3530
Table 679.SAI interrupt sources . . . . .3539
Table 680.SAI register map and reset values . . . . .3568
Table 681.SPDIFRX internal input/output signals . . . . .3571
Table 682.SPDIFRX pins. . . . .3571
Table 683.Transition sequence for preamble . . . . .3577
Table 684.Minimum spdifrx_ker_ck frequency versus audio sampling rate . . . . .3587
Table 685.Conditions of spdifrx_symb_ck generation. . . . .3588
Table 686.Bit field property versus SPDIFRX state. . . . .3591
Table 687.SPDIFRX interface register map and reset values . . . . .3603
Table 688.MDIOS input/output signals connected to package pins or balls . . . . .3605
Table 689.MDIOS internal input/output signals . . . . .3605
Table 690.Interrupt control bits . . . . .3610
Table 691.MDIOS register map and reset values . . . . .3615
Table 692.CAN subsystem I/O signals . . . . .3617
Table 693.CAN subsystem I/O pins. . . . .3618
Table 694.CAN triggers . . . . .3618
Table 695.Main features . . . . .3620
Table 696.DLC coding in FDCAN . . . . .3625
Table 697.Example of filter configuration for Rx buffers . . . . .3638
Table 698.Example of filter configuration for Debug messages . . . . .3639
Table 699.Possible configurations for frame transmission . . . . .3639
Table 700.Tx buffer/FIFO - Queue element size . . . . .3640
Table 701.First byte of level 1 reference message . . . . .3650
Table 702.First four bytes of level 2 reference message. . . . .3651
Table 703.First four bytes of level 0 reference message. . . . .3651
Table 704.TUR configuration example . . . . .3652
Table 705.System matrix, Node A. . . . .3657
Table 706.Trigger list, Node A. . . . .3658
Table 707.Number of data bytes transmitted with a reference message. . . . .3665
Table 708.Rx buffer and FIFO element . . . . .3672
Table 709.Rx buffer and FIFO element description. . . . .3672
Table 710.Tx buffer and FIFO element . . . . .3674
Table 711.Tx buffer element description . . . . .3674
Table 712.Tx Event FIFO element. . . . .3676
Table 713.Tx Event FIFO element description . . . . .3676
Table 714.Standard message ID filter element . . . . .3677
Table 715.Standard message ID filter element field description . . . . .3678
Table 716.Extended message ID filter element. . . . .3679
Table 717.Extended message ID filter element field description. . . . .3679
Table 718.Trigger memory element. . . . .3680
Table 719.Trigger memory element description . . . . .3680
Table 720.FDCAN register map and reset values . . . . .3718
Table 721.FDCAN TT register map and reset values . . . . .3740
Table 722.CCU register map and reset values . . . . .3746
Table 723.USB2 OTG high-speed Port 1 pins. . . . .3749
Table 724.USB2 OTG high-speed Port 1 internal signals . . . . .3750
Table 725.USB2 OTG high-speed Port 1 interrupt . . . . .3751
Table 726.USB2 OTG high-speed Port 1 wake-up events . . . . .3751
Table 727.USB2 OTG high-speed Port 2 pins. . . . .3753
Table 728.USB2 OTG high-speed Port 2 internal signals . . . . .3753
Table 729.USB2 OTG high-speed Port 2 interrupts . . . . .3755
Table 730.USB2 OTG high-speed Port 2 wake-up events . . . . .3755
Table 731.USB Type-C and power delivery pins. . . . .3758
Table 732.USB Type-C and power delivery internal signals . . . . .3758
Table 733.USB Type-C and power delivery interrupt . . . . .3759
Table 734.USB Type-C and power delivery events. . . . .3759
Table 735.OTG speeds supported . . . . .3761
Table 736.OTG implementation. . . . .3763
Table 737.OTG input/output pins. . . . .3764
Table 738.OTG input/output signals . . . . .3765
Table 739.Compatibility of STM32 low power modes with the OTG . . . . .3775
Table 740.Core global control and status registers (CSRs). . . . .3783
Table 741.Host-mode control and status registers (CSRs) . . . . .3784
Table 742.Device-mode control and status registers . . . . .3785
Table 743.Data FIFO (DFIFO) access register map . . . . .3787
Table 744.Power and clock gating control and status registers . . . . .3788
Table 745.TRDT values. . . . .3794
Table 746.Minimum duration for soft disconnect. . . . .3837
Table 747.OTG register map and reset values . . . . .3863
Table 748.USBPHYC implementation. . . . .3928
Table 749.USBPHYC register map and reset values . . . . .3936
Table 750.UCPD implementation . . . . .3938
Table 751.UCPD signals on pins. . . . .3939
Table 752.UCPD internal signals. . . . .3939
Table 753.4b5b symbol encoding table. . . . .3941
Table 754.Ordered sets. . . . .3943
Table 755.Validation of ordered sets. . . . .3943
Table 756.Data size. . . . .3943
Table 757.Coding for ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx . . . . .3952
Table 758.Type-C sequence (source: 3A); cable/sink connected (Rd on CC1; Ra on CC2) . . . . .3953
Table 759.Effect of low power modes on the UCPD . . . . .3955
Table 760.UCPD interrupt requests. . . . .3956
Table 761.UCPD register map and reset values . . . . .3971
Table 762.Ethernet peripheral pins . . . . .3978
Table 763.Ethernet internal input/output signals . . . . .3979
Table 764.Fixed priority scheme for DMA channels . . . . .3993
Table 765.Routing DA/SA failed packets to Rx queue . . . . .3997
Table 766.Routing DA/SA pass but VLAN filter fail packets to Rx queue . . . . .3998
Table 767.Priority routing of filter pass packets when OMCBCQ = 0. . . . .3998
Table 768.Priority routing of filter pass packets when OMCBCQ = 1 . . . . .3998
Table 769.Weight for DMA channels . . . . .4001
Table 770.Example of credit value per transmit cycle . . . . .4002
Table 771.Double VLAN processing features in Tx path . . . . .4005
Table 772.Double VLAN processing in Rx path . . . . .4006
Table 773.VLAN insertion or replacement based on VLTi bit . . . . .4007
Table 774.Destination address filtering . . . . .4011
Table 775.Source address filtering . . . . .4012
Table 776.VLAN match status . . . . .4013
Table 777.OTS and ITS bit values with at least one perfect filter enabled . . . . .4016
Table 778.OTS and ITS bit values with only VLAN Hash filter enabled . . . . .4017
Table 779.Rx Queue routing table for Unicast-tagged packets . . . . .4018
Table 780.Ordinary clock: PTP messages for snapshot . . . . .4021
Table 781.End-to-end transparent clock: PTP messages for snapshot . . . . .4022
Table 782.Peer-to-peer transparent clock: PTP messages for snapshot . . . . .4023
Table 783.Egress and ingress latency for PHY interfaces . . . . .4027
Table 784.Minimum PTP clock frequency example . . . . .4027
Table 785.Message format defined in IEEE 1588-2008 . . . . .4028
Table 786.Message format defined in IEEE 1588-2008 . . . . .4029
Table 787.IPv6-UDP PTP packet fields required for control and status . . . . .4030
Table 788.Ethernet PTP packet fields required for control and status . . . . .4031
Table 789.Timestamp Snapshot Dependency on ETH_MACTSCR bits . . . . .4032
Table 790.PTP message generation criteria . . . . .4038
Table 791.Common PTP message header fields . . . . .4040
Table 792.MAC Transmit PTP mode and one-step timestamping operation . . . . .4043
Table 793.External memory used for holding the two gate-control lists . . . . .4048
Table 794.GCL and associated registers - BTR and CTR . . . . .4052
Table 795.GCL and associated registers - BTR and CTR, execution time > CycleTime . . . . .4053
Table 796.GCL and Associated Registers - BTR and CTR . . . . .4055
Table 797.Extending to New List By Truncating the Current List . . . . .4056
Table 798.Switching to New List By Extending the Current List . . . . .4057
Table 799.Gate Control List When FPE is disabled . . . . .4059
Table 800.Gate Control List When FPE is enabled . . . . .4059
Table 801.Valid SMD Values of mPacket . . . . .4062
Table 802.Valid frag_count values . . . . .4062
Table 803.Current and Previous SMD Values . . . . .4063
Table 804.Current and previous SMD values . . . . .4063
Table 805.Preemption Control Values on MRI Interface for Various Frame Types . . . . .4067
Table 806.MMC Counters and Associated Interrupt Registers . . . . .4068
Table 807.Transmit checksum offload engine functions for different packet types . . . . .4077
Table 808.Receive checksum offload engine functions for different packet types . . . . .4080
Table 809.TSO: TCP and IP header fields . . . . .4084
Table 810.Pause packet fields . . . . .4089
Table 811.Tx MAC flow control . . . . .4090
Table 812.Rx MAC flow control . . . . .4091
Table 813.Size of the maximum receive packet . . . . .4093
Table 814.MCD clock selection . . . . .4096
Table 815.MDIO Clause 45 frame structure . . . . .4097
Table 816.MDIO Clause 22 frame structure . . . . .4098
Table 817.Remote wake-up packet filter register . . . . .4111
Table 818.Description of the remote wake-up filter fields . . . . .4111
Table 819.Remote wake-up packet and PMT interrupt generation . . . . .4113
Table 820.Transfer complete interrupt behavior . . . . .4122
Table 821.TDES0 normal descriptor (read format) . . . . .4152
Table 822.TDES1 normal descriptor (read format) . . . . .4153
Table 823.TDES2 normal descriptor (read format) . . . . .4153
Table 824.TDES3 normal descriptor (read format) . . . . .4154
Table 825.TDES0 normal descriptor (write-back format). . . . .4157
Table 826.TDES1 normal descriptor (write-back format). . . . .4157
Table 827.TDES2 normal descriptor (write-back format). . . . .4158
Table 828.TDES3 normal descriptor (write-back format). . . . .4158
Table 829.TDES0 context descriptor. . . . .4162
Table 830.TDES1 context descriptor. . . . .4162
Table 831.TDES2 context descriptor. . . . .4163
Table 832.TDES3 context descriptor. . . . .4163
Table 833.RDES0 normal descriptor (read format) . . . . .4166
Table 834.RDES1 normal descriptor (read format) . . . . .4166
Table 835.RDES2 normal descriptor (read format) . . . . .4166
Table 836.RDES3 normal descriptor (read format) . . . . .4167
Table 837.RDES0 normal descriptor (write-back format) . . . . .4168
Table 838.RDES1 normal descriptor (write-back format) . . . . .4169
Table 839.RDES2 normal descriptor (write-back format) . . . . .4171
Table 840.RDES3 normal descriptor (write-back format) . . . . .4173
Table 841.RDES0 context descriptor . . . . .4176
Table 842.RDES1 context descriptor . . . . .4177
Table 843.RDES2 context descriptor . . . . .4177
Table 844.RDES3 context descriptor . . . . .4177
Table 845.Enhanced normal descriptor (read format) . . . . .4178
Table 846.ETH_DMA common register map and reset values . . . . .4207
Table 847.ETH_DMA_CH0 register map and reset values . . . . .4208
Table 848.ETH_DMA_CH1 register map and reset values . . . . .4210
Table 849.ETH_MTL register map and reset values . . . . .4239
Table 850.Giant Packet Status based on S2KP and JE Bits . . . . .4248
Table 851.Packet Length based on the CST and ACS bits . . . . .4248
Table 852.Ethernet MAC register map and reset values . . . . .4356
Table 853.Muxing of HDP signals . . . . .4368
Table 854.HDP register map and reset values . . . . .4372
Table 855.SWJ-DP pins . . . . .4377
Table 856.Trace port pins . . . . .4377
Table 857.Serial-wire trace port pins . . . . .4377
Table 858.Trigger pins . . . . .4378
Table 859.Authentication signal initial states . . . . .4381
Table 860.JTAG-DP data registers . . . . .4385
Table 861.Packet request . . . . .4386
Table 862.ACK response . . . . .4387
Table 863.Data transfer . . . . .4387
Table 864.Debug port registers . . . . .4388
Table 865.Debug port register map and reset values . . . . .4395
Table 866.AP1-2 authentication behavior . . . . .4397
Table 867.AP0 register map and reset values . . . . .4401
Table 868.AP1 register map and reset values . . . . .4405
Table 869.AP2 register map and reset values . . . . .4410
Table 870.System ROM table . . . . .4411
Table 871.MCU ROM table . . . . .4411
Table 872.System ROM table register map and reset values . . . . .4416
Table 873.Processor ROM table . . . . .4417
Table 874.Processor ROM register map and reset values . . . . .4422
Table 875.DWT register map and reset values . . . . .4435
Table 876.PMU register map and reset values . . . . .4450
Table 877.ITM register map and reset values . . . . .4460
Table 878.BPU register map and reset values . . . . .4467
Table 879.ETM register map and reset values . . . . .4492
Table 880.Trace subsystem ROM table . . . . .4496
Table 881.Trace subsystem ROM table register map and reset values . . . . .4502
Table 882.TSGEN register map and reset values . . . . .4509
Table 883.Trace and debug subsystem CTI_0 inputs . . . . .4512
Table 884.Trace and debug subsystem CTI_0 outputs . . . . .4512
Table 885.Trace and debug subsystem CTI_1 inputs . . . . .4512
Table 886.Trace and debug subsystem CTI_1 outputs . . . . .4513
Table 887.Cortex-M55 CTI inputs . . . . .4513
Table 888.Cortex-M55 CTI outputs . . . . .4513
Table 889.CTI register map and reset values . . . . .4527
Table 890.CSTF register map and reset values . . . . .4537
Table 891.ETF register map and reset values . . . . .4556
Table 892.ETR scatter-gather page format . . . . .4561
Table 893.ETR register map and reset values . . . . .4580
Table 894.TPIU register map and reset values . . . . .4597
Table 895.ETR replicator allocation . . . . .4599
Table 896.Replicator register map and reset values . . . . .4608
Table 897.SWO register map and reset values . . . . .4618
Table 898.STM extended stimulus port memory map . . . . .4620
Table 899.STM trace packet ID mapping to AXI masters . . . . .4621
Table 900.Hardware event mapping . . . . .4622
Table 901.STM register map and reset values . . . . .4645
Table 902.DBGMCU register map and reset values . . . . .4658
Table 903.Document revision history . . . . .4667

List of figures

Figure 1. Interconnect top view - STM32N6x7 devices . . . . . 160

Figure 2. Interconnect top view - STM32N6x5 devices . . . . . 161

Figure 3. Key management principle . . . . . 194

Figure 4. BSEC block diagram. . . . . 202

Figure 5. BSEC fuse mapping overview . . . . . 204

Figure 6. RISAF block diagram . . . . . 260

Figure 7. RISAF region programming . . . . . 261

Figure 8. RISAF region on-the-fly resizing . . . . . 264

Figure 9. IAC block diagram . . . . . 281

Figure 10. FLEXMEM versus retention . . . . . 291

Figure 11. ICACHE block diagram . . . . . 310

Figure 12. ICACHE TAG and data memories functional view . . . . . 312

Figure 13. CACHEAXI block diagram . . . . . 325

Figure 14. CACHEAXI TAG and data memories functional view . . . . . 328

Figure 15. Power control block diagram . . . . . 348

Figure 16. Power supply overview. . . . . 352

Figure 17. System supply configurations. . . . . 353

Figure 18. Device startup (VCORE supplied directly from SMPS step-down converter). . . . . 354

Figure 19. Device startup (VCORE supplied from an external regulator) . . . . . 355

Figure 20. Backup domain . . . . . 358

Figure 21. Retention domain . . . . . 359

Figure 22. POR/PDR waveform. . . . . 361

Figure 23. BOR thresholds . . . . . 362

Figure 24. Vdda18pmu_ok reset threshold . . . . . 362

Figure 25. Vddcore_ok reset thresholds . . . . . 363

Figure 26. VDDCORE monitoring . . . . . 364

Figure 27. PVD thresholds. . . . . 364

Figure 28. V08CAP thresholds. . . . . 367

Figure 29. Temperature thresholds . . . . . 368

Figure 30. VCORE voltage scaling versus system power modes . . . . . 373

Figure 31. Dynamic voltage scaling in Run mode . . . . . 374

Figure 32. Dynamic voltage scaling behavior in Stop mode . . . . . 375

Figure 33. Dynamic Voltage Scaling from Standby mode . . . . . 376

Figure 34. RCC block diagram. . . . . 412

Figure 35. Simplified reset circuit. . . . . 415

Figure 36. NRST reset pulse control . . . . . 418

Figure 37. Boot sequences versus system states . . . . . 421

Figure 38. Top-level clock tree. . . . . 423

Figure 39. HSE clock source . . . . . 425

Figure 40. HSE clock generation. . . . . 426

Figure 41. LSE clock generation . . . . . 427

Figure 42. HSI calibration flow. . . . . 430

Figure 43. MSI calibration flow. . . . . 431

Figure 44. PLL block diagram . . . . . 436

Figure 45. Spread spectrum modulation . . . . . 438

Figure 46. Core and bus clock generation. . . . . 442

Figure 47. Key signals controlling low-power modes. . . . . 443

Figure 48. Clock distribution for the NPU. . . . . 454

Figure 49.Clock distribution for PSSI, CSI, and DCMIPP . . . . .455
Figure 50.Clock distribution for GPU, ICACHE, and GFXMMU . . . . .456
Figure 51.Clock distribution for LTDC . . . . .456
Figure 52.Clock distribution for VENC . . . . .457
Figure 53.Clock distribution for OTG1, OTG2, and UCPD1 . . . . .458
Figure 54.Clock distribution for ETH1 . . . . .459
Figure 55.Clock management for ETH1 . . . . .460
Figure 56.Clock distribution for MDIOS . . . . .461
Figure 57.Clock distribution for FMC and MCE4 . . . . .462
Figure 58.Clock distribution for XSPIs and MCE1/2/3 . . . . .463
Figure 59.Clock distribution for SDMMCx and companions . . . . .465
Figure 60.Clock distribution for ADCs . . . . .466
Figure 61.Clock distribution for RTC . . . . .466
Figure 62.Clock distribution for IWDG and WWDG . . . . .467
Figure 63.Clock distribution for trace and debug . . . . .468
Figure 64.Kernel clock switching . . . . .469
Figure 65.Enable logic details for peripheral kernel clock . . . . .470
Figure 66.Basic structure of an I/O port bit . . . . .784
Figure 67.Input floating/pull-up/pull-down configurations . . . . .788
Figure 68.Output configuration . . . . .789
Figure 69.AF configuration . . . . .790
Figure 70.Programmable analog configuration . . . . .790
Figure 71.I/O compensation cell control overview . . . . .810
Figure 72.HPDMA block diagram . . . . .845
Figure 73.HPDMA channel direct programming without linked-list (HPDMA_CxLLR = 0) . . . . .847
Figure 74.HPDMA channel suspend and resume sequence . . . . .848
Figure 75.HPDMA channel abort and restart sequence . . . . .849
Figure 76.Static linked-list data structure (all Uxx = 1) of a linear addressing channel x . . . . .850
Figure 77.Static linked-list data structure (all Uxx = 1) of a 2D addressing channel x . . . . .851
Figure 78.HPDMA dynamic linked-list data structure of linear addressing channel x . . . . .852
Figure 79.HPDMA dynamic linked-list data structure of a 2D addressing channel x . . . . .852
Figure 80.HPDMA channel execution and linked-list programming
in run-to-completion mode (HPDMA_CxCR.LSM = 0) . . . . .		854
Figure 81.Inserting a LLI n with an auxiliary HPDMA channel y . . . . .856
Figure 82.HPDMA channel execution and linked-list programming
in link step mode (HPDMA_CxCR.LSM = 1) . . . . .		858
Figure 83.Building LLI n+1 : HPDMA dynamic linked-lists in link step mode . . . . .859
Figure 84.Replace with a new LLI n' in register file in link step mode . . . . .860
Figure 85.Replace with a new LLI n' and LLI n+1' in memory in link step mode (option 1) . . . . .861
Figure 86.Replace with a new LLI n' and LLI n+1' in memory in link step mode (option 2) . . . . .862
Figure 87.HPDMA channel execution and linked-list programming . . . . .864
Figure 88.Programmed 2D addressing . . . . .867
Figure 89.HPDMA arbitration policy . . . . .882
Figure 90.Trigger hit, memorization and overrun waveform . . . . .886
Figure 91.HPDMA circular buffer programming: update of the memory start address
with a linear addressing channel . . . . .		887
Figure 92.Shared HPDMA channel with circular buffering: update of the memory
start address with a linear addressing channel . . . . .		888
Figure 93.GPDMA block diagram . . . . .942
Figure 94.GPDMA channel direct programming without linked-list (GPDMA_CxLLR = 0) . . . . .943
Figure 95.GPDMA channel suspend and resume sequence . . . . .944
Figure 96.GPDMA channel abort and restart sequence . . . . .945
Figure 97.Static linked-list data structure (all Uxx = 1) of a linear addressing channel x . . . . .946
Figure 98.Static linked-list data structure (all Uxx = 1) of a 2D addressing channel x . . . . .947
Figure 99.GPDMA dynamic linked-list data structure of a linear addressing channel x . . . . .948
Figure 100.GPDMA dynamic linked-list data structure of a 2D addressing channel x . . . . .948
Figure 101.GPDMA channel execution and linked-list programming in run-to-completion mode (GPDMA_CxCR.LSM = 0) . . . . .950
Figure 102.Inserting a LLI n with an auxiliary GPDMA channel y . . . . .952
Figure 103.GPDMA channel execution and linked-list programming in link step mode (GPDMA_CxCR.LSM = 1) . . . . .954
Figure 104.Building LLI n+1 : GPDMA dynamic linked-lists in link step mode . . . . .955
Figure 105.Replace with a new LLI n' in register file in link step mode . . . . .956
Figure 106.Replace with a new LLI n' and LLI n+1' in memory in link step mode (option 1) . . . . .957
Figure 107.Replace with a new LLI n' and LLI n+1' in memory in link step mode (option 2) . . . . .958
Figure 108.GPDMA channel execution and linked-list programming . . . . .960
Figure 109.Programmed 2D addressing . . . . .963
Figure 110.GPDMA arbitration policy . . . . .970
Figure 111.Trigger hit, memorization, and overrun waveform . . . . .973
Figure 112.GPDMA circular buffer programming: update of the memory start address with a linear addressing channel . . . . .974
Figure 113.Shared GPDMA channel with circular buffering: update of the memory start address with a linear addressing channel . . . . .975
Figure 114.Stream processing engine . . . . .1012
Figure 115.Chaining of processing units . . . . .1013
Figure 116.Neural-ART 14 NPU accelerator . . . . .1014
Figure 117.Stream engines . . . . .1017
Figure 118.Two dimensional lossy compression . . . . .1018
Figure 119.Decompression unit (DECUN) . . . . .1018
Figure 120.Convolutional accelerator (CONVACC) . . . . .1019
Figure 121.Example of pooling operations . . . . .1020
Figure 122.Pooling unit (POOL) . . . . .1020
Figure 123.Activation unit (ACTIV) . . . . .1021
Figure 124.Arithmetic unit (ARITH) . . . . .1024
Figure 125.Memory to memory transfer . . . . .1025
Figure 126.Simple processing . . . . .1026
Figure 127.Multiple processing . . . . .1026
Figure 128.Classical Conv-Pool-ReLU . . . . .1026
Figure 129.Chained convolutions . . . . .1027
Figure 130.Split convolution . . . . .1027
Figure 131.Neural-ART 14 integration . . . . .1030
Figure 132.DMA2D block diagram . . . . .1034
Figure 133.Intel 8080 16-bit mode (RGB565) . . . . .1041
Figure 134.Intel 8080 18/24-bit mode (RGB888) . . . . .1041
Figure 135.GFXMMU block diagram . . . . .1067
Figure 136.Virtual buffer . . . . .1069
Figure 137.Virtual buffer and physical buffer memory map . . . . .1070
Figure 138.MMU block diagram . . . . .1071
Figure 139.Block validation/comparator implementation . . . . .1073
Figure 140.GFXTIM block diagram . . . . .1083
Figure 141. Clock generator . . . . .1085
Figure 142. Waveforms in standalone . . . . .1087
Figure 143. Active counters and signals in standalone . . . . .1087
Figure 144. Waveforms with external HSYNC and VSYNC. . . . .1087
Figure 145. Waveforms with external HSYNC only . . . . .1088
Figure 146. Active counters and signals with external HSYNC only . . . . .1088
Figure 147. Waveforms with external VSYNC only . . . . .1088
Figure 148. Active counters with external VSYNC only . . . . .1089
Figure 149. Prescaling when external VSYNC only. . . . .1089
Figure 150. Waveforms with external CSYNC only . . . . .1089
Figure 151. Active counters and signals with external CSYNC only . . . . .1090
Figure 152. Prescaling when external CSYNC only . . . . .1090
Figure 153. Tearing-effect configurations . . . . .1092
Figure 154. Watchdog timer. . . . .1093
Figure 155. EXTI block diagram . . . . .1127
Figure 156. Configurable event trigger logic CPU wake-up. . . . .1131
Figure 157. EXTI direct events . . . . .1132
Figure 158. EXTI mux GPIO selection. . . . .1133
Figure 159. CRC calculation unit block diagram . . . . .1171
Figure 160. FMC block diagram. . . . .1179
Figure 161. Mode 1 read access waveforms . . . . .1194
Figure 162. Mode 1 write access waveforms. . . . .1194
Figure 163. Mode A read access waveforms. . . . .1196
Figure 164. Mode A write access waveforms . . . . .1197
Figure 165. Mode 2 and mode B read access waveforms. . . . .1199
Figure 166. Mode 2 write access waveforms. . . . .1199
Figure 167. Mode B write access waveforms . . . . .1200
Figure 168. Mode C read access waveforms . . . . .1202
Figure 169. Mode C write access waveforms . . . . .1202
Figure 170. Mode D read access waveforms . . . . .1204
Figure 171. Mode D write access waveforms . . . . .1205
Figure 172. Muxed read access waveforms . . . . .1207
Figure 173. Muxed write access waveforms . . . . .1208
Figure 174. Asynchronous wait during a read access waveforms. . . . .1211
Figure 175. Asynchronous wait during a write access waveforms. . . . .1211
Figure 176. Wait configuration waveforms. . . . .1213
Figure 177. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM). . . . .1214
Figure 178. Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . .1216
Figure 179. NAND flash controller waveforms for common memory access. . . . .1229
Figure 180. NAND flash controller waveforms for TCLR and TAR timings . . . . .1230
Figure 181. Access to NAND flash memory . . . . .1231
Figure 182. NAND flash page (2 Kbytes) layout with BCH . . . . .1235
Figure 183. Example of 2 Kbyte page program sequence with 4-bit BCH. . . . .1237
Figure 184. Chained-page read command timings . . . . .1239
Figure 185. Example of 2-Kbyte page read sequence with 4-bit BCH. . . . .1240
Figure 186. SDRAM burst write waveforms
(AXI 4-word transfer, no page boundary crossing) . . . . .		1269
Figure 187. SDRAM burst read waveforms
(AXI 4-word transfer, no page boundary crossing) . . . . .		1270
Figure 188. SDRAM burst read crossing a row boundary . . . . .1271
Figure 189. SDRAM burst write crossing a row boundary . . . . .1272
Figure 190. Read followed by write operation . . . . .1272
Figure 191. Write followed by read operation . . . . .1273
Figure 192. SDRAM Self-refresh waveforms . . . . .1274
Figure 193. Power-down mode . . . . .1275
Figure 194. Power-down with Auto-refresh . . . . .1276
Figure 195. XSPI block diagram for 16-bit configuration (1) . . . . .1291
Figure 196. XSPI block diagram for dual-octal configuration (1) . . . . .1292
Figure 197. XSPI block diagram for octal configuration . . . . .1293
Figure 198. XSPI block diagram in quad configuration . . . . .1294
Figure 199. XSPI block diagram for dual-quad configuration . . . . .1295
Figure 200. SDR read command in 16-bit configuration . . . . .1297
Figure 201. DTR read in octal-SPI mode with DQS (Macronix mode) example . . . . .1300
Figure 202. SDR write command in octal-SPI mode example . . . . .1302
Figure 203. DTR write in octal-SPI mode (Macronix mode) example . . . . .1303
Figure 204. Example of HyperBus read operation (8-bit data mode) . . . . .1306
Figure 205. HyperBus write operation with initial latency (8-bit data mode) . . . . .1307
Figure 206. HyperBus read operation with additional latency (8-bit data mode) . . . . .1308
Figure 207. HyperBus write operation with additional latency (8-bit data mode) . . . . .1308
Figure 208. HyperBus write operation with no latency (register write) . . . . .1309
Figure 209. HyperBus read operation page crossing with latency (8-bit data mode) . . . . .1309
Figure 210. HyperBus write operation with initial latency (16-bit mode) . . . . .1310
Figure 211. D0/D1 data ordering in octal-SPI DTR mode (Micron) - Read access . . . . .1317
Figure 212. OctaRAM read operation with reverse data ordering D1/D0 . . . . .1317
Figure 213. NCS when CKMODE = 0 (T = CLK period) . . . . .1324
Figure 214. Example of software control of two external memories . . . . .1325
Figure 215. Example of hardware-controlled extended memory support . . . . .1326
Figure 216. XSPIM block diagram . . . . .1359
Figure 217. XSPI direct octal mode . . . . .1362
Figure 218. XSPI direct 16-bit mode . . . . .1363
Figure 219. XSPI dual-octal mode . . . . .1364
Figure 220. XSPI swapped (octal) mode . . . . .1365
Figure 221. XSPI multiplexed mode to Port1 . . . . .1366
Figure 222. XSPI multiplexed (octal and dual-octal) mode to Port 2 . . . . .1367
Figure 223. XSPI1 and XSPI2 drive a single external memory (octal mode) . . . . .1368
Figure 224. Single XSPI driving two external memories . . . . .1369
Figure 225. SDMMC “no response” and “no data” operations . . . . .1373
Figure 226. SDMMC (multiple) block read operation . . . . .1373
Figure 227. SDMMC (multiple) block write operation . . . . .1374
Figure 228. SDMMC (sequential) stream read operation . . . . .1374
Figure 229. SDMMC (sequential) stream write operation . . . . .1374
Figure 230. SDMMC block diagram . . . . .1376
Figure 231. SDMMC Command and data phase relation . . . . .1378
Figure 232. Control unit . . . . .1380
Figure 233. Command/response path . . . . .1381
Figure 234. Command path state machine (CPSM) . . . . .1382
Figure 235. Data path . . . . .1388
Figure 236. DDR mode data packet clocking . . . . .1389
Figure 237. DDR mode CRC status / boot acknowledgment clocking . . . . .1389
Figure 238. Data path state machine (DPSM) . . . . .1390
Figure 239. CLKMUX unit . . . . .1401
Figure 240. Linked list structures . . . . .1404
Figure 241. Asynchronous interrupt generation . . . . .1407
Figure 242. Synchronous interrupt period data read . . . . .1408
Figure 243. Synchronous interrupt period data write . . . . .1408
Figure 244. Asynchronous interrupt period data read . . . . .1409
Figure 245. Asynchronous interrupt period data write . . . . .1410
Figure 246. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25. . . . .1413
Figure 247. Clock stop with SDMMC_CK for DDR50, SDR50, SDR104. . . . .1413
Figure 248. Read Wait with SDMMC_CK < 50 MHz . . . . .1414
Figure 249. Read Wait with SDMMC_CK > 50 MHz . . . . .1414
Figure 250. CMD12 stream timing . . . . .1417
Figure 251. CMD5 Sleep Awake procedure . . . . .1419
Figure 252. Normal boot mode operation . . . . .1421
Figure 253. Alternative boot mode operation. . . . .1422
Figure 254. Command response R1b busy signaling . . . . .1423
Figure 255. SDMMC state control . . . . .1424
Figure 256. Card cycle power / power up diagram . . . . .1425
Figure 257. Read block gap hardware flow timing. . . . .1426
Figure 258. CMD11 signal voltage switch sequence . . . . .1428
Figure 259. Voltage switch transceiver typical application. . . . .1430
Figure 260. DLYB block diagram . . . . .1458
Figure 261. ADC block diagram . . . . .1469
Figure 262. ADC clock scheme . . . . .1473
Figure 263. ADC1 connectivity . . . . .1475
Figure 264. ADC2 connectivity . . . . .1476
Figure 265. Enabling/disabling the ADC . . . . .1481
Figure 266. Bulb mode timing diagram . . . . .1484
Figure 267. Analog-to-digital conversion time . . . . .1489
Figure 268. Stopping ongoing regular conversions . . . . .1490
Figure 269. Stopping ongoing regular and injected conversions. . . . .1490
Figure 270. Triggers shared between ADC master and slave . . . . .1492
Figure 271. Injected conversion latency during ongoing regular conversion . . . . .1493
Figure 272. Single conversions of a sequence, software trigger . . . . .1495
Figure 273. Continuous conversion of a sequence, software trigger. . . . .1495
Figure 274. Single conversions of a sequence, hardware trigger . . . . .1496
Figure 275. Continuous conversions of a sequence, hardware trigger . . . . .1496
Figure 276. Right alignment (offset disabled, unsigned value) . . . . .1498
Figure 277. Right alignment (offset enabled, signed value). . . . .1499
Figure 278. Left alignment (offset disabled, unsigned value) . . . . .1499
Figure 279. Left alignment (offset enabled, signed value). . . . .1500
Figure 280. Example of overrun (OVRMOD = 0). . . . .1503
Figure 281. Example of overrun (OVRMOD = 1). . . . .1503
Figure 282. AUTDLY = 1, regular conversion in continuous mode, software trigger. . . . .1507
Figure 283. AUTDLY = 1, regular hardware conversions interrupted by injected conversions
(DISCEN = 0; JDISCEN = 0) . . . . .		1507
Figure 284. AUTDLY = 1, regular hardware conversions interrupted by injected conversions
(DISCEN = 1, JDISCEN = 1) . . . . .		1508
Figure 285. AUTDLY = 1, regular continuous conversions interrupted by injected conversions. . . . .1508
Figure 286. AUTDLY = 1 in autoinjection mode (JAUTO = 1) . . . . .1509
Figure 287. Analog watchdog guarded area . . . . .1510
Figure 288. ADC_AWDy_OUT signal generation (on all regular channels). . . . .1512
Figure 289. ADC_AWDy_OUT signal generation (AWDy flag not cleared by software) . . . . .1513
Figure 290. ADC_AWDy_OUT signal generation (on a single regular channel) . . . . .1513
Figure 291. ADC_AWDy_OUT signal generation (on all injected channels) . . . . .1514
Figure 292. 12-bit result oversampling with 10-bit right shift and rounding . . . . .1515
Figure 293. Triggered regular oversampling mode (TROVS bit = 1) . . . . .1517
Figure 294. Regular oversampling modes (4x ratio) . . . . .1518
Figure 295. Regular and injected oversampling modes used simultaneously . . . . .1519
Figure 296. Triggered regular oversampling with injection . . . . .1519
Figure 297. Oversampling in autoinjection mode . . . . .1520
Figure 298. Dual ADC block diagram . . . . .1522
Figure 299. Injected simultaneous mode on four channels: Dual ADC mode . . . . .1523
Figure 300. Regular simultaneous mode on 16 channels: dual ADC mode . . . . .1525
Figure 301. Interleaved mode on 1 channel in continuous conversion mode:
Dual ADC mode . . . . .		1527
Figure 302. Interleaved mode on 1 channel in single conversion mode:
Dual ADC mode . . . . .		1527
Figure 303. Interleaved conversion with injection . . . . .1528
Figure 304. Alternate trigger: injected group of each ADC . . . . .1529
Figure 305. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . .1530
Figure 306. Alternate + regular simultaneous . . . . .1530
Figure 307. Case of trigger occurring during injected conversion . . . . .1531
Figure 308. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . .1531
Figure 309. Two interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . .		1532
Figure 310. Two interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . .		1532
Figure 311. DMA requests in regular simultaneous mode when DAMDF[1:0] = 0b00 . . . . .1533
Figure 312. DMA requests in interleaved mode when DAMDF = 0b10 . . . . .1534
Figure 313. VBAT channel block diagram . . . . .1537
Figure 314. VREFINT channel block diagram . . . . .1537
Figure 315. DTS block diagram . . . . .1580
Figure 316. Serial data adapter . . . . .1583
Figure 317. SDA data format . . . . .1584
Figure 318. Falling alarms . . . . .1589
Figure 319. Rising alarms . . . . .1590
Figure 320. VREFBUF block diagram . . . . .1621
Figure 321. MDF block diagram . . . . .1629
Figure 322. SITFx overview . . . . .1632
Figure 323. SPI timing example . . . . .1633
Figure 324. Manchester timing example (SITFMOD = 11) . . . . .1635
Figure 325. CKGEN overview . . . . .1638
Figure 326. BSMX overview . . . . .1640
Figure 327. SCD functional view . . . . .1641
Figure 328. SCD timing example . . . . .1641
Figure 329. DFLT overview . . . . .1643
Figure 330. Programmable delay . . . . .1644
Figure 331. CIC3 and CIC5 frequency response with decimation ratio = 32 . . . . .1646
Figure 332. Reshape filter frequency response normalized (FRS / 2 = 1) . . . . .1651
Figure 333. Out-of-limit detector thresholds . . . . .1654
Figure 334. Trigger logic for DFLT and CKGEN . . . . .1656
Figure 335. Asynchronous continuous mode (ACQMOD[2:0] = 0) . . . . .1657
Figure 336. Asynchronous single-shot mode (ACQMOD[2:0] = 001) . . . . .1658
Figure 337. Synchronous continuous mode (ACQMOD[2:0] = 010) . . . . .1659
Figure 338. Synchronous single-shot mode (ACQMOD[2:0] = 011) . . . . .1660
Figure 339. Window continuous mode (ACQMOD[2:0] = 100) . . . . .1661
Figure 340. Snapshot mode example . . . . .1663
Figure 341. Discard function example . . . . .1664
Figure 342. Start sequence with DFLTEN, in continuous mode, audio configuration . . . . .1665
Figure 343. Start sequence with trigger input, in continuous mode, motor configuration . . . . .1666
Figure 344. Break interface simplified view . . . . .1667
Figure 345. MDF_DFLTxD data format. . . . .1667
Figure 346. Data resynchronization . . . . .1668
Figure 347. Data transfer in interleaved-transfer mode . . . . .1669
Figure 348. Data path for interleaved- and independent-transfer modes . . . . .1671
Figure 349. Example of overflow and transfer to memory . . . . .1672
Figure 350. MDF interrupt interface . . . . .1675
Figure 351. Sensor connection examples . . . . .1680
Figure 352. Global frequency response . . . . .1681
Figure 353. Detailed frequency response . . . . .1681
Figure 354. Simplified DFLT view with gain information . . . . .1683
Figure 355. ADF block diagram . . . . .1711
Figure 356. SITF overview. . . . .1713
Figure 357. SPI timing example . . . . .1714
Figure 358. Manchester timing example (SITFMOD = 11) . . . . .1715
Figure 359. CKGEN overview . . . . .1718
Figure 360. BSMX overview . . . . .1720
Figure 361. DFLT overview . . . . .1721
Figure 362. Programmable delay. . . . .1722
Figure 363. CIC4 and CIC5 frequency response with decimation ratio = 32 or 16 . . . . .1723
Figure 364. Reshape filter frequency response normalized (FRS / 2 = 1). . . . .1729
Figure 365. Trigger logic for DFLT and CKGEN . . . . .1731
Figure 366. Asynchronous continuous mode (ACQMOD[2:0] = 0) . . . . .1732
Figure 367. Asynchronous single-shot mode (ACQMOD[2:0] = 001) . . . . .1733
Figure 368. Synchronous continuous mode (ACQMOD[2:0] = 010) . . . . .1734
Figure 369. Synchronous single-shot mode (ACQMOD[2:0] = 011) . . . . .1735
Figure 370. Window continuous mode (ACQMOD[2:0] = 100) . . . . .1736
Figure 371. Discard function example . . . . .1738
Figure 372. Start sequence with DFLTEN, in continuous mode, audio configuration . . . . .1738
Figure 373. SAD block diagram . . . . .1739
Figure 374. SAD flow diagram . . . . .1741
Figure 375. SAD timing diagram example . . . . .1747
Figure 376. ADF_DFLTxD data format . . . . .1747
Figure 377. Data resynchronization . . . . .1748
Figure 378. Example of overflow and transfer to memory . . . . .1749
Figure 379. ADF interrupt interface . . . . .1752
Figure 380. Sensor connection examples . . . . .1757
Figure 381. Global frequency response. . . . .1757
Figure 382. Detailed frequency response . . . . .1758
Figure 383. Simplified DFLT view with gain information . . . . .1760
Figure 384. SAD example working with SADMOD = 01 . . . . .1763
Figure 385. SAD example working with SADMOD = 1x . . . . .1764
Figure 386. Camera subsystem block diagram . . . . .1786
Figure 387. Camera subsystem clock diagram . . . . .1787
Figure 388. DCMI block diagram . . . . .1795
Figure 389. DCMI signal waveforms . . . . .1796
Figure 390. Timing diagram . . . . .1798
Figure 391. Frame capture waveforms in snapshot mode. . . . .1800
Figure 392. Frame capture waveforms in continuous grab mode . . . . .1801
Figure 393. Coordinates and size of the window after cropping . . . . .1801
Figure 394. Data capture waveforms. . . . .1802
Figure 395. Pixel raster scan order . . . . .1803
Figure 396. DCMIPP overview. . . . .1817
Figure 397. DCMIPP block diagram . . . . .1821
Figure 398. VC flow processed by one pipe . . . . .1836
Figure 399. Two exclusive VC flows processed by one reconfigured pipe . . . . .1837
Figure 400. Two overlapping VC flows processed by two pipes . . . . .1837
Figure 401. Snapshot (CPTMODE = 1) and Continuous (CPTMODE = 0) capture modes. . . . .1838
Figure 402. Pipe0 (dump) architecture overview . . . . .1841
Figure 403. Pipe1 ISP architecture view . . . . .1846
Figure 404. Block diagram . . . . .1863
Figure 405. Downsize with coverage filtering . . . . .1866
Figure 406. Example with two ROIs. . . . .1867
Figure 407. Pipe2 architecture overview . . . . .1872
Figure 408. Use case: Pipe0 (statistics), Pipe1 (pixels). . . . .1874
Figure 409. Statistics and RGB data for single virtual channel data flow . . . . .1875
Figure 410. Three pipes within a single virtual channel in CSI2 mode . . . . .1875
Figure 411. Handling interleaved packet . . . . .1876
Figure 412. Handling interleaved packets across two pixel pipes . . . . .1876
Figure 413. Interlaced video (based on single pixel pipe) . . . . .1877
Figure 414. Interlaced video (based on two pixel pipes) . . . . .1877
Figure 415. 3D sensors (top-bottom) processed by two pixel pipes . . . . .1882
Figure 416. CSI-2 Host block diagram. . . . .2018
Figure 417. CSI-2 Host architecture . . . . .2019
Figure 418. CSI-2 Host clock domain . . . . .2021
Figure 419. Lane merger input and output (one data lane) . . . . .2022
Figure 420. Lane merger input and output (two data lanes) . . . . .2022
Figure 421. Data lane mapping . . . . .2022
Figure 422. Low-level protocol overview . . . . .2023
Figure 423. CSI2- long-packet structure for a D-PHY physical layer. . . . .2024
Figure 424. Short-packet structure based on D-PHY physical layer . . . . .2024
Figure 425. DATA ID structure in short or long packet format. . . . .2025
Figure 426. Data interleaving using data type . . . . .2026
Figure 427. Data interleaving using virtual channels . . . . .2027
Figure 428. RAW6 (BPP6) input and output format. . . . .2028
Figure 429. Raw7 (BPP7) input and output format . . . . .2029
Figure 430. Raw8 (BPP8) input and output format . . . . .2030
Figure 431. Raw 10 (BPP10) input and output format. . . . .2030
Figure 432. Raw12 (BPP12) input/output format. . . . .2031
Figure 433. Raw14 (BPP14) input format . . . . .2032
Figure 434. Raw16 (BPP16) input/output format. . . . .2033
Figure 435. PSSI block diagram . . . . .2075
Figure 436. Top-level block diagram . . . . .2075
Figure 437. Data enable in receive mode waveform diagram (CKPOL=0) . . . . .2079
Figure 438. Data enable waveform diagram in transmit mode (CKPOL=1). . . . .2079
Figure 439. Ready in receive mode waveform diagram (CKPOL=0). . . . .2080
Figure 440. Bidirectional PSSI_DE/PSSI_RDY waveform . . . . .2081
Figure 441. Bidirectional PSSI_DE/PSSI_RDY connection diagram . . . . .2081
Figure 442. Display subsystem block diagram . . . . .2089
Figure 443. Display subsystem clock diagram. . . . .2089
Figure 444. LTDC block diagram . . . . .2095
Figure 445. Layer window programmable parameters . . . . .2107
Figure 446. Blending two layers. . . . .2108
Figure 447. LTDC synchronous timings. . . . .2112
Figure 448. GPU2D block diagram . . . . .2155
Figure 449. VENC block diagram . . . . .2158
Figure 450. JPEG codec block diagram . . . . .2266
Figure 451. RNG block diagram . . . . .2288
Figure 452. NIST SP800-90B entropy source model. . . . .2289
Figure 453. RNG initialization overview. . . . .2292
Figure 454. SAES block diagram. . . . .2306
Figure 455. Encryption/ decryption typical usage . . . . .2308
Figure 456. Typical operation with authentication . . . . .2310
Figure 457. Example of suspend mode management. . . . .2311
Figure 458. ECB encryption. . . . .2312
Figure 459. ECB decryption. . . . .2312
Figure 460. CBC encryption. . . . .2313
Figure 461. CBC decryption. . . . .2313
Figure 462. Message construction in CTR mode. . . . .2316
Figure 463. CTR encryption. . . . .2317
Figure 464. Message construction in GCM . . . . .2318
Figure 465. GCM authenticated encryption . . . . .2320
Figure 466. Message construction in GMAC mode . . . . .2323
Figure 467. GMAC authentication mode . . . . .2323
Figure 468. Message construction in CCM mode . . . . .2324
Figure 469. CCM mode authenticated encryption . . . . .2326
Figure 470. Operation with wrapped keys for SAES in ECB and CBC modes . . . . .2329
Figure 471. Operation with wrapped keys for SAES in CTR mode . . . . .2332
Figure 472. Usage of Shared-key mode . . . . .2333
Figure 473. 128-bit block construction according to the data type. . . . .2336
Figure 474. Key protection mechanisms . . . . .2338
Figure 475. CRYP block diagram . . . . .2361
Figure 476. Encryption/ decryption typical usage . . . . .2363
Figure 477. Typical operation with authentication . . . . .2366
Figure 478. Example of suspend mode management. . . . .2367
Figure 479. ECB encryption. . . . .2368
Figure 480. ECB decryption. . . . .2368
Figure 481. CBC encryption. . . . .2369
Figure 482. CBC decryption. . . . .2369
Figure 483. Message construction in CTR mode. . . . .2372
Figure 484. CTR encryption. . . . .2373
Figure 485. Message construction in GCM . . . . .2375
Figure 486. GCM authenticated encryption . . . . .2376
Figure 487. Message construction in GMAC mode . . . . .2380
Figure 488. GMAC authentication mode . . . . .2380
Figure 489. Message construction in CCM mode . . . . .2381
Figure 490. CCM mode authenticated encryption . . . . .2383
Figure 491. 128-bit block construction according to the data type. . . . .2389
Figure 492. HASH block diagram . . . . .2410
Figure 493. Message data swapping feature. . . . .2412
Figure 494. HASH suspend/resume mechanism. . . . .2418
Figure 495. MCE block diagram . . . . .2432
Figure 496. MCE region programming. . . . .2433
Figure 497. MCE implementation of block ciphers . . . . .2435
Figure 498. MCE implementation of stream cipher . . . . .2436
Figure 499. PKA block diagram . . . . .2453
Figure 500. Advanced-control timer block diagram . . . . .2486
Figure 501. Counter timing diagram with prescaler division change from 1 to 2 . . . . .2492
Figure 502. Counter timing diagram with prescaler division change from 1 to 4 . . . . .2492
Figure 503. Counter timing diagram, internal clock divided by 1 . . . . .2494
Figure 504. Counter timing diagram, internal clock divided by 2 . . . . .2494
Figure 505. Counter timing diagram, internal clock divided by 4 . . . . .2495
Figure 506. Counter timing diagram, internal clock divided by N . . . . .2495
Figure 507. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded). . . . .		2496
Figure 508. Counter timing diagram, update event when ARPE = 1
(TIMx_ARR preloaded). . . . .		2497
Figure 509. Counter timing diagram, internal clock divided by 1 . . . . .2498
Figure 510. Counter timing diagram, internal clock divided by 2 . . . . .2499
Figure 511. Counter timing diagram, internal clock divided by 4 . . . . .2499
Figure 512. Counter timing diagram, internal clock divided by N . . . . .2500
Figure 513. Counter timing diagram, update event when repetition counter is not used. . . . .2500
Figure 514. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .2502
Figure 515. Counter timing diagram, internal clock divided by 2 . . . . .2502
Figure 516. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .2503
Figure 517. Counter timing diagram, internal clock divided by N . . . . .2503
Figure 518. Counter timing diagram, update event with ARPE = 1 (counter underflow) . . . . .2504
Figure 519. Counter timing diagram, Update event with ARPE = 1 (counter overflow) . . . . .2505
Figure 520. Update rate examples depending on mode and TIMx_RCR register settings . . . . .2506
Figure 522. Control circuit in normal mode, internal clock divided by 1 . . . . .2508
Figure 523. tim_ti2 external clock connection example . . . . .2508
Figure 524. Control circuit in external clock mode 1 . . . . .2509
Figure 525. External trigger input block . . . . .2510
Figure 526. Control circuit in external clock mode 2 . . . . .2511
Figure 527. Capture/compare channel (example: channel 1 input stage) . . . . .2511
Figure 528. Capture/compare channel 1 main circuit . . . . .2512
Figure 529. Output stage of capture/compare channel (channel 1, idem ch. 2, 3 and 4) . . . . .2512
Figure 530. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .2513
Figure 531. PWM input mode timing . . . . .2515
Figure 532. Output compare mode, toggle on tim_oc1 . . . . .2517
Figure 533. Edge-aligned PWM waveforms (ARR = 8) . . . . .2518
Figure 534. Center-aligned PWM waveforms (ARR = 8). . . . .2519
Figure 535. Dithering principle . . . . .2520
Figure 536. Data format and register coding in dithering mode. . . . .2521
Figure 537. PWM resolution vs frequency . . . . .2522
Figure 538. PWM dithering pattern . . . . .2523
Figure 539. Dithering effect on duty cycle in center-aligned PWM mode . . . . .2524
Figure 540. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .2526
Figure 541. Combined PWM mode on channel 1 and 3 . . . . .2527
Figure 542. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .2528
Figure 543. Complementary output with symmetrical dead-time insertion . . . . .2529
Figure 544. Asymmetrical deadtime . . . . .2530
Figure 545. Dead-time waveforms with delay greater than the negative pulse . . . . .2530
Figure 546. Dead-time waveforms with delay greater than the positive pulse. . . . .2530
Figure 547. Break and Break2 circuitry overview . . . . .2533
Figure 548. Various output behavior in response to a break event on tim_brk (OSSI = 1) . . . . .2535
Figure 549. PWM output state following tim_brk and tim_brk2 assertion (OSSI = 1) . . . . .2536
Figure 550. PWM output state following tim_brk assertion (OSSI = 0) . . . . .2537
Figure 551. Output redirection (tim_brk2 request not represented). . . . .2538
Figure 552. Clearing TIMx_tim_ocxref . . . . .2539
Figure 553. 6-step generation, COM example (OSSR = 1) . . . . .2540
Figure 554. Example of one pulse mode. . . . .2541
Figure 555. Retriggerable one-pulse mode . . . . .2543
Figure 556. Pulse generator circuitry . . . . .2543
Figure 557. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .2544
Figure 558. Extended pulsewidth in case of concurrent triggers . . . . .2545
Figure 559. Example of counter operation in encoder interface mode. . . . .2547
Figure 560. Example of encoder interface mode with tim_ti1fp1 polarity inverted. . . . .2547
Figure 561. Quadrature encoder counting modes . . . . .2548
Figure 562. Direction plus clock encoder mode. . . . .2549
Figure 563. Directional clock encoder mode (CC1P = CC2P = 0). . . . .2549
Figure 564. Directional clock encoder mode (CC1P = CC2P = 1). . . . .2550
Figure 565. Index gating options . . . . .2551
Figure 566. Jittered Index signals . . . . .2551
Figure 567. Index generation for IPOS[1:0] = 11 . . . . .2552
Figure 568. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .2552
Figure 569. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .2553
Figure 570. Counter reading with index gated on channel A and B. . . . .2553
Figure 571. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11). . . . .2554
Figure 572. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .2555
Figure 573. Index behavior in x1 and x2 mode (IPOS[1:0] = 01). . . . .2556
Figure 574. Directional index sensitivity. . . . .2556
Figure 575. Counter reset as function of FIDX bit setting . . . . .2557
Figure 576. Index blanking. . . . .2557
Figure 577. Index behavior in clock + direction mode, IPOS[0] = 1. . . . .2558
Figure 578. Index behavior in directional clock mode, IPOS[0] = 1 . . . . .2558
Figure 579. State diagram for quadrature encoded signals. . . . .2559
Figure 580. Up-counting encoder error detection . . . . .2560
Figure 581. Down-counting encode error detection. . . . .2561
Figure 582. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .2562
Figure 583. Measuring time interval between edges on three signals. . . . .2563
Figure 584. Example of Hall sensor interface . . . . .2565
Figure 585. Control circuit in reset mode . . . . .2566
Figure 586. Control circuit in Gated mode . . . . .2567
Figure 587. Control circuit in trigger mode. . . . .2568
Figure 588. Control circuit in external clock mode 2 + trigger mode . . . . .2569
Figure 589. General-purpose timer block diagram . . . . .2628
Figure 590. Counter timing diagram with prescaler division change from 1 to 2 . . . . .2633
Figure 591. Counter timing diagram with prescaler division change from 1 to 4 . . . . .2634
Figure 592. Counter timing diagram, internal clock divided by 1 . . . . .2635
Figure 593. Counter timing diagram, internal clock divided by 2 . . . . .2635
Figure 594. Counter timing diagram, internal clock divided by 4 . . . . .2636
Figure 595. Counter timing diagram, internal clock divided by N. . . . .2636
Figure 596. Counter timing diagram, Update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .2637
Figure 597. Counter timing diagram, Update event when ARPE = 1 (TIMx_ARR preloaded). . . . .2638
Figure 598. Counter timing diagram, internal clock divided by 1 . . . . .2639
Figure 599. Counter timing diagram, internal clock divided by 2 . . . . .2640
Figure 600. Counter timing diagram, internal clock divided by 4 . . . . .2640
Figure 601. Counter timing diagram, internal clock divided by N . . . . .2641
Figure 602. Counter timing diagram, Update event . . . . .2641
Figure 603. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .2643
Figure 604. Counter timing diagram, internal clock divided by 2 . . . . .2643
Figure 605. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .2644
Figure 606. Counter timing diagram, internal clock divided by N . . . . .2644
Figure 607. Counter timing diagram, Update event with ARPE = 1 (counter underflow). . . . .2645
Figure 608. Counter timing diagram, Update event with ARPE = 1 (counter overflow). . . . .2646
Figure 609. Control circuit in normal mode, internal clock divided by 1 . . . . .2647
Figure 610. tim_ti2 external clock connection example . . . . .2647
Figure 611. Control circuit in external clock mode 1 . . . . .2648
Figure 612. External trigger input block . . . . .2649
Figure 613. Control circuit in external clock mode 2 . . . . .2650
Figure 614. Capture/compare channel (example: channel 1 input stage). . . . .2650
Figure 615. Capture/compare channel 1 main circuit . . . . .2651
Figure 616. Output stage of capture/compare channel (channel 1, idem ch.2, 3 and 4). . . . .2651
Figure 617. PWM input mode timing . . . . .2654
Figure 618. Output compare mode, toggle on tim_oc1 . . . . .2656
Figure 619. Edge-aligned PWM waveforms (ARR = 8). . . . .2657
Figure 620. Center-aligned PWM waveforms (ARR = 8). . . . .2658
Figure 621. Dithering principle . . . . .2659
Figure 622. Data format and register coding in dithering mode . . . . .2660
Figure 623. PWM resolution vs frequency (16-bit mode). . . . .2661
Figure 624. PWM resolution vs frequency (32-bit mode). . . . .2661
Figure 625. PWM dithering pattern . . . . .2662
Figure 626. Dithering effect on duty cycle in center-aligned PWM mode . . . . .2663
Figure 627. Generation of two phase-shifted PWM signals with 50% duty cycle . . . . .2665
Figure 628. Combined PWM mode on channels 1 and 3 . . . . .2666
Figure 629. OCREF_CLR input selection multiplexer . . . . .2667
Figure 630. Clearing TIMx tim_ocxref . . . . .2667
Figure 631. Example of One-pulse mode . . . . .2668
Figure 632. Retriggerable one-pulse mode . . . . .2670
Figure 633. Pulse generator circuitry . . . . .2671
Figure 634. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .2671
Figure 635. Extended pulse width in case of concurrent triggers . . . . .2672
Figure 636. Example of counter operation in encoder interface mode . . . . .2674
Figure 637. Example of encoder interface mode with tim_ti1fp1 polarity inverted . . . . .2674
Figure 638. Quadrature encoder counting modes . . . . .2675
Figure 639. Direction plus clock encoder mode . . . . .2676
Figure 640. Directional clock encoder mode (CC1P = CC2P = 0). . . . .2677
Figure 641. Directional clock encoder mode (CC1P = CC2P = 1). . . . .2677
Figure 642. Index gating options . . . . .2679
Figure 643. Jittered Index signals . . . . .2679
Figure 644. Index generation for IPOS[1:0] = 11 . . . . .2680
Figure 645. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .2680
Figure 646. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .2681
Figure 647. Counter reading with index gated on channel A and B . . . . .2681
Figure 648. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11). . . . .2682
Figure 649. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .2683
Figure 650. Index behavior in x1 and x2 mode (IPOS[1:0] = 01). . . . .2684
Figure 651. Directional index sensitivity . . . . .2684
Figure 652. Counter reset as function of FIDX bit setting . . . . .2685
Figure 653. Index blanking. . . . .2685
Figure 654. Index behavior in clock + direction mode, IPOS[0] = 1. . . . .2686
Figure 655. Index behavior in directional clock mode, IPOS[0] = 1. . . . .2686
Figure 656. State diagram for quadrature encoded signals. . . . .2687
Figure 657. Up-counting encoder error detection . . . . .2688
Figure 658. Down-counting encode error detection. . . . .2689
Figure 659. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .2690
Figure 660. Control circuit in reset mode. . . . .2692
Figure 661. Control circuit in gated mode . . . . .2693
Figure 662. Control circuit in trigger mode. . . . .2693
Figure 663. Control circuit in external clock mode 2 + trigger mode . . . . .2695
Figure 664. Master/Slave timer example . . . . .2695
Figure 665. Master/slave connection example with 1 channel only timers . . . . .2696
Figure 666. Gating TIM_slv with tim_oc1ref of TIM_mstr . . . . .2697
Figure 667. Gating TIM_slv with Enable of TIM_mstr . . . . .2698
Figure 668. Triggering TIM_slv with update of TIM_mstr. . . . .2699
Figure 669. Triggering TIM_slv with Enable of TIM_mstr . . . . .2699
Figure 670. Triggering TIM_mstr and TIM_slv with TIM_mstr tim_ti1 input. . . . .2700
Figure 671. Basic timer block diagram. . . . .2740
Figure 672. Control circuit in normal mode, internal clock divided by 1. . . . .2741
Figure 673. Counter timing diagram with prescaler division change from 1 to 2. . . . .2743
Figure 674. Counter timing diagram with prescaler division change from 1 to 4. . . . .2743
Figure 675. Counter timing diagram, internal clock divided by 1 . . . . .2744
Figure 676. Counter timing diagram, internal clock divided by 2. . . . .2745
Figure 677. Counter timing diagram, internal clock divided by 4. . . . .2745
Figure 678. Counter timing diagram, internal clock divided by N. . . . .2746
Figure 679. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .2746
Figure 680. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR preloaded). . . . .2747
Figure 681. Dithering principle. . . . .2748
Figure 682. Data format and register coding in dithering mode. . . . .2748
Figure 683. FCnt resolution vs frequency . . . . .2749
Figure 684. PWM dithering pattern . . . . .2749
Figure 685. General-purpose timer block diagram (TIM9/TIM12) . . . . .2762
Figure 686. General-purpose timer block diagram (TIM10/TIM11/TIM13/TIM14) . . . . .2763
Figure 687. Counter timing diagram with prescaler division change from 1 to 2. . . . .2766
Figure 688. Counter timing diagram with prescaler division change from 1 to 4. . . . .2766
Figure 689. Counter timing diagram, internal clock divided by 1 . . . . .2767
Figure 690. Counter timing diagram, internal clock divided by 2. . . . .2768
Figure 691. Counter timing diagram, internal clock divided by 4. . . . .2768
Figure 692. Counter timing diagram, internal clock divided by N. . . . .2769
Figure 693. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .2769
Figure 694. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR preloaded). . . . .2770
Figure 695. Control circuit in normal mode, internal clock divided by 1. . . . .2771
Figure 696. tim_ti2 external clock connection example. . . . .2771
Figure 697. Control circuit in external clock mode 1 . . . . .2772
Figure 698. Capture/compare channel 1 input stage (TIM10/TIM11/TIM13/TIM14) . . . . .2773
Figure 699. Capture/compare channel 1 input stage (TIM9/TIM12) . . . . .2773
Figure 700. Capture/compare channel 1 main circuit . . . . .2774
Figure 701. Output stage of capture/compare channel 1 . . . . .2774
Figure 702. PWM input mode timing . . . . .2776
Figure 703. Output compare mode, toggle on tim_oc1. . . . .2778
Figure 704. Edge-aligned PWM waveforms (ARR = 8) . . . . .2779
Figure 705. Dithering principle . . . . .2780
Figure 706. Data format and register coding in dithering mode . . . . .2780
Figure 707. PWM resolution vs frequency . . . . .2781
Figure 708. PWM dithering pattern . . . . .2782
Figure 709. Combined PWM mode on channel 1 and 2 . . . . .2784
Figure 710. Example of one pulse mode . . . . .2785
Figure 711. Retriggerable one pulse mode . . . . .2786
Figure 712. Measuring time interval between edges on 2 signals . . . . .2787
Figure 713. Control circuit in reset mode . . . . .2788
Figure 714. Control circuit in gated mode . . . . .2789
Figure 715. Control circuit in trigger mode . . . . .2789
Figure 716. TIM15 block diagram . . . . .2825
Figure 717. TIM16/TIM17 block diagram . . . . .2826
Figure 718. Counter timing diagram with prescaler division change from 1 to 2 . . . . .2830
Figure 719. Counter timing diagram with prescaler division change from 1 to 4 . . . . .2831
Figure 720. Counter timing diagram, internal clock divided by 1 . . . . .2832
Figure 721. Counter timing diagram, internal clock divided by 2 . . . . .2833
Figure 722. Counter timing diagram, internal clock divided by 4 . . . . .2833
Figure 723. Counter timing diagram, internal clock divided by N . . . . .2834
Figure 724. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded) . . . . .		2834
Figure 725. Counter timing diagram, update event when ARPE = 1
(TIMx_ARR preloaded) . . . . .		2835
Figure 726. Update rate examples depending on mode and TIMx_RCR register settings . . . . .2836
Figure 727. Control circuit in normal mode, internal clock divided by 1 . . . . .2837
Figure 728. tim_ti2 external clock connection example . . . . .2837
Figure 729. Control circuit in external clock mode 1 . . . . .2838
Figure 730. Capture/compare channel (example: channel 1 input stage) . . . . .2839
Figure 731. Capture/compare channel 1 main circuit . . . . .2839
Figure 732. Output stage of capture/compare channel (channel 1) . . . . .2840
Figure 733. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .2840
Figure 734. PWM input mode timing . . . . .2843
Figure 735. Output compare mode, toggle on tim_oc1 . . . . .2845
Figure 736. Edge-aligned PWM waveforms (ARR = 8) . . . . .2846
Figure 737. Dithering principle . . . . .2847
Figure 738. Data format and register coding in dithering mode . . . . .2847
Figure 739. PWM resolution vs frequency . . . . .2848
Figure 740. PWM dithering pattern . . . . .2849
Figure 741. Combined PWM mode on channel 1 and 2 . . . . .2851
Figure 742. Complementary output with symmetrical dead-time insertion. . . . .2852
Figure 743. Asymmetrical deadtime . . . . .2853
Figure 744. Dead-time waveforms with delay greater than the negative pulse. . . . .2853
Figure 745. Dead-time waveforms with delay greater than the positive pulse. . . . .2853
Figure 746. Break circuitry overview . . . . .2855
Figure 747. Output behavior in response to a break event on tim_brk . . . . .2857
Figure 748. Output redirection . . . . .2859
Figure 749. tim_ocref_clr input selection multiplexer. . . . .2860
Figure 750.6-step generation, COM example (OSSR = 1) . . . . .2861
Figure 751.Example of one pulse mode. . . . .2862
Figure 752.Retriggerable one pulse mode . . . . .2864
Figure 753.Measuring time interval between edges on 2 signals . . . . .2864
Figure 754.Control circuit in reset mode . . . . .2865
Figure 755.Control circuit in gated mode . . . . .2866
Figure 756.Control circuit in trigger mode . . . . .2867
Figure 757.LPTIM1/2/3 block diagram (1) . . . . .2931
Figure 758.LPTIM4/5 block diagram (1) . . . . .2932
Figure 759.Glitch filter timing diagram . . . . .2936
Figure 760.LPTIM output waveform, single-counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . .		2938
Figure 761.LPTIM output waveform, single-counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . .		2939
Figure 762.LPTIM output waveform, Continuous counting mode configuration . . . . .2939
Figure 763.Waveform generation . . . . .2941
Figure 764.Encoder mode counting sequence . . . . .2945
Figure 765.Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . .		2946
Figure 766.Capture/compare input stage (channel 1) . . . . .2947
Figure 767.Capture/compare output stage (channel 1) . . . . .2947
Figure 768.Edge-aligned PWM mode (PRELOAD = 1) . . . . .2949
Figure 769.Edge-aligned PWM waveforms (ARR=8 and CCxP = 0) . . . . .2950
Figure 770.PWM mode with immediate update versus preloaded update . . . . .2951
Figure 771.Independent watchdog block diagram . . . . .2981
Figure 772.Reset timing due to timeout . . . . .2983
Figure 773.Reset timing due to refresh in the not allowed area . . . . .2984
Figure 774.Changing PR, RL, and performing a refresh (1) . . . . .2985
Figure 775.Window comparator update (1) . . . . .2986
Figure 776.Independent watchdog interrupt timing diagram. . . . .2988
Figure 777.Early wake-up comparator update (1) . . . . .2989
Figure 778.Watchdog block diagram . . . . .2997
Figure 779.Window watchdog timing diagram . . . . .2999
Figure 780.RTC block diagram . . . . .3005
Figure 781.TAMP block diagram . . . . .3060
Figure 782.Backup registers protection zones . . . . .3064
Figure 783.Tamper sampling with precharge pulse . . . . .3069
Figure 784.Low level detection with precharge and filtering . . . . .3070
Figure 785.Active tamper filtering . . . . .3073
Figure 786.Block diagram . . . . .3107
Figure 787.I 2 C-bus protocol . . . . .3109
Figure 788.Setup and hold timings . . . . .3111
Figure 789.I2C initialization flow . . . . .3113
Figure 790.Data reception . . . . .3114
Figure 791.Data transmission . . . . .3115
Figure 792.Target initialization flow . . . . .3118
Figure 793.Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .3120
Figure 794.Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .3121
Figure 795.Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .3122
Figure 796.Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .3123
Figure 797.Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .3124
Figure 798.Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . .3124
Figure 799. Controller clock generation . . . . .3126
Figure 800. Controller initialization flow . . . . .3128
Figure 801. 10-bit address read access with HEAD10R = 0 . . . . .3128
Figure 802. 10-bit address read access with HEAD10R = 1 . . . . .3129
Figure 803. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .3130
Figure 804. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .3131
Figure 805. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		3132
Figure 806. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .3134
Figure 807. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .3135
Figure 808. Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		3136
Figure 809. Timeout intervals for t LOW:SEXT , t LOW:MEXT . . . . .3140
Figure 810. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .3143
Figure 811. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .3144
Figure 812. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .3145
Figure 813. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .3146
Figure 814. Bus transfer diagrams for SMBus controller transmitter . . . . .3147
Figure 815. Bus transfer diagrams for SMBus controller receiver . . . . .3149
Figure 816. I3C block diagram. . . . .3174
Figure 817. I3C (primary) controller state and programming sequence diagram. . . . .3178
Figure 818. I3C target state and programing sequence diagram . . . . .3183
Figure 819. I3C CCC messages, as controller . . . . .3197
Figure 820. I3C broadcast ENTDAA CCC, as controller . . . . .3198
Figure 821. I3C broadcast, direct read and direct write RSTACT CCC, as controller . . . . .3199
Figure 822. I3C CCC messages, as target . . . . .3201
Figure 823. I3C broadcast ENTDAA CCC, as target. . . . .3202
Figure 824. I3C broadcast DEFTGTS CCC, as target. . . . .3203
Figure 825. I3C broadcast DEFGRPA CCC, as target . . . . .3204
Figure 826. I3C private read/write messages, as controller. . . . .3206
Figure 827. I3C private read/write messages, as target . . . . .3207
Figure 828. Legacy I2C read/write messages, as controller . . . . .3208
Figure 829. IBI transfer, as controller/target . . . . .3209
Figure 830. Hot-join request transfer, as controller/target . . . . .3211
Figure 831. Controller-role request transfer, as controller/target . . . . .3212
Figure 832. C-FIFO management, as controller . . . . .3213
Figure 833. TX-FIFO management, as controller . . . . .3215
Figure 834. RX-FIFO management, as controller . . . . .3217
Figure 835. S-FIFO management, as controller . . . . .3220
Figure 836. RX-FIFO management, as target on the I3C bus. . . . .3221
Figure 837. TX-FIFO management with I3C_TGTTDR, as target on the I3C bus. . . . .3223
Figure 838. TX-FIFO management by software without I3C_TGTTDR
if reading less bytes than TX-FIFO size, as target. . . . .		3225
Figure 839. USART block diagram . . . . .3283
Figure 840. Word length programming . . . . .3287
Figure 841. Configurable stop bits . . . . .3289
Figure 842. TC/TXE behavior when transmitting . . . . .3291
Figure 843. Start bit detection when oversampling by 16 or 8. . . . .3292
Figure 844. usart_ker_ck clock divider block diagram. . . . .3295
Figure 845. Data sampling when oversampling by 16. . . . .3296
Figure 846. Data sampling when oversampling by 8. . . . .3297
Figure 847. Mute mode using Idle line detection . . . . .3304
Figure 848. Mute mode using address mark detection . . . . .3305
Figure 849. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .3308
Figure 850. Break detection in LIN mode vs. Framing error detection. . . . .3309
Figure 851. USART example of synchronous master transmission. . . . .3310
Figure 852. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		3310
Figure 853. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		3311
Figure 854. USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		3312
Figure 855. ISO 7816-3 asynchronous protocol . . . . .3314
Figure 856. Parity error detection using the 1.5 stop bits . . . . .3316
Figure 857. IrDA SIR ENDEC block diagram. . . . .3320
Figure 858. IrDA data modulation (3/16) - normal mode . . . . .3320
Figure 859. Transmission using DMA . . . . .3322
Figure 860. Reception using DMA . . . . .3323
Figure 861. Hardware flow control between two USARTs. . . . .3323
Figure 862. RS232 RTS flow control . . . . .3324
Figure 863. RS232 CTS flow control . . . . .3325
Figure 864. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .3328
Figure 865. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		3328
Figure 866. LPUART block diagram . . . . .3373
Figure 867. LPUART word length programming . . . . .3376
Figure 868. Configurable stop bits . . . . .3378
Figure 869. TC/TXE behavior when transmitting . . . . .3380
Figure 870. lpuart_ker_ck clock divider block diagram . . . . .3384
Figure 871. Mute mode using Idle line detection . . . . .3388
Figure 872. Mute mode using address mark detection . . . . .3389
Figure 873. Transmission using DMA . . . . .3391
Figure 874. Reception using DMA . . . . .3392
Figure 875. Hardware flow control between two LPUARTs. . . . .3393
Figure 876. RS232 RTS flow control . . . . .3393
Figure 877. RS232 CTS flow control . . . . .3394
Figure 878. Wake-up event verified (wake-up event = address match,
FIFO disabled) . . . . .		3397
Figure 879. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		3397
Figure 880. SPI/I2S block diagram . . . . .3429
Figure 881. Full-duplex single master/ single slave application. . . . .3432
Figure 882. Half-duplex single master/ single slave application . . . . .3433
Figure 883. Simplex single master / single slave application
(master in transmit-only / slave in receive-only mode) . . . . .		3434
Figure 884. Master and three independent slaves connected in star topology . . . . .3435
Figure 885. Master and three slaves connected in circular (daisy chain) topology . . . . .3437
Figure 886. Multimaster application . . . . .3438
Figure 887. Scheme of NSS control logic . . . . .3440
Figure 888. Data flow timing control (SSOE = 1, SSOM = 0, SSM = 0) . . . . .3440
Figure 889. NSS interleaving pulses between data (SSOE = 1, SSOM = 1, SSM = 0) . . . . .3441
Figure 890. Data clock timing diagram . . . . .3443
Figure 891. Data alignment when data size is not equal to 8, 16 or 32 bits . . . . .3444
Figure 892. TI mode transfer . . . . .3453
Figure 893. Optional configurations of the slave behavior when an underrun condition is detected . . . . .3455
Figure 894. Waveform examples . . . . .3463
Figure 895. Master I2S Philips protocol waveforms (16/32-bit full accuracy) . . . . .3464
Figure 896. I2S Philips standard waveforms . . . . .3464
Figure 897. Master MSB-justified 16- or 32-bit full-accuracy length . . . . .3465
Figure 898. Master MSB-justified 16- or 24-bit data length . . . . .3465
Figure 899. Slave MSB-justified 16-, 24- or 32-bit data length . . . . .3466
Figure 900. LSB-justified 16 or 24-bit data length . . . . .3466
Figure 901. Master PCM when the frame length is equal the data length . . . . .3467
Figure 902. Master PCM standard waveforms (16 or 24-bit data length) . . . . .3467
Figure 903. Slave PCM waveforms . . . . .3468
Figure 904. Startup sequence, I2S Philips standard, master . . . . .3471
Figure 905. Startup sequence, I2S Philips standard, slave . . . . .3472
Figure 906. Stop sequence, I2S Philips standard, master . . . . .3472
Figure 907. I 2 S clock generator architecture . . . . .3473
Figure 908. Data Format . . . . .3475
Figure 909. Handling of underrun situation . . . . .3477
Figure 910. Handling of overrun situation . . . . .3478
Figure 911. Frame error detection, with FIXCH = 0 . . . . .3479
Figure 912. Frame error detection, with FIXCH = 1 . . . . .3479
Figure 913. SAI functional block diagram . . . . .3504
Figure 914. Audio frame . . . . .3508
Figure 915. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .3510
Figure 916. FS role is start of frame (FSDEF = 0) . . . . .3511
Figure 917. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .3512
Figure 918. First bit offset . . . . .3512
Figure 919. Audio block clock generator overview . . . . .3514
Figure 920. PDM typical connection and timing . . . . .3518
Figure 921. Detailed PDM interface block diagram . . . . .3519
Figure 922. Start-up sequence . . . . .3520
Figure 923. SAI_ADR format in TDM mode, 32-bit slot width . . . . .3521
Figure 924. SAI_ADR format in TDM mode, 16-bit slot width . . . . .3522
Figure 925. SAI_ADR format in TDM mode, 8-bit slot width . . . . .3523
Figure 926. AC'97 audio frame . . . . .3526
Figure 927. Example of typical AC'97 configuration on devices featuring at least two embedded SAIs (three external AC'97 decoders) . . . . .3527
Figure 928. SPDIF format . . . . .3528
Figure 929. SAI_xDR register ordering . . . . .3529
Figure 930. Data companding hardware in an audio block in the SAI . . . . .3532
Figure 931. Tristate strategy on SD output line on an inactive slot . . . . .3534
Figure 932. Tristate on output data line in a protocol like I2S . . . . .3535
Figure 933. Overrun detection error . . . . .3536
Figure 934. FIFO underrun event . . . . .3536
Figure 935. SPDIFRX block diagram . . . . .3571
Figure 936. S/PDIF sub-frame format . . . . .3572
Figure 937. S/PDIF block format . . . . .3573
Figure 938. S/PDIF preambles . . . . .3573
Figure 939. Channel coding example . . . . .3574
Figure 940. SPDIFRX decoder . . . . .3575
Figure 941. Noise filtering and edge detection . . . . .3575
Figure 942. Thresholds . . . . .3577
Figure 943. Synchronization flowchart. . . . .3579
Figure 944. Synchronization process scheduling . . . . .3580
Figure 945. SPDIFRX states . . . . .3581
Figure 946. SPDIFRX_FMTx_DR register format . . . . .3583
Figure 947. Channel/user data format . . . . .3584
Figure 948. S/PDIF overrun error when RXSTEO = 0 . . . . .3586
Figure 949. S/PDIF overrun error when RXSTEO = 1 . . . . .3587
Figure 950. SPDIFRX interface interrupt mapping diagram . . . . .3590
Figure 951. MDIOS block diagram . . . . .3605
Figure 952. MDIO protocol write frame waveform . . . . .3606
Figure 953. MDIO protocol read frame waveform . . . . .3606
Figure 954. CAN subsystem . . . . .3619
Figure 955. FDCAN block diagram . . . . .3621
Figure 956. Transceiver delay measurement . . . . .3626
Figure 957. Pin control in bus monitoring mode . . . . .3628
Figure 958. Pin control in loop back mode. . . . .3630
Figure 959. CAN error state diagram. . . . .3631
Figure 960. Message RAM configuration. . . . .3632
Figure 961. Standard message ID filter path . . . . .3635
Figure 962. Extended message ID filter path. . . . .3636
Figure 963. Example of mixed configuration dedicated Tx buffers / Tx FIFO . . . . .3642
Figure 964. Example of mixed configuration dedicated Tx buffers / Tx queue . . . . .3642
Figure 965. Bit timing . . . . .3644
Figure 966. Bypass operation . . . . .3646
Figure 967. FSM calibration. . . . .3647
Figure 968. Cycle time and global time synchronization . . . . .3662
Figure 969. TTCAN level 0 and level 2 drift compensation . . . . .3663
Figure 970. Level 0 schedule synchronization state machine . . . . .3670
Figure 971. Level 0 master to slave relation . . . . .3671
Figure 972. USB subsystem overview. . . . .3748
Figure 973. USB2 OTG high-speed Port 1 block diagram. . . . .3749
Figure 974. USB2 OTG high-speed Port 1 resets . . . . .3750
Figure 975. USB2 OTG high-speed Port 2 block diagram. . . . .3753
Figure 976. USB2 OTG high-speed Port 2 resets . . . . .3754
Figure 977. USB Type-C implementation: OTG HS Port 1 example . . . . .3757
Figure 978. USB Type-C and power delivery block diagram. . . . .3758
Figure 979. USB Type-C and power delivery reset . . . . .3759
Figure 980. Multiplexing of debug signals in the USB subsystem . . . . .3760
Figure 981. OTG1/OTG2 high-speed block diagram. . . . .3764
Figure 982. OTG A-B device connection . . . . .3766
Figure 983. OTG peripheral-only connection. . . . .3767
Figure 984. OTG host-only connection . . . . .3771
Figure 985. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .3774
Figure 986. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .3776
Figure 987. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .3777
Figure 988. Host-mode FIFO address mapping and AHB FIFO access mapping. . . . .3778
Figure 989. Interrupt hierarchy. . . . .3782
Figure 990. Transmit FIFO write task . . . . .3875
Figure 991. Receive FIFO read task . . . . .3876
Figure 992. Normal bulk/control OUT/SETUP . . . . .3877
Figure 993. Bulk/control IN transactions . . . . .3881
Figure 994. Normal interrupt OUT . . . . .3884
Figure 995. Normal interrupt IN . . . . .3889
Figure 996. Isochronous OUT transactions . . . . .3891
Figure 997. Isochronous IN transactions . . . . .3894
Figure 998. Normal bulk/control OUT/SETUP transactions - DMA . . . . .3896
Figure 999. Normal bulk/control IN transaction - DMA. . . . .3898
Figure 1000. Normal interrupt OUT transactions - DMA mode . . . . .3899
Figure 1001. Normal interrupt IN transactions - DMA mode . . . . .3900
Figure 1002. Normal isochronous OUT transaction - DMA mode . . . . .3901
Figure 1003. Normal isochronous IN transactions - DMA mode . . . . .3902
Figure 1004. Receive FIFO packet read . . . . .3908
Figure 1005. Processing a SETUP packet . . . . .3910
Figure 1006. Bulk OUT transaction . . . . .3917
Figure 1007. TRDT max timing case . . . . .3926
Figure 1008. UCPD block diagram . . . . .3939
Figure 1009. Clock division and timing elements. . . . .3940
Figure 1010. K-code transmission . . . . .3942
Figure 1011. Transmit order for various sizes of data . . . . .3944
Figure 1012. Packet format . . . . .3944
Figure 1013. Line format of Hard Reset. . . . .3945
Figure 1014. Line format of Cable Reset. . . . .3945
Figure 1015. BIST test data frame. . . . .3946
Figure 1016. BIST Carrier Mode 2 frame. . . . .3947
Figure 1017. UCPD BMC transmitter architecture. . . . .3947
Figure 1018. UCPD BMC receiver architecture. . . . .3949
Figure 1019. Ethernet high-level block diagram . . . . .3981
Figure 1020. DMA transmission flow (standard mode) . . . . .3983
Figure 1021. DMA transmission flow (OSP mode) . . . . .3985
Figure 1022. Receive DMA flow . . . . .3987
Figure 1023. Overview of MAC transmission flow . . . . .3990
Figure 1024. MAC reception flow . . . . .3992
Figure 1025. Packet filtering sequence . . . . .4009
Figure 1026. Networked time synchronization. . . . .4023
Figure 1027. Propagation delay calculation in clocks supporting
peer-to-peer path correction . . . . .		4024
Figure 1028. System time update using fine correction method . . . . .4034
Figure 1029. Time aware shaper implementation for traffic scheduling. . . . .4046
Figure 1030. Implementing a guard band to avoid delays due to interfering frames . . . . .4047
Figure 1031. GCL governing gate close and open events block diagram
(from IEEE 802.1 Qbv specifications) . . . . .		4048
Figure 1032. GCL and associated registers - BaseTime and CycleTime . . . . .4052
Figure 1033. GCL and associated registers - BaseTime and CycleTime list execution
time > CycleTime . . . . .		4053
Figure 1034. Switching to a new Configuration that is Aligned with the Existing Configuration. . . . .4054
Figure 1035. Switching to the New List by Truncating the Current List . . . . .4056
Figure 1036. Switching to New List By Extending the Current List . . . . .4057
Figure 1037. mPacket formats. . . . .4061
Figure 1038. MAC data Alignment Feature . . . . .4066
Figure 1039. Time-based scheduler implementation. . . . .4074
Figure 1040. Time-based scheduling flow . . . . .4075
Figure 1041. TCP segmentation offload overview. . . . .4081
Figure 1042. TCP segmentation offload flow . . . . .4082
Figure 1043. Header and payload fields of segmented packets . . . . .4085
Figure 1044. Supported PHY interfaces . . . . .4095
Figure 1045. SMA Interface block . . . . .4096
Figure 1046. MDIO packet structure (Clause 45) . . . . .4097
Figure 1047. MDIO packet structure (Clause 22) . . . . .4098
Figure 1048. SMA write operation flow . . . . .4099
Figure 1049. Write data packet . . . . .4100
Figure 1050. Read data packet . . . . .4100
Figure 1051. Media independent interface (MII) signals . . . . .4102
Figure 1052. RMII block diagram . . . . .4104
Figure 1053. Transmission bit order . . . . .4105
Figure 1054. Receive bit order . . . . .4106
Figure 1055. RGMII block diagram and interface signals . . . . .4107
Figure 1056. LPI transitions (Transmit, 100 Mbds) . . . . .4116
Figure 1057. LPI Tx clock gating (when LPITCSE = 1) . . . . .4117
Figure 1058. LPI transitions (receive, 100 Mbit/s) . . . . .4118
Figure 1059. Descriptor ring structure . . . . .4149
Figure 1060. DMA descriptor ring . . . . .4150
Figure 1061. Descriptor tail pointer example 1 . . . . .4151
Figure 1062. Descriptor tail pointer example 2 . . . . .4151
Figure 1063. Transmit descriptor (read format) . . . . .4152
Figure 1064. Transmit descriptor write-back format . . . . .4157
Figure 1065. Transmit context descriptor format . . . . .4162
Figure 1066. Receive normal descriptor (read format) . . . . .4165
Figure 1067. Receive normal descriptor (write-back format) . . . . .4168
Figure 1068. Receive context descriptor . . . . .4176
Figure 1069. Enhanced normal descriptor (read format) . . . . .4178
Figure 1070. Enhanced normal descriptor (write format) . . . . .4179
Figure 1071. Enhanced context descriptor (read format) . . . . .4180
Figure 1072. Enhanced context descriptor (write format) . . . . .4181
Figure 1073. Generation of ETH_DMAISR flags . . . . .4200
Figure 1074. HDP block diagram . . . . .4370
Figure 1075. Block diagram of debug infrastructure . . . . .4377
Figure 1076. Debug reset control logic . . . . .4379
Figure 1077. JTAG TAP state machine . . . . .4384
Figure 1078. SWD successful data transfer . . . . .4387
Figure 1079. Debug and access port connections . . . . .4396
Figure 1080. Cortex-M55 debug topology . . . . .4418
Figure 1081. Trace subsystem CoreSight topology . . . . .4497
Figure 1082. CoreSight timestamp distribution . . . . .4503
Figure 1083. Embedded cross trigger . . . . .4511
Figure 1084. Mapping trigger inputs to outputs . . . . .4514
Figure 1085. ETR state transition diagram . . . . .4560
Figure 1086. Scatter-gather operation . . . . .4561
Figure 1087. System trace macrocell . . . . .4620

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