62. Revision history

Document scope extended to STM32H523/533xx devices.

Updated Section 2.3.3: Embedded SRAMs , Section 5.6.8: GTZC1 TZSC memory x subregion A watermark configuration register (GTZC1_TZSC_MPCWMxACFGGR) , DataProvisioning , Section 7.4.5: Description of data protection option bytes , Section 7.4.6: Description of boot address option bytes , Section 7.7.2: RSS user functions , Section 10.2: PWR main features , Clock security system on LSE , Section 8.4: ICACHE functional description , Section 8.4.7: Address remapping , Section 23.4.14: OCTOSPI device configuration , Section 48.7: I2C DMA requests , Section 32.7.1: RNG control register (RNG_CR) , Section 43.4.20: DMA requests , Section 43.7.3: LPTIMx interrupt and status register [alternate] (LPTIMx_ISR) (x = 1 to 3, 5, 6) , Section 46.3.11: RTC initialization and configuration , Section 46.6.20: RTC status register (RTC_SR) , Section 55.6.2: USB SRAM registers , and Debug authentication provisioning .

Added Section 5.6.10: GTZC1 TZSC memory x subregion B watermark configuration register (GTZC1_TZSC_MPCWMxBCFGGR) , Section 48.7.1: Transmission using DMA , Section 25.3: DLYB implementation , Section 36.3: PKA implementation , Memory types , Section 50.8.5: USART control register 3 [alternate] (USART_CR3) , Section 50.8.7: USART guard time and prescaler register (USART_GTPR) , Section 51.7.5: LPUART control register 3 [alternate] (LPUART_CR3) , Section 55.4.2: USB pins and internal signals , and Section 55.4.3: USB reset and clocks .

Added notes to Section 46.6.21: RTC nonsecure masked interrupt status register (RTC_MISR) and to Section 46.6.22: RTC secure masked interrupt status register (RTC_SMISR) .

Updated Figure 2: Memory map based on IDAU mapping , Figure 25: Flash high-cycle data memory map on 2-Mbyte devices , Figure 26: Flash high-cycle data memory map on 1-Mbyte devices , Figure 48: Clock tree , Figure 147: HyperBus read operation page crossing with latency , Figure 283: PSSI block diagram , Figure 284: Top-level block diagram , Figure 626: I2C initialization flow , Figure 629: Slave initialization flow , Figure 782: USB peripheral block diagram , and Figure 796: DMA transmission flow (standard mode) .

Added Figure 27: Flash high-cycle data memory map on 512-Kbyte devices and Figure 27: Flash high-cycle data memory map on 512-Kbyte devices .

Updated Table 3: Memory map and peripheral register addresses , Table 43: Specific OB modifying rules , Table 62: Product states, debug states and debug policy , Table 69: Macros for RSS services , Table 70: RSS lib interface functions , Table 75: Register map and reset value table , Table 79: RSSLIB/NSSLIB entry point access , Table 203: OCTOSPI implementation , Table 291: PSSI input/output pins , Table 298: RNG interrupt requests , and Table 299: RNG configurations . Added Table 78: RSSLIB/NSSLIB accesses .

Minor text edits across the whole document.

Updated Section 3.7.1: Temporal isolation using secure hide protection (HDP) , Section 3.11.2: Life cycle management, Flash memory architecture , Section 11.8.44: RCC kernel clock configuration register (RCC_CCIPR5) , Section 11.8.46: RCC reset status register (RCC_RSR) , Section 14.5.4: SBS debug control register (SBS_DBGCR) , Section 14.5.9: SBS product mode and configuration register (SBS_PMCR) , Section 15.3.5: Clock sources to timers , Section 18.6.18: EXTI external interrupt selection register (EXTI_EXTICR4) , SDRAM timing register x (FMC_SDTRx) , Section 59.5: ROM tables , and Section 59.12.4: DBGMCU registers .

Replaced SQRx and JSQRx by ADC_SQRY and ADC_JSQR registers, when referring to registers, JSQRI and SQRi registers by JSQi and SQi bits, when referring to bits in Section 26: Analog-to-digital converters (ADC1/2) .

Updated Table 49: Memory map and swapping options (STM32H523/533xx devices) , Table 51: Option bytes organization , Table 85: Register map and reset value table , Table 133: Peripherals interconnect matrix , Table 146: STM32H562/563/573xx vector table , Table 147: STM32H523/533xx vector table , and Table 548: Instance implementation .

Updated Figure 52: Clock tree , Figure 132: Burst write SDRAM access waveforms , Figure 133: Burst read SDRAM access , Figure 135: Read access crossing row boundary , and Figure 136: Write access crossing row boundary .

Updated footnote 4 of Table 115: Kernel clock distribution overview , and added footnote 2 to Table 150: EXTI line connections .