47. Tamper and backup registers (TAMP)

47.1 TAMP introduction

The anti-tamper detection circuit is used to protect sensitive data from external attacks. 32 32-bit backup registers are retained in all low-power modes and also in \( V_{BAT} \) mode. The backup registers, as well as other secrets in the device, are protected by this anti-tamper detection circuit with 11 tamper pins and 13 internal tampers. The external tamper pins can be configured for edge detection, or level detection with or without filtering, or active tamper which increases the security level by auto checking that the tamper pins are not externally opened or shorted.

47.2 TAMP main features

• • A tamper detection can optionally erase the backup registers, backup SRAM, SRAM2, caches, and cryptographic peripherals. The device resources protected by tamper are named “device secrets”.
• • 32 32-bit backup registers:
  • – The backup registers (TAMP_BKPxR) are implemented in the backup domain that remains powered-on by \( V_{BAT} \) when the \( V_{DD} \) power is switched off.
• • Up to 11 tamper pins for 8 external tamper detection events:
  • – Active tamper mode: continuous comparison between tamper output and input to protect from physical open-short attacks.
  • – Flexible active tamper I/O management: from 5 meshes (each input associated to its own exclusive output) to 8 meshes (single output shared for up to 8 tamper inputs)
  • – Passive tampers: ultra-low power edge or level detection with internal pull-up hardware management.
  • – Configurable digital filter.
• • 13 internal tamper events to protect against transient or environmental perturbation attacks
• • Each tamper can be configured in two modes:
  • – Confirmed mode: immediate erase of secrets on tamper detection, including backup registers erase
  • – Potential mode: most of the secrets erase following a tamper detection are launched by software
• • Any tamper detection can generate a RTC timestamp event.
• • TrustZone support:
  • – Tamper secure or nonsecure configuration.
  • – Backup registers configuration in 3 configurable-size areas:
    • 1 read/write secure area.
    • 1 write secure/read nonsecure area.
    • 1 read/write nonsecure area.
  • – Boot hardware key for secure AES, stored in backup registers, protected against read and write access.
• • Tamper configuration and backup registers privilege protection
• • Monotonic counter.

47.3 TAMP functional description

47.3.1 TAMP block diagram

Figure 625. TAMP block diagram

1. The number of external and internal tampers depends on products.

47.3.2 TAMP pins and internal signals

Table 505. TAMP input/output pins

Table 506. TAMP internal input/output signals

Table 506. TAMP internal input/output signals (continued)

1. Refer to Table 507: TAMP interconnection .

The TAMP kernel clock is usually the LSE at 32.768 kHz although it is possible to select other clock sources in the RCC (refer to RCC for more details). The TAMP kernel clock is required only for external tamper inputs level with filtering, and for external active tamper detection modes. Internal tampers detection and external tampers inputs edge detection are functional without requiring any kernel clock.

Read and write access to backup registers and all other TAMP registers are also functional without any kernel clock (only APB clock is needed).

Some detections modes are not available in some low-power modes or V _BAT depending on the selected clock (refer to Section 47.4: TAMP low-power modes for more details).

Table 507. TAMP interconnection

Table 507. TAMP interconnection (continued)

1. This monitoring must be enabled by setting MONEN in PWR Backup domain control register (PWR_BDCR) .

2. This monitoring must be enabled by setting LSEON in PWR Backup domain control register (PWR_BDCR) .

3. This signal is generated in the TAMP peripheral.

The TZEN option bit is used to activate TrustZone in the device.

TZEN = 1: TrustZone activated.

TZEN = 0: TrustZone disabled.

When TrustZone is disabled, the APB access to the TAMP registers are nonsecure.

47.3.3 GPIOs controlled by the RTC and TAMP

Refer to Section 46.3.3: GPIOs controlled by the RTC and TAMP .

47.3.4 TAMP register write protection

After system reset, the TAMP registers (including backup registers) are protected against parasitic write access by the DBP bit in the power control peripheral (refer to the PWR power control section). DBP bit must be set in order to enable TAMP registers write access.

47.3.5 TAMP secure protection modes

By default after a backup domain power-on reset, all TAMP registers can be read or written in both secure and nonsecure modes, except for the TAMP secure configuration register (TAMP_SECCFGR) which can be written in secure mode only. The TAMP protection configuration is not affected by a system reset.

• • When the TAMPSEC bit is set in the TAMP_SECCFGR register:
  • – Writing the TAMP registers is possible only in secure mode, except for the backup registers which have their own protection setting.
  • – Reading TAMP_SECCFGR, TAMP_PRIVCFGR and TAMP_MISR is always possible in secure and nonsecure modes. All the other TAMP registers can be read only in secure mode, except for the backup registers and monotonic counters which have their own protection setting.
• • When the CNT1SEC bit is set in the TAMP_SECCFGR register: the TAMP_COUNT1R can be read and written only in secure mode.

A nonsecure access to a secure-protected register is denied:

• • There is no bus error generated.
• • A notification is generated through a flag/interrupt in the TZIC (TrustZone illegal access controller).
• • When write protected, the bits are not written.
• • When read protected they are read as 0.

As soon as at least one function is configured to be secured, the TAMP reset and clock control is also secured in the RCC.

47.3.6 Backup registers protection zones

The backup registers protection is configured thanks to BKPRWSEC[7:0] and BKPWSEC[7:0] (refer to the figure below):

Figure 626. Backup registers protection zones

1. I = last backup register index

In case TZEN = 1, the bits BKPWPRIV and BKPRWPRIV in the TAMP_PRIVCFGGR can be written only in secure mode.

47.3.7 TAMP privilege protection modes

By default after a backup domain power-on reset, all TAMP registers can be read or written in both privileged and non-privileged modes, except for the TAMP privilege configuration register (TAMP_PRIVCFGGR) which can be written in privilege mode only. The TAMP protection configuration is not affected by a system reset.

When the TAMPPRIV bit is set in the TAMP_PRIVCFGGR register:

• • Writing the TAMP registers is possible only in privilege mode, except for the backup registers and the monotonic counter which have their own protection setting.
• • When the CNT1PRIV bit is set in the TAMP_PRIVCFGGR register: the TAMP_COUNT1R can be read and written only in privilege mode.
• • Reading TAMP_SECCFGR, TAMP_PRIVCFGGR is always possible in privilege and non-privilege modes. All the other TAMP registers can be read only in privileged mode, except for the backup registers and the monotonic counter which have their own protection setting.

The backup registers protection is configured thanks to BKPRWSEC[7:0] and BKPRWPRIV for the protection zone 1, and thanks to BKPRWSEC[7:0], BKPWSEC[7:0] and BKPRWPRIV for the protection zone 2 (refer to Figure 626 ). The BHKLOCK bit can be written only in privileged mode when the BKPRWPRIV bit is set.

A non-privileged access to a privileged-protected register is denied:

• • There is no bus error generated.
• • When write protected, the bits are not written.
• • When read protected they are read as 0.

47.3.8 Boot hardware key (BHK)

The eight first backup registers from TAMP_BKP0R to TAMP_BKP7R can be used to store a boot hardware key for the secure AES.

For this purpose, these registers must belong to the Protection Zone 1: BKPRWSEC must be greater or equal to 8.

Once the backup registers are written with the boot hardware key, the BHKLOCK bit must be set in the TAMP_SECCFGR register. Once BHKLOCK is set, the 8 backup registers cannot be accessed anymore by software: they are read as 0 and write to these registers is ignored. BHKLOCK cannot be cleared by software, and is cleared by hardware following a tamper event or when the product state is opened. It is also cleared with BKERASE command (in all cases the backup registers are also erased).

Refer to section secure AES co-processor (SAES) for details on procedure to download the boot hardware key in the SAES.

47.3.9 Tamper detection

The tamper detection main purpose is to protect the device secrets from device external attacks. The detection is made on events on TAMP_INx (x = pin index) I/Os, or on internal monitors detecting out-of-range device conditions.

The tamper detection can be configured for the following purposes:

• • erase the backup registers and other device secrets stored in SRAMs or peripherals listed in Table 507: TAMP interconnection . The device secrets list is configurable thanks to TAMP resources protection configuration register (TAMP_RPCFGR) .
• • block the read/write access to the backup registers and other device secrets stored in SRAMs or peripherals listed in Table 507: TAMP interconnection . The device secrets list is configurable thanks to TAMP_RPCFGR.
• • generate an interrupt, capable to wake-up from low-power modes
• • generate a hardware trigger for the low-power timers, or a RTC timestamp event

The external I/Os tamper detection supports 2 main configurations:

• • Passive mode: TAMP_INx I/Os are monitored and a tamper is detected either on edge or on level.
• • Active mode: TAMP_INx (x = pin index) is continuously compared with TAMP_OUTy (y = pin index) allowing open-short detection.

A digital filter can be applied on external tamper detection to avoid false detection. In addition, it is possible to configure each tamper source in potential mode, so that the secrets erase is not launched by hardware on tamper detection. The secrets erase can then be launched by software after software checks.

47.3.10 TAMP backup registers and other device secrets erase

The backup registers (TAMP_BKPxR) are not reset by system reset or when the device wakes up from Standby mode.

The backup registers and the other device secrets are not reset when the corresponding mask is set (TAMPxMSK=1 in the TAMP_CR2 register).

Note: The backup registers are also erased when the product state is changed from Closed to Open.

Tamper detection – confirmed mode

The confirmed mode is selected for TAMPx (external tamper x) when TAMPxPOM = 0 in the TAMP_CR2 register. The confirmed mode is selected for ITAMPx (internal tamper x) when ITAMPxPOM = 0 in the TAMP_CR3 register. The effects of a tamper detection in confirmed mode are described with tamp_confirmed and tamp_confirmed_rpcfgx signals in the Table 507: TAMP interconnection .

This mode is selected to erase automatically the device secrets when the tamper is detected.

Tamper detection – potential mode

The potential mode is selected for TAMPx (external tamper x) when TAMPxPOM = 1 in the TAMP_CR2 register. The potential tamper mode is selected for ITAMPx (internal tamper x) when ITAMPxPOM = 1 in the TAMP_CR3 register. The effects of a tamper detection in potential mode are described with tamp_potential and tamp_potential_rpcfgx signals in the Table 507: TAMP interconnection .

This mode is selected to avoid irreversible erasure of some device secrets when the tamper is detected. In this mode, some device secrets are not erased when the corresponding tamper event is detected. In addition, the read and write accesses to these device secrets are blocked as soon as the tamper detection flag is set in potential mode, until this flag is cleared by setting the corresponding clear flag in the TAMP_SCR register. Therefore the software can perform some checks to discriminate false from true tampers, and decide to launch secrets erase only in case of the potential tamper is confirmed to be a true tamper. The device secrets are erased by software by setting the BKERASE bit in the TAMP_CR2 register.

Potential tamper to confirmed tamper timeout

Some internal tampers generate a tamper event if the independent watchdog reset occurs when another tamper flag is set (refer to Table 507: TAMP interconnection ). The IWDG tamper must be configured with ITAMPxPOM = 0. This permits the erasure of device secrets to be forced by hardware after a timeout, in case the previous tamper event was in potential mode. This is equivalent to change the “potential tamper” into “confirmed tamper” if a watchdog reset occurs before any software decision following the potential tamper event.

Device resources protection configuration

Some device resources can be configured in order to be included to the list of the device secrets protected by tamper detection.

When RPCFGz = 0 in the TAMP_RPCFGR, the device resource associated to RPCFGz is not protected by the TAMP peripheral:

• • It is not affected by tamper detection (whatever confirmed or potential mode)
• • It is not affected by BKERASE software command
• • It is not affected by BKBLOCK software command

When RPCFGz = 1 in the TAMP_RPCFGR, the device resource associated to RPCFGz is protected by the TAMP peripheral:

• • It is affected by confirmed tamper detection and BKERASE software command, as described with tamp_confirmed_rpcfgz signal in Table 507: TAMP interconnection
• • It is affected by potential tamper detection and BKBLOCK software command, as described with tamp_potential_rpcfgz signal in Table 507: TAMP interconnection

1. Refer to Table 507: TAMP interconnection .

Device secrets access blocked by software

By default, the device secrets can be accessed by the application, except if a tamper event flag is detected: the device secrets access is not possible as long as a tamper flag is set.

It is possible to block the access to the device secrets by software, by setting the BKBLOCK bit of the TAMP_CR2 register. The device secrets access is possible only when BKBLOCK = 0 and no tamper flag is set.

47.3.11 Tamper detection configuration and initialization

Each input can be enabled by setting the corresponding TAMPxE bits to 1 in the TAMP_CR register.

Each TAMP_INx tamper detection input is associated with a flag TAMPxF in the TAMP_SR register.

By setting the TAMPxIE bit in the TAMP_IER register, an interrupt is generated when a tamper detection event occurs (when TAMPxF is set). Setting TAMPxIE is not allowed when the corresponding TAMPxMSK is set.

Trigger output generation on tamper event

The tamper event detection can be used as trigger input by the low-power timers.

When TAMPxMSK bit is cleared in TAMP_CR register, the TAMPxF flag must be cleared by software in order to allow a new tamper detection on the same pin.

When TAMPxMSK bit is set, the TAMPxF flag is masked, and kept cleared in TAMP_SR register. This configuration permits the low-power timers to be triggered automatically in Stop mode, without requiring the system wake-up to perform the TAMPxF clearing. In this case, the backup registers are not cleared.

This feature is available only when the tamper is configured in level detection with filtering mode (TAMPFLT = 00 and active mode is not selected). Refer to Section : Level detection with filtering on tamper inputs (passive mode) .

Timestamp on tamper event

With TAMPTS set to 1 in the RTC_CR, any internal or external tamper event causes a timestamp to occur. In case a timestamp occurs due to tamper event, either the TSF bit or the TSOVF bit is set in RTC_SR, in the same manner as if a normal timestamp event occurs.

Note: TSF is set up to 3 ck_apre cycles after TAMPxF flags. TSF is not set if RTCCLK is stopped (it is set when RTCCLK restarts).

Note: If TAMPxF is cleared before the expected rise of TSF, TSF is not set. Consequently, in case TAMPTS = 1, the software should either wait for timestamp flag before clearing the tamper flag, or should read the RTC counters values in the TAMP interrupt routine.

Edge detection on tamper inputs (passive mode)

If the TAMPFLT bits are 00, the TAMP_INx pins generate tamper detection events when either a rising edge or a falling edge is observed depending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the TAMP_INx inputs are deactivated when edge detection is selected.

Caution: When TAMPFLT = 00 and TAMPxTRG = 0 (rising edge detection), a tamper event may be detected by hardware if the tamper input is already at high level before enabling the tamper detection.

After a tamper event has been detected and cleared, the TAMP_INx should be disabled and then re-enabled (TAMPxE set to 1) before re-programming the backup registers (TAMP_BKPxR). This prevents the application from writing to the backup registers while the TAMP_INx input value still indicates a tamper detection. This is equivalent to a level detection on the TAMP_INx input.

Note: Tamper detection is still active when V _DD power is switched off. To avoid unwanted resetting of the backup registers, the pin to which the TAMPx is mapped should be externally tied to the correct level.

Level detection with filtering on tamper inputs (passive mode)

Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive samples are observed at the level designated by the TAMPxTRG bits.

The TAMP_INx inputs are precharged through the I/O internal pull-up resistance before its state is sampled, unless disabled by setting TAMPPUDIS to 1. The duration of the precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the TAMP_INx inputs.

The trade-off between tamper detection latency and power consumption through the pull-up can be optimized by using TAMPFREQ to determine the frequency of the sampling for level detection. The TAMP_IN I/O schmitt trigger is enabled only during the precharge duration to avoid any extra consumption if the tamper switch is open (floating state).

Figure 627. Tamper sampling with precharge pulse

Figure 628. Low level detection with precharge and filtering

Note: Refer to the microcontroller datasheet for the electrical characteristics of the pull-up resistors.

Active tamper detection

When the TAMPxAM bit is set in the TAMP_ATCR, the tamper events are configured in active mode, which is based on a comparison between a TAMP_OUTy pin and a TAMP_INx pin. By default (ATOSHARE = 0) the comparison is made between TAMP_INx and TAMP_OUTx (y = x). When ATOSHARE bit is set, the same output can be used for several tamper inputs. The TAMP_OUTy function is enabled on the I/O as soon as it is selected for comparison with an active tamper input TAMP_INx (TAMPxEN = TAMPxAM = 1), thanks to

ATOSHARE and ATOSELx bits. Refer to ATOSHARE and ATOSEL bits descriptions in the TAMP_ATCRx (x = 1, 2) registers.

Every two CK_ATPER cycles ( \( CK\_ATPER = 2^{ATPER} \times CK\_ATPRE \) ), TAMP_OUTy output pin provides a value provided by a pseudo random number generator (PRNG). After outputting this value, the TAMP_OUTy pin outputs its opposite value one CK_ATPER cycle after.

Table 509. Active tamper output change period

1. Assuming \( f_{RTCCLK} = 32768 \) Hz.

2. This setting requires that (PREDIV_A+1) = 128 and (PREDIV_S+1) is a multiple of 16.

PRNG is consumed by the selected tamper outputs at a different frequency depending on

the number of selected tamper outputs. The number of selected outputs depends on TAMPxAM, TAMPxE, ATOSEL and ATOSHARE.

• • When only 1 output is selected: PRNG is consumed every 16 CK_ATPER periods.
• • When 2 outputs are selected: PRNG is consumed every 8 CK_ATPER periods.
• • When 3 or 4 outputs are selected: PRNG is consumed every 4 CK_ATPER periods.
• • When 5 or more outputs are selected: PRNG is consumed every 2 CK_ATPER periods.

The PRNG needs minimum 9 CK_ATPRE cycles to output a new value. Consequently the minimum ATPER values for correct functionality are provided in the table below:

Table 510. Minimum ATPER value

The TAMP_INx pin is externally connected to TAMP_OUTy pin. The comparison is made between TAMP_OUTy output value and TAMP_INx received value, every CK_ATPRE cycle. In case a comparison mismatch occurs, the TAMPxF bit is set in the TAMP_SR register.

As an example, TAMP_OUT1 can be used for comparison with TAMP_IN1 and TAMP_IN2 by configuring and enabling both TAMP1 and TAMP2 in active mode, with ATOSHARE = 1, ATOSEL1 = 000 and ATOSEL2 = 000.

The active tamper can be combined with input filtering when FLTEN = 1. In this case, the tamper is detected only when 2 comparisons are false, in 4 consecutive comparison samples.

Figure 629. Active tamper filtering

As illustrated in Figure 629, if FLTEN = 0, any mismatch between the TAMP_OUTy output and the associated TAMP_INx input when the latter is sampled generates a tamper. This is the case in all three examples (a), (b) and (c).

If FLTEN = 1, example (a) does not generate a tamper, since only one mismatch is detected in four consecutive comparisons. In example (b), a tamper is generated since two successive mismatches are detected. Example (c) also generates a tamper, since two mismatches occur in four consecutive comparisons, even though the mismatches do not occur on successive samples.

Setting FLTEN = 1 avoids unwanted detection of tampers due to glitches, bounce or transitory states on the TAMP_INx inputs, by ignoring single pulses which are shorter than one period of CK_ATPRE, programmed in the ATCKSEL field of the TAMP_ATCR1 register. The minimum filtered pulse width is listed in Table 511 for each possible setting of ATCKSEL, assuming \( f_{RTCCLK} = 32.768 \) kHz.

Table 511. Active tamper filtered pulse duration

1. This setting requires that (PREDIV_A+1) = 128 and (PREDIV_S+1) is a multiple of 16.

Note: Multiple pulses which are shorter than one CK_ATPRE period may nevertheless cause a tamper if they result in two mismatches in four consecutive comparisons.

Caution: Entering RTC initialization mode stops CK_ATPRE and CK_ATPER clocks when ATCKSEL[3] = 1. Therefore, TAMP_OUTy pin stops toggling until INIT mode exit.

Refer to Calendar initialization and configuration .

Refer also to RTC alarm A subsecond register (RTC_ALRMASSR) , RTC alarm B subsecond register (RTC_ALRMBSSR) , RTC alarm A binary mode register (RTC_ALRABINR) and RTC alarm B binary mode register (RTC_ALRBBINR) in case RTC binary mode is used in conjunction with ATCKSEL[3] = 1.

Caution: The active tamper detection is no more functional in case of calendar overflow when ATCKSEL[3] = 1. It is mandatory to enable the internal tamper 5 on calendar overflow to ensure tamper protection.

The pseudo-random generator must be initialized with a seed. This is done by writing consecutively four 32-bit random values in the TAMP_ATSEEDR register. Programming the seed automatically sends it to the PRNG. As long as the new seed is transferred and elaborated by the PRNG, the SEEDF bit is set in the TAMP_ATOR and it is not allowed to switch off the TAMP APB clock. The duration of the elaboration is up to 184 APB clock cycles after the forth seed is written. Consequently, after writing a new seed, the user must wait until SEEDF is cleared before entering low-power modes.

The active tamper outputs are activated only after the first seed is written and the elaboration is completed. Then new seeds can be written and elaborated during active tamper activity.

Active tamper initialization

Here is the software procedure to initialize the active tampers after system reset:

Read INITS in TAMP_ATOR register.

• • If INITS = 0x0 (initialization was not done):
  • a) Write TAMP_ATCR to configure Active tamper clock, filter and output sharing if any, and active mode.
  • b) Write TAMP_CR1 to enable tampers (all the needed tampers must be enabled in the same write access).
  • c) Write SEED by writing four times in the TAMP_ATSEEDR.
  • d) Wait until SEEDF = 0 in TAMP_ATOR. Backup registers are then protected by active tamper.
• • If INITS = 0x1 (initialization already done):

  No initialization. To increase randomness a new SEED should be provided regularly. When a new SEED is provided, wait until SEEDF = 0 before entering a low-power mode which switches off the TAMP APB clock.

• • In case the tampers are disabled by software, and re-enabled afterwards, the SEED must be written after enabling tampers:
  • a) Write TAMP_CR1 to enable tampers (all the needed tampers must be enabled in the same write access).
  • b) Write SEED by writing four times in the TAMP_ATSEEDR.
  • c) Wait until SEEDF = 0 in TAMP_ATOR. Backup registers are then protected by active tamper.

47.4 TAMP low-power modes

Table 512. Effect of low-power modes on TAMP

Table 513. TAMP pins functionality over modes

1. 1. Only PC13, PI8, PA0, PA1 and PA2 are functional in Standby and V _BAT modes.
2. 2. Only PC13, PA1 and PI8 are functional in Standby mode.
3. 3. Only PC13, PA1 and PI8 are functional in V _BAT mode.

47.5 TAMP interrupts

The interrupt channel is set in the masked interrupt status register or in the secure masked interrupt status register depending on its security mode configuration (TAMPSEC).

Table 514. Interrupt requests

1. 1. The event flags are in the TAMP_SR register.
2. 2. The number of tampers and internal tampers events depend on products.
3. 3. Refer to Table 512: Effect of low-power modes on TAMP for more details about available features in the low-power modes.

47.6 TAMP registers

Refer to Section 1.2 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit).

47.6.1 TAMP control register 1 (TAMP_CR1)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7 :

TAMP privilege protection modes.

Address offset: 0x00

Backup domain reset value: 0x0000 0000

System reset: not affected

Bit 31 Reserved, must be kept at reset value.

Bit 30 ITAMP15E : Internal tamper 15 enable

0: Internal tamper 15 disabled.

1: Internal tamper 15 enabled.

Bit 29 Reserved, must be kept at reset value.

Bit 28 ITAMP13E : Internal tamper 13 enable

0: Internal tamper 13 disabled.

1: Internal tamper 13 enabled.

Bit 27 ITAMP12E : Internal tamper 12 enable

0: Internal tamper 12 disabled.

1: Internal tamper 12 enabled.

Bit 26 ITAMP11E : Internal tamper 11 enable

0: Internal tamper 11 disabled.

1: Internal tamper 11 enabled.

Bit 25 Reserved, must be kept at reset value.

Bit 24 ITAMP9E : Internal tamper 9 enable

0: Internal tamper 9 disabled.

1: Internal tamper 9 enabled.

Bit 23 ITAMP8E : Internal tamper 8 enable

0: Internal tamper 8 disabled.

1: Internal tamper 8 enabled.

Bit 22 ITAMP7E : Internal tamper 7 enable

0: Internal tamper 7 disabled.

1: Internal tamper 7 enabled

Bit 21 ITAMP6E : Internal tamper 6 enable

0: Internal tamper 6 disabled.

1: Internal tamper 6 enabled.

Bit 20 ITAMP5E : Internal tamper 5 enable

0: Internal tamper 5 disabled.

1: Internal tamper 5 enabled.

Bit 19 ITAMP4E : Internal tamper 4 enable

0: Internal tamper 4 disabled.

1: Internal tamper 4 enabled.

Bit 18 ITAMP3E : Internal tamper 3 enable

0: Internal tamper 3 disabled.

1: Internal tamper 3 enabled.

Bit 17 ITAMP2E : Internal tamper 2 enable

0: Internal tamper 2 disabled.

1: Internal tamper 2 enabled.

Bit 16 ITAMP1E : Internal tamper 1 enable

0: Internal tamper 1 disabled.

1: Internal tamper 1 enabled.

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 TAMP8E : Tamper detection on TAMP_IN8 enable ⁽¹⁾

0: Tamper detection on TAMP_IN8 is disabled.

1: Tamper detection on TAMP_IN8 is enabled.

Bit 6 TAMP7E : Tamper detection on TAMP_IN7 enable ⁽¹⁾

0: Tamper detection on TAMP_IN7 is disabled.

1: Tamper detection on TAMP_IN7 is enabled.

Bit 5 TAMP6E : Tamper detection on TAMP_IN6 enable ⁽¹⁾

0: Tamper detection on TAMP_IN6 is disabled.

1: Tamper detection on TAMP_IN6 is enabled.

Bit 4 TAMP5E : Tamper detection on TAMP_IN5 enable ⁽¹⁾

0: Tamper detection on TAMP_IN5 is disabled.

1: Tamper detection on TAMP_IN5 is enabled.

Bit 3 TAMP4E : Tamper detection on TAMP_IN4 enable ⁽¹⁾

0: Tamper detection on TAMP_IN4 is disabled.

1: Tamper detection on TAMP_IN4 is enabled.

Bit 2 TAMP3E : Tamper detection on TAMP_IN3 enable ⁽¹⁾

0: Tamper detection on TAMP_IN3 is disabled.

1: Tamper detection on TAMP_IN3 is enabled.

Bit 1 TAMP2E : Tamper detection on TAMP_IN2 enable ⁽¹⁾

0: Tamper detection on TAMP_IN2 is disabled.

1: Tamper detection on TAMP_IN2 is enabled.

Bit 0 TAMP1E : Tamper detection on TAMP_IN1 enable ⁽¹⁾

0: Tamper detection on TAMP_IN1 is disabled.

1: Tamper detection on TAMP_IN1 is enabled.

1. 1. Tamper detection mode (selected with TAMP_FLTCR, TAMP_ATCR1, TAMP_ATCR2 registers and TAMPxTRG bits in TAMP_CR2), must be configured before enabling the tamper detection.

47.6.2 TAMP control register 2 (TAMP_CR2)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7 :

TAMP privilege protection modes.

Address offset: 0x04

Backup domain reset value: 0x0000 0000

System reset: not affected

Bit 31 TAMP8TRG : Active level for tamper 8 input (active mode disabled)

• 0: If TAMPFLT ? 00 tamper 8 input staying low triggers a tamper detection event.
  If TAMPFLT = 00 tamper 8 input rising edge triggers a tamper detection event.
• 1: If TAMPFLT ? 00 tamper 8 input staying high triggers a tamper detection event.
  If TAMPFLT = 00 tamper 8 input falling edge triggers a tamper detection event.

Bit 30 TAMP7TRG : Active level for tamper 7 input (active mode disabled)

• 0: If TAMPFLT ? 00 tamper 7 input staying low triggers a tamper detection event.
  If TAMPFLT = 00 tamper 7 input rising edge triggers a tamper detection event.
• 1: If TAMPFLT ? 00 tamper 7 input staying high triggers a tamper detection event.
  If TAMPFLT = 00 tamper 7 input falling edge triggers a tamper detection event.

Bit 29 TAMP6TRG : Active level for tamper 6 input (active mode disabled)

• 0: If TAMPFLT ? 00 tamper 6 input staying low triggers a tamper detection event.
  If TAMPFLT = 00 tamper 6 input rising edge triggers a tamper detection event.
• 1: If TAMPFLT ? 00 tamper 6 input staying high triggers a tamper detection event.
  If TAMPFLT = 00 tamper 6 input falling edge triggers a tamper detection event.

Bit 28 TAMP5TRG : Active level for tamper 5 input (active mode disabled)

• 0: If TAMPFLT ? 00 tamper 5 input staying low triggers a tamper detection event.
  If TAMPFLT = 00 tamper 5 input rising edge triggers a tamper detection event.
• 1: If TAMPFLT ? 00 tamper 5 input staying high triggers a tamper detection event.
  If TAMPFLT = 00 tamper 5 input falling edge triggers a tamper detection event.

Bit 27 TAMP4TRG : Active level for tamper 4 input (active mode disabled)

• 0: If TAMPFLT ? 00 tamper 4 input staying low triggers a tamper detection event.
  If TAMPFLT = 00 tamper 4 input rising edge triggers a tamper detection event.
• 1: If TAMPFLT ? 00 tamper 4 input staying high triggers a tamper detection event.
  If TAMPFLT = 00 tamper 4 input falling edge triggers a tamper detection event.

Bit 26 TAMP3TRG : Active level for tamper 3 input

• 0: If TAMPFLT ? 00 tamper 3 input staying low triggers a tamper detection event.
  If TAMPFLT = 00 tamper 3 input rising edge triggers a tamper detection event.
• 1: If TAMPFLT ? 00 tamper 3 input staying high triggers a tamper detection event.
  If TAMPFLT = 00 tamper 3 input falling edge triggers a tamper detection event.

Bit 25 TAMP2TRG : Active level for tamper 2 input

• 0: If TAMPFLT = 00 tamper 2 input staying low triggers a tamper detection event.
  If TAMPFLT = 00 tamper 2 input rising edge triggers a tamper detection event.
• 1: If TAMPFLT = 00 tamper 2 input staying high triggers a tamper detection event.
  If TAMPFLT = 00 tamper 2 input falling edge triggers a tamper detection event.

Bit 24 TAMP1TRG : Active level for tamper 1 input

• 0: If TAMPFLT = 00 tamper 1 input staying low triggers a tamper detection event.
  If TAMPFLT = 00 tamper 1 input rising edge triggers a tamper detection event.
• 1: If TAMPFLT = 00 tamper 1 input staying high triggers a tamper detection event.
  If TAMPFLT = 00 tamper 1 input falling edge triggers a tamper detection event.

Bit 23 BKERASE : Backup registers and device secrets ⁽¹⁾ erase

Writing '1' to this bit reset the backup registers and device secrets ⁽¹⁾ . Writing 0 has no effect. This bit is always read as 0.

Bit 22 BKBLOCK : Backup registers and device secrets ⁽¹⁾ access blocked

• 0: backup registers and device secrets ⁽¹⁾ can be accessed if no tamper flag is set
• 1: backup registers and device secrets ⁽¹⁾ cannot be accessed

Bits 21:19 Reserved, must be kept at reset value.

Bit 18 TAMP3MSK : Tamper 3 mask

• 0: Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection.
• 1: Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers and device secrets ⁽¹⁾ are not erased.
  The tamper 3 interrupt must not be enabled when TAMP3MSK is set.

Bit 17 TAMP2MSK : Tamper 2 mask

• 0: Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection.
• 1: Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers and device secrets ⁽¹⁾ are not erased.
  The tamper 2 interrupt must not be enabled when TAMP2MSK is set.

Bit 16 TAMP1MSK : Tamper 1 mask

• 0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection.
• 1: Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers and device secrets ⁽¹⁾ are not erased.
  The tamper 1 interrupt must not be enabled when TAMP1MSK is set.

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 TAMP8POM : Tamper 8 potential mode

• 0: Tamper 8 event detection is in confirmed mode ⁽¹⁾ .
• 1: Tamper 8 event detection is in potential mode ⁽²⁾ .

Bit 6 TAMP7POM : Tamper 7 potential mode

• 0: Tamper 7 event detection is in confirmed mode ⁽¹⁾ .
• 1: Tamper 7 event detection is in potential mode ⁽²⁾ .

Bit 5 TAMP6POM : Tamper 6 potential mode

• 0: Tamper 6 event detection is in confirmed mode ⁽¹⁾ .
• 1: Tamper 6 event detection is in potential mode ⁽²⁾ .

• Bit 4 TAMP5POM : Tamper 5 potential mode
  • 0: Tamper 5 event detection is in confirmed mode ⁽¹⁾ .
  • 1: Tamper 5 event detection is in potential mode ⁽²⁾ .
• Bit 3 TAMP4POM : Tamper 4 potential mode
  • 0: Tamper 4 event detection is in confirmed mode ⁽¹⁾ .
  • 1: Tamper 4 event detection is in potential mode ⁽²⁾ .
• Bit 2 TAMP3POM : Tamper 3 potential mode
  • 0: Tamper 3 event detection is in confirmed mode ⁽¹⁾ .
  • 1: Tamper 3 event detection is in potential mode ⁽²⁾ .
• Bit 1 TAMP2POM : Tamper 2 potential mode
  • 0: Tamper 2 event detection is in confirmed mode ⁽¹⁾ .
  • 1: Tamper 2 event detection is in potential mode ⁽²⁾ .
• Bit 0 TAMP1POM : Tamper 1 potential mode
  • 0: Tamper 1 event detection is in confirmed mode ⁽¹⁾ .
  • 1: Tamper 1 event detection is in potential mode ⁽²⁾ .

1. 1. The effects of tamper detection in confirmed mode is described with tamp_confirmed and tamp_confirmed_rpcfgx signals in Table 507: TAMP interconnection .
2. 2. The effects of tamper detection in potential mode is described with tamp_potential and tamp_potential_rpcfgx signals in Table 507: TAMP interconnection .

47.6.3 TAMP control register 3 (TAMP_CR3)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: 0x08

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 Reserved, must be kept at reset value.

• Bit 14 ITAMP15POM : Internal tamper 15 potential mode
  • 0: Internal tamper 15 event detection is in confirmed mode ⁽¹⁾ .
  • 1: Internal tamper 15 event detection is in potential mode ⁽²⁾ .

Bit 13 Reserved, must be kept at reset value.

1. Bit 12 ITAMP13POM : Internal tamper 13 potential mode
   0: Internal tamper 13 event detection is in confirmed mode ⁽¹⁾ .
   1: Internal tamper 13 event detection is in potential mode ⁽²⁾ .
2. Bit 11 ITAMP12POM : Internal tamper 12 potential mode
   0: Internal tamper 12 event detection is in confirmed mode ⁽¹⁾ .
   1: Internal tamper 12 event detection is in potential mode ⁽²⁾ .
3. Bit 10 ITAMP11POM : Internal tamper 11 potential mode
   0: Internal tamper 11 event detection is in confirmed mode ⁽¹⁾ .
   1: Internal tamper 11 event detection is in potential mode ⁽²⁾ .
4. Bit 9 Reserved, must be kept at reset value.
5. Bit 8 ITAMP9POM : Internal tamper 9 potential mode
   0: Internal tamper 9 event detection is in confirmed mode ⁽¹⁾ .
   1: Internal tamper 9 event detection is in potential mode ⁽²⁾ .
6. Bit 7 ITAMP8POM : Internal tamper 8 potential mode
   0: Internal tamper 8 event detection is in confirmed mode ⁽¹⁾ .
   1: Internal tamper 8 event detection is in potential mode ⁽²⁾ .
7. Bit 6 ITAMP7POM : Internal tamper 7 potential mode
   0: Internal tamper 7 event detection is in confirmed mode ⁽¹⁾ .
   1: Internal tamper 7 event detection is in potential mode ⁽²⁾ .
8. Bit 5 ITAMP6POM : Internal tamper 6 potential mode
   0: Internal tamper 6 event detection is in confirmed mode ⁽¹⁾ .
   1: Internal tamper 6 event detection is in potential mode ⁽²⁾ .
9. Bit 4 ITAMP5POM : Internal tamper 5 potential mode
   0: Internal tamper 5 event detection is in confirmed mode ⁽¹⁾ .
   1: Internal tamper 5 event detection is in potential mode ⁽²⁾ .
10. Bit 3 ITAMP4POM : Internal tamper 4 potential mode
    0: Internal tamper 4 event detection is in confirmed mode ⁽¹⁾ .
    1: Internal tamper 4 event detection is in potential mode ⁽²⁾ .
11. Bit 2 ITAMP3POM : Internal tamper 3 potential mode
    0: Internal tamper 3 event detection is in confirmed mode ⁽¹⁾ .
    1: Internal tamper 3 event detection is in potential mode ⁽²⁾ .
12. Bit 1 ITAMP2POM : Internal tamper 2 potential mode
    0: Internal tamper 2 event detection is in confirmed mode ⁽¹⁾ .
    1: Internal tamper 2 event detection is in potential mode ⁽²⁾ .
13. Bit 0 ITAMP1POM : Internal tamper 1 potential mode
    0: Internal tamper 1 event detection is in confirmed mode ⁽¹⁾ .
    1: Internal tamper 1 event detection is in potential mode ⁽²⁾ .

1. 1. The effects of internal tamper detection in confirmed mode is described with tamp_confirmed and tamp_confirmed_rpcfgx signals in Table 507: TAMP interconnection
2. 2. The effects of internal tamper detection in potential mode is described with tamp_potential and tamp_potential_rpcfgx signals in Table 507: TAMP interconnection .

47.6.4 TAMP filter control register (TAMP_FLTCR)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP

secure protection modes.

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: 0x0C

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 TAMPPUDIS : TAMP_INx pull-up disable

This bit determines if each of the TAMPx pins are precharged before each sample.

0: Precharge TAMP_INx pins before sampling (enable internal pull-up)

1: Disable precharge of TAMP_INx pins.

Bits 6:5 TAMPPRCH[1:0] : TAMP_INx precharge duration

These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs.

0x0: 1 RTCCLK cycle

0x1: 2 RTCCLK cycles

0x2: 4 RTCCLK cycles

0x3: 8 RTCCLK cycles

Bits 4:3 TAMPFLT[1:0] : TAMP_INx filter count

These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs.

0x0: Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input).

0x1: Tamper event is activated after 2 consecutive samples at the active level.

0x2: Tamper event is activated after 4 consecutive samples at the active level.

0x3: Tamper event is activated after 8 consecutive samples at the active level.

Bits 2:0 TAMPFREQ[2:0] : Tamper sampling frequency

Determines the frequency at which each of the TAMP_INx inputs are sampled.

0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)

0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)

0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)

0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)

0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)

0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)

0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)

0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)

Note: This register concerns only the tamper inputs in passive mode.

47.6.5 TAMP active tamper control register 1 (TAMP_ATCR1)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: 0x10

Backup domain reset value: 0x0007 0000

System reset: not affected

Bit 31 FLTEN : Active tamper filter enable

0: Active tamper filtering disable

1: Active tamper filtering enable: a tamper event is detected when 2 comparison mismatches occur out of 4 consecutive samples.

Bit 30 ATOSHARE : Active tamper output sharing

0: Each active tamper input TAMP_INi is compared with its dedicated output TAMP_OUTi

1: Each active tamper input TAMP_INi is compared with TAMPOUTSELi defined by ATOSELi bits.

Bits 29:27 Reserved, must be kept at reset value.

Bits 26:24 ATPER[2:0] : Active tamper output change period

The tamper output is changed every \( CK\_ATPER = (2^{ATPER} \times CK\_ATPRE) \) cycles. Refer to Table 510: Minimum ATPER value .

Bits 23:20 Reserved, must be kept at reset value.

Bits 19:16 ATCKSEL[3:0] : Active tamper RTC asynchronous prescaler clock selection

These bits selects the RTC asynchronous prescaler stage output. The selected clock is CK_ATPRE.

0000: RTCCLK is selected

0001: RTCCLK/2 is selected

0010: RTCCLK/4 is selected

0011: RTCCLK/8 is selected

0100: RTCCLK/16 is selected

0101: RTCCLK/32 is selected

0110: RTCCLK/64 is selected

0111: RTCCLK/128 is selected

1011: RTCCLK/2048 is selected when (PREDIV_A+1) = 128 and (PREDIV_S+1) is a multiple of 16.

Others: Reserved

Note: These bits can be written only when all active tampers are disabled. The write protection remains for up to 1.5 CK_ATPRE cycles after all the active tampers are disable.

Bits 15:14 ATOSEL4[1:0] : Active tamper shared output 4 selection

00: TAMPOUTSEL4 = TAMP_OUT1

01: TAMPOUTSEL4 = TAMP_OUT2

10: TAMPOUTSEL4 = TAMP_OUT3

11: TAMPOUTSEL4 = TAMP_OUT4

If the TAMP_OUTx output is not available in the package pinout, the ouput selection value is reserved and must not be used.

Bits 13:12 ATOSEL3[1:0] : Active tamper shared output 3 selection

00: TAMPOUTSEL3 = TAMP_OUT1

01: TAMPOUTSEL3 = TAMP_OUT2

10: TAMPOUTSEL3 = TAMP_OUT3

11: TAMPOUTSEL3 = TAMP_OUT4

If the TAMP_OUTx output is not available in the package pinout, the ouput selection value is reserved and must not be used.

Bits 11:10 ATOSEL2[1:0] : Active tamper shared output 2 selection

00: TAMPOUTSEL2 = TAMP_OUT1

01: TAMPOUTSEL2 = TAMP_OUT2

10: TAMPOUTSEL2 = TAMP_OUT3

11: TAMPOUTSEL2 = TAMP_OUT4

If the TAMP_OUTx output is not available in the package pinout, the ouput selection value is reserved and must not be used.

Bits 9:8 ATOSEL1[1:0] : Active tamper shared output 1 selection

00: TAMPOUTSEL1 = TAMP_OUT1

01: TAMPOUTSEL1 = TAMP_OUT2

10: TAMPOUTSEL1 = TAMP_OUT3

11: TAMPOUTSEL1 = TAMP_OUT4

If the TAMP_OUTx output is not available in the package pinout, the ouput selection value is reserved and must not be used.

Bit 7 TAMP8AM : Tamper 8 active mode

0: Tamper 8 detection mode is passive.

1: Tamper 8 detection mode is active.

1. Bit 6 TAMP7AM : Tamper 7 active mode
   0: Tamper 7 detection mode is passive.
   1: Tamper 7 detection mode is active.
2. Bit 5 TAMP6AM : Tamper 6 active mode
   0: Tamper 6 detection mode is passive.
   1: Tamper 6 detection mode is active.
3. Bit 4 TAMP5AM : Tamper 5 active mode
   0: Tamper 5 detection mode is passive.
   1: Tamper 5 detection mode is active.
4. Bit 3 TAMP4AM : Tamper 4 active mode
   0: Tamper 4 detection mode is passive.
   1: Tamper 4 detection mode is active.
5. Bit 2 TAMP3AM : Tamper 3 active mode
   0: Tamper 3 detection mode is passive.
   1: Tamper 3 detection mode is active.
6. Bit 1 TAMP2AM : Tamper 2 active mode
   0: Tamper 2 detection mode is passive.
   1: Tamper 2 detection mode is active.
7. Bit 0 TAMP1AM : Tamper 1 active mode
   0: Tamper 1 detection mode is passive.
   1: Tamper 1 detection mode is active.

Note: Changing the active tamper configuration in this register is not allowed when a TAMPxAM bit is set, unless the corresponding TAMPxE bits are all cleared in the TAMP_CR1 register. All tamper configured in active mode must be enabled at the same time (by setting all related TAMPxE in the same TAMP_CR1 write). All tamper configured in active mode must be disabled at the same time (by clearing all related TAMPxE in the same TAMP_CR1 write). A minimum duration of 1 CK_ATPRE period must be waited for after disabling the active tamper and before re-enabling them.

47.6.6 TAMP active tamper seed register (TAMP_ATSEEDR)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: 0x14

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:0 SEED[31:0] : Pseudo-random generator seed value

This register must be written four times with 32-bit values to provide the 128-bit seed to the PRNG. Writing to this register automatically sends the seed value to the PRNG.

47.6.7 TAMP active tamper output register (TAMP_ATOR)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: 0x18

Backup domain reset value: 0x0000 0000

System reset: not affected, except for SEEDF which is reset to 0.

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 INITS : Active tamper initialization status

This flag is set by hardware when the PRNG has absorbed the first 128-bit seed, meaning that the enabled active tampers are functional. This flag is cleared when the active tampers are disabled.

Bit 14 SEEDF : Seed running flag

This flag is set by hardware when a new seed is written in the TAMP_ATSEEDR. It is cleared by hardware when the PRNG has absorbed this new seed, and by system reset. The TAMP APB clock must not be switched off as long as SEEDF is set.

Bits 13:8 Reserved, must be kept at reset value.

Bits 7:0 PRNG[7:0] : Pseudo-random generator value

This field provides the values of the PRNG output. Because of potential inconsistencies due to synchronization delays, PRNG must be read at least twice. The read value is correct if it is equal to previous read value.

This field can only be read when the APB is in secure mode.

47.6.8 TAMP active tamper control register 2 (TAMP_ATCR2)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: 0x1C

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:29 ATOSEL8[2:0] : Active tamper shared output 8 selection

000: TAMPOUTSEL8 = TAMP_OUT1
001: TAMPOUTSEL8 = TAMP_OUT2
010: TAMPOUTSEL8 = TAMP_OUT3
011: TAMPOUTSEL8 = TAMP_OUT4
100: TAMPOUTSEL8 = TAMP_OUT5
101: TAMPOUTSEL8 = TAMP_OUT6
110: TAMPOUTSEL8 = TAMP_OUT7
111: TAMPOUTSEL8 = TAMP_OUT8

If the TAMP_OUTx output is not available in the package pinout, the output selection value is reserved and must not be used.

Bits 28:26 ATOSEL7[2:0] : Active tamper shared output 7 selection

000: TAMPOUTSEL7 = TAMP_OUT1
001: TAMPOUTSEL7 = TAMP_OUT2
010: TAMPOUTSEL7 = TAMP_OUT3
011: TAMPOUTSEL7 = TAMP_OUT4
100: TAMPOUTSEL7 = TAMP_OUT5
101: TAMPOUTSEL7 = TAMP_OUT6
110: TAMPOUTSEL7 = TAMP_OUT7
111: TAMPOUTSEL7 = TAMP_OUT8

If the TAMP_OUTx output is not available in the package pinout, the output selection value is reserved and must not be used.

Bits 25:23 ATOSEL6[2:0] : Active tamper shared output 6 selection

000: TAMPOUTSEL6 = TAMP_OUT1
001: TAMPOUTSEL6 = TAMP_OUT2
010: TAMPOUTSEL6 = TAMP_OUT3
011: TAMPOUTSEL6 = TAMP_OUT4
100: TAMPOUTSEL6 = TAMP_OUT5
101: TAMPOUTSEL6 = TAMP_OUT6
110: TAMPOUTSEL6 = TAMP_OUT7
111: TAMPOUTSEL6 = TAMP_OUT8

If the TAMP_OUTx output is not available in the package pinout, the output selection value is reserved and must not be used.

Bits 22:20 ATOSEL5[2:0] : Active tamper shared output 5 selection

000: TAMPOUTSEL5 = TAMP_OUT1
001: TAMPOUTSEL5 = TAMP_OUT2
010: TAMPOUTSEL5 = TAMP_OUT3
011: TAMPOUTSEL5 = TAMP_OUT4
100: TAMPOUTSEL5 = TAMP_OUT5
101: TAMPOUTSEL5 = TAMP_OUT6
110: TAMPOUTSEL5 = TAMP_OUT7
111: TAMPOUTSEL5 = TAMP_OUT8

If the TAMP_OUTx output is not available in the package pinout, the output selection value is reserved and must not be used.

Bits 19:17 ATOSEL4[2:0] : Active tamper shared output 4 selection

000: TAMPOUTSEL4 = TAMP_OUT1
001: TAMPOUTSEL4 = TAMP_OUT2
010: TAMPOUTSEL4 = TAMP_OUT3
011: TAMPOUTSEL4 = TAMP_OUT4
100: TAMPOUTSEL4 = TAMP_OUT5
101: TAMPOUTSEL4 = TAMP_OUT6
110: TAMPOUTSEL4 = TAMP_OUT7
111: TAMPOUTSEL4 = TAMP_OUT8

If the TAMP_OUTx output is not available in the package pinout, the output selection value is reserved and must not be used.

Bits 18:17 are the mirror of ATOSEL4[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1.

Bits 16:14 ATOSEL3[2:0] : Active tamper shared output 3 selection

000: TAMPOUTSEL3 = TAMP_OUT1
001: TAMPOUTSEL3 = TAMP_OUT2
010: TAMPOUTSEL3 = TAMP_OUT3
011: TAMPOUTSEL3 = TAMP_OUT4
100: TAMPOUTSEL3 = TAMP_OUT5
101: TAMPOUTSEL3 = TAMP_OUT6
110: TAMPOUTSEL3 = TAMP_OUT7
111: TAMPOUTSEL3 = TAMP_OUT8

If the TAMP_OUTx output is not available in the package pinout, the output selection value is reserved and must not be used.

Bits 15:14 are the mirror of ATOSEL3[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1.

Bits 13:11 ATOSEL2[2:0] : Active tamper shared output 2 selection

000: TAMPOUTSEL2 = TAMP_OUT1
001: TAMPOUTSEL2 = TAMP_OUT2
010: TAMPOUTSEL2 = TAMP_OUT3
011: TAMPOUTSEL2 = TAMP_OUT4
100: TAMPOUTSEL2 = TAMP_OUT5
101: TAMPOUTSEL2 = TAMP_OUT6
110: TAMPOUTSEL2 = TAMP_OUT7
111: TAMPOUTSEL2 = TAMP_OUT8

If the TAMP_OUTx output is not available in the package pinout, the output selection value is reserved and must not be used.

Bits 12:11 are the mirror of ATOSEL2[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1.

Bits 10:8 ATOSEL1[2:0] : Active tamper shared output 1 selection

000: TAMPOUTSEL1 = TAMP_OUT1
001: TAMPOUTSEL1 = TAMP_OUT2
010: TAMPOUTSEL1 = TAMP_OUT3
011: TAMPOUTSEL1 = TAMP_OUT4
100: TAMPOUTSEL1 = TAMP_OUT5
101: TAMPOUTSEL1 = TAMP_OUT6
110: TAMPOUTSEL1 = TAMP_OUT7
111: TAMPOUTSEL1 = TAMP_OUT8

If the TAMP_OUTx output is not available in the package pinout, the output selection value is reserved and must not be used.

Bits 9:8 are the mirror of ATOSEL1[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1.

Bits 7:0 Reserved, must be kept at reset value.

Note: Changing the active tamper configuration in this register is not allowed when a TAMPxAM bit is set, unless the corresponding TAMPxE bits are all cleared in the TAMP_CR1 register. All tamper configured in active mode must be enabled at the same time (by setting all related TAMPxE in the same TAMP_CR1 write). All tamper configured in active mode must be disabled at the same time (by clearing all related TAMPxE in the same TAMP_CR1 write). A minimum duration of 1 CK_ATPRE period must be waited for after disabling the active tamper and before re-enabling them.

47.6.9 TAMP secure configuration register (TAMP_SECCFGR)

If TZEN = 1, this register can be written only when the APB access is secure. If TZEN = 0, BKPRWSEC[7:0], BKPWSEC[7:0] and BHKLOCK can be written with nonsecure APB access, and TAMPSEC, CNT1SEC cannot be written.

This register can be globally write-protected, or each bit of this register can be individually write-protected against non-privileged access depending on the TAMP_PRIVCFGR configuration (refer to Section 47.3.7: TAMP privilege protection modes ).

Address offset: 0x20

Backup domain reset value: 0x0000 0000

System reset: not affected

Bit 31 TAMPSEC : Tamper protection (excluding monotonic counters and backup registers)

0: Tamper configuration and interrupt can be written when the APB access is secure or nonsecure.

1: Tamper configuration and interrupt can be written only when the APB access is secure.

Note: Refer to Section 47.3.5: TAMP secure protection modes for details on the read protection.

Bit 30 BHKLOCK : Boot hardware key lock

This bit can be read and can only be written to 1 by software. It is cleared by hardware together with the backup registers following a tamper detection event or when the product state is opened.

0: The Backup registers from TAMP_BKP0R to TAMP_BKP7R can be accessed according to the Protection zone they belong to.

1: The backup registers from TAMP_BKP0R to TAMP_BKP7R cannot be accessed neither in read nor in write (they are read as 0 and write ignore).

Bits 29:24 Reserved, must be kept at reset value.

Bits 23:16 BKPWSEC[7:0] : Backup registers write protection offset

BKPWSEC value must be from 0 to 32.

Protection zone 2 is defined for backup registers from TAMP_BKPyR (y = BKPRWSEC) to TAMP_BKPzR (z = BKPWSEC-1, with BKPWSEC > BKPRWSEC):

• – if TZEN=1, these backup registers can be written only with secure access.
• – They can be read with secure or nonsecure access.

If BKPWSEC = 0 or if BKPWSEC = BKPRWSEC: there is no protection zone 2.

Protection zone 3 is defined for backup registers from TAMP_BKPtR (t = BKPWSEC if BKPWSEC = BKPRWSEC, else t = BKPRWSEC).

• – They can be read or written with secure or nonsecure access.

If BKPWSEC = 32: there is no protection zone 3.

Refer to Figure 626: Backup registers protection zones.

Note: If TZEN=0: the protection zone 2 can be read and written with nonsecure access.

Note: If BKPWPRIV is set, BKPRWSEC[7:0] can be written only in privileged mode.

Bit 15 CNT1SEC : Monotonic counter 1 secure protection

0: Monotonic counter 1 (TAMP_COUNT1R) can be read and written when the APB access is secure or nonsecure.

1: Monotonic counter 1 (TAMP_COUNT1R) can be read and written only when the APB access is secure.

Bits 14:8 Reserved, must be kept at reset value.

Bits 7:0 BKPRWSEC[7:0] : Backup registers read/write protection offset

BKPRWSEC value must be from 0 to 32.

Protection zone 1 is defined for backup registers from TAMP_BKP0R to TAMP_BKPxR (x = BKPRWSEC-1, with \( BKPRWSEC \ge 1 \) ).

– if TZEN=1, these backup registers can be read and written only with secure access.
If BKPRWSEC = 0: there is no protection zone 1.

Refer to Figure 626: Backup registers protection zones .

Note: If TZEN=0: the protection zone 1 can be read and written with nonsecure access.

Note: If BKPRWPRIV is set, BKPRWSEC[7:0] can be written only in privileged mode.

47.6.10 TAMP privilege configuration register (TAMP_PRIVCFGR)

This register can be written only when the APB access is privileged.

When TZEN = 1, this register can be write-protected, or each bit of this register can be individually write-protected against nonsecure access depending on the TAMP_SECCFGR configuration (refer to Section 47.3.5: TAMP secure protection modes ).

Address offset: 0x24

Backup domain reset value: 0x0000 0000

System reset: not affected

Bit 31 TAMPPRIV : Tamper privilege protection (excluding backup registers)

0: Tamper configuration and interrupt can be written with privileged or unprivileged access.

1: Tamper configuration and interrupt can be written only with privileged access.

Note: Refer to Section 47.3.7: TAMP privilege protection modes for details on the read protection.

Bit 30 BKPWPRIV : Backup registers zone 2 privilege protection

0: Backup registers zone 2 can be written with privileged or unprivileged access.

1: Backup registers zone 2 can be written only with privileged access.

Bit 29 BKPRWPRIV : Backup registers zone 1 privilege protection

0: Backup registers zone 1 can be read and written with privileged or unprivileged access.

1: Backup registers zone 1 can be read and written only with privileged access

Bits 28:16 Reserved, must be kept at reset value.

Bit 15 CNT1PRIV : Monotonic counter 1 privilege protection

0: Monotonic counter 1 (TAMP_COUNT1R) can be read and written when the APB access is privileged or non-privileged.

1: Monotonic counter 1 (TAMP_COUNT1R) can be read and written only when the APB access is privileged.

Bits 14:0 Reserved, must be kept at reset value.

47.6.11 TAMP interrupt enable register (TAMP_IER)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: 0x2C

Backup domain reset value: 0x0000 0000

System reset: not affected

Bit 31 Reserved, must be kept at reset value.

Bit 30 ITAMP15IE : Internal tamper 15 interrupt enable

0: Internal tamper 15 interrupt disabled.

1: Internal tamper 15 interrupt enabled.

Bit 29 Reserved, must be kept at reset value.

Bit 28 ITAMP13IE : Internal tamper 13 interrupt enable

0: Internal tamper 13 interrupt disabled.

1: Internal tamper 13 interrupt enabled.

1. Bit 27 ITAMP12IE : Internal tamper 12 interrupt enable
   0: Internal tamper 12 interrupt disabled.
   1: Internal tamper 12 interrupt enabled.
2. Bit 26 ITAMP11IE : Internal tamper 11 interrupt enable
   0: Internal tamper 11 interrupt disabled.
   1: Internal tamper 11 interrupt enabled.
3. Bit 25 Reserved, must be kept at reset value.
4. Bit 24 ITAMP9IE : Internal tamper 9 interrupt enable
   0: Internal tamper 9 interrupt disabled.
   1: Internal tamper 9 interrupt enabled.
5. Bit 23 ITAMP8IE : Internal tamper 8 interrupt enable
   0: Internal tamper 8 interrupt disabled.
   1: Internal tamper 8 interrupt enabled.
6. Bit 22 ITAMP7IE : Internal tamper 7 interrupt enable
   0: Internal tamper 7 interrupt disabled.
   1: Internal tamper 7 interrupt enabled.
7. Bit 21 ITAMP6IE : Internal tamper 6 interrupt enable
   0: Internal tamper 6 interrupt disabled.
   1: Internal tamper 6 interrupt enabled.
8. Bit 20 ITAMP5IE : Internal tamper 5 interrupt enable
   0: Internal tamper 5 interrupt disabled.
   1: Internal tamper 5 interrupt enabled.
9. Bit 19 ITAMP4IE : Internal tamper 4 interrupt enable
   0: Internal tamper 4 interrupt disabled.
   1: Internal tamper 4 interrupt enabled.
10. Bit 18 ITAMP3IE : Internal tamper 3 interrupt enable
    0: Internal tamper 3 interrupt disabled.
    1: Internal tamper 3 interrupt enabled.
11. Bit 17 ITAMP2IE : Internal tamper 2 interrupt enable
    0: Internal tamper 2 interrupt disabled.
    1: Internal tamper 2 interrupt enabled.
12. Bit 16 ITAMP1IE : Internal tamper 1 interrupt enable
    0: Internal tamper 1 interrupt disabled.
    1: Internal tamper 1 interrupt enabled
13. Bits 15:8 Reserved, must be kept at reset value.
14. Bit 7 TAMP8IE : Tamper 8 interrupt enable
    0: Tamper 8 interrupt disabled.
    1: Tamper 8 interrupt enabled.
15. Bit 6 TAMP7IE : Tamper 7 interrupt enable
    0: Tamper 7 interrupt disabled.
    1: Tamper 7 interrupt enabled.
16. Bit 5 TAMP6IE : Tamper 6 interrupt enable
    0: Tamper 6 interrupt disabled.
    1: Tamper 6 interrupt enabled.

Bit 4 TAMP5IE : Tamper 5 interrupt enable

0: Tamper 5 interrupt disabled.
1: Tamper 5 interrupt enabled.

Bit 3 TAMP4IE : Tamper 4 interrupt enable

0: Tamper 4 interrupt disabled.
1: Tamper 4 interrupt enabled.

Bit 2 TAMP3IE : Tamper 3 interrupt enable

0: Tamper 3 interrupt disabled.
1: Tamper 3 interrupt enabled..

Bit 1 TAMP2IE : Tamper 2 interrupt enable

0: Tamper 2 interrupt disabled.
1: Tamper 2 interrupt enabled.

Bit 0 TAMP1IE : Tamper 1 interrupt enable

0: Tamper 1 interrupt disabled.
1: Tamper 1 interrupt enabled.

47.6.12 TAMP status register (TAMP_SR)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: 0x30

Backup domain reset value: 0x0000 0000

System reset: not affected

Bit 31 Reserved, must be kept at reset value.

Bit 30 ITAMP15F : Internal tamper 15 flag

This flag is set by hardware when a tamper detection event is detected on the internal tamper 15.

Bit 29 Reserved, must be kept at reset value.

Bit 28 ITAMP13F : Internal tamper 13 flag

This flag is set by hardware when a tamper detection event is detected on the internal tamper 13.

Bit 27 ITAMP12F : Internal tamper 12 flag

This flag is set by hardware when a tamper detection event is detected on the internal tamper 12.

1. Bit 26 ITAMP11F : Internal tamper 11 flag
   This flag is set by hardware when a tamper detection event is detected on the internal tamper 11.
2. Bit 25 Reserved, must be kept at reset value.
3. Bit 24 ITAMP9F : Internal tamper 9 flag
   This flag is set by hardware when a tamper detection event is detected on the internal tamper 9.
4. Bit 23 ITAMP8F : Internal tamper 8 flag
   This flag is set by hardware when a tamper detection event is detected on the internal tamper 8.
5. Bit 22 ITAMP7F : Internal tamper 7 flag
   This flag is set by hardware when a tamper detection event is detected on the internal tamper 7.
6. Bit 21 ITAMP6F : Internal tamper 6 flag
   This flag is set by hardware when a tamper detection event is detected on the internal tamper 6.
7. Bit 20 ITAMP5F : Internal tamper 5 flag
   This flag is set by hardware when a tamper detection event is detected on the internal tamper 5.
8. Bit 19 ITAMP4F : Internal tamper 4 flag
   This flag is set by hardware when a tamper detection event is detected on the internal tamper 4.
9. Bit 18 ITAMP3F : Internal tamper 3 flag
   This flag is set by hardware when a tamper detection event is detected on the internal tamper 3.
10. Bit 17 ITAMP2F : Internal tamper 2 flag
    This flag is set by hardware when a tamper detection event is detected on the internal tamper 2.
11. Bit 16 ITAMP1F : Internal tamper 1 flag
    This flag is set by hardware when a tamper detection event is detected on the internal tamper 1.
12. Bits 15:8 Reserved, must be kept at reset value.
13. Bit 7 TAMP8F : TAMP8 detection flag
    This flag is set by hardware when a tamper detection event is detected on the TAMP8 input.
14. Bit 6 TAMP7F : TAMP7 detection flag
    This flag is set by hardware when a tamper detection event is detected on the TAMP7 input.
15. Bit 5 TAMP6F : TAMP6 detection flag
    This flag is set by hardware when a tamper detection event is detected on the TAMP6 input.
16. Bit 4 TAMP5F : TAMP5 detection flag
    This flag is set by hardware when a tamper detection event is detected on the TAMP5 input.
17. Bit 3 TAMP4F : TAMP4 detection flag
    This flag is set by hardware when a tamper detection event is detected on the TAMP4 input.

Bit 2 TAMP3F : TAMP3 detection flag

This flag is set by hardware when a tamper detection event is detected on the TAMP3 input.

Bit 1 TAMP2F : TAMP2 detection flag

This flag is set by hardware when a tamper detection event is detected on the TAMP2 input.

Bit 0 TAMP1F : TAMP1 detection flag

This flag is set by hardware when a tamper detection event is detected on the TAMP1 input.

47.6.13 TAMP nonsecure masked interrupt status register (TAMP_MISR)

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: 0x34

Backup domain reset value: 0x0000 0000

System reset: not affected

Bit 31 Reserved, must be kept at reset value.

Bit 30 ITAMP15MF : internal tamper 15 nonsecure interrupt masked flag

This flag is set by hardware when the internal tamper 15 nonsecure interrupt is raised.

Bit 29 Reserved, must be kept at reset value.

Bit 28 ITAMP13MF : internal tamper 13 nonsecure interrupt masked flag

This flag is set by hardware when the internal tamper 13 nonsecure interrupt is raised.

Bit 27 ITAMP12MF : internal tamper 12 nonsecure interrupt masked flag

This flag is set by hardware when the internal tamper 12 nonsecure interrupt is raised.

Bit 26 ITAMP11MF : internal tamper 11 nonsecure interrupt masked flag

This flag is set by hardware when the internal tamper 11 nonsecure interrupt is raised.

Bit 25 Reserved, must be kept at reset value.

Bit 24 ITAMP9MF : internal tamper 9 nonsecure interrupt masked flag

This flag is set by hardware when the internal tamper 9 nonsecure interrupt is raised.

Bit 23 ITAMP8MF : Internal tamper 8 nonsecure interrupt masked flag

This flag is set by hardware when the internal tamper 8 nonsecure interrupt is raised.

Bit 22 ITAMP7MF : Internal tamper 7 tamper nonsecure interrupt masked flag

This flag is set by hardware when the internal tamper 7 nonsecure interrupt is raised.

Bit 21 ITAMP6MF : Internal tamper 6 nonsecure interrupt masked flag

This flag is set by hardware when the internal tamper 6 nonsecure interrupt is raised.

Bit 20 ITAMP5MF : Internal tamper 5 nonsecure interrupt masked flag
This flag is set by hardware when the internal tamper 5 nonsecure interrupt is raised.

Bit 19 ITAMP4MF : Internal tamper 4 nonsecure interrupt masked flag
This flag is set by hardware when the internal tamper 4 nonsecure interrupt is raised.

Bit 18 ITAMP3MF : Internal tamper 3 nonsecure interrupt masked flag
This flag is set by hardware when the internal tamper 3 nonsecure interrupt is raised.

Bit 17 ITAMP2MF : Internal tamper 2 nonsecure interrupt masked flag
This flag is set by hardware when the internal tamper 2 nonsecure interrupt is raised.

Bit 16 ITAMP1MF : Internal tamper 1 nonsecure interrupt masked flag
This flag is set by hardware when the internal tamper 1 nonsecure interrupt is raised.

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 TAMP8MF : TAMP8 nonsecure interrupt masked flag
This flag is set by hardware when the tamper 8 nonsecure interrupt is raised.

Bit 6 TAMP7MF : TAMP7 nonsecure interrupt masked flag
This flag is set by hardware when the tamper 7 nonsecure interrupt is raised.

Bit 5 TAMP6MF : TAMP6 nonsecure interrupt masked flag
This flag is set by hardware when the tamper 6 nonsecure interrupt is raised.

Bit 4 TAMP5MF : TAMP5 nonsecure interrupt masked flag
This flag is set by hardware when the tamper 5 nonsecure interrupt is raised.

Bit 3 TAMP4MF : TAMP4 nonsecure interrupt masked flag
This flag is set by hardware when the tamper 4 nonsecure interrupt is raised.

Bit 2 TAMP3MF : TAMP3 nonsecure interrupt masked flag
This flag is set by hardware when the tamper 3 nonsecure interrupt is raised.

Bit 1 TAMP2MF : TAMP2 nonsecure interrupt masked flag
This flag is set by hardware when the tamper 2 nonsecure interrupt is raised.

Bit 0 TAMP1MF : TAMP1 nonsecure interrupt masked flag
This flag is set by hardware when the tamper 1 nonsecure interrupt is raised.

47.6.14 TAMP secure masked interrupt status register (TAMP_SMISR)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: 0x38

Backup domain reset value: 0x0000 0000

System reset: not affected

Bit 31 Reserved, must be kept at reset value.

Bit 30 ITAMP15MF : internal tamper 15 secure interrupt masked flag

This flag is set by hardware when the internal tamper 15 secure interrupt is raised.

Bit 29 Reserved, must be kept at reset value.

Bit 28 ITAMP13MF : internal tamper 13 secure interrupt masked flag

This flag is set by hardware when the internal tamper 13 secure interrupt is raised.

Bit 27 ITAMP12MF : internal tamper 12 secure interrupt masked flag

This flag is set by hardware when the internal tamper 12 secure interrupt is raised.

Bit 26 ITAMP11MF : internal tamper 11 secure interrupt masked flag

This flag is set by hardware when the internal tamper 11 secure interrupt is raised.

Bit 25 Reserved, must be kept at reset value.

Bit 24 ITAMP9MF : internal tamper 9 secure interrupt masked flag

This flag is set by hardware when the internal tamper 9 secure interrupt is raised.

Bit 23 ITAMP8MF : Internal tamper 8 secure interrupt masked flag

This flag is set by hardware when the internal tamper 8 secure interrupt is raised.

Bit 22 ITAMP7MF : Internal tamper 7 secure interrupt masked flag

This flag is set by hardware when the internal tamper 7 secure interrupt is raised.

Bit 21 ITAMP6MF : Internal tamper 6 secure interrupt masked flag

This flag is set by hardware when the internal tamper 6 secure interrupt is raised.

Bit 20 ITAMP5MF : Internal tamper 5 secure interrupt masked flag

This flag is set by hardware when the internal tamper 5 secure interrupt is raised.

Bit 19 ITAMP4MF : Internal tamper 4 secure interrupt masked flag

This flag is set by hardware when the internal tamper 4 secure interrupt is raised.

Bit 18 ITAMP3MF : Internal tamper 3 secure interrupt masked flag

This flag is set by hardware when the internal tamper 3 secure interrupt is raised.

Bit 17 ITAMP2MF : Internal tamper 2 secure interrupt masked flag

This flag is set by hardware when the internal tamper 2 secure interrupt is raised.

Bit 16 ITAMP1MF : Internal tamper 1 secure interrupt masked flag

This flag is set by hardware when the internal tamper 1 secure interrupt is raised.

Bits 15:8 Reserved, must be kept at reset value.

• Bit 7 TAMP8MF : TAMP8 secure interrupt masked flag
  This flag is set by hardware when the tamper 8 secure interrupt is raised.
• Bit 6 TAMP7MF : TAMP7 secure interrupt masked flag
  This flag is set by hardware when the tamper 7 secure interrupt is raised.
• Bit 5 TAMP6MF : TAMP6 secure interrupt masked flag
  This flag is set by hardware when the tamper 6 secure interrupt is raised.
• Bit 4 TAMP5MF : TAMP5 secure interrupt masked flag
  This flag is set by hardware when the tamper 5 secure interrupt is raised.
• Bit 3 TAMP4MF : TAMP4 secure interrupt masked flag
  This flag is set by hardware when the tamper 4 secure interrupt is raised.
• Bit 2 TAMP3MF : TAMP3 secure interrupt masked flag
  This flag is set by hardware when the tamper 3 secure interrupt is raised.
• Bit 1 TAMP2MF : TAMP2 secure interrupt masked flag
  This flag is set by hardware when the tamper 2 secure interrupt is raised.
• Bit 0 TAMP1MF : TAMP1 secure interrupt masked flag
  This flag is set by hardware when the tamper 1 secure interrupt is raised.

47.6.15 TAMP status clear register (TAMP_SCR)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: 0x3C

System reset value: 0x0000 0000

• Bit 31 Reserved, must be kept at reset value.
• Bit 30 CITAMP15F : Clear ITAMP15 detection flag
  Writing 1 in this bit clears the ITAMP15F bit in the TAMP_SR register.
• Bit 29 Reserved, must be kept at reset value.
• Bit 28 CITAMP13F : Clear ITAMP13 detection flag
  Writing 1 in this bit clears the ITAMP13F bit in the TAMP_SR register.
• Bit 27 CITAMP12F : Clear ITAMP12 detection flag
  Writing 1 in this bit clears the ITAMP12F bit in the TAMP_SR register.

1. Bit 26 CITAMP11F : Clear ITAMP11 detection flag
   Writing 1 in this bit clears the ITAMP11F bit in the TAMP_SR register.
2. Bit 25 Reserved, must be kept at reset value.
3. Bit 24 CITAMP9F : Clear ITAMP9 detection flag
   Writing 1 in this bit clears the ITAMP9F bit in the TAMP_SR register.
4. Bit 23 CITAMP8F : Clear ITAMP8 detection flag
   Writing 1 in this bit clears the ITAMP8F bit in the TAMP_SR register.
5. Bit 22 CITAMP7F : Clear ITAMP7 detection flag
   Writing 1 in this bit clears the ITAMP7F bit in the TAMP_SR register.
6. Bit 21 CITAMP6F : Clear ITAMP6 detection flag
   Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register.
7. Bit 20 CITAMP5F : Clear ITAMP5 detection flag
   Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register.
8. Bit 19 CITAMP4F : Clear ITAMP4 detection flag
   Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register.
9. Bit 18 CITAMP3F : Clear ITAMP3 detection flag
   Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register.
10. Bit 17 CITAMP2F : Clear ITAMP2 detection flag
    Writing 1 in this bit clears the ITAMP2F bit in the TAMP_SR register.
11. Bit 16 CITAMP1F : Clear ITAMP1 detection flag
    Writing 1 in this bit clears the ITAMP1F bit in the TAMP_SR register.
12. Bits 15:8 Reserved, must be kept at reset value.
13. Bit 7 CTAMP8F : Clear TAMP8 detection flag
    Writing 1 in this bit clears the TAMP8F bit in the TAMP_SR register.
14. Bit 6 CTAMP7F : Clear TAMP7 detection flag
    Writing 1 in this bit clears the TAMP7F bit in the TAMP_SR register.
15. Bit 5 CTAMP6F : Clear TAMP6 detection flag
    Writing 1 in this bit clears the TAMP6F bit in the TAMP_SR register.
16. Bit 4 CTAMP5F : Clear TAMP5 detection flag
    Writing 1 in this bit clears the TAMP5F bit in the TAMP_SR register.
17. Bit 3 CTAMP4F : Clear TAMP4 detection flag
    Writing 1 in this bit clears the TAMP4F bit in the TAMP_SR register.
18. Bit 2 CTAMP3F : Clear TAMP3 detection flag
    Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register.
19. Bit 1 CTAMP2F : Clear TAMP2 detection flag
    Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register.
20. Bit 0 CTAMP1F : Clear TAMP1 detection flag
    Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register.

47.6.16 TAMP monotonic counter 1 register (TAMP_COUNT1R)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: 0x040

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:0 COUNT[31:0]:

This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value.

47.6.17 TAMP option register (TAMP_OR)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: 0x50

Backup domain reset value: 0x0000 0000

System reset: not affected

1. Bits 31:11 Reserved, must be kept at reset value.
2. Bit 10 IN4_RMP : TAMP_IN4 mapping
   0: TAMP_IN4 is on PA2
   1: TAMP_IN4 is on PI11
3. Bit 9 IN3_RMP : TAMP_IN3 mapping
   0: TAMP_IN3 is on PC1
   1: TAMP_IN3 is on PE6
4. Bit 8 IN2_RMP : TAMP_IN2 mapping
   0: TAMP_IN2 is on PA0
   1: TAMP_IN2 is on PI8
5. Bits 7:4 Reserved, must be kept at reset value.
6. Bit 3 OUT5_RMP : TAMP_OUT5 mapping
   0: TAMP_OUT5 is on PI11
   1: TAMP_OUT5 is on PC1
7. Bits 2:1 OUT3_RMP[1:0] : TAMP_OUT3 mapping
   00: TAMP_OUT3 is on PC13
   01: TAMP_OUT3 is on PI8
   10: TAMP_OUT3 is on PE3
   11: TAMP_OUT3 is on PA2
8. Bit 0 Reserved, must be kept at reset value.

47.6.18 TAMP resources protection configuration register (TAMP_RPCFGR)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: 0x54

Backup domain reset value: 0x0000 0000

System reset: not affected

Bit 31 Reserved, must be kept at reset value.

Bits 30:8 Reserved, must be kept at reset value.

Bit 7 Reserved, must be kept at reset value.

Bit 6 Reserved, must be kept at reset value.

Bit 5 Reserved, must be kept at reset value.

Bit 4 Reserved, must be kept at reset value.

Bit 3 Reserved, must be kept at reset value.

Bit 2 Reserved, must be kept at reset value.

Bit 1 Reserved, must be kept at reset value.

Bit 0 RPCFG0 : Configurable resource 0 protection ⁽¹⁾

0: Resource 0 is not included in the device secrets protected by TAMP peripheral
1: Resource 0 is included in the device secrets protected by TAMP peripheral

1. 1. Refer to tamp_confirmed_rpcfg0 and tamp_potential_rpcfg0 signals in Table 505: TAMP input/output pins and Table 507: TAMP interconnection .

47.6.19 TAMP backup x register (TAMP_BKPxR)

This register can be protected against nonsecure access. Refer to Section 47.3.5: TAMP secure protection modes .

This register can be protected against non-privileged access. Refer to Section 47.3.7: TAMP privilege protection modes .

Address offset: \( 0x100 + 0x04 * x \) , ( \( x = 0 \) to \( 31 \) )

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:0 BKP[31:0]:

The application can write or read data to and from these registers.

In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the product state is opened.

47.6.20 TAMP register map

Table 515. TAMP register map and reset values

Table 515. TAMP register map and reset values (continued)

Refer to Section 2.3: Memory organization for the register boundary addresses.