18. Extended interrupts and event controller (EXTI)

The extended interrupts and event controller (EXTI) manages the individual CPU and system wake-up through configurable and direct event inputs. It provides wake-up requests to the power control and generates an interrupt request to the CPU NVIC and events to the CPU event input. For the CPU, an additional event generation block (EVG) is needed to generate the CPU event signal.

The EXTI wake-up requests allow the system to be woken up from Stop modes.

The interrupt request and event request generation can be used also in Run modes.

The EXTI also includes the EXTI mux IO port selection.

18.1 EXTI main features

The EXTI main features are the following:

• • Up to 59 input events supported
• • All event inputs allow the possibility to wake up the system.
• • Events that do not have an associated wake-up flag in the peripheral, have a flag in the EXTI and generate an interrupt to the CPU from the EXTI.
• • Events can be used to generate a CPU wake-up event.

The asynchronous event inputs are classified in two groups:

• • Configurable events (signals from I/Os or peripherals able to generate a pulse), with the following features
  • – Selectable active trigger edge
  • – Interrupt pending status register bits independent for the rising and falling edge
  • – Individual interrupt and event generation mask, used for conditioning the CPU wake-up, interrupt and event generation
  • – Software trigger possibility
  • – Secure events: The access to control and configuration bits of secure input events can be made secure and or privilege.
  • – EXTI IO port selection
• • Direct events (interrupt and wake-up sources from peripherals having an associated flag which requires to be cleared in the peripheral), with the following features:
  • – Fixed rising edge active trigger
  • – No interrupt pending status register bit in the EXTI (the interrupt pending status flag is provided by the peripheral generating the event)
  • – Individual interrupt and event generation mask, used to condition the CPU wake-up and event generation
  • – No software trigger possibility

18.2 EXTI block diagram

The EXTI consists of a register block accessed via an AHB interface, the event input trigger block, the masking block and EXTI mux as shown in Figure 91 .

The register block contains all the EXTI registers.

The event input trigger block provides event input edge trigger logic.

The masking block provides the event input distribution to the different wake-up, interrupt and event outputs, and their masking.

The EXTI mux provides the IO port selection on to the EXTI event signal.

Figure 91. EXTI block diagram

Table 148. EXTI signals

Table 149. EVG signals

18.2.1 EXTI connections between peripherals and CPU

Some peripherals able to generate wake-up or interrupt events when the system is in Stop mode, are connected to the EXTI.

• • Peripheral wake-up signals that generate a pulse or do not have an interrupt status bits in the peripheral, are connected to an EXTI configurable event input. For these events, the EXTI provides a status pending bit to be cleared. It is the EXTI interrupt, associated with the status bit, that interrupts the CPU.
• • Peripheral interrupt and wake-up signals with a status bit in the peripheral to be cleared are connected to an EXTI direct event input. There is no status pending bit within the EXTI. The interrupt or wake-up is cleared by the CPU in the peripheral. It is the peripheral interrupt that interrupts the CPU directly.

All GPIO ports input to the EXTI multiplexer allow the selection of a port pin to wake up the system via a configurable event.

The EXTI configurable event interrupts are connected to the NVIC.

The dedicated EXTI/EVG CPU event is connected to the CPU rxev input.

The EXTI CPU wake-up signals are connected to the PWR and are used to wake up the system and the CPU sub-system bus clocks.

18.2.2 EXTI interrupt/event mapping

The EXTI lines are connected as shown in the following table.

Table 150. EXTI line connections

Table 150. EXTI line connections (continued)

1. Not available on STM32H523/33xx devices.

1. Available only on STM32H523/33xx devices.

18.3 EXTI functional description

The events features are controlled from register bits as follows:

• Active trigger edge enable
  • by rising edge selection in the EXTI rising trigger selection register (EXTI_RTSR1) and EXTI rising trigger selection register 2 (EXTI_RTSR2)
  • by falling edge selection in the EXTI falling trigger selection register (EXTI_FTSR1) and EXTI falling trigger selection register 2 (EXTI_FTSR2)
• Software trigger in the EXTI software interrupt event register (EXTI_SWIER1) and EXTI software interrupt event register 2 (EXTI_SWIER2)
• Interrupt pending flag in the
  • EXTI rising edge pending register (EXTI_RPR1) and EXTI rising edge pending register 2 (EXTI_RPR2)
  • EXTI falling edge pending register (EXTI_FPR1) and EXTI falling edge pending register 2 (EXTI_FPR2)
• CPU wake-up and interrupt enable in the
  • EXTI CPU wake-up with interrupt mask register (EXTI_IMR1) and EXTI CPU wake-up with interrupt mask register 2 (EXTI_IMR2)
• CPU wake-up and event enable
  • EXTI CPU wake-up with event mask register (EXTI_EMR1) and EXTI CPU wake-up with event mask register 2 (EXTI_EMR2)

18.3.1 EXTI configurable event input wake-up

The figure below is a detailed representation of the logic associated with configurable event inputs that wake up the CPU sub-system bus clocks and generate an EXTI pending flag and interrupt to the CPU, and/or a CPU wake-up event.

Figure 92. Configurable event trigger logic CPU wake-up

1. Only for the input events that support CPU rxeu generation c_event.

The software interrupt event register allows configurable events to be triggered by software, writing the corresponding register bit, whatever the edge selection setting.

The configurable event active trigger edge (or both edges) is selected and enabled in the rising/falling edge selection registers.

The CPU has its dedicated wake-up (interrupt) mask register and a dedicated event mask registers. When the event is enabled, it is generated to the CPU. All events for the CPU are ORed together into a single CPU event signal. The event pending registers (EXTI_RPR and EXTI_FPR) are not set for an unmasked CPU event.

The configurable events have unique interrupt pending request registers. The pending register is only set for an unmasked interrupt. Each configurable event provides a common interrupt to the CPU. The configurable event interrupts must be acknowledged by software in the EXTI_RPR and/or EXTI_FPR registers.

When a CPU wake-up (interrupt) or CPU event is enabled, the asynchronous edge detection circuit is reset by the clocked delay and rising edge detect pulse generator. This guarantees that the EXTI hclk clock is woken up before the asynchronous edge detection circuit is reset.

Note: A detected configurable event interrupt pending request can be cleared by the CPU with the correct access permission. The system is not able to enter into low-power modes as long as an interrupt pending request is active.

18.3.2 EXTI direct event input wake-up

The direct events do not have an associated EXTI interrupt. The EXTI only wakes up the system and CPU subsystem clocks, and can generate a CPU wake-up event. The peripheral synchronous interrupt, associated with the direct wake-up event, wakes up the CPU.

The EXTI direct event is able to generate a CPU event that wakes up the CPU. The CPU event may occur before the associated peripheral interrupt flag is set.

Figure 93. EXTI direct events

18.3.3 EXTI mux selection

The EXTI mux allows the selection of GPIOs as interrupts and wake-up. GPIOs are connected via 16 EXTI mux lines to the first 16 EXTI events as configurable event. The selection of GPIO port as EXTI mux output is controlled in the EXTI external interrupt selection register (EXTI_EXTICR1) .

Figure 94. EXTI mux GPIO selection

The EXTI mux outputs are available as output signals from the EXTI to trigger other peripherals, whatever the masking in EXTI_IMR and EXTI_EMR registers.

18.4 EXTI functional behavior

The configurable events are enabled by enabling at least one of the trigger edges.

Once an event input is enabled, the CPU wake-up generation is conditioned by the CPU interrupt mask and CPU event mask.

Table 151. Masking functionality

1. The single exti(n) interrupt goes to the CPU. If no interrupt is required for CPU(m), the exti(n) interrupt must be masked in the CPU NVIC.

2. Only if CPU interrupt is enabled in EXTI_IMR.IMn.

For configurable event inputs, when the enabled edges occur on the event input, an event request is generated. When the associated CPU interrupt is unmasked, the corresponding pending bits EXTI_RPR.RPIFn and/or EXTI_FPR.FPIFn is/are set: the CPU sub-system is woken up and the CPU interrupt signal is activated. The EXTI_RPR.RPIFn and/or

EXTI_FPR.FPIFn pending bits must be cleared by software writing it to 1. This action clears the CPU interrupt.

For the configurable event inputs, an event request can be generated by software when writing a 1 in the software interrupt/event register EXTI_SWIER, allowing the generation of a rising edge on the event. The rising edge event pending bit is set in EXTI_RPR, whatever the setting in EXTI_RTSR.

18.5 EXTI event protection

The EXTI is able to protect event register bits from being modified by non-secure and unprivileged accesses. The protection is individually activated per input event via the register bits in EXTI_SECCFGR and EXTI_PRIVCFGR. At EXTI level, the protection consists in preventing the following unauthorized write access:

• • Change the settings of the secure and/or privileged configurable events.
• • Change the masking of the secure and/or privileged input events.
• • Clear pending status of the secure and/or privileged input events.

Table 152. Register protection overview

1. Security is enabled with the individual input event (EXTI_SECCFGR register).

2. Privilege is enabled with the individual Input event (EXTI_PRIVCFGR register).

18.5.1 EXTI security protection

When security is enabled for an input event, the associated input event configuration and control bits can only be modified and read by a secure access. A non-secure write access is discarded and a read returns 0.

When input events are non-secure, the security is disabled. The associated input event configuration and control bits can be modified and read by a secure access and non-secure access.

The security configuration in registers EXTI_SECCFGR can be globally locked after reset by EXTI_LOCKR.LOCK.

18.5.2 EXTI privilege protection

When privilege is enabled for an input event, the associated input event configuration and control bits can only be modified and read by a privileged access. An unprivileged write access is discarded and a read returns 0.

When input events are unprivileged, the privilege is disabled. The associated input event configuration and control bits can be modified and read by a privileged access and unprivileged access.

The privileged configuration in registers EXTI_PRIVCFGR can be globally locked after reset by EXTI_LOCKR.LOCK.

18.6 EXTI registers

Table 153. EXTI register map sections

All registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit) access.

18.6.1 EXTI rising trigger selection register (EXTI_RTSR1)

Address offset: 0x000

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:17 Reserved, must be kept at reset value.

Bits 16:0 RTx : Rising trigger event configuration bit of configurable event input x ⁽¹⁾ (x = 16 to 0)

When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, RTx can be accessed only with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, RTx can be accessed only with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0.

0: Rising trigger disabled (for event and interrupt) for input line

1: Rising trigger enabled (for event and interrupt) for input line

1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a rising edge on the configurable event input occurs during writing of the register, the associated pending bit is not set. Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

18.6.2 EXTI falling trigger selection register (EXTI_FTSR1)

Address offset: 0x004

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:17 Reserved, must be kept at reset value.

Bits 16:0 FTx : Falling trigger event configuration bit of configurable event input x ⁽¹⁾ (x = 16 to 0)

When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, FTx can be accessed only with secure access.

Non-secure write to this FTx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, FTx can be accessed only with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0.

0: Falling trigger disabled (for event and Interrupt) for input line

1: Falling trigger enabled (for event and Interrupt) for input line.

1. 1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs.
   If a falling edge on the configurable event input occurs during writing of the register, the associated pending bit is not set.
   Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

18.6.3 EXTI software interrupt event register (EXTI_SWIER1)

Address offset: 0x008

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:17 Reserved, must be kept at reset value.

Bits 16:0 SWIx : Software interrupt on event x (x = 16 to 0)

When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, SWIx can be accessed only with secure access.

Non-secure write to this SWIx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can be accessed only with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0.

A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read.

0: Writing 0 has no effect.

1: Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware.

18.6.4 EXTI rising edge pending register (EXTI_RPR1)

Address offset: 0x00C

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:17 Reserved, must be kept at reset value.

Bits 16:0 RPIFx : configurable event inputs x rising edge pending bit (x = 16 to 0)

When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, RPIFx can be accessed only with secure access.

Non-secure write to this RPIFx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can be accessed only with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0.

0: No rising edge trigger request occurred

1: Rising edge trigger request occurred

This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it.

18.6.5 EXTI falling edge pending register (EXTI_FPR1)

Address offset: 0x010

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:17 Reserved, must be kept at reset value.

Bits 16:0 FPIFx : configurable event inputs x falling edge pending bit (x = 16 to 0)

When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, FPIFx can be accessed only with secure access.

Non-secure write to this FPIFx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can be accessed only with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0.

0: No falling edge trigger request occurred

1: Falling edge trigger request occurred

This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it.

18.6.6 EXTI security configuration register (EXTI_SECCFGR1)

Address offset: 0x014

Reset value: 0x0000 0000

This register provides write access security, a non-secure write access is ignored and causes the generation of an illegal access event. A non-secure read returns the register data.

Contains only register bits for security capable input events.

Bits 31:0 SECx : Security enable on event input x (x = 31 to 0)

When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access.

Unprivileged write to this SECx is discarded.

0: Event security disabled (non-secure)

1: Event security enabled (secure)

18.6.7 EXTI privilege configuration register (EXTI_PRIVCFG1)

Address offset: 0x018

Reset value: 0x0000 0000

This register provides privileged write access protection. An unprivileged read returns the register data.

Contains only register bits for privilege capable input events.

Bits 31:0 PRIVx : Security enable on event input x (x = 31 to 0)

When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.

When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access.

Non-secure write to this PRIVx is discarded.

0: Event privilege disabled (unprivileged)

1: Event privilege enabled (privileged)

18.6.8 EXTI rising trigger selection register 2 (EXTI_RTSR2)

Address offset: 0x020

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:22, 20:19, 17:15, 13:0 Reserved, must be kept at reset value.

Bit 21 RT53 : Rising trigger event configuration bit of configurable event input x ⁽¹⁾

When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access.
When EXTI_SECCFGR.SECx is enabled, RTx can be accessed only with secure access.
Non-secure write to this bit x is discarded and non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access.
When EXTI_PRIVCFGR.PRIVx is enabled, RTx can be accessed only with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0.
0: Rising trigger disabled (for event and interrupt) for input line
1: Rising trigger enabled (for event and interrupt) for input line

Bit 18 RT50 : Rising trigger event configuration bit of configurable event input x ⁽¹⁾

When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access.
When EXTI_SECCFGR.SECx is enabled, RTx can be accessed only with secure access.
Non-secure write to this bit x is discarded and non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access.
When EXTI_PRIVCFGR.PRIVx is enabled, RTx can be accessed only with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0.
0: Rising trigger disabled (for event and interrupt) for input line
1: Rising trigger enabled (for event and interrupt) for input line

Bit 14 RT46 : Rising trigger event configuration bit of configurable event input x ⁽¹⁾

When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access.
When EXTI_SECCFGR.SECx is enabled, RTx can be accessed only with secure access.
Non-secure write to this bit x is discarded and non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access.
When EXTI_PRIVCFGR.PRIVx is enabled, RTx can be accessed only with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0.
0: Rising trigger disabled (for event and interrupt) for input line
1: Rising trigger enabled (for event and interrupt) for input line

1. 1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs.
   If a rising edge on the configurable event input occurs during writing of the register, the associated pending bit is not set.
   Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

18.6.9 EXTI falling trigger selection register 2 (EXTI_FTSR2)

Address offset: 0x024

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:22, 20:19,
17:15, 13:0 Reserved, must be kept at reset value.

Bit 21 FT53 : Falling trigger event configuration bit of configurable event input x ⁽¹⁾

When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, FTx can be accessed only with secure access.

Non-secure write to this FTx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, FTx can be accessed only with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0.

0: Falling trigger disabled (for event and Interrupt) for input line

1: Falling trigger enabled (for event and Interrupt) for input line.

Bit 18 FT50 : Falling trigger event configuration bit of configurable event input x ⁽¹⁾

When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, FTx can be accessed only with secure access.

Non-secure write to this FTx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, FTx can be accessed only with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0.

0: Falling trigger disabled (for event and Interrupt) for input line

1: Falling trigger enabled (for event and Interrupt) for input line.

Bit 14 FT46 : Falling trigger event configuration bit of configurable event input x ⁽¹⁾

When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, FTx can be accessed only with secure access.

Non-secure write to this FTx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, FTx can be accessed only with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0.

0: Falling trigger disabled (for event and Interrupt) for input line

1: Falling trigger enabled (for event and Interrupt) for input line.

1. 1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs.
   If a falling edge on the configurable event input occurs during writing of the register, the associated pending bit is not set.
   Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

18.6.10 EXTI software interrupt event register 2 (EXTI_SWIER2)

Address offset: 0x028

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:22, 20:19, 17:15, 13:0 Reserved, must be kept at reset value.

Bit 21 SWI53: Software interrupt on event x

When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, SWIx can be accessed only with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can be accessed only with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0.

A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read.

0: Writing 0 has no effect.

1: Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware.

Bit 18 SWI50: Software interrupt on event x

When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, SWIx can be accessed only with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can be accessed only with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0.

A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read.

0: Writing 0 has no effect.

1: Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware.

Bit 14 SWI46: Software interrupt on event x

When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, SWIx can be accessed only with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can be accessed only with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0.

A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read.

0: Writing 0 has no effect.

1: Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware.

18.6.11 EXTI rising edge pending register 2 (EXTI_RPR2)

Address offset: 0x02C

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:22, 20:19, 17:15, 13:0 Reserved, must be kept at reset value.

Bit 21 RPIF53: configurable event inputs x rising edge pending bit

When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, RPIFx can be accessed only with secure access.

Non-secure write to this RPIFx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can be accessed only with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0.

0: No rising edge trigger request occurred

1: Rising edge trigger request occurred

This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it.

Bit 18 RPIF50: configurable event inputs x rising edge pending bit

When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, RPIFx can be accessed only with secure access.

Non-secure write to this RPIFx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can be accessed only with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0.

0: No rising edge trigger request occurred

1: Rising edge trigger request occurred

This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it.

Bit 14 RPIF46 : configurable event inputs x rising edge pending bit

When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, RPIFx can be accessed only with secure access.

Non-secure write to this RPIFx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can be accessed only with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0.

0: No rising edge trigger request occurred

1: Rising edge trigger request occurred

This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it.

18.6.12 EXTI falling edge pending register 2 (EXTI_FPR2)

Address offset: 0x030

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:22, 20:19, 17:15, 13:0 Reserved, must be kept at reset value.

Bit 21 FPIF53 : configurable event inputs x falling edge pending bit

When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, FPIFx can be accessed only with secure access.

Non-secure write to this FPIFx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can be accessed only with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0.

0: No falling edge trigger request occurred

1: Falling edge trigger request occurred

This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it.

Bit 18 FPIF50 : configurable event inputs x falling edge pending bit

When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, FPIFx can be accessed only with secure access.

Non-secure write to this FPIFx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can be accessed only with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0.

0: No falling edge trigger request occurred

1: Falling edge trigger request occurred

This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it.

Bit 14 FPIF46 : configurable event inputs x falling edge pending bit

When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, FPIFx can be accessed only with secure access.

Non-secure write to this FPIFx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can be accessed only with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0.

0: No falling edge trigger request occurred

1: Falling edge trigger request occurred

This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it.

18.6.13 EXTI security configuration register 2 (EXTI_SECCFGR2)

Address offset: 0x034

Reset value: 0x0000 0000

This register provides write access security, a non-secure write access is ignored and causes the generation of an illegal access event. A non-secure read returns the register data.

Contains only register bits for privilege capable input events.

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:0 SECx : Security enable on event input x (x = 57 to 32)
When EXTI_PRIVCFG.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access.
When EXTI_PRIVCFG.PRIVx is enabled, SECx can only be written with privileged access.
Unprivileged write to this SECx is discarded.
0: Event security disabled (non-secure)
1: Event security enabled (secure)

18.6.14 EXTI privilege configuration register 2 (EXTI_PRIVCFG2)

Address offset: 0x038

Reset value: 0x0000 0000

This register provides privileged write access protection. An unprivileged read returns the register data.

Contains only register bits for security capable input events.

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:0 PRIVx : Security enable on event input x (x = 57 to 32)
When EXTI_SECCFG.SECx is disabled, PRIVx can be accessed with secure and non-secure access.
When EXTI_SECCFG.SECx is enabled, PRIVx can only be written with secure access.
Non-secure write to this PRIVx is discarded.
0: Event privilege disabled (unprivileged)
1: Event privilege enabled (privileged)

18.6.15 EXTI external interrupt selection register (EXTI_EXTICR1)

Address offset: 0x060

(EXTI mux 0, 1, 2, 3)

Reset value: 0x0000 0000

These bits are written by software to select the source input for EXTI3 external interrupt. When EXTI_SECCFGR1.SEC3 is disabled, EXTI3 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC3 is enabled, EXTI3 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV3 is disabled, EXTI3 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV3 is enabled, EXTI3 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA3 pin

0x01: PB3 pin

0x02: PC3 pin

0x03: PD3 pin

0x04: PE3 pin

0x05: PF3 pin

0x06: PG3 pin

0x07: PH3 pin

0x08: PI3 pin

Others: reserved

These bits are written by software to select the source input for EXTI2 external interrupt.

When EXTI_SECCFGR1.SEC2 is disabled, EXTI2 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC2 is enabled, EXTI2 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV2 is disabled, EXTI2 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV2 is enabled, EXTI2 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA2 pin

0x01: PB2 pin

0x02: PC2 pin

0x03: PD2 pin

0x04: PE2 pin

0x05: PF2 pin

0x06: PG2 pin

0x07: PH2 pin

0x08: PI2 pin

Others: reserved

These bits are written by software to select the source input for EXTI1 external interrupt. When EXTI_SECCFGR1.SEC1 is disabled, EXTI1 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC1 is enabled, EXTI1 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV1 is disabled, EXTI1 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV1 is enabled, EXTI1 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA1 pin

0x01: PB1 pin

0x02: PC1 pin

0x03: PD1 pin

0x04: PE1 pin

0x05: PF1 pin

0x06: PG1 pin

0x07: PH1 pin

0x08: PI1 pin

Others: reserved

These bits are written by software to select the source input for EXTI0 external interrupt.

When EXTI_SECCFGR1.SEC0 is disabled, EXTI0 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC0 is enabled, EXTI0 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV0 is disabled, EXTI0 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV0 is enabled, EXTI0 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA0 pin

0x01: PB0 pin

0x02: PC0 pin

0x03: PD0 pin

0x04: PE0 pin

0x05: PF0 pin

0x06: PG0 pin

0x07: PH0 pin

0x08: PI0 pin

Others: reserved

18.6.16 EXTI external interrupt selection register (EXTI_EXTICR2)

Address offset: 0x064

(EXTI mux 4, 5, 6, 7)

Reset value: 0x0000 0000

Bits 31:24 EXTI7[7:0] : EXTI7 GPIO port selection

These bits are written by software to select the source input for EXTI7 external interrupt. When EXTI_SECCFGR1.SEC7 is disabled, EXTI7 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC7 is enabled, EXTI7 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV7 is disabled, EXTI7 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV7 is enabled, EXTI7 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA7 pin

0x01: PB7 pin

0x02: PC7 pin

0x03: PD7 pin

0x04: PE7 pin

0x05: PF7 pin

0x06: PG7 pin

0x07: PH7 pin

0x08: PI7 pin

Others: reserved

Bits 23:16 EXTI6[7:0] : EXTI6 GPIO port selection

These bits are written by software to select the source input for EXTI6 external interrupt. When EXTI_SECCFGR1.SEC6 is disabled, EXTI6 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC6 is enabled, EXTI6 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV6 is disabled, EXTI6 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV6 is enabled, EXTI6 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA6 pin

0x01: PB6 pin

0x02: PC6 pin

0x03: PD6 pin

0x04: PE6 pin

0x05: PF6 pin

0x06: PG6 pin

0x07: PH6 pin

0x08: PI6 pin

Others: reserved

These bits are written by software to select the source input for EXTI5 external interrupt. When EXTI_SECCFGR1.SEC5 is disabled, EXTI5 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC5 is enabled, EXTI5 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV5 is disabled, EXTI5 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV5 is enabled, EXTI5 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA5 pin

0x01: PB5 pin

0x02: PC5 pin

0x03: PD5 pin

0x04: PE5 pin

0x05: PF5 pin

0x06: PG5 pin

0x07: PH5 pin

0x08: PI5 pin

Others: reserved

These bits are written by software to select the source input for EXTI4 external interrupt.

When EXTI_SECCFGR1.SEC4 is disabled, EXTI4 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC4 is enabled, EXTI4 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV4 is disabled, EXTI4 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV4 is enabled, EXTI4 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA4 pin

0x01: PB4 pin

0x02: PC4 pin

0x03: PD4 pin

0x04: PE4 pin

0x05: PF4 pin

0x06: PG4 pin

0x07: PH4 pin

0x08: PI4 pin

Others: reserved

18.6.17 EXTI external interrupt selection register (EXTI_EXTICR3)

Address offset: 0x068

(EXTI mux 8, 9, 10, 11)

Reset value: 0x0000 0000

Bits 31:24 EXTI11[7:0] : EXTI11 GPIO port selection

These bits are written by software to select the source input for EXTI11 external interrupt. When EXTI_SECCFGR1.SEC11 is disabled, EXTI11 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC11 is enabled, EXTI11 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV11 is disabled, EXTI11 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV11 is enabled, EXTI11 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA11 pin

0x01: PB11 pin

0x02: PC11 pin

0x03: PD11 pin

0x04: PE11 pin

0x05: PF11 pin

0x06: PG11 pin

0x07: PH11 pin

0x08: PI11 pin

Others: reserved

Bits 23:16 EXTI10[7:0] : EXTI10 GPIO port selection

These bits are written by software to select the source input for EXTI10 external interrupt.

When EXTI_SECCFGR1.SEC10 is disabled, EXTI10 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC10 is enabled, EXTI10 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV10 is disabled, EXTI10 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV10 is enabled, EXTI10 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA10 pin

0x01: PB10 pin

0x02: PC10 pin

0x03: PD10 pin

0x04: PE10 pin

0x05: PF10 pin

0x06: PG10 pin

0x07: PH10 pin

0x08: PI10 pin

Others: reserved

These bits are written by software to select the source input for EXTI9 external interrupt. When EXTI_SECCFGR1.SEC9 is disabled, EXTI9 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC9 is enabled, EXTI9 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV9 is disabled, EXTI9 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV9 is enabled, EXTI9 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA9 pin

0x01: PB9 pin

0x02: PC9 pin

0x03: PD9 pin

0x04: PE9 pin

0x05: PF9 pin

0x06: PG9 pin

0x07: PH9 pin

0x08: PI9 pin

Others: reserved

These bits are written by software to select the source input for EXTI8 external interrupt.

When EXTI_SECCFGR1.SEC8 is disabled, EXTI8 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC8 is enabled, EXTI8 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV8 is disabled, EXTI8 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV8 is enabled, EXTI8 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA8 pin

0x01: PB8 pin

0x02: PC8 pin

0x03: PD8 pin

0x04: PE8 pin

0x05: PF8 pin

0x06: PG8 pin

0x07: PH8 pin

0x08: PI8 pin

Others: reserved

Address offset: 0x06C

(EXTI mux 12, 13, 14, 15)

Reset value: 0x0000 0000

Bits 31:24 EXTI15[7:0] : EXTI15 GPIO port selection

These bits are written by software to select the source input for EXTI15 external interrupt. When EXTI_SECCFGR1.SEC15 is disabled, EXTI15 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC15 is enabled, EXTI15 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV15 is disabled, EXTI15 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV15 is enabled, EXTI15 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA15 pin

0x01: PB15 pin

0x02: PC15 pin

0x03: PD15 pin

0x04: PE15 pin

0x05: PF15 pin

0x06: PG15 pin

0x07: PH15 pin

Others: reserved

Bits 23:16 EXTI14[7:0] : EXTI14 GPIO port selection

These bits are written by software to select the source input for EXTI14 external interrupt.

When EXTI_SECCFGR1.SEC14 is disabled, EXTI14 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC14 is enabled, EXTI14 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV14 is disabled, EXTI14 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV14 is enabled, EXTI14 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA14 pin

0x01: PB14 pin

0x02: PC14 pin

0x03: PD14 pin

0x04: PE14 pin

0x05: PF14 pin

0x06: PG14 pin

0x07: PH14 pin

Others: reserved

These bits are written by software to select the source input for EXTI13 external interrupt. When EXTI_SECCFGR1.SEC13 is disabled, EXTI13 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC13 is enabled, EXTI13 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV13 is disabled, EXTI13 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV13 is enabled, EXTI13 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA13 pin

0x01: PB13 pin

0x02: PC13 pin

0x03: PD13 pin

0x04: PE13 pin

0x05: PF13 pin

0x06: PG13 pin

0x07: PH13 pin

Others: reserved

These bits are written by software to select the source input for EXTI12 external interrupt.

When EXTI_SECCFGR1.SEC12 is disabled, EXTI12 can be accessed with non-secure and secure access.

When EXTI_SECCFGR1.SEC12 is enabled, EXTI12 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR1.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR1.PRIV12 is enabled, EXTI12 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA12 pin

0x01: PB12 pin

0x02: PC12 pin

0x03: PD12 pin

0x04: PE12 pin

0x05: PF12 pin

0x06: PG12 pin

0x07: PH12 pin

Others: reserved

18.6.19 EXTI lock register (EXTI_LOCKR)

Address offset: 0x070

Reset value: 0x0000 0000

This register provides write access security: a non-secure write access is ignored, a read access returns zero data, and both generate an illegal access event.

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 LOCK : Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock

This bit is written once after reset.

0: Security and privilege configuration open, can be modified.

1: Security and privilege configuration locked, can no longer be modified.

18.6.20 EXTI CPU wake-up with interrupt mask register (EXTI_IMR1)

Address offset: 0x080

Reset value: 0xFFFFE 0000

Contains register bits for configurable events.

Bits 31:0 IMx : CPU wake-up with interrupt mask on event input x ⁽¹⁾ (x = 31 to 0)

When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, IMx can be accessed only with secure access.

Non-secure write to this bit is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, IMx can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0: Wake-up with interrupt request from input event x is masked.

1: Wake-up with interrupt request from input event x is unmasked.

Bit IM31 is not available on all devices, refer to Table 150 . If not present, consider this bit as reserved, and keep it at reset value.

1. 1. The reset value for configurable event inputs is set to 0 in order to disable the interrupt by default.

18.6.21 EXTI CPU wake-up with event mask register (EXTI_EMR1)

Address offset: 0x084

Reset value: 0x0000 0000

Bits 31:0 EMx : CPU wake-up with event generation mask on event input x (x = 31 to 0)

When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, EMx can be accessed only with secure access.

Non-secure write to this bit x is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, EMx can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0: Wake-up with event generation from Line x is masked.

1: Wake-up with event generation from Line x is unmasked.

Bit EM31 is not available on all devices, refer to Table 150 . If not present, consider this bit as reserved, and keep it at reset value.

18.6.22 EXTI CPU wake-up with interrupt mask register 2 (EXTI_IMR2)

Address offset: 0x090

Reset value: 0x07DB BFFF

Contains register bits for configurable events.

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:0 IMx : CPU wake-up with interrupt mask on event input x ⁽¹⁾ (x = 58 to 0)

When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, IMx can be accessed only with secure access.

Non-secure write to this bit is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, IMx can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0: Wake-up with interrupt request from input event x is masked.

1: Wake-up with interrupt request from input event x is unmasked.

Bits IM[58:54], IM[46:44], and IM[36:32] are not available on all devices, refer to Table 150 . If not present, consider these bits as reserved, and keep them at reset value.

1. 1. The reset value for configurable event inputs is set to 0 in order to disable the interrupt by default.

18.6.23 EXTI CPU wake-up with event mask register 2 (EXTI_EMR2)

Address offset: 0x094

Reset value: 0x0000 0000

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:0 EMx : CPU wake-up with event generation mask on event input x (x = 58 to 32)

When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, EMx can be accessed only with secure access.

Non-secure write to this bit x is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, EMx can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0: Wake-up with event generation from Line x is masked.

1: Wake-up with event generation from Line x is unmasked.

Bits EM[58:54], EM[46:44], and EM[36:32] are not available on all devices, refer to Table 150 . If not present, consider these bits as reserved, and keep them at reset value.

18.6.24 EXTI register map

Table 154. EXTI register map and reset values

Table 154. EXTI register map and reset values (continued)

1. Some bits in this register are not available on some devices, refer to Table 150 . If not present, consider these bits as reserved, and keep them at reset value.

Refer to Section 2.3 for the register boundary addresses.