15. Peripherals interconnect matrix

15.1 Interconnect matrix introduction

Several peripherals have direct connections between them, enabling autonomous communication and/or synchronization: this approach saves CPU resources, and power supply consumption. In addition, these hardware connections remove software latency and help the design of predictable system.

Depending on peripherals, these interconnections can operate in Run, Sleep, and Stop modes.

15.2 Connection summary

Table 133. Peripherals interconnect matrix ^(1)(2)(3)

1. Numbers in this table are links to corresponding subsections of Section 15.3 .

2. “-” means no interconnect.

3. Refer to the product datasheet for the availability of peripherals. If the peripheral is not present, consider the associated interconnection as unavailable.

15.3 Interconnection details

15.3.1 Master to slave interconnection for timers

From timer (TIM1/2/3/4/5/8/12/13/14/15/16/17) to timer (TIM1/2/3/4/5/8/12/15).

Purpose

Some timers are linked together internally for synchronization or chaining.

When one timer is configured in master mode, it can reset, start, stop, or clock the counter of another timer configured in slave mode.

A description of the feature is provided in Section 39.4.23: Timer synchronization .

The synchronization modes are detailed in:

• • Section 38.3.30 for advanced-control timers TIM1/8
• • Section 39.4.22 for general-purpose timers TIM2/3/4/5
• • Section 41 for the general-purpose timers TIM12/13/14
• • Section 42.4.23 for the general-purpose timer TIM15

Triggering signals

The output (from master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1/8) following a configurable timer event. It can be also from signals tim16_oc1 and tim17_oc1 in case of TIM16/17. The input (to slave) is on signals TIMx_ITR0/1/2/3.

The possible master/slave connections are given in:

• • Table 398 for advanced-control timers TIM1/8
• • Table 421 for general-purpose timers TIM2/3/4/5
• • Table 442 for the general-purpose timers TIM12/13/14
• • Table 454 for the general-purpose timer TIM15

Active power mode

Timers are optionally active in Run and Sleep modes. The effects of low-power modes on TIMx are given in:

• • Table 410: Effect of low-power modes on TIM1/TIM8
• • Table 428: Effect of low-power modes on TIM2/TIM3/TIM4/TIM5
• • Table 444: Effect of low-power modes on TIM12/TIM13/TIM14
• • Table 460: Effect of low-power modes on TIM15/TIM16/TIM17

15.3.2 Triggers to ADCs

From EXTI, timers (TIM1/2/3/4/6/8/15) and LP timers (LPTIM1/2) to ADC1/ADC2.

Purpose

A conversion (or a sequence of conversions) can be triggered either by software or by an external event (such as timer capture or input pins). For ADC12, if the EXTEN[1:0] (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, external events can trigger a conversion with the selected polarity.

More details in:

• • Section 26.4.18: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN)
• • EXTEN[1:0] defined in ADC configuration register (ADC_CFGR)
• • JEXTEN[1:0] defined in ADC injected sequence register (ADC_JSQR)

General-purpose timers (TIM2/3/4), basic timer (TIM6), advanced-control timers (TIM1/8), and general-purpose timer (TIM15) can be used to generate the ADC triggering event through the timer outputs tim_oc and tim_trgo.

Low-power timers (LPTIM1/2) can be used to generate the ADC triggering event through the LPTIM channels, in addition to the EXTI on channels 11 and 15.

Triggering signals

For ADC1/ADC2, the input triggering signals and the description of the interconnection between ADC1/ADC2 and timers are given in:

• • adc_ext_trg: Table 257: ADC interconnection
• • adc_jext_trg: Table 257: ADC interconnection
• • Section 26.4.18: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN)
• • Section 26.4.25: Timing diagrams example (single/continuous modes, hardware/software triggers)

Active power mode

This interconnection is active in Run and Sleep modes for all ADCs. The timers are active only in Run and Sleep modes. The effects of low-power modes are given in:

• • Table 410: Effect of low-power modes on TIM1/TIM8
• • Table 428: Effect of low-power modes on TIM2/TIM3/TIM4/TIM5
• • Table 460: Effect of low-power modes on TIM15/TIM16/TIM17
• • Table 466: STM32H5 LPTIM features
• • Table 481: Effect of low-power modes on the LPTIM

15.3.3 ADC analog watchdogs as triggers to timers

From ADC1/ADC2 to TIM1/8.

Purpose

The internal analog watchdog output signals coming from ADC1/ADC2 are connected to on-chip timers. ADC1/ADC2 can provide trigger events through analog watchdog signals to advanced-control timers (TIM1/8) to reset, start, stop, or clock the counter.

Settings description of the ADC analog watchdog and timer trigger, are provided in:

• • Section 38.3.6: External trigger input for TIM1/8
• • Table 399 for the internal ADC1/ADC2 sources connected to TIM1/8 (tim_etr) input multiplexer
• • Section 26.4.28 for the ADC1/ADC2/ADC_AWDy_OUT signal output generation

Triggering signals

The output (from ADC) is on signals ADCn_AWDx_OUT, with n being the ADC instance and x = 1, 2, 3 (three watchdogs per ADC). The input (to timer) is on signal TIMx_ETR (external trigger).

Active power mode

ADC1/ADC2 are active in Run and Sleep modes.

15.3.4 Triggers to DAC

From timer (TIM1/2/4/5/6/7/8/15), low-power timers (LPTIM1/2), and EXTI to DAC.

Purpose

General-purpose timers (TIM2/4/5/15), basic timers (TIM6/7), advanced-control timers (TIM1/8), LP timers (LPTIM1/2) outputs channels (lptim1_ch1 and lptim2_ch1), and EXTI can be used as triggering event to start a DAC conversion.

Triggering signals

The output (from timer) on the TIMx_TRGO signal and from LP timers are directly connected to corresponding DAC inputs.

The selection of input triggers on DAC is provided in:

• • Table 281: DAC interconnection
• • Section 28.4.8: DAC trigger selection

Active power mode

This interconnect is active in Run, Sleep, and Stop modes.

15.3.5 Clock sources to timers

From HSE, LSE, LSI, HSI, and MCO to timers (TIM2/12/15/16/17) and LP timers (LPTIM1/2).

Purpose

A timer input or counter can receive different clock sources, and can be used, for example, to calibrate the internal oscillator on a reference clock.

External clocks (HSE, LSE), internal clocks (LSI, CSI, HSI), and microcontroller output clock (MCO) can be used as input to timers:

• • LSE, HSI, and CSI are assigned to general purpose timers TIM2/12 as external inputs signals. LSE can be selected as counter clock provided by an external clock source in mode1 (tim_ti1_in) and mode2 (external trigger input tim_etr_in). Inputs assignment and clock selection description are detailed in:
  • – Section 39.4.5: Clock selection for TIM2
  • – External clock mode1: Table 440: Interconnect to the tim_ti1 input multiplexer for TIM12, tim_ti1_in4 (HSI), and tim_ti1_in5 (CSI)
  • – External clock mode2: Table 422: Interconnect to the tim_etr input multiplexer for tim_etr3 (LSE)
• • LSE, LSI, CSI, and HSE are assigned to general purpose timers TIM15/16/17 as external inputs signals. LSE/LSI/CSI/HSE can be selected as counter clock provided by an external clock source in mode1 (tim_ti1 or tim_ti2 signals). Inputs assignment and clock selection description are detailed in:
  • – Section 42.4.6: Clock selection for TIM15/16/17. External clock mode1: external input pin (tim_ti1 or tim_ti2, if available)
  • – Table 440: Interconnect to the tim_ti1 input multiplexer , tim_ti1_in1 (LSI-TIM16), tim_ti1_in2 (LSE-TIM16/HSE-TIM17), tim_ti1_in4 (LSE- TIM15), and tim_ti1_in5 (CSI-TIM15)
• • Microcontroller output clock (MCO): MCO1 is connected as external input to general-purpose timer TIM17, MCO2 is connected as external input to general-purpose timer TIM15.
  • – Table 452: Interconnect to the tim_ti1 input multiplexer for TIM15/TIM16/TIM17
• • LSI and LSE can be selected as input capture 2 to LPTIM1 as described in Table 475: LPTIM1 input capture 2 connections .
• • HSI/1024, CSI/128, and HSI/8 can be selected as input capture 2 to LPTIM2 as described in Table 476: LPTIM2 input capture 2 connections .

Triggering signals

lptim_ic2_mux1 LPTIM input capture selection can be set in the LPTIM configuration register 2 (LPTIM_CFGR2). For timers, the internal clock signal can be selected as counter clock provided by an external clock source in mode1 (tim_ti1_in) and mode2 (external trigger input tim_etr_in).

Active power mode

This feature is available under Run and Sleep modes.

15.3.6 Triggers to low-power timers

From EXTI, TAMP, and RTC alarm to LP timers (LPTIM1/2/3/4/5/6).

Purpose

LPTIM1/2/3/4/5/6 counters can be started either by software, or after the detection of an active edge on one of the eight trigger inputs (see Section 43.4.7: Trigger multiplexer ).

GPIO can also be selected as LPTIM input capture selection or LPTIM input selection, according to the LPTIM configuration register 2 (LPTIM_CFGR2).

Triggering signals

This trigger feature is described in Section 43.4.7: Trigger multiplexer and the following sections. The input selection is described in Table 471: LPTIM1/2/3/4/5/6 external trigger connections .

Active power mode

This interconnection is active in Run, Sleep, and Stop modes.

15.3.7 RTC wake-up as inputs to timers

From RTC to timer (TIM16).

Purpose

RTC wake-up interrupt can be used as input to general-purpose timer (TIM16) channel 1.

Triggering signals

RTC wake-up signal is connected to tim_ti1_in3 signal as described in Table 452: Interconnect to the tim_ti1 input multiplexer for TIM16.

Active power mode

This interconnection is active down to Stop mode. Timers are not active but the count is performed at wake-up.

15.3.8 System errors as break signals to timers

From system errors to timers (TIM1/8/15/16/17).

Purpose

CSS, CPU lockup, SRAM2/3 ECC double errors, SRAM1 parity errors, FLASH ECC double-error detection, and PVD can generate system errors in the form of timer break toward timers (TIM1/8/15/16/17).

The purpose of the break function is to protect power switches driven by PWM signals generated by the timers.

Triggering signals

The possible sources of break are described in:

• • Section 38.3.18: Using the break function for TIM1/8
• • Section 42.4.15: Using the break function for TIM15/16/17
• • Table 402: System break interconnect for TIM1/8
• • Table 456: System break interconnect for TIM15/16/17

Active power mode

Timers are optionally active in Run and Sleep modes. The effects of low-power modes on TIMx are given in:

• • Table 410: Effect of low-power modes on TIM1/TIM8
• • Table 428: Effect of low-power modes on TIM2/TIM3/TIM4/TIM5
• • Table 460: Effect of low-power modes on TIM15/TIM16/TIM17

15.3.9 Triggers for communication peripherals

From Ethernet to timers (TIM2/TIM3).

Purpose

To synchronize system clock with network, internal connections are available between timers and PTP to check for clock drifts.

Triggering signals

• • The outputs (from timer) are directly connected to Ethernet PTP triggers inputs. More details are given in the sections below:
• • Section 57.3: Ethernet pins and internal signals
• • Table 417: Interconnect to the tim_ti1 input multiplexer
• • Table 422: Interconnect to the tim_etr input multiplexer

Active power mode

These interconnections remain active in Run and Sleep modes.

15.3.10 Triggers to GPDMA1/2

From EXTI, RTC (alarm/wake-up), TAMP, timers (TIM2/12/15), LP timers (LPTIM1/2/3/4/5/6), GPDMA1 transfer complete (gpdma1_chx_tc, gpdma2_chx_tcf) to GPDMA1/2.

Purpose

A GPDMA trigger can be assigned to GPDMA channel x. A programmed GPDMA transfer can be triggered by a rising/falling edge of a selected input trigger event. The trigger mode can also be programmed to condition the LLI link transfer. More details are given in the sections below:

• • Section 16.3.7: GPDMA triggers
• • Section 16.4.12: GPDMA triggered transfer

• • GPDMA channel x transfer register 2 (GPDMA_CxTR2) for more details on:
  • – Trigger selection TRIGSEL[5:0] field
  • – Trigger mode (LLI) defined by TRIGM[1:0]
  • – Trigger polarity as defined by TRIGPOL[1:0]

Triggering signals

GPDMA trigger mapping is specified in Table 140: Programmed GPDMA1/2 trigger , according to GPDMA_CxTR2.TRIGSEL[5:0].

Active power mode

This interconnection remains functional in Sleep mode.

Refer to:

• • Section 16.6: GPDMA in low-power modes

15.3.11 Internal analog signals to analog peripherals

From internal analog source to ADC (ADC1/2).

Purpose

The internal reference voltage ( \( V_{REFINT} \) ), the internal temperature sensor ( \( V_{SENSE} \) ), the internal digital core voltage ( \( V_{DDCORE} \) ), and the \( V_{BAT} \) monitoring channel are connected to ADC (ADC1/2) input channels.

This is according to:

• • Section 26.2: ADC main features
• • Section 26.4.11: Channel selection (ADC_SQRy, ADC_JSQR)

15.3.12 Clock source for the DAC sample and hold mode

From LSI/LSE to DAC1.

Purpose

DAC1 can run in Stop mode. The sample and hold block and its associated registers use the LSI or LSE clock source (dac_hold_ck) in Stop mode.

Table 280: DAC internal input/output signals : dac_hold_ck, Input, DAC low-power clock used in sample and hold mode

Active power mode

This feature remains available in Run, Sleep and Stop modes.

15.3.13 Internal tamper sources

From internal peripherals, clocks, or monitoring, to tamper.

Purpose

To detect any abnormal activity or tentative to corrupt the device, embedded tampers alert the system of undesired events. Different actions can be taken as consequence.

The list of tamper sources can be found in Table 507: TAMP interconnection .

Active power mode

This interconnection is active in all power modes if the tamper source is activated.

15.3.14 Output from tamper to RTC

From TAMP to RTC.

Purpose

The RTC can timestamp a tamper event to retrieve history of the detection. The RTC can also control GPIOs, and set a signal based on tamp or alarm status outside the MCU.

Refer to Section 46.3.3: GPIOs controlled by the RTC and TAMP for more details.

Active power mode

This interconnection remains active in all power modes.

15.3.15 Encryption keys to AES/SAES

From TAMP backup registers, system flash memory to and in between SAES and AES.

Purpose

The encryption mechanism requires an hardware key that must be stored in a protected non-volatile memory. Different approaches are implemented to load them in a non-readable way. Tamper backup registers or system flash memory can be used to store respectively BHK or RHUK, and to implement a dedicated bus to pass it to the SAES.

Refer to Section 34.4.14: SAES operation with wrapped keys for more details.

The AES encryption mechanism (faster than the SAES) can benefit from the sharing key of the SAES. Refer to Section 34.4.15: SAES operation with shared keys for more details.

Active power mode

AES and SAES are operating under Run and Sleep modes.