11. Reset and clock control (RCC)

11.1 Introduction

The reset and clock control (RCC) manages the different resets, and generates the clocks for the bus and peripherals.

11.2 RCC pins and internal signals

Table 111 lists the RCC inputs and output signals connected to package pins or balls.

Table 111. RCC input/output signals connected to package pins or balls

11.3 RCC reset functional description

There are three types of reset:

• • a system reset
• • a power reset
• • a Backup domain reset

11.3.1 Power reset

A power reset is generated when one of the following events occurs:

• • a brownout reset (BOR)
• • when exiting Standby mode

A brownout reset, including power-on or power-down reset (POR/PDR), sets all registers to their reset values except the ones in the Backup domain.

When exiting Standby mode, all registers in the core domain are set to their reset value. Registers outside the core domain (RTC, WKUP, IWDG, and GPIO pullup/pulldown configuration during Standby and Standby mode exit) are not impacted.

11.3.2 System reset

A system reset sets all registers to their reset values except the reset flags in RCC reset status register (RCC_RSR) and the registers in the Backup domain.

A system reset is generated when one of the following events occurs:

• • a low level on the NRST pin (external reset)
• • a window watchdog event (WWDG reset)
• • an independent watchdog event (IWDG reset)
• • a software reset (SW reset) (see Software reset )
• • a low-power mode security reset (see Low-power mode security reset )
• • a brownout reset

The reset source can be identified by checking the reset flags in RCC reset status register (RCC_RSR) .

These sources act on the NRST pin and this pin is always kept low during the delay phase. The reset service routine vector is selected depending on product state, on Boot option bytes or on both.

The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low.

In case of an internal reset, the internal pull-up \( R_{PU} \) is deactivated to save the power consumption through the pull-up resistor.

Figure 51. Simplified diagram of the reset circuit

Software reset

The SYSRESETREQ bit in Cortex-M33 application interrupt and reset control register must be set to force a software reset on the device.

Low-power mode security reset

To avoid that critical applications mistakenly enter a low-power mode, the following low-power mode security resets are available. If enabled in option bytes, the resets are generated in any of the following conditions:

• • Entering Standby mode: this type of reset is enabled by resetting nRST_STDBY bit in user option bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.
• • Entering Stop mode: this type of reset is enabled by resetting nRST_STOP bit in user option bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode.

For further information on the user option bytes, refer to Section 7.4.1: Option bytes description .

11.3.3 Backup domain reset

The Backup domain has two specific resets, generated after one of the following events:

• • a software reset, triggered by setting the VSWRST bit in the RCC Backup domain control register (RCC_BDCR) . Write access to this domain must be enabled before setting VSWRST bit to perform the reset.
• • a V _DD or V _BAT power on, if both supplies have previously been powered off

A Backup domain reset affects the LSE oscillator, the RTC, the backup registers, the backup SRAM, and the RCC_BDCR register.

11.3.4 Reset source identification

The application can identify the reset source by checking the reset flags in the RCC_RSR register. The software can reset the flags by setting the RMVF bit.

Table 112 shows how the status bits of the RCC_RSR register behave according to the situation that generated the reset. For example, when an IWDG timeout occurs, if the CPU is reading the RCC_RSR register during the boot phase, both PINRSTF and IWDGRSTF bits are set, indicating that the IWDG also generated a pin reset.

Table 112. Reset source identification (RCC_RSR) ⁽¹⁾

1. Gray cells highlight the register bits that are set.

11.4 RCC clocks functional description

Four different clock sources can be used to drive the system clock (SYSCLK):

• • HSI: high-speed internal up to 64 MHz RC oscillator clock
• • CSI: low power internal RC oscillator clock
• • HSE: high-speed external crystal or clock, from 4 to 50 MHz
• • PLL1 clock

The HSI is used as system clock source after startup from reset, configured at 32 MHz.

The device has the following additional clock sources:

• • LSI: 32 kHz low-speed internal RC that drives the independent watchdog and optionally the RTC used for auto-wakeup from Stop and Standby modes
• • LSE: 32.768 kHz low-speed external crystal or clock that optionally drives the real-time clock (rtc_ck)
• • HSI48: internal 48 MHz RC that potentially drives the USB FS and the RNG
• • PLL2 and PLL3 clocks

Each clock source can be switched on or off independently when it is not used, to optimize power consumption.

Several prescalers can be used to configure the AHB frequency, the APB1 and APB2 domains. The maximum frequency of the AHB and APB domains is 250 MHz.

The peripheral clocks are derived from their bus clock (HCLK, PCLK1, PCLK2 or PCLK3), except those that receive an independent kernel clock. This kernel clock can be selected by software between several sources thanks to RCC_CCIPRx registers (x = 1,2,3,4,5).

In addition, the RTC kernel clock is selected by software in RCC_BDCR. The IWDG clock is always the LSI 32 kHz clock.

The RCC feeds the Cortex system timer (SysTick) external clock with the AHB clock (HCLK) divided by eight, or LSE or LSI. The SysTick can work either with this clock or directly with the Cortex clock (HCLK), configurable in the SysTick control and status register.

FCLK acts as Cortex-M33 free-running clock.

Figure 52. Clock tree

1. For details on the internal/external clock source, refer to the Electrical characteristics in the datasheet.

11.4.1 HSE clock

The HSE block can generate a clock from an external crystal/ceramic resonator, or from an external clock source.

Figure 53. HSE/LSE clock sources

External clock source (HSE bypass)

In this mode, an external clock source must be provided to OSC_IN pin. The external clock can be low swing (analog) or digital. If this clock is directly used by a peripheral, the duty cycle requirement is defined by the peripheral and the application (refer to datasheet for more details).

In case of an analog clock (low swing) the HSEBYP and HSEON bits must be set to 1 in the RCC clock control register (RCC_CR) .

In case of a digital clock, the HSEBYP and the HSEEXT bits must be set to 1 followed by setting the HSEON bit to 1 in the RCC clock control register (RCC_CR) .

External crystal/ceramic resonator

The oscillator is enabled by setting the HSEBYP bit to 0 and HSEON bit to 1.

The HSE can be used when the product requires a very accurate high-speed clock.

The associated hardware configuration is shown in Figure 53 : the resonator and the load capacitors must be placed as close as possible to the oscillator pins to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected crystal or ceramic resonator. Refer to the electrical characteristics section of the datasheet for more details.

The HSERDY flag of the RCC clock control register (RCC_CR) indicates whether the HSE oscillator is stable or not. At startup, the hse_ck clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock source interrupt enable register (RCC_CIER) .

The HSE can be switched ON and OFF through the HSEON bit. Note that the HSE cannot be switched OFF if one of the following two conditions is met:

• • the HSE is used directly (via software mux) as system clock
• • the HSE is selected as reference clock for PLL1, with PLL1 enabled and selected to provide the system clock (via software mux).

In that case the hardware does not allow programming the HSEON bit to 0.

The HSE is automatically disabled by hardware, when the system enters Stop or Standby mode.

In addition, the HSE clock can be driven to the MCO1 and MCO2 outputs and used as clock source for other application components.

11.4.2 HSI clock

The HSI block provides the default clock to the product.

The HSI is a high-speed internal RC oscillator that can be used directly as system clock, peripheral clock, or as PLL input. A predivider allows the application to select an HSI output frequency of 8, 16, 32 or 64 MHz. This predivider is controlled by the HSIDIV.

The HSI advantages are the following:

• • low-cost clock source, as no external crystal is required
• • faster startup time than HSE (a few microseconds)

The HSI frequency, even with frequency calibration, is less accurate than an external crystal oscillator or ceramic resonator.

The HSI can be switched ON and OFF using the HSION bit. Note that the HSI cannot be switched OFF if one of the two conditions is met:

• • the HSI is used directly (via software mux) as system clock
• • the HSI is selected as reference clock for PLL1, with PLL1 enabled and selected to provide the system clock (via software mux).

In that case the hardware does not allow programming the HSION bit to 0. Note that the HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case the hardware does not update the HSIDIV with the new value. However it is possible to change the HSIDIV if the HSI is used directly as system clock.

The HSIRDY flag indicates if the HSI is stable or not. At startup, the HSI output clock is not released until this bit is set by hardware.

The HSI clock can also be used as a backup source (auxiliary clock) if the HSE fails (refer to Section 11.4.10: Clock security system (CSS) ). The HSI can be disabled or not when the system enters Stop mode.

In addition, the HSI clock can be driven to the MCO1 output and used as clock source for other application components.

Care must be taken when the HSI is used as kernel clock for communication peripherals, the application must take into account the following parameters:

• • the time interval between the moment where the peripheral generates a kernel clock request and the moment where the clock is really available
• • the frequency accuracy.

Note: The HSI can remain enabled when the system is in Stop mode.

HSI calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process variations. That is why each device is factory calibrated by STMicroelectronics to achieve an accuracy of ACCHSI (refer to the product datasheet for more information).

After a power-on reset, the factory calibration value is loaded in the HSICAL[11:0] bits. If the application is subject to voltage or temperature variations, this may affect the RC oscillator frequency. The user application can trim the HSI frequency using the HSITRIM[6:0] bits.

Note: HSICAL[11:0] and HSITRIM[6:0] are located in the RCC CSI calibration register (RCC_CSI/CFGR) .

11.4.3 CSI oscillator

The CSI is a low-power RC oscillator that can be used directly as system clock, peripheral clock, or PLL input.

The CSI advantages are the following:

• • low-cost clock source since no external crystal is required
• • faster startup time than HSE (a few microseconds)
• • very low-power consumption,

The CSI provides a clock frequency of about 4 MHz, while the HSI is able to provide a clock up to 64 MHz.

CSI frequency, even with frequency calibration, is less accurate than an external crystal oscillator or ceramic resonator.

The CSI can be switched ON and OFF through the CSION bit. The CSIRDY flag indicates whether the CSI is stable or not. At startup, the CSI output clock is not released until this bit is set by hardware.

The CSI cannot be switched OFF if one of the two conditions is met:

• • The CSI is used directly (via software mux) as system clock.
• • The CSI is selected as reference clock for PLL1, with PLL1 enabled and selected to provide the system clock (via software mux).

In that case the hardware does not allow programming the CSION bit to 0.

The CSI can be disabled or not when the system enters Stop mode.

In addition, the CSI clock can be driven to the MCO2 output and used as clock source for other application components.

Even if the CSI settling time is faster than the HSI, care must be taken when the CSI is used as kernel clock for communication peripherals: the application must take into account the following parameters:

• • the time interval between the moment where the peripheral generates a kernel clock request and the moment where the clock is really available,
• • the frequency precision.

Note: CSION and CSIRDY bits are located in the RCC clock control register (RCC_CR) .

CSI calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated to achieve ACC _CSI accuracy (refer to the product datasheet for more information). After reset, the factory calibration value is loaded in the CSICAL[7:0] bits.

Voltage and/or temperature variations affect the RC oscillator frequency. The user application can trim the CSI frequency using the CSITRIM[5:0] bits.

Note: Bits CSICAL[7:0] and CSITRIM[5:0] are located into the RCC CSI calibration register (RCC_CSICFGR) .

Figure 54. CSI calibration flow

graph LR
    subgraph RCC
        direction TB
        CSICFGR[RCC_CSICFGR]
        CSICAL[CSICAL[7:0] unsigned]
        CSITRIM[CSITRIM[5:0] unsigned]
        Adder((+))
        csi_cal[csi_cal[7:0]]
        CSICFGR -- CSICAL --> CSICAL
        CSICFGR -- CSITRIM --> CSITRIM
        CSITRIM --> Adder
        FLASH_CSI_opt[FLASH_CSI_opt[7:0]] --> Adder
        Adder --> csi_cal
        csi_cal --> CSICAL
    end
    EOB[Engineering option bytes factory calibration] -- FLASH_CSI_opt --> FLASH_CSI_opt
    CSICAL -- CSICAL --> CSI
    subgraph CSI
        CAL[CAL[7:0]]
    end
    CAL --> CSICAL
  

11.4.4 HSI48 clock

The HSI48 clock signal is generated from an internal 48 MHz RC oscillator, and can be used directly for USB and for random number generator (RNG).

The internal 48 MHz RC oscillator is mainly dedicated to provide a high-precision clock to the USB peripheral by means of a special clock recovery system (CRS) circuitry. The CRS can use the USB SOF signal, the LSE, or an external signal to automatically and quickly adjust the oscillator frequency on-the-fly. It is disabled as soon as the system enters Stop or Standby mode. When the CRS is not used, the HSI48 RC oscillator runs on its default frequency, subject to manufacturing process variations.

For more details on how to configure and use the CRS peripheral, refer to Section 12: Clock recovery system (CRS) .

The HSI48RDY flag in the RCC_CR register indicates whether the HSI48 RC oscillator is stable or not. At startup, the HSI48 RC oscillator output clock is not released until this bit is set by hardware.

The HSI48 can be switched on and off using the HSI48ON bit in the RCC_CR register.

11.4.5 PLL description

The RCC features three PLLs:

• • a main PLL (PLL1), generally used to provide clocks to the CPU and some peripherals
• • two dedicated PLLs (PLL2 and PLL3), used to generate the kernel clock for peripherals

The PLLs integrated into the RCC are completely independent. They offer the following features:

• • A VCO supporting two modes:
  • – a wide-range
  • – a low-range used, for instance, in audio applications
• • Input frequency range:
  • – 2 to 16 MHz for the VCO in wide-range mode
  • – 1 to 2 MHz for the VCO in low-range mode
• • Capability to work either in integer or fractional mode
• • 13-bit sigma-delta modulator, to fine-tune the VCO frequency by 11 to 0.3 ppm steps
• • The sigma-delta modulator can be updated on-the-fly without generating frequency overshoots on PLLs outputs
• • Each PLL offers three outputs with post-dividers

Figure 55. PLL block diagram

The PLLs are controlled via RCC_PLLxDIVR, RCC_PLLxFRACR, RCC_PLLCFGR, and RCC_CR registers.

The frequency of the reference clock provided to the PLLs ( refx_ck ) must range from 1 to 16 MHz. The PLLxM dividers of the RCC PLLx clock source selection register (RCC_PLLxCFGR) must be properly programmed to match this condition. In addition, the PLLxRGE[1:0] field of the RCC PLLx clock source selection register (RCC_PLLxCFGR) must be set according to the reference input frequency to optimize performance.

The user application can then configure the VCO. The smaller range (150 to 420 MHz) must be chosen when the reference clock frequency is lower than 2 MHz.

To reduce the power consumption, it is recommended to configure the VCO output to the smaller range.

DIVNx loop divider must be programmed to achieve the expected frequency at VCO output. In addition, the VCO output range must be respected.

The PLLs operate in integer mode when the value of SH_REG bit of the FRACNx shadow register is set to 0. The SH_REG bit is updated with the FRACNx value when PLLxFRACEN

bit goes from 0 to 1. The sigma-delta modulator is designed to minimize the jitter impact, while allowing very small frequency steps.

The PLLs can be enabled by setting PLLxON to 1. The PLLxRDY bits indicate that the PLL is ready (locked).

Note: Before enabling the PLLs, make sure that the reference frequency ( refx_ck ) provided to it is stable, so the hardware does not allow changing PLLxM when the PLLx is ON, and it is also not possible to change PLLSRC when one of the PLLs is ON.

The hardware prevents writing PLL1ON to 0 if the PLL1 is currently used to deliver the system clock. There are other hardware protections on the clock generators (refer to HSE clock , HSI clock , and CSI oscillator ).

The following PLL parameters cannot be changed once the PLL is enabled: DIVNx, PLLxRGE, PLLxVCOSEL, PLLxP (DIVP), PLLxQ (DIVQ), and PLLxR (DIVR).

For optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, the application must set the enable bit (DIVyEN) as well as the corresponding post-divider bits (DIVP, DIVQ or DIVR) to 0.

If the above rules are not respected, the PLL output frequency is not guaranteed.

Output frequency computation

When the PLL is configured in integer mode (SH_REG = 0), the VCO frequency ( \( F_{VCO} \) ) is given by the following expression:

When the PLL is configured in fractional mode (SH_REG different from 0), the DIVN divider must be initialized before enabling the PLLs. However, it is possible to change the value of FRACNx on-the-fly without disturbing the PLL output.

This feature can be used either to generate a specific frequency from any crystal value with a good accuracy, or to fine-tune the frequency on-the-fly.

For each PLL, the VCO frequency is given by the following formula:

Note: For PLL1, DIVP can only take odd values.

The PLLs are disabled by hardware when:

• • the system enters Stop or Standby mode
• • an HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock

PLL initialization phase

Figure 56 shows the recommended PLL initialization sequence in integer and fractional mode. The PLLx are supposed to be disabled at the start of the initialization sequence:

1. 1. Initialize the PLLs registers according to the required frequency.
   • – Set PLLxFRACEN of RCC PLLx clock source selection register (RCC_PLLxCFGR) to 0 for integer mode.
   • – For fractional mode, set FRACN to the required initial value (FracInitValue) and then set PLLxFRACEN to 1.
2. 2. Once the PLLxON bit is set to 1, the user application must wait until PLLxRDY bit is set to 1. If the PLLx is in fractional mode, the PLLxFRACEN bit must not be set back to 0 as long as PLLxRDY = 0.
3. 3. Once the PLLxRDY bit is set to 1, the PLLx is ready to be used.
4. 4. If the application intends to tune the PLLx frequency on-the-fly (possible only in fractional mode), then:
   1. a) PLLxFRACEN must be set to 0. When PLLxFRACEN = 0, the sigma-delta modulator is still operating with the value latched into SH_REG. The application must wait for three clock periods of refx_ck (PLLxFRACEN bit propagation delay).
   2. b) A new value must be uploaded into PLLxFRACR (FracValue(n)).
   3. c) PLLxFRACEN must be set to 1, to latch the content of PLLxFRACR into its shadow register. The new value is considered after three clock periods of refx_ck (PLLxFRACEN bit propagation delay).

Note: When the PLLxRDY goes to 1 the difference between the PLLx output frequency and the target value is lower than \( \pm 2\% \) .

Figure 56. PLLs initialization flow

graph TD
    subgraph IntegerMode [PLL enable sequence integer mode]
        I1([PLL enable sequence integer mode]) --> I2[Select clock source (RCC_CKSELR)
- PLLSRC]
        I2 --> I3[Init pre-divider (RCC_CKSELR)
- PLLxM]
        I3 --> I4[PLLx config (RCC_PLLxCFGR) -
PLLxVCOSEL, PLLxRGE
- PLLxFRACEN = 0
- PLLxPEN, PLLxEN, PLLxREN
Init PLLx dividers (RCC_PLLxDIVR)
- DIVNx, DIVPx, DIVQx, DIVRx]
        I4 --> I5[Enable PLLx (RCC_CR)
- PLLxON = 1]
        I5 --> I6{PLLxRDY = 1 ?}
        I6 -- No --> I5
        I6 -- Yes --> I7([Ready for use in integer mode])
    end

    subgraph FractionalMode [PLL enable sequence fractional mode]
        F1([PLL enable sequence fractional mode]) --> F2[Select clock source (RCC_CKSELR)
- PLLSRC]
        F2 --> F3[Init pre-divider (RCC_CKSELR)
- PLLxM]
        F3 --> F4[Init fractional value (RCC_PLLxFRACR)
- FRACN= FracInitValue
PLLx config (RCC_PLLxCFGR) -
PLLxVCOSEL, PLLxRGE
- PLLxFRACEN = 1
- PLLxPEN, PLLxEN, PLLxREN
Init PLLx dividers (RCC_PLLxDIVR)
- DIVNx, DIVPx, DIVQx, DIVRx]
        F4 --> F5[Enable PLLx (RCC_CR)
- PLLxON = 1]
        F5 --> F6{PLLxRDY = 1 ?}
        F6 -- No --> F5
        F6 -- Yes --> F7([Ready for use in fractional mode])
    end

    F3 -.-> G[Can be repeated for each PLL]
    G -.-> F3

    I7 --> F8[Disable fractional mode (RCC_PLLxCFGR)
- PLLxFRACEN = 0
Init fractional value (RCC_PLLxFRACR)
- FRACN= FracValue(n)
Enable fractional mode (RCC_PLLxCFGR)
- PLLxFRACEN = 1]
    F8 --> F9([Ready for use in fractional mode])
    F8 -.-> H[Value update on-the-fly]
    H -.-> F9
  

MSV67379V4

11.4.6 LSE clock

The LSE can generate a clock from an external crystal/ceramic resonator, or from an external user clock.

External clock source (LSE bypass)

In this mode, an external clock source must be provided to OSC32_IN pin (see Figure 53). The input clock can have a frequency up to 1 MHz, and be low swing (analog) or digital. A duty cycle close to 50% is recommended.

In case of an analog clock (low swing), the LSEBYP and LSEON bits must be set to 1 ( RCC Backup domain control register (RCC_BDCR) ).

In case of a digital clock, the LSEBYP and the LSEEXT bits must be set to 1 followed by setting the LSEON bit to 1 ( RCC Backup domain control register (RCC_BDCR) ). If the RTC

is used, the LSE bypass must not be configured in digital mode, but in low swing analog mode (default value after reset).

External crystal/ceramic resonator (LSE crystal)

The LSE clock is generated from a 32.768 kHz crystal or ceramic resonator. It has the advantage to provide a low-power, highly accurate clock source to the real-time clock (RTC) for clock/calendar or other timing functions.

The LSERDY flag of the RCC Backup domain control register (RCC_BDCR) indicates whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock source interrupt enable register (RCC_CIER) .

The LSE oscillator is switched ON and OFF using the LSEON bit. The LSE remains enabled when the system enters Stop or Standby mode.

In addition, the LSE clock can be driven to the MCO1 output and used as clock source for other application components.

The LSE also offers a programmable driving capability (LSEDRV[1:0]), which can be used to modulate the amplifier driving capability. This driving capability is chosen according to the external crystal/ceramic component requirement to ensure a stable oscillation.

The driving capability must be set before enabling the LSE oscillator.

11.4.7 LSI clock

The LSI acts as a low-power clock source that can be kept running when the system is in Stop or Standby mode for the independent watchdog (IWDG) and auto-wakeup unit (AWU).

The clock frequency is around 32 kHz. For more details, refer to the electrical characteristics section of the datasheet.

The LSI can be switched ON and OFF using the LSION bit. The LSIRDY flag indicates whether the LSI oscillator is stable or not. If an independent watchdog is started either by hardware or software, the LSI is forced ON and cannot be disabled.

The LSI remains enabled when the system enters Stop or Standby mode.

At LSI startup, the clock is not provided until the hardware sets the LSIRDY bit. An interrupt can be generated if enabled in the RCC clock source interrupt enable register (RCC_CIER) .

In addition, the LSI clock can be driven to the MCO2 output, and used as a clock source for other application components.

Note: Bits LSION and LSIRDY are located in the RCC Backup domain control register (RCC_BDCR).

11.4.8 System clock (SYSCLK) selection

Four different clock sources can be used to drive the system clock (SYSCLK):

• • HSI oscillator
• • CSI oscillator
• • HSE oscillator
• • PLL

The system clock maximum frequency is 250 MHz. After a system reset (or after leaving Standby mode), the HSI oscillator, at 32 MHz, is selected as system clock. When a clock source is used directly or through the PLL as a system clock, it is not possible to stop it.

A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source not yet ready is selected, the switch occurs when the clock source becomes ready. Status bits in the RCC clock control register (RCC_CR) indicate which clocks are ready, and which clock is currently used as a system clock.

11.4.9 Handling clock generators in stop and standby modes

When the whole system enters Stop mode, all the clocks (system and kernel clocks) are stopped, as well as the following clock sources:

• • CSI, HSI (depending on HSIKERON and CSIKERON bits)
• • HSE
• • PLL1, PLL2, and PLL3
• • HSI48

The content of the RCC registers is not altered except for PLL1ON, PLL2ON, PLL3ON, HSEON, and HSI48ON, set to 0.

Exiting Stop mode

When the system exits this mode via a wake-up event, the application can select which oscillator (HSI and/or CSI) is used to restart. The STOPWUCK bit selects the oscillator used as system clock. The STOPKERWUCK bit selects the oscillator used as kernel clock for peripherals. The STOPKERWUCK bit is useful if after a system Stop, a peripheral needs a kernel clock generated by an oscillator different from the one used for the system clock.

These bits belong to the RCC clock configuration register1 (RCC_CFGR1)

Table 113. STOPWUCK and STOPKERWUCK description

During Stop mode

There are two specific cases where the HSI or CSI can be enabled during this mode.

• • When a dedicated peripheral requests the kernel clock the peripheral receives the HSI or CSI according to the kernel clock source selected for this peripheral (via CKPERSEL[1:0]).
• • When the HSIKERON or CSIKERON bits of the RCC clock control register (RCC_CR) are set, the HSI and CSI are kept running, but the outputs are gated. The clock is then

available immediately when the system exits Stop mode, or when a peripheral requests the kernel clock (see Table 111 for details).

Table 114. HSIKERON and CSIKERON behavior

1. 1. \( t_{su(HSI)} \) and \( t_{su(CSI)} \) are the startup times of, respectively, the HSI and CSI oscillators (refer to the product datasheet for the values of these parameters).

When the microcontroller exists system standby mode, the HSI is selected as system and kernel clock. The RCC registers are reset to their initial values except for the RCC_RSR and RCC_BDCR registers.

Note: The HSI and CSI outputs provide two clock paths:

• • one path for the system clock (hsi_ck or csi_ck)
• • one path for the peripheral kernel clock (hsi_ker_ck or csi_ker_ck).

When a peripheral requests the kernel clock in system stop mode, only the path providing the hsi_ker_ck or csi_ker_ck is activated.

11.4.10 Clock security system (CSS)

Clock security system on HSE

The clock security system can be enabled by software via the HSECSSON bit, which can be enabled even when the HSEON is set to 0.

The CSS on HSE is enabled by the hardware when the HSE is enabled and ready, and HSECSSON set to 1.

The CSS on HSE is disabled when the HSE is disabled. As a result, this function does not work when the system is in Stop mode.

It is not possible to clear directly the HSECSSON bit by software.

The HSECSSON bit is cleared by hardware when a system reset occurs or when the system enters Standby mode.

If a failure is detected on the HSE clock, the system automatically switches to the HSI or CSI, depending on STOPWUCK bit configuration in RCC clock configuration register1 (RCC_CFGR1) , to provide a safe clock. The HSE is then automatically disabled, a clock failure event is sent to the break inputs of the advanced-control timers (TIM1, TIM8), and an NMI is automatically generated to inform the application about the failure, allowing the MCU to perform rescue operations. If the HSE output was used as clock source for PLLs when the failure occurred, the PLLs are also disabled.

If an HSE clock failure occurs when the CSS is enabled, the CSS generates an interrupt that causes the automatic generation of an NMI. The HSECSSF flag in RCC clock source interrupt flag register (RCC_CIFR) is set to 1 to allow the application to identify the failure source. The NMI routine is executed indefinitely until the HSECSSF bit is cleared. As a consequence, the application must clear the HSECSSF flag in the NMI ISR by setting the HSECSSC bit in the RCC clock source interrupt clear register (RCC_CICR) .

Clock security system on LSE

A clock security system on LSE can be activated by software writing the LSECSSON bit in the RCC Backup domain control register (RCC_BDCR) . This bit can be disabled only by a hardware or RTC software reset, or after a failure detection on LSE. LSECSSON must be written after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware), and after the RTC clock has been selected by RTCSEL.

The CSS operates in all modes, including VBAT. It works also under system reset (excluding power-on reset). The system detects when the LSE disappears, or if it is over frequency.

If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied to the RTC, but no hardware action is made to the registers.

The CSS on LSE detection event is connected to the internal tamper 3 of the TAMP peripheral. The internal tamper 3 must be enabled (ITAMP3E = 1 in TAMP_CR1 register) and the associated interrupt enabled (ITAMP3IE in TAMP_IER) to wake up from the low-power modes. This erases also the TAMP backup registers and backup SRAM unless the ITAMP3NOER = 1 in the TAMP_CR3 (see Section 47: Tamper and backup registers (TAMP) for more details).

In case of CSS on LSE detection event (LSECSSD = 1 in the RCC_BDCR), the software must disable the LSECSSON bit, stop the defective 32 kHz oscillator (disabling LSEON), and change the RTC clock source (no clock or LSI or HSE, with RTCSEL), or take actions to secure the application.

Refer to datasheet for CSS on LSE electrical characteristics.

11.4.11 Clock output generation (MCO1/MCO2)

Two microcontroller clock output pins (MCO1 and MCO2) are available. A clock source can be selected for each output. The selected clock can be divided thanks to configurable prescaler (refer to Figure 52 for additional information on signal selection).

MCO1 and MCO2 outputs are controlled via MCO1PRE[3:0], MCO1[2:0], MCO2PRE[3:0], and MCO2[2:0], located in the RCC clock configuration register1 (RCC_CFGR1) .

The GPIO port corresponding to each MCO pin must be programmed in alternate function mode.

The clock provided to the MCOs outputs must not exceed the maximum pin speed (refer to the product datasheet for information on the supported speed).

Another output (LSCO) allows one of the low-speed clocks (LSI, LSE) to be output onto the external LSCO pin. This output is available in Stop mode, not available in Standby and VBAT modes. The selection is controlled by the LSCOSEL bit, and enabled by the LSCOEN bit in the RCC Backup domain control register (RCC_BDCR) .

The MCO clock output requires the corresponding alternate function selected on the MCO pin. The LSCO pin must be left in default POR state.

11.4.12 Kernel clock selection

Some peripherals are designed to work with two different clock domains that operate asynchronously:

• • a clock domain synchronous with the register and bus interface ( ckg_bus_perx clock)
• • a clock domain generally synchronous with the peripheral (kernel clock)

The benefit of having peripherals supporting these two clock domains is that the user application has more freedom to choose optimized clock frequency for the CPU, bus matrix and for the kernel part of the peripheral. The user application can thus change the bus frequency without reprogramming the peripherals. As an example, an ongoing transfer with UART is not disturbed if its APB clock is changed on-the-fly.

Table 115 shows the kernel clock that the RCC can deliver to the peripherals. Each row represents a multiplexer and the peripherals connected to its output.

Table 115. Kernel clock distribution overview

Table 115. Kernel clock distribution overview (continued)

1. For the actual availability of the peripheral refer to the device datasheet.

2. The bus (APB or AHB) clocks are the bus interface clocks to whom the peripherals are connected.

3. The per_ck clock can be hse_ck, hsi_ker_ck, or csi_ker_ck, according to CKPERSEL selection.

4. With a duty cycle close to 50%, meaning that PLL1Q or PLL2R values must be even. For SDMMCx the duty cycle must be 50% when supporting DDR.

5. Clock CSI divided by 122.

6. With a duty cycle close to 50%, meaning that PLL2R values must be even

7. Clock HSI divided by 4.

8. Clock HSE divided by RTCPRE.

To reduce the number of switches, some peripherals share the same kernel clock source, but all have their dedicated enable signal.

Peripherals dedicated to audio applications

The audio peripherals generally need specific accurate frequencies, the kernel clock of the SAIs or SPI(I2S)s can be generated by:

• • PLL1 when the amount of active PLLs must be reduced (for SAIs and SPI1 to 3)
• • APB2 peripheral clock (for SPI4 and 5)
• • APB3 peripheral clock (for SPI6)
• • PLL2 or 3 for optimal flexibility in frequency generation
• • HSE, HSI, or CSI when the current consumption is critical
• • AUDIOCLK when an external clock reference must be used

Peripherals dedicated to control and data transfer

Peripherals such as SPIs, I2Cs, UARTs do not need a specific kernel clock frequency but a clock fast enough to generate the correct baud rate, or the required bit clock on the serial interface. For that purpose the source can be selected among the following ones:

• • PLL1 when the amount of active PLLs must be reduced
• • PLL2 or PLL3 if better flexibility is required. As an example, this solution allows changing the frequency bus via PLL1 without affecting the speed of some serial interfaces.
• • HSI or CSI for low-power use-cases or when the peripheral must quickly wake up from Stop mode (such as UART or I2C)

Note: UARTs also need the LSE clock when high baud rates are not required.

The OCTOSPI and SDMMC1/2 can also use a clock different from the bus interface one for more flexibility.

RTC/AWU clock

The rtc_ck clock source can be one of the following:

• • the hse_1M_ck ( hse_ck divided by a programmable prescaler)
• • the lse_ck
• • the lsi_ck clock

The source clock is selected by programming the RTCSEL[1:0] bits in the RCC Backup domain control register (RCC_BDCR) and the RTCPRE[5:0] bits in the RCC clock configuration register1 (RCC_CFGR1) .

This selection cannot be modified without resetting the Backup domain.

If the LSE is selected as RTC clock, the RTC works normally even if the backup or the \( V_{DD} \) supply disappears.

The LSE clock is in the Backup domain, whereas the other oscillators are not. As a consequence:

• • If LSE is selected as RTC clock, the RTC continues working even if the \( V_{DD} \) supply is switched OFF, provided the \( V_{BAT} \) supply is maintained.
• • If LSI is selected as the RTC clock, the AWU state is not guaranteed if the \( V_{DD} \) supply is powered off.
• • If the HSE clock is used as RTC clock, the RTC state is not guaranteed if the \( V_{DD} \) supply is powered off or if the \( V_{CORE} \) supply is powered off.

The rtc_ck clock is enabled through RTCEN bit located in the RCC Backup domain control register (RCC_BDCR) .

The RTC bus interface clock (APB clock) is enabled through RTCAPBEN and RTCAPBLPEN bits located in RCC_APB3ENR/LPENR registers.

Note: To read the RTC calendar register when the APB clock frequency is less than seven times the RTC clock frequency ( \( F_{APB} < 7 \times F_{RTCLK} \) ), the software must read the calendar time and date registers twice. The data are correct if the second read access to RTC_TR gives the same result than the first one. Otherwise a third read access must be performed.

Watchdog clocks

The RCC provides the clock for the two watchdog blocks available on the circuit. The independent watchdog (IWDG) is connected to the LSI. The window watchdog (WWDG) is connected to the APB clock.

If an independent watchdog is started by either hardware option or software access, the LSI is forced ON and cannot be disabled. After the LSI oscillator setup delay, the clock is provided to the IWDG.

Clock frequency measurement using TIMx

Most of the clock source generator frequencies can be measured by means of the input capture of TIMx.

• • Calibrating the HSI or CSI with the LSE:

The primary purpose of having the LSE connected to a TIMx input capture is to be able to accurately measure the HSI or CSI. This requires to use the HSI or CSI as system clock source either directly or via PLL1. The number of system clock counts between consecutive edges of the LSE signal gives a measurement of the internal clock period. Taking advantage of the high precision of LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency with the same resolution, and trim the source to compensate for manufacturing-process and/or temperature- and voltage-related frequency deviations.

The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio). The precision is therefore tightly linked to the ratio between the two clock sources. The greater the ratio is, the more accurate the measurement is.

The HSI and CSI oscillators have dedicated user-accessible calibration bits for this purpose (see RCC CSI calibration register (RCC_CSICFGR) ). When HSI or CSI is used via the PLLx, the system clock can also be fine-tuned by using the fractional divider of the PLLs.

• • Calibrating the LSI with the HSI:

The LSI frequency can also be measured: this is useful for applications that do not have a crystal. The ultra-low-power LSI oscillator has a large manufacturing process deviation. The LSI clock frequency can be measured using the more precise HSI clock source. Using this measurement, a more accurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or an IWDG timeout with an acceptable accuracy can be obtained.

11.4.13 RTC and TAMP clock

The RTCCLK clock source is used by RTC and TAMP, and can be either the HSE / 32, LSE or LSI clock. It is selected by programming the RTCSEL[1:0] bits in the RCC Backup domain control register (RCC_BDCR) . This selection cannot be modified without resetting the Backup domain. The system must always be configured so as to get a PCLK frequency greater than or equal to the RTCCLK frequency for a proper operation of the RTC. The TAMP does not require any kernel clock if only the backup registers are used, with tamper in edge detection mode. All other tamper detection modes require a kernel clock (refer to Section 47: Tamper and backup registers (TAMP) for more details).

The LSE is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently:

• • If LSE is selected as RTC and TAMP clock, these peripherals continue to work even if the \( V_{DD} \) supply is switched off, provided the \( V_{BAT} \) supply is maintained.
• • If the HSE clock divided by a prescaler is used as the RTC or TAMP clock, the RTC state is not guaranteed if the \( V_{DD} \) supply is powered off or if the internal voltage regulator is powered off (removing power from the core domain). Depending on the TAMP configuration, this one can remain functional if used in a mode that does not need any kernel clock.
• • If the LSI is used as the RTC or TAMP clock, the RTC state is not guaranteed if the \( V_{DD} \) supply is powered off. Depending on the TAMP configuration, this one can remain functional if used in a mode that does not need any kernel clock.

When the RTC and TAMP clock is LSE or LSI, the RTC remains clocked and functional under system reset.

11.4.14 Timer clock

The timer clock frequencies are automatically defined by hardware.

There are two cases:

• • If the APB prescaler equals 1, the timer clock frequencies are set to the APB domain frequency.
• • Otherwise, they are set to twice ( \( \times 2 \) ) the APB domain frequency.

11.4.15 Watchdog clock

If the independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced on and cannot be disabled. After the LSI oscillator temporization, the LSI 32 kHz clock is provided to the IWDG.

11.4.16 Peripherals clock gating and autonomous mode

Peripherals clock gating in Run mode

Each peripheral clock can be enabled by the corresponding EN bit in the RCC_AHBxENR and RCC_APBxENR registers.

When the peripheral clock is not active, read or write accesses to the peripheral registers are not supported.

The enable bit has a synchronization mechanism to create a glitch-free clock for the peripheral. After the enable bit is set, there the clock is active after 2 cycles of the peripheral bus clock.

Caution: Just after enabling the clock for a peripheral, the software must wait for these 2 clock cycles before accessing the peripheral registers.

Peripherals clock gating in Sleep mode

When a peripheral is enabled, its clock can be automatically gated off when the device is in Sleep mode, by clearing the peripheral LPEN bit in the RCC_AHBxLPENR and RCC_APBxLPENR registers. Both EN and LPEN bit of the peripheral must be set to keep the clock on in Sleep mode.

11.5 RCC security and privilege functional description

11.5.1 RCC TrustZone security protection modes

When the TrustZone security is activated by the TZEN option byte in the Flash option byte configuration register, the RCC is able to secure RCC configuration and status bits from being modified by non-secure accesses.

This is configured through the RCC secure configuration register (RCC_SECCFGR) to prevent non-secure access to read or modify the following features:

• • HSE, HSE-CSS, HSI, CSI, LSI, LSE, LSE-CSS, LSCO, HSI48 configuration and status bits
• • PLL1, PLL2, PLL3, AHB and APB prescalers configuration and status bits
• • system clock (SYSCLK) and ICLK source clock selection and status bits
• • MCO clock output configuration and STOPWUCK and STOPKERWUCK bit
• • Remove reset flag RMVF configuration

If SPRIV is set in the RCC privilege configuration register (RCC_PRIVCFGR) , the RCC_SECCFGR register can be written only by secure and privileged access. If SPRIV is cleared in RCC_PRIVCFGR, RCC_SECCFGR can be written only by secure access, privileged or unprivileged.

RCC_SECCFGR can be read by secure, non-secure, privileged and unprivileged access.

When a peripheral is configured as secure, its related clock, reset, clock source selection and clock enable during low-power modes control bits, are also secure in the RCC_AHBxENR, RCC_APBxENR, RCC_CCIPRx and RCC_BDCR registers.

A peripheral is secure when:

• • For securable peripherals by TZSC (see Section 5.4.3: TrustZone security controller (TZSC) ), the SEC security bit corresponding to this peripheral is set in the GTZC TZSC secure configuration registers.
• • For TrustZone ^® -aware peripherals, a security feature of this peripheral is enabled through its dedicated bits.

Table 116 summarizes the RCC secured bits following the security configuration bit in the RCC_SECCFGR register.

When one security configuration bit is set, some configuration and status bits are secured. The RCC registers may contain secure and non-secure bits:

• • Secured bits: read and write operations are only allowed by a secure access. Non-secure read returns 0 and write accesses are ignored. No illegal access event is generated.
• • Non-secure bits: no restriction. Read and write operations are allowed by both secure and non-secure accesses.
• • A non-secure write access to RCC_SECCFGR is ignored and generates an illegal access event. An illegal access interrupt is generated if the RCC illegal access interrupt is enabled in the GTZC TZIC registers. RCC_SECCFGR can be read by secure or non-secure access.

When the TrustZone security is disabled (TZEN = 0xC3), all registers are non-secure. RCC_SECCFGR write accesses are ignored.

Table 116. RCC security configuration summary

Table 116. RCC security configuration summary (continued)

1. TRIM field of the HSI48 is located in CRS peripheral. Be sure to secure it using CRSSEC bit in GTZC1 TZSC secure configuration register 1.

11.5.2 RCC privilege protection modes

By default, after reset, all RCC registers can be read or written with both privileged and unprivileged access except RCC privilege configuration register (RCC_PRIVCFGR) that can be written with privileged access only. RCC_PRIVCFGR can be read by secure and non secure, privileged and unprivileged access.

The SPRIV bit in RCC_PRIVCFGR can be written with secure privileged access only. This bit configures the privileged access of all RCC secure functions (as defined by RCC secure configuration register (RCC_SECCFGR) or by the GTZC for securable peripherals, or by the peripheral itself in case of TrustZone-aware peripherals).

When the SPRIV bit is set in RCC_PRIVCFGR:

• • Writing the RCC secure bits is possible only with privileged access, including RCC_SECCFGR.
• • The RCC secure bits can be read only with privileged access except RCC_SECCFGR and RCC_PRIVCFGR that can be read by privileged or unprivileged access.
• • An unprivileged access to a privileged RCC bit or register is discarded: the bits are read as zero and the write to these bits is ignored (RAZ/WI).

The NSPRIV bit in RCC_PRIVCFGR can be written with privileged access only, secure or non-secure. This bit configures the privileged access of all RCC non-secure functions (as defined by RCC_SECCFGR, or by the GTZC for securable peripherals, or by the peripheral itself in case of TrustZone-aware peripherals).

When the NSPRIV bit is set in RCC_PRIVCFGR:

• • Writing the RCC non-secure bits is possible only with privileged access.
• • The RCC non-secure bits can be read only with privileged access except RCC_PRIVCFGR that can be read by privileged or unprivileged access.
• • An unprivileged access to a privileged RCC bit or register is discarded: the bits are read as zero and the write to these bits is ignored (RAZ/WI).

11.6 RCC low-power modes

• • AHB and APB peripheral clocks, including DMA clock, can be disabled by software.
• • Sleep mode stops the CPU clock. The memory interface clocks (flash memory, caches and all SRAM interfaces) can be stopped by software during Sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep mode when all the clocks of the peripherals connected to them are disabled.
• • Stop mode stops all the clocks in the core domain and disable the PLLs, HSI, HSI48, CSI and HSE oscillators. However, HSI or CSI can be switched ON to generate a wakeup interrupt. LSI and LSE remain active in Stop mode.
• • Standby mode stops all the clocks in the core domain and disable the PLLs, HSI, HSI48, CSI and HSE oscillators.

The CPU DeepSleep mode can be overridden for debugging by setting the DBG_STOP or DBG_STANDBY bit in the DBGMCU_CR register.

When exiting Stop mode, the system clock is either HSI or CSI, depending on the software configuration of STOPWUCK in the RCC CPU domain clock configuration register 2 (RCC_CFGR2) . The frequency (range and user trim) of the HSI is the one configured before entering Stop mode.

The other internal oscillator can be automatically woken up in addition to the one used by the system clock, to avoid waiting for the other oscillator wake-up time when the device is back in Run mode. This is done thanks to STOPKERWUCK in RCC_CFGR1.

When leaving the Standby mode, the system clock is HSI (32 MHz). The user trim is lost.

If a flash memory programming operation is ongoing, Stop or Standby mode entry is delayed until the flash memory interface access is finished. If an access to the APB domain is ongoing, Stop or Standby mode entry is delayed until the APB access is finished.

11.7 RCC interrupts

Table 117 summarizes the interrupt sources and the way to control them.

Table 117. Interrupt sources and control

Table 117. Interrupt sources and control (continued)

1. 1. The RCC secure interrupt vector is used only when TrustZone is enabled.
2. 2. The LSE CSS failure event (LSECSSD) is connected to TAMP internal tamper 3. to get the interrupt associated to this event, the internal tamper 3 must be enabled, and the internal tamper 3 interrupt must be enabled. The ITAMP3F, ITAMP3E, ITAMP3IE, and CITAMP3F bits are in the TAMP peripheral.
3. 3. It is not possible to mask this interrupt when the security system feature is enabled (HSECSSON = 1).

11.8 RCC registers

11.8.1 RCC clock control register (RCC_CR)

Address offset: 0x000

Reset value: 0x0000 002B

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 PLL3RDY : PLL3 clock ready flag

Set by hardware to indicate that the PLL3 is locked.

0: PLL3 unlocked (default after reset)

1: PLL3 locked

Bit 28 PLL3ON : PLL3 enable

Set and cleared by software to enable PLL3.

Cleared by hardware when entering Stop or Standby mode.

0: PLL3 OFF (default after reset)

1: PLL3 ON

Bit 27 PLL2RDY : PLL2 clock ready flag

Set by hardware to indicate that the PLL is locked.

0: PLL2 unlocked

1: PLL2 locked

Bit 26 PLL2ON : PLL2 enable

Set and cleared by software to enable PLL2.

Cleared by hardware when entering Stop or Standby mode.

0: PLL2 OFF (default after reset)

1: PLL2 ON

Bit 25 PLL1RDY : PLL1 clock ready flag

Set by hardware to indicate that the PLL1 is locked.

0: PLL1 unlocked (default after reset)

1: PLL1 locked

Bit 24 PLL1ON : PLL1 enable

Set and cleared by software to enable PLL1.

Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock.

0: PLL1 OFF (default after reset)

1: PLL1 ON

Bits 23:21 Reserved, must be kept at reset value.

Bit 20 HSEEXT : external high speed clock type in Bypass mode

Set and reset by software to select the external clock type (analog or digital).

The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled.

0: HSE in analog mode (default after reset)

1: HSE in digital mode

Bit 19 HSECSSON : HSE clock security system enable

Set by software to enable clock security system on HSE.

This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected.

0: CSS on HSE OFF (clock detector OFF) (default after reset)

1: CSS on HSE ON (clock detector ON if the HSE oscillator is stable, OFF if not).

Bit 18 HSEBYP : HSE clock bypass

Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device.

The HSEBYP bit can be written only if the HSE oscillator is disabled.

0: HSE oscillator not bypassed (default after reset)

1: HSE oscillator bypassed with an external clock

Bit 17 HSERDY : HSE clock ready flag

Set by hardware to indicate that the HSE oscillator is stable.

0: HSE clock is not ready (default after reset)

1: HSE clock is ready

Bit 16 HSEON : HSE clock enable

Set and cleared by software.

Cleared by hardware to stop the HSE when entering Stop or Standby mode.

This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1).

0: HSE is OFF (default after reset)

1: HSE is ON

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 HSI48RDY : HSI48 clock ready flag

Set by hardware to indicate that the HSI48 oscillator is stable.

0: HSI48 clock is not ready (default after reset)

1: HSI48 clock is ready

Bit 12 HSI48ON : HSI48 clock enable

Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode.

0: HSI48 is OFF (default after reset)

1: HSI48 is ON

Bit 11 Reserved, must be kept at reset value.

Bit 10 CSIKERON : CSI clock enable in Stop mode

Set and reset by software to force the CSI to ON, even in Stop mode, to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION.

0: no effect on CSI (default after reset)

1: CSI is forced to ON even in Stop mode

Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request).

0: CSI clock is not ready (default after reset)

1: CSI clock is ready

Set and reset by software to enable/disable CSI clock for system and/or peripheral.

Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.

This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1).

0: CSI is OFF (default after reset)

1: CSI is ON

Bits 7:6 Reserved, must be kept at reset value.

Set and reset by hardware.

As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the

current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV.

0: new division ratio not yet propagated to hsi_ck, hsi_ker_ck (default after reset)

1: hsi_ck, hsi_ker_ck clock frequency reflects the new HSIDIV value (default register value when the clock setting is completed).

Set and reset by software.

These bits allow selecting a division ratio to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored.

00: division by 1, hsi_ck, hsi_ker_ck = 64 MHz

01: division by 2, hsi_ck, hsi_ker_ck = 32 MHz (default after reset)

10: division by 4, hsi_ck, hsi_ker_ck = 16 MHz

11: division by 8, hsi_ck, hsi_ker_ck = 8 MHz

Set and reset by software to force the HSI to ON, even in Stop mode, to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION.

0: no effect on HSI (default after reset)

1: HSI is forced to ON even in Stop mode

Set by hardware to indicate that the HSI oscillator is stable.

0: HSI clock is not ready (default after reset)

1: HSI clock is ready

Bit 0 HSION : HSI clock enable

Set and cleared by software.

Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.

Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source.

This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1).

0: HSI is OFF

1: HSI is ON (default after reset)

11.8.2 RCC HSI calibration register (RCC_HSICFGR)

Address offset: 0x010

Reset value: 0x0040 0XXX

Reset value depends on the flash memory option bytes setting.

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 HSITRIM[6:0] : HSI clock trimming

Set by software to adjust calibration.

HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) to form the calibration trimming value.

HSICAL = HSITRIM + FLASH_HSI_OPT.

After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated

Note: The reset value of the field is 0x40.

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 HSICAL[11:0] : HSI clock calibration

Set by hardware by option byte loading during system reset. Adjusted by software through trimming bits HSITRIM.

This field represents the sum of engineering option byte calibration and HSITRIM bits values.

11.8.3 RCC clock recovery RC register (RCC_CRRRCR)

Address offset: 0x014

Reset value: 0x0000 0XXX

Reset value depends on the flash option bytes setting

Bits 31:10 Reserved, must be kept at reset value.

Bits 9:0 HSI48CAL[9:0] : Internal RC 48 MHz clock calibration

Set by hardware by option-byte loading during system reset NRESET. Read-only.

11.8.4 RCC CSI calibration register (RCC_CSICFGR)

Address offset: 0x018

Reset value: 0x0020 0XXX

Reset value depends on the flash option bytes setting

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:16 CSITRIM[5:0] : CSI clock trimming

Set by software to adjust calibration.

CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) to form the calibration trimming value.

CSICAL = CSITRIM + FLASH_CSI_OPT.

Note: The reset value of the field is 0x20.

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 CSICAL[7:0] : CSI clock calibration

Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM.

This field represents the sum of engineering option byte calibration value and CSITRIM bits value.

11.8.5 RCC clock configuration register1 (RCC_CFGR1)

Address offset: 0x01C

Reset value: 0x0000 0000

Access: 0 ≤ wait state ≤ 2; word, half-word and byte access

One or two wait states are inserted only if the access occurs during clock source switch.

Bits 31:29 MCO2SEL[2:0] : microcontroller clock output 2

Set and cleared by software. Clock source selection may generate glitches on MCO2.

It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.

000: system clock selected ( sys_ck ) (default after reset)

001: PLL2 oscillator clock selected ( pll2_p_ck )

010: HSE clock selected ( hse_ck )

011: PLL1 clock selected ( pll1_p_ck )

100: CSI clock selected ( csi_ck )

101: LSI clock selected ( lsi_ck )

Others: reserved

Bits 28:25 MCO2PRE[3:0] : MCO2 prescaler

Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.

0000: prescaler disabled (default after reset)

0001: division by 1 (bypass)

0010: division by 2

0011: division by 3

0100: division by 4

...

1111: division by 15

Bits 24:22 MCO1SEL[2:0] : Microcontroller clock output 1

Set and cleared by software. Clock source selection may generate glitches on MCO1.

It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.

000: HSI clock selected ( hsi_ck ) (default after reset)

001: LSE oscillator clock selected ( lse_ck )

010: HSE clock selected ( hse_ck )

011: PLL1 clock selected ( pll1_q_ck )

100: HSI48 clock selected ( hsi48_ck )

Others: reserved

Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.
0000: prescaler disabled (default after reset)
0001: division by 1 (bypass)
0010: division by 2
0011: division by 3
0100: division by 4
...
1111: division by 15

Bits 17:16 Reserved, must be kept at reset value.

This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains.

0: The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to \( 2 \times F_{\text{rcc\_pclk1}} \) or \( 2 \times F_{\text{rcc\_pclk2}} \) (default after reset)

1: The timers kernel clock is equal to \( 2 \times F_{\text{rcc\_pclk1}} \) or \( 2 \times F_{\text{rcc\_pclk2}} \) if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to \( 4 \times F_{\text{rcc\_pclk1}} \) or \( 4 \times F_{\text{rcc\_pclk2}} \)

Bit 14 Reserved, must be kept at reset value.

Set and cleared by software to divide the HSE to generate a clock for RTC.

Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source.

000000: no clock (default after reset)
000001: no clock
000010: HSE/2
000011: HSE/3
000100: HSE/4
...
111110: HSE/62
111111: HSE/63

Set and reset by software to select the kernel wakeup clock from system Stop.

0: HSI selected as wakeup clock from system Stop (default after reset)
1: CSI selected as wakeup clock from system Stop

Set and reset by software to select the system wakeup clock from system Stop.

The selected clock is also used as emergency clock for the clock security system (CSS) on HSE.
0: HSI selected as wakeup clock from system Stop (default after reset)
1: CSI selected as wakeup clock from system Stop

Caution: STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10).

Bit 5 Reserved, must be kept at reset value.

Bits 4:3 SWS[1:0] : system clock switch status

Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock ( hsi_ck ) (default after reset).

01: CSI used as system clock ( csi_ck )

10: HSE used as system clock ( hse_ck )

11: PLL1 used as system clock ( pll1_p_ck )

Others: reserved

Bit 2 Reserved, must be kept at reset value.

Bits 1:0 SW[1:0] : system clock and trace clock switch

Set and reset by software to select system clock and trace clock sources ( sys_ck ).

Set by hardware to force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode, and to force the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock

00: HSI selected as system clock ( hsi_ck ) (default after reset)

01: CSI selected as system clock ( csi_ck )

10: HSE selected as system clock ( hse_ck )

11: PLL1 selected as system clock ( pll1_p_ck for sys_ck )

Others: reserved

11.8.6 RCC CPU domain clock configuration register 2 (RCC_CFGR2)

Address offset: 0x020

Reset value: 0x0000 0000

1 or 2 wait states are inserted only if the access occurs during clock source switch.

From 0 to 15 wait states are inserted if the access occurs when the APB or AHB prescalers values update is ongoing.

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 APB3DIS : APB3 clock disable value. Set and cleared by software

This bit can be set to further reduce power consumption, when none of the APB3 peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off.

0: APB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits

1: APB3 clock disabled

This bit can be set to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off.

0: APB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits

1: APB2 clock disabled

This bit can be set to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG.

0: APB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits

1: APB1 clock disabled

This bit can be set to further reduce power consumption, when none of the AHB4 peripherals from RCC_AHB4ENR are used and when their clocks are disabled in RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from RCC_AHB4ENR are off.

0: AHB4 clock enabled, distributed to peripherals according to their dedicated clock enable control bits

1: AHB4 clock disabled

Bit 18 Reserved, must be kept at reset value.

This bit can be set to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR are used and when their clocks are disabled in RCC_AHB2ENR.

When this bit is set, all the AHB2 peripherals clocks are off, except for SRAM2 and SRAM3.

0: AHB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits

1: AHB2 clock disabled

This bit can be set to further reduce power consumption, when none of the AHB1 peripherals from RCC_AHB1ENR are used and when their clocks are disabled in RCC_AHB1ENR.

When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1.

0: AHB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits

1: AHB1 clock disabled

Bit 15 Reserved, must be kept at reset value.

Set and reset by software to control APB low-speed clocks division factor.

The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write.

0xx: rcc_pclk3 = rcc_hclk1

100: rcc_pclk3 = rcc_hclk1 / 2

101: rcc_pclk3 = rcc_hclk1 / 4

110: rcc_pclk3 = rcc_hclk1 / 8

111: rcc_pclk3 = rcc_hclk1 / 16

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 PPRE2[2:0] : APB high-speed prescaler (APB2)

Set and reset by software to control APB high-speed clocks division factor.

The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write.

0xx: rcc_pclk2 = rcc_hclk1

100: rcc_pclk2 = rcc_hclk1 / 2

101: rcc_pclk2 = rcc_hclk1 / 4

110: rcc_pclk2 = rcc_hclk1 / 8

111: rcc_pclk2 = rcc_hclk1 / 16

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 PPRE1[2:0] : APB low-speed prescaler (APB1)

Set and reset by software to control the division factor of rcc_pclk1.

The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write.

0xx: rcc_pclk1 = rcc_hclk1 (default after reset)

100: rcc_pclk1 = rcc_hclk1 / 2

101: rcc_pclk1 = rcc_hclk1 / 4

110: rcc_pclk1 = rcc_hclk1 / 8

111: rcc_pclk1 = rcc_hclk1 / 16

Bits 3:0 HPRE[3:0] : AHB prescaler

Set and reset by software to control the division factor of rcc_hclk. Changing this division ratio has an impact on the frequency of all bus matrix clocks

0xxx: rcc_hclk = sys_ck (default after reset)

1000: rcc_hclk = sys_ck / 2

1001: rcc_hclk = sys_ck / 4

1010: rcc_hclk = sys_ck / 8

1011: rcc_hclk = sys_ck / 16

1100: rcc_hclk = sys_ck / 64

1101: rcc_hclk = sys_ck / 128

1110: rcc_hclk = sys_ck / 256

1111: rcc_hclk = sys_ck / 512

Caution: Be careful when using the voltage scaling. Due to the propagation delay of the new division factor, after a prescaler factor change, and before lowering the \( V_{CORE} \) voltage, this register must be read to check that the new prescaler value has been taken into account.

Depending upon the clock source frequency and the voltage range, the software application must program a correct value in HPRE to make sure that the system frequency does not exceed the maximum frequency.

11.8.7 RCC PLL clock source selection register (RCC_PLL1CFGR)

Address offset: 0x028

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 PLL1REN : PLL1 DIVR divider output enable

Set and reset by software to enable the pll1_r_ck output of the PLL1.

To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used.

This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).

0: pll1_r_ck output disabled (default after reset)

1: pll1_r_ck output enabled

Bit 17 PLL1QEN : PLL1 DIVQ divider output enable

Set and reset by software to enable the pll1_q_ck output of the PLL1.

To save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.

This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).

0: pll1_q_ck output disabled (default after reset)

1: pll1_q_ck output enabled

Bit 16 PLL1PEN : PLL1 DIVP divider output enable

Set and reset by software to enable the pll1_p_ck output of the PLL1.

This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).

To save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled.

0: pll1_p_ck output disabled (default after reset)

1: pll1_p_ck output enabled

Bits 15:14 Reserved, must be kept at reset value.

Bits 13:8 PLL1M[5:0] : prescaler for PLL1

Set and cleared by software to configure the prescaler of the PLL1.

The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1).

To save power when PLL1 is not used, the value of PLL1M must be set to 0.

000000: prescaler disabled (default after reset)

000001: division by 1 (bypass)

000010: division by 2

000011: division by 3

...

100000: division by 32

...

111111: division by 63

Bits 7:6 Reserved, must be kept at reset value.

Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1.

0: wide VCO range: 192 to 836 MHz (default after reset)

1: medium VCO range: 150 to 420 MHz

Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator.

To latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator.

Set and reset by software to select the proper reference frequency range used for PLL1.

This bit must be written before enabling the PLL1.

00: PLL1 input (ref1_ck) clock range frequency between 1 and 2 MHz (default after reset)

01: PLL1 input (ref1_ck) clock range frequency between 2 and 4 MHz

10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz

11: PLL1 input (ref1_ck) clock range frequency between 8 and 16 MHz

Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled.

To save power, when no PLL is used, the value of PLL1SRC must be set to '00'.

00: no clock send to PLL1M divider and PLLs (default after reset).

01: HSI selected as PLL clock (hsi_ck)

10: CSI selected as PLL clock (csi_ck)

11: HSE selected as PLL clock (hse_ck)

11.8.8 RCC PLL clock source selection register (RCC_PLL2CFGR)

Address offset: 0x02C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Bits 31:19 Reserved, must be kept at reset value.

Set and reset by software to enable the pll2_r_ck output of the PLL2.

To save power, DIVR2EN and DIVR2 bits must be set to 0 when the pll2_r_ck is not used.

0: pll2_r_ck output disabled (default after reset)

1: pll2_r_ck output enabled

Bit 17 PLL2QEN : PLL2 DIVQ divider output enable

Set and reset by software to enable the pll2_q_ck output of the PLL2.

To save power, when the pll2_q_ck output of the PLL2 is not used, the pll2_q_ck must be disabled.

0: pll2_q_ck output disabled (default after reset)

1: pll2_q_ck output enabled

Bit 16 PLL2PEN : PLL2 DIVP divider output enable

Set and reset by software to enable the pll2_p_ck output of the PLL2.

To save power, when the pll2_p_ck output of the PLL2 is not used, the pll2_p_ck must be disabled.

0: pll2_p_ck output disabled (default after reset)

1: pll2_p_ck output enabled

Bits 15:14 Reserved, must be kept at reset value.

Bits 13:8 PLL2M[5:0] : prescaler for PLL2

Set and cleared by software to configure the prescaler of the PLL2.

The hardware does not allow any modification of this prescaler when PLL2 is enabled (PLL2ON = 1 or PLL2RDY = 1).

To save power when PLL2 is not used, the value of PLL2M must be set to 0.

000000: prescaler disabled (default after reset)

000001: division by 1 (bypass)

000010: division by 2

000011: division by 3

...

100000: division by 32

...

111111: division by 63

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 PLL2VCOSEL : PLL2 VCO selection

Set and reset by software to select the proper VCO frequency range used for PLL2.

This bit must be written before enabling the PLL2.

0: wide VCO range 192 to 836 MHz (default after reset)

1: medium VCO range 150 to 420 MHz

Bit 4 PLL2FRACEN : PLL2 fractional latch enable

Set and reset by software to enable the pll2_p_ck output of the PLL2.

To save power, when the pll2_p_ck output of the PLL2 is not used, the pll2_p_ck must be disabled.

0: pll2_p_ck output disabled (default after reset)

1: pll2_p_ck output enabled

Bits 3:2 PLL2RGE[1:0] : PLL2 input frequency range

Set and reset by software to select the proper reference frequency range used for PLL2.

These bits must be written before enabling the PLL2.

00: PLL2 input (ref2_ck) clock range frequency between 1 and 2 MHz (default after reset)

01: PLL2 input (ref2_ck) clock range frequency between 2 and 4 MHz

10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz

11: PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz

Bits 1:0 PLL2SRC[1:0] : PLL2M and PLLs clock source selection

Set and reset by software to select the PLL clock source.

These bits can be written only when all PLLs are disabled.

To save power, when no PLL is used, the value of PLL2SRC must be set to '00'.

00: no clock send to PLL2M divider and PLLs (default after reset)

01: HSI selected as PLL clock (hsi_ck)

10: CSI selected as PLL clock (csi_ck)

11: HSE selected as PLL clock (hse_ck)

11.8.9 RCC PLL clock source selection register (RCC_PLL3CFGR)

Address offset: 0x030

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 PLL3REN : PLL3 DIVR divider output enable

Set and reset by software to enable the pll3_r_ck output of the PLL3.

To save power, DIVR2EN and DIVR2 bits must be set to 0 when the pll3_r_ck is not used.

0: pll3_r_ck output disabled (default after reset)

1: pll3_r_ck output enabled

Bit 17 PLL3QEN : PLL3 DIVQ divider output enable

Set and reset by software to enable the pll3_q_ck output of the PLL3.

To save power, when the pll3_q_ck output of the PLL3 is not used, the pll3_q_ck must be disabled.

0: pll3_q_ck output disabled (default after reset)

1: pll3_q_ck output enabled

Bit 16 PLL3PEN : PLL3 DIVP divider output enable

Set and reset by software to enable the pll3_p_ck output of the PLL3.

To save power, when the pll3_p_ck output of the PLL3 is not used, the pll3_p_ck must be disabled.

0: pll3_p_ck output disabled (default after reset)

1: pll3_p_ck output enabled

Bits 15:14 Reserved, must be kept at reset value.

Bits 13:8 PLL3M[5:0] : prescaler for PLL3

Set and cleared by software to configure the prescaler of the PLL3.

The hardware does not allow any modification of this prescaler when PLL3 is enabled (PLL3ON = 1 or PLL3RDY = 1).

To save power when PLL3 is not used, the value of PLL3M must be set to 0.

000000: prescaler disabled (default after reset)

000001: division by 1 (bypass)

000010: division by 2

000011: division by 3

...

100000: division by 32

...

111111: division by 63

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 PLL3VCOSEL : PLL3 VCO selection

Set and reset by software to select the proper VCO frequency range used for PLL3.

This bit must be written before enabling the PLL3.

0: wide VCO range 192 to 836 MHz (default after reset)

1: medium VCO range 150 to 420 MHz

Bit 4 PLL3FRACEN : PLL3 fractional latch enable

Set and reset by software to latch the content of FRACN3 into the sigma-delta modulator.

To latch the FRACN3 value into the sigma-delta modulator, PLL3FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN3 into the modulator.

Bits 3:2 PLL3RGE[1:0] : PLL3 input frequency range

Set and reset by software to select the proper reference frequency range used for PLL3.

This bit must be written before enabling the PLL3.

00: PLL3 input (ref3_ck) clock range frequency between 1 and 2 MHz (default after reset)

01: PLL3 input (ref3_ck) clock range frequency between 2 and 4 MHz

10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz

11: PLL3 input (ref3_ck) clock range frequency between 8 and 16 MHz

Bits 1:0 PLL3SRC[1:0] : PLL3M and PLLs clock source selection

Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled.

To save power, when no PLL is used, the value of PLL3SRC must be set to '00'.

00: no clock send to PLL3M divider and PLLs (default after reset)

01: HSI selected as PLL clock (hsi_ck)

10: CSI selected as PLL clock (csi_ck)

11: HSE selected as PLL clock (hse_ck)

11.8.10 RCC PLL1 dividers register (RCC_PLL1DIVR)

Address offset: 0x034

Reset value: 0x0101 0280

Access: no wait state, word, half-word and byte access

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 PLL1R[6:0] : PLL1 DIVR division factor

Set and reset by software to control the frequency of the pll1_r_ck clock.

These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).

0000000: pll1_r_ck = vco1_ck / 1

0000001: pll1_r_ck = vco1_ck / 2 (default after reset)

0000010: pll1_r_ck = vco1_ck / 3

0000011: pll1_r_ck = vco1_ck / 4

...

1111111: pll1_r_ck = vco1_ck / 128

Bit 23 Reserved, must be kept at reset value.

Bits 22:16 PLL1Q[6:0] : PLL1 DIVQ division factor

Set and reset by software to control the frequency of the pll1_q_ck clock.

These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).

0000000: pll1_q_ck = vco1_ck

0000001: pll1_q_ck = vco1_ck / 2 (default after reset)

0000010: pll1_q_ck = vco1_ck / 3

0000011: pll1_q_ck = vco1_ck / 4

...

1111111: pll1_q_ck = vco1_ck / 128

Bits 15:9 PLL1P[6:0] : PLL1 DIVP division factor

Set and reset by software to control the frequency of the pll1_p_ck clock.

These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).

Note that odd division factors are not allowed.

0000000: Not allowed

0000001: pll1_p_ck = vco1_ck / 2 (default after reset)

0000010: Not allowed

0000011: pll1_p_ck = vco1_ck / 4

...

1111111: pll1_p_ck = vco1_ck / 128

Bits 8:0 PLL1N[8:0] : Multiplication factor for PLL1VCO

Set and reset by software to control the multiplication factor of the VCO.

These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).

0x003: PLL1N = 4

0x004: PLL1N = 5

0x005: PLL1N = 6

...

0x080: PLL1N = 129 (default after reset)

...

0x1FF: PLL1N = 512

Others: reserved

11.8.11 RCC PLL1 fractional divider register (RCC_PLL1FRACR)

Address offset: 0x038

Reset value: 0x0000 0000

Access: no wait state; word and half-word access

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:3 PLL1FRACN[12:0] : fractional part of the multiplication factor for PLL1 VCO

Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.

Caution: The software must set correctly these bits to insure that the VCO output frequency is in the valid frequency range, that is:

• * 128 to 560 MHz if PLL1VCOSEL = 0
• * 150 to 420 MHz if PLL1VCOSEL = 1

VCO output frequency = \( F_{ref1\_ck} \times (PLL1N + (PLL1FRACN / 2^{13})) \) , with

• * PLL1N between 8 and 420
• * PLL1FRACN between 0 and \( 2^{13} - 1 \)
• * The input frequency \( F_{ref1\_ck} \) must be between 1 and 16 MHz.

To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:

• * Set the bit PLL1FRACEN to 0
• * Write the new fractional value into PLL1FRACN
• * Set the bit PLL1FRACEN to 1

Bits 2:0 Reserved, must be kept at reset value.

11.8.12 RCC PLL1 dividers register (RCC_PLL2DIVR)

Address offset: 0x03C

Reset value: 0x0101 0280

Access: no wait state, word, half-word and byte access

Bit 31 Reserved, must be kept at reset value.

Set and reset by software to control the frequency of the pll2_r_ck clock.

These bits can be written only when the PLL1 is disabled (PLL2ON = 0 and PLL2RDY = 0).

0000000: pll2_r_ck = vco2_ck

0000001: pll2_r_ck = vco2_ck / 2 (default after reset)

0000010: pll2_r_ck = vco2_ck / 3

0000011: pll2_r_ck = vco2_ck / 4

...

1111111: pll2_r_ck = vco2_ck / 128

Bit 23 Reserved, must be kept at reset value.

Set and reset by software to control the frequency of the pll2_q_ck clock.

These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).

0000000: pll2_q_ck = vco2_ck

0000001: pll2_q_ck = vco2_ck / 2 (default after reset)

0000010: pll2_q_ck = vco2_ck / 3

0000011: pll2_q_ck = vco2_ck / 4

...

1111111: pll2_q_ck = vco2_ck / 128

Set and reset by software to control the frequency of the pll2_p_ck clock.

These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).

0000000: pll2_p_ck = vco2_ck

0000001: pll2_p_ck = vco2_ck / 2 (default after reset)

0000010: pll2_p_ck = vco2_ck / 3

0000011: pll2_p_ck = vco2_ck / 4

...

1111111: pll2_p_ck = vco2_ck / 128

Set and reset by software to control the multiplication factor of the VCO.

These bits can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0).

0x003: PLL2N = 4

0x004: PLL2N = 5

0x005: PLL2N = 6

...

0x080: PLL2N = 129 (default after reset)

...

0x1FF: PLL2N = 512

Others: reserved

11.8.13 RCC PLL2 fractional divider register (RCC_PLL2FRACR)

Address offset: 0x040

Reset value: 0x0000 0000

Access: no wait state; word and half-word access

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:3 PLL2FRACN[12:0] : fractional part of the multiplication factor for PLL2 VCO

Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO.

Caution: The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:

• * 128 to 560 MHz if PLL2VCOSEL = 0
• * 150 to 420 MHz if PLL2VCOSEL = 1

VCO output frequency = \( F_{ref2\_ck} \times (PLL2N + (PLL2FRACN / 2^{13})) \) , with

• * PLL2N between 8 and 420
• * PLL2FRACN can be between 0 and \( 2^{13} - 1 \)
• * The input frequency \( F_{ref2\_ck} \) must be between 1 and 16 MHz.

To change the PLL2FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:

• * Set the bit PLL2FRACEN to 0
• * Write the new fractional value into PLL2FRACN
• * Set the bit PLL2FRACEN to 1

Bits 2:0 Reserved, must be kept at reset value.

11.8.14 RCC PLL3 dividers register (RCC_PLL3DIVR)

Address offset: 0x044

Reset value: 0x0101 0280

Access: no wait state; word, half-word and byte access

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 PLL3R[6:0] : PLL3 DIVR division factor

Set and reset by software to control the frequency of the pll3_r_ck clock.

These bits can be written only when the PLL1 is disabled (PLL3ON = 0 and PLL3RDY = 0).

0000000: pll3_r_ck = vco3_ck

0000001: pll3_r_ck = vco3_ck / 2 (default after reset)

0000010: pll3_r_ck = vco3_ck / 3

0000011: pll3_r_ck = vco3_ck / 4

...

1111111: pll3_r_ck = vco3_ck / 128

Bit 23 Reserved, must be kept at reset value.

Bits 22:16 PLL3Q[6:0] : PLL3 DIVQ division factor

Set and reset by software to control the frequency of the pll3_q_ck clock.

These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).

0000000: pll3_q_ck = vco3_ck

0000001: pll3_q_ck = vco3_ck / 2 (default after reset)

0000010: pll3_q_ck = vco3_ck / 3

0000011: pll3_q_ck = vco3_ck / 4

...

1111111: pll3_q_ck = vco3_ck / 128

Bits 15:9 PLL3P[6:0] : PLL3 DIVP division factor

Set and reset by software to control the frequency of the pll3_p_ck clock.

These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).

0000000: pll3_p_ck = vco3_ck

0000001: pll3_p_ck = vco3_ck / 2 (default after reset)

0000010: pll3_p_ck = vco3_ck / 3

0000011: pll3_p_ck = vco3_ck / 4

...

1111111: pll3_p_ck = vco3_ck / 128

Bits 8:0 PLL3N[8:0] : Multiplication factor for PLL3VCO

Set and reset by software to control the multiplication factor of the VCO.

These bits can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0).

0x003: PLL3N = 4

0x004: PLL3N = 5

0x005: PLL3N = 6

...

0x080: PLL3N = 129 (default after reset)

...

0x1FF: PLL3N = 512

Others: reserved

11.8.15 RCC PLL3 fractional divider register (RCC_PLL3FRAGR)

Address offset: 0x048

Reset value: 0x0000 0000

Access: no wait state; word and half-word access

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:3 PLL3FRACN[12:0] : fractional part of the multiplication factor for PLL3 VCO

Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO.

Caution: The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:

• * 128 to 560 MHz if PLL3VCOSEL = 0

• * 150 to 420 MHz if PLL3VCOSEL = 1

VCO output frequency = Fref3_ck x (PLL3N + (PLL3FRACN / 213)), with

• * PLL3N between 8 and 420

• * PLL3FRACN can be between 0 and 213 - 1

• * The input frequency Fref3_ck must be between 1 and 16 MHz.

To change the PLL3FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:

• * Set the bit PLL3FRACEN to 0

• * Write the new fractional value into PLL3FRACN

• * Set the bit PLL3FRACEN to 1

Bits 2:0 Reserved, must be kept at reset value.

11.8.16 RCC clock source interrupt enable register (RCC_CIER)

Address offset: 0x050

Reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 PLL3RDYIE : PLL3 ready interrupt enable

Set and reset by software to enable/disable interrupt caused by PLL3 lock.

0: PLL3 lock interrupt disabled (default after reset)

1: PLL3 lock interrupt enabled

Bit 7 PLL2RDYIE : PLL2 ready interrupt enable

Set and reset by software to enable/disable interrupt caused by PLL2 lock.

0: PLL2 lock interrupt disabled (default after reset)

1: PLL2 lock interrupt enabled

• Bit 6 PLL1RDYIE : PLL1 ready interrupt enable
  Set and reset by software to enable/disable interrupt caused by PLL1 lock.
  0: PLL1 lock interrupt disabled (default after reset)
  1: PLL1 lock interrupt enabled

• Bit 5 HSI48RDYIE : HSI48 ready interrupt enable
  Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization.
  0: HSI48 ready interrupt disabled (default after reset)
  1: HSI48 ready interrupt enabled

• Bit 4 HSERDYIE : HSE ready interrupt enable
  Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization.
  0: HSE ready interrupt disabled (default after reset)
  1: HSE ready interrupt enabled

• Bit 3 HSIRDYIE : HSI ready interrupt enable
  Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization.
  0: HSI ready interrupt disabled (default after reset)
  1: HSI ready interrupt enabled

• Bit 2 CSIRDYIE : CSI ready interrupt enable
  Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization.
  0: CSI ready interrupt disabled (default after reset)
  1: CSI ready interrupt enabled

• Bit 1 LSERDYIE : LSE ready interrupt enable
  Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization.
  0: LSE ready interrupt disabled (default after reset)
  1: LSE ready interrupt enabled

• Bit 0 LSIRDYIE : LSI ready interrupt enable
  Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization.
  0: LSI ready interrupt disabled (default after reset)
  1: LSI ready interrupt enabled

11.8.17 RCC clock source interrupt flag register (RCC_CIFR)

Address offset: 0x054

Reset value: 0x0000 0000

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 HSECSSF : HSE clock security system interrupt flag

Reset by software by writing HSECSSC bit.

Set by hardware in case of HSE clock failure.

0: no clock security interrupt caused by HSE clock failure (default after reset)

1: clock security interrupt caused by HSE clock failure

Bit 9 Reserved, must be kept at reset value.

Bit 8 PLL3RDYF : PLL3 ready interrupt flag

Reset by software by writing PLL3RDYC bit.

Set by hardware when the PLL3 locks and PLL3RDYIE is set.

0: no clock ready interrupt caused by PLL3 lock (default after reset)

1: clock ready interrupt caused by PLL3 lock

Bit 7 PLL2RDYF : PLL2 ready interrupt flag

Reset by software by writing PLL2RDYC bit.

Set by hardware when the PLL2 locks and PLL2RDYIE is set.

0: no clock ready interrupt caused by PLL2 lock (default after reset)

1: clock ready interrupt caused by PLL2 lock

Bit 6 PLL1RDYF : PLL1 ready interrupt flag

Reset by software by writing PLL1RDYC bit.

Set by hardware when the PLL1 locks and PLL1RDYIE is set.

0: no clock ready interrupt caused by PLL1 lock (default after reset)

1: clock ready interrupt caused by PLL1 lock

Bit 5 HSI48RDYF : HSI48 ready interrupt flag

Reset by software by writing HSI48RDYC bit.

Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.

0: no clock ready interrupt caused by the HSI48 oscillator (default after reset)

1: clock ready interrupt caused by the HSI48 oscillator

Bit 4 HSERDYF : HSE ready interrupt flag

Reset by software by writing HSERDYC bit.

Set by hardware when the HSE clock becomes stable and HSERDYIE is set.

0: no clock ready interrupt caused by the HSE (default after reset)

1: clock ready interrupt caused by the HSE

Bit 3 HSIRDYF : HSI ready interrupt flag

Reset by software by writing HSIRDYC bit.

Set by hardware when the HSI clock becomes stable and HSIRDYIE is set.

0: no clock ready interrupt caused by the HSI (default after reset)

1: clock ready interrupt caused by the HSI

Bit 2 CSIRDYF : CSI ready interrupt flag

Reset by software by writing CSIRDYC bit.

Set by hardware when the CSI clock becomes stable and CSIRDYIE is set.

0: no clock ready interrupt caused by the CSI (default after reset)

1: clock ready interrupt caused by the CSI

Bit 1 LSERDYF : LSE ready interrupt flag

Reset by software by writing LSERDYC bit.

Set by hardware when the LSE clock becomes stable and LSERDYIE is set.

0: no clock ready interrupt caused by the LSE (default after reset)

1: clock ready interrupt caused by the LSE

Bit 0 LSIRDYF : LSI ready interrupt flag

Reset by software by writing LSIRDYC bit.

Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.

0: no clock ready interrupt caused by the LSI (default after reset)

1: clock ready interrupt caused by the LSI

11.8.18 RCC clock source interrupt clear register (RCC_CICR)

Address offset: 0x058

Reset value: 0x0000 0000

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 HSECSSC : HSE clock security system interrupt clear

Set by software to clear HSECSSF.

Reset by hardware when clear done.

0: HSECSSF no effect (default after reset)

1: HSECSSF cleared

Bit 9 Reserved, must be kept at reset value.

Bit 8 PLL3RDYC : PLL3 ready interrupt clear

Set by software to clear PLL3RDYF.

Reset by hardware when clear done.

0: PLL3RDYF no effect (default after reset)

1: PLL3RDYF cleared

Bit 7 PLL2RDYC : PLL2 ready interrupt clear

Set by software to clear PLL2RDYF.

Reset by hardware when clear done.

0: PLL2RDYF no effect (default after reset)

1: PLL2RDYF cleared

Bit 6 PLL1RDYC : PLL1 ready interrupt clear

Set by software to clear PLL1RDYF.

Reset by hardware when clear done.

0: PLL1RDYF no effect (default after reset)

1: PLL1RDYF cleared

Bit 5 HSI48RDYC : HSI48 ready interrupt clear

Set by software to clear HSI48RDYF.

Reset by hardware when clear done.

0: HSI48RDYF no effect (default after reset)

1: HSI48RDYF cleared

1. Bit 4 HSERDYC : HSE ready interrupt clear
   Set by software to clear HSERDYF.
   Reset by hardware when clear done.
   0: HSERDYF no effect (default after reset)
   1: HSERDYF cleared
2. Bit 3 HSIRDYC : HSI ready interrupt clear
   Set by software to clear HSIRDYF.
   Reset by hardware when clear done.
   0: HSIRDYF no effect (default after reset)
   1: HSIRDYF cleared
3. Bit 2 CSIRDYC : HSI ready interrupt clear
   Set by software to clear CSIRDYF.
   Reset by hardware when clear done.
   0: CSIRDYF no effect (default after reset)
   1: CSIRDYF cleared
4. Bit 1 LSERDYC : LSE ready interrupt clear
   Set by software to clear LSERDYF.
   Reset by hardware when clear done.
   0: LSERDYF no effect (default after reset)
   1: LSERDYF cleared
5. Bit 0 LSIRDYC : LSI ready interrupt clear
   Set by software to clear LSIRDYF.
   Reset by hardware when clear done.
   0: LSIRDYF no effect (default after reset)
   1: LSIRDYF cleared

11.8.19 RCC AHB1 reset register (RCC_AHB1RSTR)

Address offset: 0x060

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 ETHRST : ETHRST block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset ETHRST block (default after reset)

1: resets the ETHRST block

Bit 18 Reserved, must be kept at reset value.

Bit 17 RAMCFG_RST : RAMCFG block reset

Set and reset by software.

0: does not reset RAMCFG block (default after reset)

1: resets RAMCFG block

Bit 16 Reserved, must be kept at reset value.

Bit 15 FMAC_RST : FMAC block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset FMAC block (default after reset)

1: resets FMAC block

Bit 14 CORDIC_RST : CORDIC block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset CORDIC block (default after reset)

1: resets CORDIC block

Bit 13 Reserved, must be kept at reset value.

Bit 12 CRCCRST : CRC block reset

Set and reset by software.

0: does not reset CRC block (default after reset)

1: resets CRC block

Bits 11:2 Reserved, must be kept at reset value.

Bit 1 GPDMA2_RST : GPDMA2 block reset

Set and reset by software.

0: does not reset GPDMA2 block (default after reset)

1: resets GPDMA2 block

Bit 0 GPDMA1_RST : GPDMA1 block reset

Set and reset by software.

0: does not reset GPDMA1 block (default after reset)

1: resets GPDMA1 block

11.8.20 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)

Address offset: 0x064

Reset value: 0x0000 0000

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 SAESRST : SAES block reset

Set and reset by software.

0: does not reset SAES block (default after reset)

1: resets SAES block

Bit 19 PKARST : PKA block reset

Set and reset by software.

0: does not reset PKA block (default after reset)

1: resets PKA block

Bit 18 RNGRST : RNG block reset

Set and reset by software.

0: does not reset RNG block (default after reset)

1: resets RNG block

Bit 17 HASHRST : HASH block reset

Set and reset by software.

0: does not reset HASH block (default after reset)

1: resets HASH block

Bit 16 AESRST : AES block reset

Set and reset by software.

0: does not reset AES block (default after reset)

1: resets AES block

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 DCMI_PSSIRST : digital camera interface block reset (DCMI or PSSI depending which interface is active)

Set and reset by software.

0: does not reset the DCMI/PSSI block (default after reset)

1: resets the DCMI/PSSI block

Bit 11 DAC1RST : DAC block reset

Set and reset by software.

0: does not reset DAC block (default after reset)

1: resets DAC block

Bit 10 ADCRST : ADC1 and 2 blocks reset

Set and reset by software.

0: does not reset ADC1 and 2 blocks (default after reset)

1: resets ADC1 and 2 blocks

Bit 9 Reserved, must be kept at reset value.

Bit 8 GPIOIRST : GPIOI block reset

Set and reset by software. Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the GPIOI block (default after reset)

1: resets the GPIOI block

Bit 7 GPIOHRST : GPIOH block reset

Set and reset by software.

0: does not reset the GPIOH block (default after reset)

1: resets the GPIOH block

• Bit 6 GPIOGRST : GPIOG block reset
  Set and reset by software.
  0: does not reset the GPIOG block (default after reset)
  1: resets the GPIOG block
• Bit 5 GPIOFRST : GPIOF block reset
  Set and reset by software.
  0: does not reset the GPIOF block (default after reset)
  1: resets the GPIOF block
• Bit 4 GPIOERST : GPIOE block reset
  Set and reset by software.
  0: does not reset the GPIOE block (default after reset)
  1: resets the GPIOE block
• Bit 3 GPIODRST : GPIOD block reset
  Set and reset by software.
  0: does not reset the GPIOD block (default after reset)
  1: resets the GPIOD block
• Bit 2 GPIOCRST : GPIOC block reset
  Set and reset by software.
  0: does not reset the GPIOC block (default after reset)
  1: resets the GPIOC block
• Bit 1 GPIOBRST : GPIOB block reset
  Set and reset by software.
  0: does not reset the GPIOB block (default after reset)
  1: resets the GPIOB block
• Bit 0 GPIOARST : GPIOA block reset
  Set and reset by software.
  0: does not reset the GPIOA block (default after reset)
  1: resets the GPIOA block

11.8.21 RCC AHB4 peripheral reset register (RCC_AHB4RSTR)

Address offset: 0x06C

Reset value: 0x0000 0000

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 OCTOSPI1RST : OCTOSPI1 block reset

Set and reset by software.

0: does not reset OCTOSPI1 block (default after reset)

1: resets OCTOSPI1 block

Bits 19:17 Reserved, must be kept at reset value.

Bit 16 FMCRST : FMC block reset

Set and reset by software.

0: does not reset FMC block (default after reset)

1: resets FMC block

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 SDMMC2RST : SDMMC2 and SDMMC2 delay blocks reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset SDMMC2 and SDMMC2 delay blocks (default after reset)

1: resets SDMMC2 and SDMMC2 delay blocks

Bit 11 SDMMC1RST : SDMMC1 and SDMMC1 delay blocks reset

Set and reset by software.

0: does not reset SDMMC1 and SDMMC1 delay blocks (default after reset)

1: resets SDMMC1 and SDMMC1 delay blocks

Bits 10:8 Reserved, must be kept at reset value.

Bit 7 OTFDEC1RST : OTFDEC1 block reset

Set and reset by software.

0: does not reset OTFDEC1 block (default after reset)

1: resets OTFDEC1 block

Bits 6:0 Reserved, must be kept at reset value.

11.8.22 RCC APB1 peripheral low reset register (RCC_APB1LRSTR)

Address offset: 0x074

Reset value: 0x0000 0000

Bit 31 UART8RST : UART8 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the UART8 block (default after reset)

1: resets the UART8 block

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the UART7 block (default after reset)

1: resets the UART7 block

Bit 29 Reserved, must be kept at reset value.

Set and reset by software.

0: does not reset the HDMI-CEC block (default after reset)

1: resets the HDMI-CEC block

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the USART11 block (default after reset)

1: resets the USART11 block

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the USART10 block (default after reset)

1: resets the USART10 block

Set and reset by software.

0: does not reset the USART6 block (default after reset)

1: resets the USART6 block

Set and reset by software.

0: does not reset the CRS block (default after reset)

1: resets the CRS block

Set and reset by software.

0: does not reset the I3C1 block (default after reset)

1: resets the I3C1 block

Set and reset by software.

0: does not reset the I2C2 block (default after reset)

1: resets the I2C2 block

Set and reset by software.

0: does not reset the I2C1 block (default after reset)

1: resets the I2C1 block

Set and reset by software.

0: does not reset the UART5 block (default after reset)

1: resets the UART5 block

Bit 19 UART4RST : UART4 block reset

Set and reset by software.

0: does not reset the UART4 block (default after reset)

1: resets the UART4 block

Bit 18 USART3RST : USART3 block reset

Set and reset by software.

0: does not reset the USART3 block (default after reset)

1: resets the USART3 block

Bit 17 USART2RST : USART2 block reset

Set and reset by software.

0: does not reset the USART2 block (default after reset)

1: resets the USART2 block

Bit 16 Reserved, must be kept at reset value.

Bit 15 SPI3RST : SPI3 block reset

Set and reset by software.

0: does not reset the SPI3 block (default after reset)

1: resets the SPI3 block

Bit 14 SPI2RST : SPI2 block reset

Set and reset by software.

0: does not reset the SPI2 block (default after reset)

1: resets the SPI2 block

Bits 13:9 Reserved, must be kept at reset value.

Bit 8 TIM14RST : TIM14 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the TIM14 block (default after reset)

1: resets the TIM14 block

Bit 7 TIM13RST : TIM13 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the TIM13 block (default after reset)

1: resets the TIM13 block

Bit 6 TIM12RST : TIM12 block reset

Set and reset by software.

0: does not reset the TIM12 block (default after reset)

1: resets the TIM12 block

Bit 5 TIM7RST : TIM7 block reset

Set and reset by software.

0: does not reset the TIM7 block (default after reset)

1: resets the TIM7 block

Bit 4 TIM6RST : TIM6 block reset

Set and reset by software.

0: does not reset the TIM6 block (default after reset)

1: resets the TIM6 block

Bit 3 TIM5RST : TIM5 block reset

Set and reset by software.

0: does not reset the TIM5 block (default after reset)

1: resets the TIM5 block

Bit 2 TIM4RST : TIM4 block reset

Set and reset by software.

0: does not reset the TIM4 block (default after reset)

1: resets the TIM4 block

Bit 1 TIM3RST : TIM3 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the TIM3 block (default after reset)

1: resets the TIM3 block

Bit 0 TIM2RST : TIM2 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the TIM2 block (default after reset)

1: resets the TIM2 block

11.8.23 RCC APB1 peripheral high reset register (RCC_APB1HRSTR)

Address offset: 0x078

Reset value: 0x0000 0000

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 UCPD1RST : UCPD1 block reset

Set and reset by software.

0: does not reset the UCPD block (default after reset)

1: resets the UCPD block

Bits 22:10 Reserved, must be kept at reset value.

Bit 9 FDCANRST : FDCAN1 and FDCAN2 blocks reset

Set and reset by software.

0: does not reset the FDCAN1 and FDCAN2 blocks (default after reset)

1: resets the FDCAN1 and FDCAN2 blocks

Bits 8:6 Reserved, must be kept at reset value.

1. Bit 5 LPTIM2RST : LPTIM2 block reset
   Set and reset by software.
   0: does not reset the LPTIM2 block (default after reset)
   1: resets the LPTIM2 block
2. Bit 4 Reserved, must be kept at reset value.
3. Bit 3 DTSRST : DTS block reset
   Set and reset by software.
   0: does not reset the DTS block (default after reset)
   1: resets the DTS block
4. Bit 2 Reserved, must be kept at reset value.
5. Bit 1 UART12RST : UART12 block reset
   Set and reset by software.
   0: does not reset the UART12 block (default after reset)
   1: resets the UART12 block
6. Bit 0 UART9RST : UART9 block reset
   Set and reset by software.
   0: does not reset UART9 block (default after reset)
   1: resets UART9 block

11.8.24 RCC APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x07C

Reset value: 0x0000 0000

Bits 31:25 Reserved, must be kept at reset value.

1. Bit 24 USBRST : USB block reset
   Set and reset by software.
   0: does not reset the USB block (default after reset)
   1: resets the USB block
2. Bit 23 Reserved, must be kept at reset value.
3. Bit 22 SAI2RST : SAI2 block reset
   Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.
   0: does not reset the SAI2 block (default after reset)
   1: resets the SAI2 block

Bit 21 SAI1RST : SAI1 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the SAI1 (default after reset)

1: resets the SAI1

Bit 20 SPI6RST : SPI6 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the SPI6 block (default after reset)

1: resets the SPI6 block

Bit 19 SPI4RST : SPI4 block reset

Set and reset by software.

0: does not reset the SPI4 block (default after reset)

1: resets the SPI4 block

Bit 18 TIM17RST : TIM17 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the TIM17 block (default after reset)

1: resets the TIM17 block

Bit 17 TIM16RST : TIM16 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the TIM16 block (default after reset)

1: resets the TIM16 block

Bit 16 TIM15RST : TIM15 block reset

Set and reset by software.

0: does not reset the TIM15 block (default after reset)

1: resets the TIM15 block

Bit 15 Reserved, must be kept at reset value.

Bit 14 USART1RST : USART1 block reset

Set and reset by software.

0: does not reset the USART1 block (default after reset)

1: resets the USART1 block

Bit 13 TIM8RST : TIM8 block reset

Set and reset by software.

0: does not reset the TIM8 block (default after reset)

1: resets the TIM8 block

Bit 12 SPI1RST : SPI1 block reset

Set and reset by software.

0: does not reset the SPI1 block (default after reset)

1: resets the SPI1 block

Bit 11 TIM1RST : TIM1 block reset

Set and reset by software.

0: does not reset the TIM1 block (default after reset)

1: resets the TIM1 block

Bits 10:0 Reserved, must be kept at reset value.

11.8.25 RCC APB3 peripheral reset register (RCC_APB3RSTR)

Address offset: 0x080

Reset value: 0x0000 0000

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 VREFRST : VREFBUF block reset

Set and reset by software.

0: does not reset the VREFBUF block (default after reset)

1: resets the VREFBUF block

Bits 19:16 Reserved, must be kept at reset value.

Bit 15 LPTIM6RST : LPTIM6 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the LPTIM6 block (default after reset)

1: resets the LPTIM6 block

Bit 14 LPTIM5RST : LPTIM5 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the LPTIM5 block (default after reset)

1: resets the LPTIM5 block

Bit 13 LPTIM4RST : LPTIM4 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the LPTIM4 block (default after reset)

1: resets the LPTIM4 block

Bit 12 LPTIM3RST : LPTIM3 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the LPTIM3 block (default after reset)

1: resets the LPTIM3 block

Bit 11 LPTIM1RST : LPTIM1 block reset

Set and reset by software.

0: does not reset the LPTIM1 block (default after reset)

1: resets the LPTIM1 block

Bit 10 Reserved, must be kept at reset value.

Bit 9 I3C2RST : I3C2 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the I3C2 block (default after reset)

1: resets the I3C2 block

Bit 8 I2C4RST : I2C4 block reset

Set and reset by software.

0: does not reset the I2C4 block (default after reset)

1: resets the I2C4 block

Bit 7 I2C3RST : I2C3 block reset

Set and reset by software.

0: does not reset the I2C3 block (default after reset)

1: resets the I2C3 block

Bit 6 LPUART1RST : LPUART1 block reset

Set and reset by software.

0: does not reset the LPUART1 block (default after reset)

1: resets the LPUART1 block

Bit 5 SPI5RST : SPI5 block reset

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: does not reset the SPI5 block (default after reset)

1: resets the SPI5 block

Bits 4:0 Reserved, must be kept at reset value.

11.8.26 RCC AHB1 peripherals clock register (RCC_AHB1ENR)

Address offset: 0x088

Reset value: 0xD000 0100

Bit 31 SRAM1EN : SRAM1 clock enable

Set and reset by software.

0: SRAM1 clock disabled

1: SRAM1 clock enabled (default after reset)

Bit 30 DCACHEEN : DCACHE clock enable

Set and reset by software

0: DCACHE peripheral clock disabled (default after reset)

1: DCACHE peripheral clock enabled

Bit 29 Reserved, must be kept at reset value.

Bit 28 BKPRAMEN : BKPRAM clock enable

Set and reset by software.

0: BKPRAM peripheral clock disabled (default after reset)

1: BKPRAM peripheral clock enabled

Bits 27:25 Reserved, must be kept at reset value.

Bit 24 TZSC1EN : TZSC1 clock enable

Set and reset by software.

0: TZSC1 peripheral clock disabled (default after reset)

1: TZSC1 peripheral clock enabled

Bits 23:22 Reserved, must be kept at reset value.

Bit 21 ETHRXEN : ETHRX clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: ETHRX clock disabled (default after reset)

1: ETHRX clock enabled

Bit 20 ETH TXEN : ETHTX clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: ETHTX clock disabled (default after reset)

1: ETHTX clock enabled

Bit 19 ETHEN : ETH clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: ETH peripheral clock disabled (default after reset)

1: ETH peripheral clock enabled

Bit 18 Reserved, must be kept at reset value.

Bit 17 RAMCFGEN : RAMCFG clock enable

Set and reset by software.

0: RAMCFG peripheral clock disabled (default after reset)

1: RAMCFG peripheral clock enabled

Bit 16 Reserved, must be kept at reset value.

Bit 15 FMACEN : FMAC clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: FMAC peripheral clock disabled (default after reset)

1: FMAC peripheral clock enabled

Bit 14 CORDICEN : CORDIC clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: CORDIC peripheral clock disabled (default after reset)

1: CORDIC peripheral clock enabled

Bit 13 Reserved, must be kept at reset value.

Bit 12 CREN : CRC clock enable

Set and reset by software.

0: CRC peripheral clock disabled (default after reset)

1: CRC peripheral clock enabled

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 FLITFEN : Flash interface clock enable

Set and reset by software.

0: FLASH interface clock disabled

1: FLASH interface clock enabled (default after reset)

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 GPDMA2EN : GPDMA2 clock enable

Set and reset by software.

0: GPDMA2 peripheral clock disabled (default after reset)

1: GPDMA2 peripheral clock enabled

Bit 0 GPDMA1EN : GPDMA1 clock enable

Set and reset by software.

0: GPDMA1 peripheral clock disabled (default after reset)

1: GPDMA1 peripheral clock enabled

11.8.27 RCC AHB2 peripheral clock register (RCC_AHB2ENR)

Address offset: 0x08C

Reset value: 0xC000 0000

Bit 31 SRAM3EN : SRAM3 clock enable

Set and reset by software.

0: SRAM3 clock disabled

1: SRAM3 clock enabled (default after reset)

Bit 30 SRAM2EN : SRAM2 clock enable

Set and reset by software.

0: SRAM2 clock disabled

1: SRAM2 clock enabled (default after reset)

Bits 29:21 Reserved, must be kept at reset value.

Bit 20 SAESEN : SAES clock enable

Set and reset by software.

0: SAES peripheral clock disabled (default after reset)

1: SAES peripheral clock enabled

Bit 19 PKAEN : PKA clock enable

Set and reset by software.

0: PKA peripheral clock disabled (default after reset)

1: PKA peripheral clock enabled

Bit 18 RNGEN : RNG clock enable
Set and reset by software.
0: RNG peripheral clock disabled (default after reset)
1: RNG peripheral clock enabled

Bit 17 HASHEN : HASH clock enable
Set and reset by software.
0: HASH peripheral clock disabled (default after reset)
1: HASH peripheral clock enabled

Bit 16 AESEN : AES clock enable
Set and reset by software.
0: AES peripheral clock disabled (default after reset)
1: AES peripheral clock enabled

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 DCMI_PSSIEN : digital camera interface clock enable (DCMI or PSSI, depending which interface is active)
Set and reset by software.
0: DCMI/PSSI peripheral clock disabled (default after reset)
1: DCMI/PSSI peripheral clock enabled

Bit 11 DAC1EN : DAC clock enable
Set and reset by software.
0: DAC peripheral clock disabled (default after reset)
1: DAC peripheral clock enabled

Bit 10 ADCEN : ADC1 and 2 peripherals clock enable
Set and reset by software.
0: ADC1 and 2 peripherals clock disabled (default after reset)
1: ADC1 and 2 peripherals clock enabled

Bit 9 Reserved, must be kept at reset value.

Bit 8 GPIOIEN : GPIOI clock enable
Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.
0: GPIOI peripheral clock disabled (default after reset)
1: GPIOI peripheral clock enabled

Bit 7 GPIOHEN : GPIOH clock enable
Set and reset by software.
0: GPIOH peripheral clock disabled (default after reset)
1: GPIOH peripheral clock enabled

Bit 6 GPIOGEN : GPIOG clock enable
Set and reset by software.
0: GPIOG peripheral clock disabled (default after reset)
1: GPIOG peripheral clock enabled

Bit 5 GPIOFEN : GPIOF clock enable
Set and reset by software.
0: GPIOF peripheral clock disabled (default after reset)
1: GPIOF peripheral clock enabled

1. Bit 4 GPIOEEN : GPIOE clock enable
   Set and reset by software.
   0: GPIOE peripheral clock disabled (default after reset)
   1: GPIOE peripheral clock enabled
2. Bit 3 GPIODEN : GPIOD clock enable
   Set and reset by software.
   0: GPIOD peripheral clock disabled (default after reset)
   1: GPIOD peripheral clock enabled
3. Bit 2 GPIOCEN : GPIOC clock enable
   Set and reset by software.
   0: GPIOC peripheral clock disabled (default after reset)
   1: GPIOC peripheral clock enabled
4. Bit 1 GPIOBEN : GPIOB clock enable
   Set and reset by software.
   0: GPIOB peripheral clock disabled (default after reset)
   1: GPIOB peripheral clock enabled
5. Bit 0 GPIOAEN : GPIOA clock enable
   Set and reset by software.
   0: GPIOA peripheral clock disabled (default after reset)
   1: GPIOA peripheral clock enabled

11.8.28 RCC AHB4 peripheral clock register (RCC_AHB4ENR)

Address offset: 0x094

Reset value: 0x0000 0000

Bits 31:21 Reserved, must be kept at reset value.

1. Bit 20 OCTOSPI1EN : OCTOSPI1 clock enable
   Set and reset by software.
   0: OCTOSPI1 peripheral clock disabled (default after reset)
   1: OCTOSPI1 peripheral clock enabled

Bits 19:17 Reserved, must be kept at reset value.

1. Bit 16 FMCEN : FMC clock enable
   Set and reset by software.
   0: FMC peripheral clock disabled (default after reset)
   1: FMC peripheral clock enabled

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 SDMMC2EN : SDMMC2 and SDMMC2 delay peripheral clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: SDMMC2 and SDMMC2 delay peripherals clock disabled (default after reset)

1: SDMMC2 and SDMMC2 delay peripherals clock enabled

Bit 11 SDMMC1EN : SDMMC1 and SDMMC1 delay peripheral clock enable reset

0: SDMMC1 and SDMMC1 delay peripherals clock disabled (default after reset)

1: SDMMC1 and SDMMC1 delay peripherals clock enabled

Bits 10:8 Reserved, must be kept at reset value.

Bit 7 OTFDEC1EN : OTFDEC1 clock enable

Set and reset by software.

0: OTFDEC1 peripheral clock disabled (default after reset)

1: OTFDEC1 peripheral clock enabled

Bits 6:0 Reserved, must be kept at reset value.

11.8.29 RCC APB1 peripheral clock register (RCC_APB1LENR)

Address offset: 0x09C

Reset value: 0x0000 0000

Bit 31 UART8EN : UART8 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: UART8 peripheral clock disabled (default after reset)

1: UART8 peripheral clock enabled

Bit 30 UART7EN : UART7 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: UART7 peripheral clock disabled (default after reset)

1: UART7 peripheral clock enabled

Bit 29 Reserved, must be kept at reset value.

Bit 28 CECEN : HDMI-CEC clock enable

Set and reset by software.

0: HDMI-CEC peripheral clock disabled (default after reset)

1: HDMI-CEC peripheral clock enabled

Bit 27 USART11EN : USART11 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: USART11 peripheral clock disabled (default after reset)

1: USART11 peripheral clock enabled

Bit 26 USART10EN : USART10 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: USART10 peripheral clock disabled (default after reset)

1: USART10 peripheral clock enabled

Bit 25 USART6EN : USART6 clock enable

Set and reset by software.

0: USART6 peripheral clock disabled (default after reset)

1: USART6 peripheral clock enabled

Bit 24 CRSEN : CRS clock enable

Set and reset by software.

0: CRS peripheral clock disabled (default after reset)

1: CRS peripheral clock enabled

Bit 23 I3C1EN : I3C1 clock enable

Set and reset by software.

0: I3C1 peripheral clock disabled (default after reset)

1: I3C1 peripheral clock enabled

Bit 22 I2C2EN : I2C2 clock enable

Set and reset by software.

0: I2C2 peripheral clock disabled (default after reset)

1: I2C2 peripheral clock enabled

Bit 21 I2C1EN : I2C1 clock enable

Set and reset by software.

0: I2C1 peripheral clock disabled (default after reset)

1: I2C1 peripheral clock enabled

Bit 20 UART5EN : UART5 clock enable

Set and reset by software.

0: UART5 peripheral clock disabled (default after reset)

1: UART5 peripheral clock enabled

Bit 19 UART4EN : UART4 clock enable

Set and reset by software.

0: UART4 peripheral clock disabled (default after reset)

1: UART4 peripheral clock enabled

Bit 18 USART3EN : USART3 clock enable

Set and reset by software.

0: USART3 peripheral clock disabled (default after reset)

1: USART3 peripheral clock enabled

Bit 17 USART2EN : USART2 clock enable

Set and reset by software.

0: USART2 peripheral clock disabled (default after reset)

1: USART2 peripheral clock enabled

Bit 16 Reserved, must be kept at reset value.

Bit 15 SPI3EN : SPI3 clock enable

Set and reset by software.

0: SPI3 peripheral clock disabled (default after reset)

1: SPI3 peripheral clock enabled

Bit 14 SPI2EN : SPI2 clock enable

Set and reset by software.

0: SPI2 peripheral clock disabled (default after reset)

1: SPI2 peripheral clock enabled

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WWDGEN : WWDG clock enable

Set and reset by software.

0: WWDG peripheral clock disabled (default after reset)

1: WWDG peripheral clock enabled

Bits 10:9 Reserved, must be kept at reset value.

Bit 8 TIM14EN : TIM14 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: TIM14 peripheral clock disabled (default after reset)

1: TIM14 peripheral clock enabled

Bit 7 TIM13EN : TIM13 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: TIM13 peripheral clock disabled (default after reset)

1: TIM13 peripheral clock enabled

Bit 6 TIM12EN : TIM12 clock enable

Set and reset by software.

0: TIM12 peripheral clock disabled (default after reset)

1: TIM12 peripheral clock enabled

Bit 5 TIM7EN : TIM7 clock enable

Set and reset by software.

0: TIM7 peripheral clock disabled (default after reset)

1: TIM7 peripheral clock enabled

Bit 4 TIM6EN : TIM6 clock enable

Set and reset by software.

0: TIM6 peripheral clock disabled (default after reset)

1: TIM6 peripheral clock enabled

Bit 3 TIM5EN : TIM5 clock enable

Set and reset by software.

0: TIM5 peripheral clock disabled (default after reset)

1: TIM5 peripheral clock enabled

Bit 2 TIM4EN : TIM4 clock enable

Set and reset by software.

0: TIM4 peripheral clock disabled (default after reset)

1: TIM4 peripheral clock enabled

Bit 1 TIM3EN : TIM3 clock enable

Set and reset by software.

0: TIM3 peripheral clock disabled (default after reset)

1: TIM3 peripheral clock enabled

Bit 0 TIM2EN : TIM2 clock enable

Set and reset by software.

0: TIM2 peripheral clock disabled (default after reset)

1: TIM2 peripheral clock enabled

11.8.30 RCC APB1 peripheral clock register (RCC_APB1HENR)

Address offset: 0x0A0

Reset value: 0x0000 0000

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 UCPD1EN : UCPD1 clock enable

Set and reset by software.

0: UCPD peripheral clock disabled (default after reset)

1: UCPD peripheral clock enabled

Bits 22:10 Reserved, must be kept at reset value.

Bit 9 FDCANEN : FDCAN1 and FDCAN2 peripheral clock enable

Set and reset by software.

0: FDCAN1 and FDCAN2 peripheral clock disabled (default after reset)

1: FDCAN1 and FDCAN2 peripheral clock enabled

Bits 8:6 Reserved, must be kept at reset value.

Bit 5 LPTIM2EN : LPTIM2 clock enable

Set and reset by software.

0: LPTIM2 peripheral clock disabled (default after reset)

1: LPTIM2 peripheral clock enabled

Bit 4 Reserved, must be kept at reset value.

Bit 3 DTSSEN : DTS clock enable

Set and reset by software.

0: DTS peripheral clock disabled (default after reset)

1: DTS peripheral clock enabled

Bit 2 Reserved, must be kept at reset value.

Bit 1 UART12EN : UART12 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: UART12 peripheral clock disabled (default after reset)

1: UART12 peripheral clock enabled

Bit 0 UART9EN : UART9 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: UART9 peripheral clock disabled (default after reset)

1: resets UART9 peripheral clock enabled

11.8.31 RCC APB2 peripheral clock register (RCC_APB2ENR)

Address offset: 0x0A4

Reset value: 0x0000 0000

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 USBEN : USB clock enable

Set and reset by software.

0: USB peripheral clock disabled (default after reset)

1: USB peripheral clock enabled

Bit 23 Reserved, must be kept at reset value.

Bit 22 SAI2EN : SAI2 clock enable

Set and cleared by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: SAI2 clock disabled

1: SAI2 clock enabled

Bit 21 SAI1EN : SAI1 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: SAI1 peripheral clock disabled (default after reset)

1: SAI1 peripheral clock enabled

Bit 20 SPI6EN : SPI6 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: SPI6 peripheral clock disabled (default after reset)

1: SPI6 peripheral clock enabled

Bit 19 SPI4EN : SPI4 clock enable

Set and reset by software.

0: SPI4 peripheral clock disabled (default after reset)

1: SPI4 peripheral clock enabled

Bit 18 TIM17EN : TIM17 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: TIM17 peripheral clock disabled (default after reset)

1: TIM17 peripheral clock enabled

Bit 17 TIM16EN : TIM16 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: TIM16 peripheral clock disabled (default after reset)

1: TIM16 peripheral clock enabled

Bit 16 TIM15EN : TIM15 clock enable

Set and reset by software.

0: TIM15 peripheral clock disabled (default after reset)

1: TIM15 peripheral clock enabled

Bit 15 Reserved, must be kept at reset value.

Bit 14 USART1EN : USART1 clock enable

Set and reset by software.

0: USART1 peripheral clock disabled (default after reset)

1: USART1 peripheral clock enabled

Bit 13 TIM8EN : TIM8 clock enable

Set and reset by software.

0: TIM8 peripheral clock disabled (default after reset)

1: TIM8 peripheral clock enabled

Bit 12 SPI1EN : SPI1 clock enable

Set and reset by software.

0: SPI1 peripheral clock disabled (default after reset)

1: SPI1 peripheral clock enabled

Bit 11 TIM1EN : TIM1 clock enable

Set and reset by software.

0: TIM1 peripheral clock disabled (default after reset)

1: TIM1 peripheral clock enabled

Bits 10:0 Reserved, must be kept at reset value.

11.8.32 RCC APB3 peripheral clock register (RCC_APB3ENR)

Address offset: 0x0A8

Reset value: 0x0000 0000

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 RTCAPBEN : RTC APB interface clock enable

Set and reset by software.

0: RTC APB interface clock disabled (default after reset)

1: RTC APB interface clock enabled

Bit 20 VREFBUFEN : VREFBUF clock enable

Set and reset by software.

0: VREFBUF peripheral clock disabled (default after reset)

1: VREFBUF peripheral clock enabled

Bits 19:16 Reserved, must be kept at reset value.

Bit 15 LPTIM6EN : LPTIM6 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: LPTIM6 peripheral clock disabled (default after reset)

1: LPTIM6 peripheral clock enabled

Bit 14 LPTIM5EN : LPTIM5 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: LPTIM5 peripheral clock disabled (default after reset)

1: LPTIM5 peripheral clock enabled

Bit 13 LPTIM4EN : LPTIM4 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: LPTIM4 peripheral clock disabled (default after reset)

1: LPTIM4 peripheral clock enabled

Bit 12 LPTIM3EN : LPTIM3 clock enable

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: LPTIM3 peripheral clock disabled (default after reset)

1: LPTIM3 peripheral clock enabled

Bit 11 LPTIM1EN : LPTIM1 clock enable

Set and reset by software.

0: LPTIM1 peripheral clock disabled (default after reset)

1: LPTIM1 peripheral clock enabled

Bit 10 Reserved, must be kept at reset value.

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.
0: I3C2 peripheral clock disabled (default after reset)
1: I3C2 peripheral clock enabled

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.
0: I2C4 peripheral clock disabled (default after reset)
1: I2C4 peripheral clock enabled

Set and reset by software.
0: I2C3 peripheral clock disabled (default after reset)
1: I2C3 peripheral clock enabled

Set and reset by software.
0: LPUART1 peripheral clock disabled (default after reset)
1: LPUART1 peripheral clock enabled

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.
0: SPI5 peripheral clock disabled (default after reset)
1: SPI5 peripheral clock enabled

Bits 4:2 Reserved, must be kept at reset value.

Set and reset by software.
0: SBS peripheral clock disabled (default after reset)
1: SBS peripheral clock enabled

Bit 0 Reserved, must be kept at reset value.

11.8.33 RCC AHB1 sleep clock register (RCC_AHB1LPENR)

Address offset: 0x0B0

Reset value: 0xF13A D103 (for STM32H562/563/573xx)

Reset value: 0xF102 1103 (for STM32H523/533xx)

Bit 31 SRAM1LPEN : SRAM1 clock enable during Sleep mode

Set and reset by software

0: SRAM1 peripheral clock disabled during Sleep mode

1: SRAM1 peripheral clock enabled during Sleep mode (default after reset)

Bit 30 DCACHELPEN : DCACHE clock enable during Sleep mode

Set and reset by software

0: DCACHE peripheral clock disabled during Sleep mode

1: DCACHE peripheral clock enabled during Sleep mode (default after reset)

Bit 29 ICACHELPEN : ICACHE clock enable during Sleep mode

Set and reset by software.

0: ICACHE peripheral clock disabled during Sleep mode

1: ICACHE peripheral clock enabled during Sleep mode (default after reset)

Bit 28 BKPRAMLPEN : BKPRAM clock enable during Sleep mode

Set and reset by software.

0: BKPRAM peripheral clock disabled during Sleep mode

1: BKPRAM peripheral clock enabled during Sleep mode (default after reset)

Bits 27:25 Reserved, must be kept at reset value.

Bit 24 TZSC1LPEN : TZSC1 clock enable during Sleep mode

Set and reset by software.

0: TZSC1 peripheral clock disabled during Sleep mode

1: TZSC1 peripheral clock enabled during Sleep mode (default after reset)

Bits 23:22 Reserved, must be kept at reset value.

Bit 21 ETHRXLPEN : ETHRX clock enable during Sleep mode

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: ETHRX clock disabled during Sleep mode

1: ETHRX clock enabled during Sleep mode (default after reset)

Bit 20 ETHTXLPEN : ETHTX clock enable during Sleep mode

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: ETHTX clock disabled during Sleep mode

1: ETHTX clock enabled during Sleep mode (default after reset)

Bit 19 ETHLPEN : ETH clock enable during Sleep mode

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: ETH peripheral clock disabled during Sleep mode

1: ETH peripheral clock enabled during Sleep mode (default after reset)

Bit 18 Reserved, must be kept at reset value.

Bit 17 RAMCFG LPEN : RAMCFG clock enable during Sleep mode

Set and reset by software.

0: RAMCFG peripheral clock disabled during Sleep mode

1: RAMCFG peripheral clock enabled during Sleep mode (default after reset)

Bit 16 Reserved, must be kept at reset value.

Bit 15 FMACLPEN : FMAC clock enable during Sleep mode

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.
0: FMAC peripheral clock disabled during Sleep mode
1: FMAC peripheral clock enabled during Sleep mode (default after reset)

Bit 14 CORDICLPEN : CORDIC clock enable during Sleep mode

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.
0: CORDIC peripheral clock disabled during Sleep mode
1: CORDIC peripheral clock enabled during Sleep mode (default after reset)

Bit 13 Reserved, must be kept at reset value.

Bit 12 CRCLPEN : CRC clock enable during Sleep mode

Set and reset by software.
0: CRC peripheral clock disabled during Sleep mode
1: CRC peripheral clock enabled during Sleep mode (default after reset)

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 FLITFLPEN : Flash interface (FLITF) clock enable during Sleep mode

Set and reset by software.
0: FLITF peripheral clock disabled during Sleep mode
1: FLITF peripheral clock enabled during Sleep mode (default after reset)

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 GPDMA2LPEN : GPDMA2 clock enable during Sleep mode

Set and reset by software.
0: GPDMA2 peripheral clock disabled during Sleep mode
1: GPDMA2 peripheral clock enabled during Sleep mode (default after reset)

Bit 0 GPDMA1LPEN : GPDMA1 clock enable during Sleep mode

Set and reset by software.
0: GPDMA1 peripheral clock disabled during Sleep mode
1: GPDMA1 peripheral clock enabled during Sleep mode (default after reset)

11.8.34 RCC AHB2 sleep clock register (RCC_AHB2LPENR)

Address offset: 0x0B4

Reset value: 0xC01F 1DFF (for STM32H562/563/573xx)

Reset value: 0xC01F 1CFF (for STM32H523/533xx)

1. Bit 31 SRAM3LPEN : SRAM3 clock enable during Sleep mode
   Set and reset by software.
   0: SRAM3 peripheral clock disabled during Sleep mode
   1: SRAM3 peripheral clock enabled during Sleep mode (default after reset)
2. Bit 30 SRAM2LPEN : SRAM2 clock enable during Sleep mode
   Set and reset by software.
   0: SRAM2 peripheral clock disabled during Sleep mode
   1: SRAM2 peripheral clock enabled during Sleep mode (default after reset)
3. Bits 29:21 Reserved, must be kept at reset value.
4. Bit 20 SAESLPEN : SAES clock enable during Sleep mode
   Set and reset by software.
   0: SAES peripheral clock disabled during Sleep mode
   1: SAES peripheral clock enabled during Sleep mode (default after reset)
5. Bit 19 PKALPEN : PKA clock enable during Sleep mode
   Set and reset by software.
   0: PKA peripheral clock disabled during Sleep mode
   1: PKA peripheral clock enabled during Sleep mode (default after reset)
6. Bit 18 RNGLPEN : RNG clock enable during Sleep mode
   Set and reset by software.
   0: RNG peripheral clock disabled during Sleep mode
   1: RNG peripheral clock enabled during Sleep mode (default after reset)
7. Bit 17 HASHPEN : HASH clock enable during Sleep mode
   Set and reset by software.
   0: HASH peripheral clock disabled during Sleep mode
   1: HASH peripheral clock enabled during Sleep mode (default after reset)
8. Bit 16 AESLPEN : AES clock enable during Sleep mode
   Set and reset by software.
   0: AES peripheral clock disabled during Sleep mode
   1: AES peripheral clock enabled during Sleep mode (default after reset)
9. Bits 15:13 Reserved, must be kept at reset value.
10. Bit 12 DCMI_PSSILPEN : digital camera interface clock enable during Sleep mode (DCMI or PSSI, depending which interface is active)
    Set and reset by software.
    0: DCMI/PSSI peripheral clock disabled during Sleep mode
    1: DCMI/PSSI peripheral clock enabled during Sleep mode (default after reset)
11. Bit 11 DAC1LPEN : DAC clock enable during Sleep mode
    Set and reset by software.
    0: DAC peripheral clock disabled during Sleep mode
    1: DAC peripheral clock enabled during Sleep mode (default after reset)
12. Bit 10 ADCLPEN : ADC1 and 2 peripherals clock enable during Sleep mode
    Set and reset by software.
    0: ADC1 and 2 peripherals clock disabled during Sleep mode
    1: ADC1 and 2 peripherals clock enabled during Sleep mode (default after reset)
13. Bit 9 Reserved, must be kept at reset value.

Bit 8 GPIOILPEN : GPIOI clock enable during Sleep mode

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: GPIOI peripheral clock disabled during Sleep mode

1: GPIOI peripheral clock enabled during Sleep mode (default after reset)

Bit 7 GPIOHPEN : GPIOH clock enable during Sleep mode

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: GPIOH peripheral clock disabled during Sleep mode

1: GPIOH peripheral clock enabled during Sleep mode (default after reset)

Bit 6 GPIOGLPEN : GPIOG clock enable during Sleep mode

Set and reset by software.

0: GPIOG peripheral clock disabled during Sleep mode

1: GPIOG peripheral clock enabled during Sleep mode (default after reset)

Bit 5 GPIOFLPEN : GPIOF clock enable during Sleep mode

Set and reset by software.

0: GPIOF peripheral clock disabled during Sleep mode

1: GPIOF peripheral clock enabled during Sleep mode (default after reset)

Bit 4 GPIOELPEN : GPIOE clock enable during Sleep mode

Set and reset by software.

0: GPIOE peripheral clock disabled during Sleep mode

1: GPIOE peripheral clock enabled during Sleep mode (default after reset)

Bit 3 GPIODPEN : GPIOD clock enable during Sleep mode

Set and reset by software.

0: GPIOD peripheral clock disabled during Sleep mode

1: GPIOD peripheral clock enabled during Sleep mode (default after reset)

Bit 2 GPIOCPEN : GPIOC clock enable during Sleep mode

Set and reset by software.

0: GPIOC peripheral clock disabled during Sleep mode

1: GPIOC peripheral clock enabled during Sleep mode (default after reset)

Bit 1 GPIOBLPEN : GPIOB clock enable during Sleep mode

Set and reset by software.

0: GPIOB peripheral clock disabled during Sleep mode

1: GPIOB peripheral clock enabled during Sleep mode (default after reset)

Bit 0 GPIOALPEN : GPIOA clock enable during Sleep mode

Set and reset by software.

0: GPIOA peripheral clock disabled during Sleep mode

1: GPIOA peripheral clock enabled during Sleep mode (default after reset)

11.8.35 RCC AHB4 sleep clock register (RCC_AHB4LPENR)

Address offset: 0x0BC

Reset value: 0x0011 1880 (for STM32H562/563/573xx)

Reset value: 0x0011 0880 (for STM32H523/533xx)

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 OCTOSPI1LPEN : OCTOSPI1 clock enable during Sleep mode

Set and reset by software.

0: OCTOSPI1 peripheral clock disabled during Sleep mode

1: OCTOSPI1 peripheral clock enabled during Sleep mode (default after reset)

Bits 19:17 Reserved, must be kept at reset value.

Bit 16 FMCLPEN : FMC clock enable during Sleep mode

Set and reset by software.

0: FMC peripheral clock disabled during Sleep mode

1: FMC peripheral clock enabled during Sleep mode (default after reset)

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 SDMMC2LPEN : SDMMC2 and SDMMC2 delay peripheral clock enable during Sleep mode

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: SDMMC2 and SDMMC2 delay peripherals clock disabled during Sleep mode

1: SDMMC2 and SDMMC2 delay peripherals clock enabled during Sleep mode (default after reset)

Bit 11 SDMMC1LPEN : SDMMC1 and SDMMC1 delay peripheral clock enable during Sleep mode

Set and reset by software

0: SDMMC1 and SDMMC1 delay peripherals clock disabled during Sleep mode

1: SDMMC1 and SDMMC1 delay peripherals clock enabled during Sleep mode (default after reset)

Bits 10:8 Reserved, must be kept at reset value.

Bit 7 OTFDEC1LPEN : OTFDEC1 clock enable during Sleep mode

Set and reset by software.

0: OTFDEC1 peripheral clock disabled during Sleep mode

1: OTFDEC1 peripheral clock enabled during Sleep mode (default after reset)

Bits 6:0 Reserved, must be kept at reset value.

11.8.36 RCC APB1 sleep clock register (RCC_APB1LLPENR)

Address offset: 0x0C4

Reset value: 0xDFE C9FF (for STM32H562/563/573xx)

Reset value: 0x13FE C87F (for STM32H523/533xx)

Bit 31 UART8LPEN : UART8 clock enable during Sleep mode

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: UART8 peripheral clock disabled during Sleep mode

1: UART8 peripheral clock enabled during Sleep mode (default after reset)

Bit 30 UART7LPEN : UART7 clock enable during Sleep mode

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: UART7 peripheral clock disabled during Sleep mode

1: UART7 peripheral clock enabled during Sleep mode (default after reset)

Bit 29 Reserved, must be kept at reset value.

Bit 28 CECLPEN : HDMI-CEC clock enable during Sleep mode

Set and reset by software.

0: HDMI-CEC peripheral clock disabled during Sleep mode

1: HDMI-CEC peripheral clock enabled during Sleep mode (default after reset)

Bit 27 USART11LPEN : USART11 clock enable during Sleep mode

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: USART11 peripheral clock disabled during Sleep mode

1: USART11 peripheral clock enabled during Sleep mode (default after reset)

Bit 26 USART10LPEN : USART10 clock enable during Sleep mode

Set and reset by software. For the actual availability of this bit refer to the datasheet. If not present, consider it as reserved, and keep it at reset value.

0: USART10 peripheral clock disabled during Sleep mode

1: USART10 peripheral clock enabled during Sleep mode (default after reset)

Bit 25 USART6LPEN : USART6 clock enable during Sleep mode

Set and reset by software.