6. RAMs configuration controller (RAMCFG)

6.1 Introduction

The RAMCFG configures the features of the internal SRAMs (SRAM1, SRAM2, SRAM3, and BKPSRAM).

6.2 RAMCFG main features

The internal SRAMs support the features listed hereafter, configured in RAMCFG:

• • Error code correction (ECC):
  • – Single error detection and correction with interrupt generation
  • – Double error detection with interrupt or NMI generation
  • – Status with failing address
• • Write protection (1-Kbyte granularity)
• • SRAM software erase

6.3 RAMCFG functional description

6.3.1 Internal SRAMs features

Five SRAMs are embedded in the devices, each with specific features:

• • SRAM1, SRAM2, SRAM3 are the main SRAMs (see Table 39 ), made of several blocks that can be powered down in Stop mode to reduce consumption.
• • The backup SRAM (BKPSRAM) can be retained in all low-power modes and when \( V_{DD} \) is off in VBAT mode. Refer to Section 10: Power control (PWR) for more details.
• • SRAM2 is erased when a system reset occurs if the SRAM2_RST option bit is selected in the flash memory user option bytes. SRAM1 and SRAM3 are erased when a system reset occurs if the SRAM13_RST option bit is selected in the flash memory user option bytes. Refer to Section 7: Embedded flash memory (FLASH) for more details.
• • SRAM2 and (optionally) backup SRAM are protected by the tamper detection circuit, and are erased by hardware in case of tamper detection. Refer to Section 47: Tamper and backup registers (TAMP) for more details.
• • The RAMCFG embeds the registers related to the internal SRAMs ECC, write protection and software erase.

Table 39. SRAMs density (Kbytes)

Table 40 summarizes the features supported by each internal SRAM.

Table 40. Internal SRAMs features

1. 1. Optional: BKPSRAM can be configured to be erased or not on tamper detection.
2. 2. Available only on STM32H562/563/573xx devices.

6.3.2 Error code correction (SRAM2, SRAM3, BKPSRAM)

The ECC is supported by SRAM2, SRAM3 ^(a) and BKPSRAM when enabled with the SRAM2_ECC, SRAM3_ECC ^(b) and BKPRAM_ECC user option bits. Refer to Section 7: Embedded flash memory (FLASH) for more details.

Seven ECC bits are added per 32 bits of SRAM, allowing two bits error detection and one bit error correction on memory read access.

As the ECC is calculated and checked for a 32-bit word, the byte and half-word write accesses are managed by the SRAM interface by first reading the whole word, then write the word again with the new byte/half-word value. ECC double errors are also detected during these byte or half-word AHB write accesses (read/modify/write done by interface). The byte or half-word write access latency is two AHB clock cycles.

Caution: In case of a byte or half-word write on SRAM with ECC, the read/modify/write operation is done in a buffer. The buffer content is written into the SRAM two AHB clock cycles after the SRAM AHB is released (when SRAM is no more accessed).

Single and double ECC errors

When a single error is detected, it is automatically corrected and the SEDC/CSEDC bits are set, respectively, in the RAMCFG memory interrupt status register (RAMCFG_MxISR) / RAMCFG memory x interrupt clear register x (RAMCFG_MxICR) . An interrupt is generated if enabled by the SEIE bit in the RAMCFG memory x interrupt enable register (RAMCFG_MxIER) . The failing address is stored in the RAMCFG memory x ECC single error address register (RAMCFG_MxSEAR) if the ALE bit is set in the RAMCFG memory x control register (RAMCFG_MxCR) .

Caution: Single errors cannot be detected when the SEDC bit is set.

1. a. Available only on STM32H562/563/573xx devices.
2. b. Refer to the device datasheet for the actual availability. If not present, consider this bit as reserved, and keep it at reset value.

When a double error is detected, the DED and CDED bits are set in the RAMCFG memory interrupt status register (RAMCFG_MxISR) and RAMCFG memory x interrupt clear register x (RAMCFG_MxICR) respectively. An interrupt or NMI is generated if enabled by the DEIE or ECCNMI bit in the RAMCFG memory x interrupt enable register (RAMCFG_MxIER) . The failing address is stored in the RAMCFG memory x ECC double error address register (RAMCFG_MxDEAR) if the ALE bit is set in the RAMCFG memory x control register (RAMCFG_MxCN) .

Caution: Double errors cannot be detected when the DED bit is set.

SRAM3 ECC specific management

On STM32H562/563/573xx devices, when the ECC is enabled for SRAM3, only the first 256 Kbytes of SRAM3 are with ECC. The next 64 Kbytes are without ECC, and the last block is used to store the ECC, hence it cannot be used by the application.

Figure 20 shows the SRAM areas, when SRAM2 and SRAM3 ECC are enabled. Figure 21 shows the SRAM areas, when SRAM2 ECC and SRAM3 are enabled.

Figure 20. Memory map: SRAM1, SRAM2/3 with ECC (STM32H562/72/73xx devices)

Figure 21. Memory map: SRAM1/3, SRAM2 with ECC (STM32H523/33xx devices)

When ECC is enabled by user option bits, the ECCE bit is automatically set after system reset in the related RAMCFG memory x control register (RAMCFG_MxCR) .

The ECC can be deactivated by executing the following software sequence:

1. 1. Write 0xAE in the RAMCFG memory x ECC key register (RAMCFG_MxECCKEYR) .
2. 2. Write 0x75 in the RAMCFG memory x ECC key register (RAMCFG_MxECCKEYR) .
3. 3. Write 0 in the ECCE bit of the RAMCFG memory x control register (RAMCFG_MxCR) .

When ECC is deactivated (ECCE = 0), the SRAM3 ECC storage area can be read and written for ECC user test purpose. When the ECC is activated (ECCE = 1), this area is reserved for ECC storage purpose and cannot be neither read, nor written.

6.3.3 Write protection (SRAM2)

The SRAM2 is made of 1-Kbyte pages, each of them can be write-protected by setting its corresponding PxWP bit in the RAMCFG memory 2 write protection register 1 (RAMCFG_M2WPR1) , RAMCFG memory 2 write protection register 2 (RAMCFG_M2WPR2) , and RAMCFG memory 2 write protection register 3 (RAMCFG_M2WPR3) ^(a) .

Table 41. SRAM2 features

a. This register is available only on STM32H523/533 devices. If not present, consider this register as reserved, and keep its bits at reset value.

6.3.4 Software erase

SRAM erase can be requested by executing this software sequence:

1. 1. Write 0xCA in the RAMCFG memory x erase key register (RAMCFG_MxERKEYR) .
2. 2. Write 0x53 in the RAMCFG memory x erase key register (RAMCFG_MxERKEYR) .
3. 3. Write 1 in the SRAMER bit of the RAMCFG memory x control register (RAMCFG_MxCR) .

SRAMBUSY flag is set in the related SRAM interrupt status register as long as the erase is ongoing.

The total duration of each SRAM erase is N AHB clock cycles, where N is the size of the SRAM in 32-bit words.

If the SRAM is read or written while an erase is ongoing, wait states are inserted on the AHB bus until the end of the operation.

6.4 RAMCFG low-power modes

Table 42. Effect of low-power modes on RAMCFG

6.5 RAMCFG interrupts

Table 43. RAMCFG interrupt requests

6.6 RAMCFG registers

In the registers described below, x refers to:

• • SRAM1/2/3 when x = 1/2/3, respectively
• • BKPSRAM when x = 5

6.6.1 RAMCFG memory x control register (RAMCFG_MxCR)

Address offset: \( 0x000 + 0x040 * (x - 1) \) , ( \( x = 1, 2, 3, 5 \) )

Reset value: 0x0000 000X

ECCE reset value depends on ECC enable user option bit.

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SRAMER : SRAM erase

This bit can be set by software only after writing the unlock sequence in the ERASEKEY field of the RAMCFG_MxERKEYR register. Setting this bit starts the SRAM erase. This bit is automatically cleared by hardware at the end of the erase operation.

0: No erase operation on going

1: Erase operation on going

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 ALE : Address latch enable

0: Failing address not stored in the SRAMx ECC single/double error address registers

1: Failing address stored in the SRAMx ECC single/double error address registers

Note: For SRAM1 and SRAM3 (when ECC is not available) this bit is reserved and must be kept at reset value in control registers.

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 ECCE : ECC enable.

This bit reset value is defined by the user option bit configuration. When set, it can be cleared by software only after writing the unlock sequence in the RAMCFG_MxECCKEYR register.

0: ECC disabled

1: ECC enabled

Note: For SRAM1 and SRAM3 (when ECC is not available) this bit is reserved and must be kept at reset value in control registers.

6.6.2 RAMCFG memory x interrupt enable register (RAMCFG_MxIER)

Address offset: \( 0x004 + 0x040 * (x - 1) \) , ( \( x = 2, 3, 5 \) )

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 ECCNMI : Double error NMI

This bit is set by software and cleared only by a global RAMCFG reset.

0: NMI not generated in case of ECC double error

1: NMI generated in case of ECC double error

Note: if ECCNMI is set, the RAMCFG maskable interrupt is not generated whatever DEIE bit value.

Bit 2 Reserved, must be kept at reset value.

Bit 1 DEIE : ECC double error interrupt enable

0: Double error interrupt disabled

1: Double error interrupt enabled

Bit 0 SEIE : ECC single error interrupt enable

0: Single error interrupt disabled

1: Single error interrupt enabled

6.6.3 RAMCFG memory interrupt status register (RAMCFG_MxISR)

Address offset: 0x008 + 0x040 * (x - 1), (x = 1, 2, 3, 5)

Reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SRAMBUSY : SRAM busy with erase operation

0: No erase operation on going

1: Erase operation on going

Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the option bit is enabled, tamper detection or readout protection regression. Refer to Table 40.

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 DED : ECC double error detected

0: No double error

1: Double error detected

Note: For SRAM1 and SRAM3 (when ECC is not available) this bit is reserved and must be kept at reset value in control registers.

Bit 0 SEDC : ECC single error detected and corrected

0: No single error

1: Single error detected and corrected

Note: For SRAM1 and SRAM3 (when ECC is not available) this bit is reserved and must be kept at reset value in control registers.

6.6.4 RAMCFG memory x ECC single error address register (RAMCFG_MxSEAR)

Address offset: \( 0x00C + 0x040 * (x - 1) \) , ( \( x = 2, 3, 5 \) )

Reset value: 0x0000 0000

Bits 31:0 ESEA[31:0] : ECC single error address

When the ALE bit is set in the RAMCFG_MxCR register, this field is updated with the address corresponding to the ECC single error.

6.6.5 RAMCFG memory x ECC double error address register (RAMCFG_MxDEAR)

Address offset: \( 0x010 + 0x040 * (x - 1) \) , ( \( x = 2, 3, 5 \) )

Reset value: 0x0000 0000

Bits 31:0 EDEA[31:0] : ECC double error address

When the ALE bit is set in the RAMCFG_MxCR register, this field is updated with the address corresponding to the ECC double error.

6.6.6 RAMCFG memory x interrupt clear register x (RAMCFG_MxICR)

Address offset: \( 0x014 + 0x040 * (x - 1) \) , ( \( x = 2, 3, 5 \) )

Reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 CDED : Clear ECC double error detected

Writing 1 to this flag clears the DED bit in the RAMCFG_MxISR register. Reading this flag returns the DED value.

Bit 0 CSEDC : Clear ECC single error detected and corrected

Writing 1 to this flag clears the SEDC bit in the RAMCFG_MxISR register. Reading this flag returns the SEDC value.

6.6.7 RAMCFG memory 2 write protection register 1 (RAMCFG_M2WPR1)

Address offset: 0x058

Reset value: 0x0000 0000

Bits 31:0 PyWP : SRAM2 1-Kbyte page y write protection (y = 31 to 0)

These bits are set by software and cleared only by a global RAMCFG reset.

0: Write protection of SRAM2 1-Kbyte page y is disabled.

1: Write protection of SRAM2 1-Kbyte page y is enabled.

6.6.8 RAMCFG memory 2 write protection register 2 (RAMCFG_M2WPR2)

Address offset: 0x05C

Reset value: 0x0000 0000

Bits 31:0 PyWP : SRAM2 1-Kbyte page y write protection (y = 63 to 32)

These bits are set by software and cleared only by a global RAMCFG reset.

0: Write protection of SRAM2 1-Kbyte page y is disabled.

1: Write protection of SRAM2 1-Kbyte page y is enabled.

6.6.9 RAMCFG memory 2 write protection register 3 (RAMCFG_M2WPR3)

Address offset: 0x060

Reset value: 0x0000 0000

This register is available only for STM32H523/33xx devices.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PyWP : SRAM2 1-Kbyte page y write protection (y = 79 to 64)

These bits are set by software and cleared only by a global RAMCFG reset.

0: Write protection of SRAM2 1-Kbyte page y is disabled.

1: Write protection of SRAM2 1-Kbyte page y is enabled.

6.6.10 RAMCFG memory x ECC key register (RAMCFG_MxECCKEYR)

Address offset: 0x024 + 0x040 * (x - 1), (x = 2, 3, 5)

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 ECCKEY[7:0] : ECC write protection key

The following steps are required to unlock the write protection of the ECCE bit in the RAMCFG_MxCR register.

1) Write 0xAE into ECCKEY[7:0].

2) Write 0x75 into ECCKEY[7:0].

Note: Writing a wrong key reactivates the write protection.

6.6.11 RAMCFG memory x erase key register (RAMCFG_MxERKEYR)

Address offset: \( 0x028 + 0x040 * (x - 1) \) , ( \( x = 1 \) to \( 5 \) )

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 ERASEKEY[7:0] : Erase write protection key

The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register.

1. 1) Write 0xCA into ERASEKEY[7:0].
2. 2) Write 0x53 into ERASEKEY[7:0].

Note: Writing a wrong key reactivates the write protection.

6.6.12 RAMCFG register map

Table 44. RAMCFG register map and reset values

Table 44. RAMCFG register map and reset values (continued)

Table 44. RAMCFG register map and reset values (continued)

1. Available only on STM32H523/33xx devices.

Refer to Section 2.3 for the register boundary addresses.