2. Memory and bus architecture

2.1 System architecture

The architecture relies on a Arm Cortex-M33 core optimized for execution thanks to an instruction cache having a direct access to the embedded flash memory.

This architecture also features a 32-bit multilayer AHB bus matrix with the interconnections detailed in Table 1 and Table 2 .

Table 1. Implementation of masters

1. Not available on STM32H562xx devices.

Table 2. Implementation of slaves

Table 2. Implementation of slaves (continued)

1. STM32H523/533xx devices do not support SDRAM.

The bus matrix provides access from a master to a slave, enabling concurrent accesses and efficient operation even when several high-speed peripherals work simultaneously. This architecture is shown in Figure 1 .

Figure 1. System architecture

2.1.1 Fast C-bus

This bus connects the C-bus of the Cortex-M33 core to the internal flash memory and to the BusMatrix via the instruction cache. This bus is used for instruction fetch and data access to the internal memories mapped in code region. This bus targets the internal flash memory and the internal SRAMs (SRAM1, SRAM2 and SRAM3).

SRAM1, SRAM2 and SRAM3 are accessible on this bus with a continuous mapping.

2.1.2 Slow C-bus

This bus connects the C-bus of the Cortex-M33 core to the BusMatrix via the instruction cache. This bus is used for instruction fetch and data access to the external memories mapped in code region. This bus targets the external memories (FMC and OCTOSPI).

2.1.3 S-bus

This bus connects the system bus of the Cortex-M33 core to the BusMatrix. This bus is used by the core to access data located in a peripheral or SRAM area. This bus targets the internal SRAMs (SRAM1, SRAM2, SRAM3, and BKPSRAM), the AHB1 peripherals including the APB1, APB2, AHB2, AHB3 and AHB4 peripherals.

SRAM1, SRAM2 and SRAM3 are accessible on this bus with a continuous mapping.

Note: The Bus Matrix has a zero latency when accessing SRAM1, SRAM2 and SRAM3.

2.1.4 DCache S-bus

This bus connects the system bus of the Cortex-M33 core to the BusMatrix via the data cache. This bus is used for instruction fetch and data access to the external memories mapped in data region. This bus targets the external memories (FMC and OCTOSPI).

Note: Fetching instructions through this bus is less efficient than fetching instructions through the slow C-bus.

2.1.5 GPDMA1 and GPDMA2 buses

These buses connect the four AHB master interfaces of the GPDMA1 and GPDMA2 to the BusMatrix. These buses target the internal flash memory, the internal SRAMs (SRAM1, SRAM2, SRAM3, and BKPSRAM), the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals, the AHB3 peripherals, AHB4 peripherals and the external memories through FMC or OCTOSPI.

2.1.6 SDMMC1 and SDMMC2 ^(a) controllers DMA buses

These buses connect the SDMMC1 and SDMMC2 DMA master interfaces to the BusMatrix. They are used only by the SDMMC1 and SDMMC2 DMA to load/store data from/to the memory. These buses target the data memories: internal flash memory, internal SRAMs (SRAM1, SRAM2 and SRAM3), and external memories through FMC or OCTOSPI.

2.1.7 BusMatrix

The BusMatrix manages the access arbitration between masters. The arbitration uses a round-robin algorithm. This BusMatrix features a fast bus multiplexer used to connect each master to a given slave without latency (see Figure 1 ). For the same master, other slaves undergo a latency of at least one cycle at each new access.

a. SDMMC2 is not available on STM32H523/533xx devices.

2.1.8 AHB/APB bridges

The three AHB/APB bridges provide full synchronous connections between the AHB and the APB buses, allowing flexible selection of the peripheral frequency.

Refer to Section 2.3.2: Memory map and register boundary addresses for the address mapping of the peripherals connected to these bridges.

After each device reset, all peripheral clocks are disabled (except for the internal SRAMs and flash memory interfaces). Before using a peripheral, its clock must be enabled in the RCC_AHBxENR and RCC_APBxENR registers.

Note: When a 8- or 16-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 8- or 16-bit data to feed the 32-bit vector.

2.1.9 Ethernet MAC ^(a)

The Ethernet MAC uses a 32-bit bus, connected to the AHB bus matrix. Through the system bus matrices, it can access the internal flash memory, the internal memories, and the external memories through the OCTOSPI and the FMC.

2.2 TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M mainline extension.

The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.

When the TrustZone is enabled, the SAU (security-attribution unit) and IDAU (implementation-defined-attribution unit) defines the access permissions based on secure and non-secure states.

• • SAU: Up to eight SAU configurable regions are available for security attribution.
• • IDAU: provides a first memory partition as non-secure or non-secure callable attributes. The IDAU memory map partition is not configurable, it is fixed by hardware implementation (refer to Figure 2: Memory map based on IDAU mapping (STM32H562/563/573xx devices) and Figure 3: Memory map based on IDAU mapping (STM32H523/533xx devices) ). It is then combined with the results from the SAU security attribution, and the higher security state is selected.

Based on IDAU security attribution, the flash memory, system SRAMs and peripherals memory spaces are aliased twice for secure and non-secure states. However, the external memories space is not aliased.

2.2.1 Default TrustZone security state

When the TrustZone security is activated by the TZEN option bit in the FLASH_OPTR, the default system security state is detailed below:

• • CPU:
  • – Cortex-M33 is in secure state after reset. The boot address must be at a secure address.
• • Memory map:

a. Not available on STM32H523/533xx and STM32H562xx devices.

• – SAU is fully secure after reset. Consequently, all memory map is fully secure. Up to eight SAU configurable regions are available for security attribution.
• • Flash memory:
  • – The flash memory security area is defined by watermark user options.
  • – Block-based security attributions are non-secure after reset.
• • SRAMs:
  • – All SRAMs are secure after reset. MPCBBx (block-based memory protection controller) are secure.
• • External memories:
  • – FMC and OCTOSPI banks are secure after reset. MPCWMx (watermark-based memory protection controller) are secure.
• • Peripherals (see Table 3 and Table 4 for a list of securable and TrustZone-aware peripherals)
  • – Securables peripherals are non-secure after reset.
  • – TrustZone-aware peripherals are non-secure after reset. Their secure configuration registers are secure.
• • All GPIO are secure after reset.
• • Interrupts:
  • – NVIC: All interrupts are secure after reset. NVIC is banked for secure and non-secure state.
  • – TZIC: All illegal access interrupts are disabled after reset (see GTZC TrustZone system architecture ).

2.2.2 TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either securable or TrustZone-aware type as follows:

• • Securables: peripheral protected by an AHB/APB firewall gate that is controlled from TZSC controller to define security properties
• • TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing a specific TrustZone behavior such as a subset of registers being secure.

Refer to GTZC TrustZone system architecture for more details.

The following tables list the securable and TrustZone-aware peripherals within the system.

Table 3. Securables peripherals by TZSC

Table 3. Securables peripherals by TZSC (continued)

Table 3. Securable peripherals by TZSC (continued)

Table 3. Securable peripherals by TZSC (continued)

1. Not available on STM32H562xx devices.

1. 2. Available only on devices with cryptography (STM32H533/573xx)

Table 4. TrustZone-aware peripherals

2.3 Memory organization

2.3.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

2.3.2 Memory map and register boundary addresses

Figure 2. Memory map based on IDAU mapping (STM32H562/563/573xx devices)

Figure 3. Memory map based on IDAU mapping (STM32H523/533xx devices)

All the memory map areas not allocated to on-chip memories and peripherals are reserved.
Table 5 and Table 6 give the boundary addresses of the available peripherals.

Table 5. Memory map and peripheral register addresses (STM32H562/563/573xx)

Table 5. Memory map and peripheral register addresses (STM32H562/563/573xx) (continued)

Table 5. Memory map and peripheral register addresses (STM32H562/563/573xx) (continued)

Table 5. Memory map and peripheral register addresses (STM32H562/563/573xx) (continued)

Table 5. Memory map and peripheral register addresses (STM32H562/563/573xx) (continued)

1. Not available on STM32H562xx devices.

Table 6. Memory map and peripheral register addresses (STM32H523/533xx)

Table 6. Memory map and peripheral register addresses (STM32H523/533xx) (continued)

Table 6. Memory map and peripheral register addresses (STM32H523/533xx) (continued)

Table 6. Memory map and peripheral register addresses (STM32H523/533xx) (continued)

2.3.3 Embedded SRAMs

The STM32H562/563/573xx devices feature up to 644-Kbyte SRAMs:

• • 256-Kbyte SRAM1
• • 64-Kbyte SRAM2 with ECC
• • 320-Kbyte SRAM3 with optional ECC
• • 4-Kbyte BKPSRAM with ECC

The STM32H523/533xx devices feature up to 274-Kbyte SRAMs:

• • 128-Kbyte SRAM1
• • 80-Kbyte SRAM2 with ECC
• • 64-Kbyte SRAM3
• • 2-Kbyte BKPSRAM with ECC

The SRAMs can be accessed by byte, half-word (16 bits), or full word (32 bits).

The memories can be addressed both by CPU and DMAs. The CPU can access the SRAM1, SRAM2 and SRAM3 through the system bus or through the C-bus, depending on the selected address. The CPU can access the BKPSRAM only through the system bus.

When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAMs can be programmed as non-secure with a block granularity. For more details, refer to Section 5: Global TrustZone® controller (GTZC) .

SRAM features are detailed in Section 6.3.1: Internal SRAMs features .

2.3.4 Flash memory overview

The flash memory is composed of two distinct physical areas:

• • The main memory block, which contains the application program and user data.
• • The information block, composed of the following parts:
  • – option bytes for hardware and memory protection user configuration
  • – system memory, with the ST proprietary code
  • – OTP (one-time programmable) area

The flash interface implements instruction and data access based on the AHB protocol. It also implements the logic necessary to carry out the program/erase operations controlled through the FLASH registers plus security access control features. Refer to Section 7: Embedded flash memory (FLASH) for more details.

2.3.5 Boot modes

At startup, the core jumps to the boot address configured through the BOOT0 pin, the BOOT_ADDR option bytes, the TZEN option bit, debug request and the product state.

If BOOT_ADDR is not yet configured, dedicated libraries (programmed during ST production), can be used for secure boot. They are located in system flash memory:

• • ST libraries in system flash memory assist the application software boot with special features such as secure boot and secure firmware install (SFI-RSS).
• • ST iROT (immutable root of trust) secure software in user flash memory are used for secure firmware update and provisioning (SFU).

If a debugger is attached to the product, the entry point is a debug authentication policy, used to unlock the device when attached to debugger. Digital signature must be provided to perform a regression to product state, where debug is allowed.

Embedded bootloader

The embedded bootloader is located in the system memory, programmed by ST during production. Refer to AN2606 “ STM32 microcontroller system memory boot mode ”.