RM0481-STM32H523-33-562-63-573

Introduction

This document is addressed to application developers. It provides complete information on how to use the STM32H523xx, STM32H533xx, STM32H562xx, STM32H563xx, and STM32H573xx microcontrollers memory and peripherals.

For ordering information, mechanical and electrical device characteristics, refer to the corresponding datasheets.

For information on the Arm ® Cortex ® -M33 core, refer to the corresponding Arm ® Technical Reference Manuals available on http://infocenter.arm.com .

Contents

3.4Secure update . . . . .132
3.5Resource isolation using hide protection levels . . . . .132
3.6Resource isolation using TrustZone . . . . .132
3.6.1TrustZone security architecture . . . . .133
3.6.2Armv8-M security extension of Cortex-M33 . . . . .133
3.6.3Memory and peripheral allocation using IDAU/SAU . . . . .134
3.6.4Memory and peripheral allocation using GTZC . . . . .136
3.6.5Managing security in TrustZone-aware peripherals . . . . .140
3.6.6Activating TrustZone security . . . . .146
3.6.7Deactivating TrustZone security . . . . .147
3.7Other resources isolation . . . . .147
3.7.1Temporal isolation using secure hide protection (HDP) . . . . .148
3.7.2Resource isolation using Cortex privileged mode . . . . .148
3.8Secure execution . . . . .152
3.8.1Memory protection unit (MPU) . . . . .152
3.8.2Embedded flash memory write protection . . . . .153
3.8.3Tamper detection and response . . . . .153
3.9Secure storage . . . . .155
3.9.1Hardware secret key management . . . . .156
3.9.2Unique ID . . . . .157
3.10Crypto engines . . . . .157
3.10.1Crypto engines features . . . . .157
3.10.2Secure AES co-processor (SAES) . . . . .158
3.10.3On-the-fly decryption engine (OTFDEC) . . . . .159
3.11Product life cycle . . . . .159
3.11.1Product configurations and security services . . . . .160
3.11.2Life cycle management . . . . .161
3.11.3Recommended product settings . . . . .164
3.12Software intellectual property protection and collaborative development . . . . .164
3.12.1Software intellectual property protection . . . . .166
3.12.2Software intellectual property protection with OTFDEC . . . . .166
3.12.3Other software intellectual property protections . . . . .168
4Boot modes . . . . .169
4.1STM32H523/62/63xx boot modes . . . . .170
4.2STM32H533/73xx boot modes . . . . .171
5Global TrustZone® controller (GTZC) . . . . .172
5.1GTZC introduction . . . . .172
5.2GTZC main features . . . . .172
5.3GTZC implementation . . . . .174
5.4GTZC functional description . . . . .176
5.4.1GTZC block diagram . . . . .176
5.4.2Illegal access definition . . . . .177
5.4.3TrustZone security controller (TZSC) . . . . .178
5.4.4Memory protection controller - block based (MPCBB) . . . . .179
5.4.5TrustZone illegal access controller (TZIC) . . . . .180
5.4.6Power-on/reset state . . . . .180
5.5GTZC interrupts . . . . .180
5.6GTZC1 TZSC registers . . . . .181
5.6.1GTZC1 TZSC control register (GTZC1_TZSC_CR) . . . . .181
5.6.2GTZC1 TZSC secure configuration register 1
(GTZC1_TZSC_SECCFGR1) . . . . .		181
5.6.3GTZC1 TZSC secure configuration register 2
(GTZC1_TZSC_SECCFGR2) . . . . .		184
5.6.4GTZC1 TZSC secure configuration register 3
(GTZC1_TZSC_SECCFGR3) . . . . .		186
5.6.5GTZC1 TZSC privilege configuration register 1
(GTZC1_TZSC_PRIVCFGR1) . . . . .		188
5.6.6GTZC1 TZSC privilege configuration register 2
(GTZC1_TZSC_PRIVCFGR2) . . . . .		191
5.6.7GTZC1 TZSC privilege configuration register 3
(GTZC1_TZSC_PRIVCFGR3) . . . . .		193
5.6.8GTZC1 TZSC memory x subregion A watermark configuration
register (GTZC1_TZSC_MPCWMxACFGR) . . . . .		195
5.6.9GTZC1 TZSC memory x subregion A watermark register
(GTZC1_TZSC_MPCWMxAR) . . . . .		196
5.6.10GTZC1 TZSC memory x subregion B watermark configuration
register (GTZC1_TZSC_MPCWMxBCFGR) . . . . .		196
5.6.11GTZC1 TZSC memory x subregion B watermark register
(GTZC1_TZSC_MPCWMxBR) . . . . .		197
5.6.12GTZC1 TZSC register map . . . . .199
5.7GTZC1 TZIC registers . . . . .201
5.7.1GTZC1 TZIC interrupt enable register 1 (GTZC1_TZIC_IER1) . . . . .201
5.7.2GTZC1 TZIC interrupt enable register 2 (GTZC1_TZIC_IER2) . . . . .203
5.7.3GTZC1 TZIC interrupt enable register 3 (GTZC1_TZIC_IER3) . . . . .205
5.7.4GTZC1 TZIC interrupt enable register 4 (GTZC1_TZIC_IER4) . . . . .207
5.7.5GTZC1 TZIC status register 1 (GTZC1_TZIC_SR1) . . . . .209
5.7.6GTZC1 TZIC status register 2 (GTZC1_TZIC_SR2) . . . . .212
5.7.7GTZC1 TZIC status register 3 (GTZC1_TZIC_SR3) . . . . .214
5.7.8GTZC1 TZIC status register 4 (GTZC1_TZIC_SR4) . . . . .216
5.7.9GTZC1 TZIC flag clear register 1 (GTZC1_TZIC_FCR1) . . . . .218
5.7.10GTZC1 TZIC flag clear register 2 (GTZC1_TZIC_FCR2) . . . . .220
5.7.11GTZC1 TZIC flag clear register 3 (GTZC1_TZIC_FCR3) . . . . .222
5.7.12GTZC1 TZIC flag clear register 4 (GTZC1_TZIC_FCR4) . . . . .224
5.7.13GTZC1 TZIC register map . . . . .227
5.8GTZC1 MPCBBz registers (z = 1 to 3) . . . . .229
5.8.1GTZC1 SRAMz MPCBB control register
(GTZC1_MPCBBz_CR) (z = 1 to 3) . . . . .		229
5.8.2GTZC1 SRAMz MPCBB configuration lock register 1
(GTZC1_MPCBBz_CFGLOCK1) (z = 1 to 3) . . . . .		229
5.8.3GTZC1 SRAMz MPCBB security configuration for super-block x
register (GTZC1_MPCBBz_SECCFGRx) (z = 1 to 3) . . . . .		230
5.8.4GTZC1 SRAMz MPCBB privileged configuration for super-block x
register (GTZC1_MPCBBz_PRIVCFGRx) (z = 1 to 3) . . . . .		230
5.8.5GTZC1 MPCBBz register map (z = 1 to 3) . . . . .231
6RAMs configuration controller (RAMCFG) . . . . .232
6.1Introduction . . . . .232
6.2RAMCFG main features . . . . .232
6.3RAMCFG functional description . . . . .232
6.3.1Internal SRAMs features . . . . .232
6.3.2Error code correction (SRAM2, SRAM3, BKPSRAM) . . . . .233
6.3.3Write protection (SRAM2) . . . . .235
6.3.4Software erase . . . . .236
6.4RAMCFG low-power modes . . . . .236
6.5RAMCFG interrupts . . . . .236
6.6RAMCFG registers . . . . .237
6.6.1RAMCFG memory x control register (RAMCFG_MxCR) . . . . .237
6.6.2RAMCFG memory x interrupt enable register (RAMCFG_MxIER) . . . . .237
6.6.3RAMCFG memory interrupt status register (RAMCFG_MxISR) . . . . .238
6.6.4RAMCFG memory x ECC single error address register
(RAMCFG_MxSEAR) . . . . .		239
6.6.5RAMCFG memory x ECC double error address register (RAMCFG_MxDEAR) . . . . .239
6.6.6RAMCFG memory x interrupt clear register x (RAMCFG_MxICR) . . . . .239
6.6.7RAMCFG memory 2 write protection register 1 (RAMCFG_M2WPR1) . . . . .240
6.6.8RAMCFG memory 2 write protection register 2 (RAMCFG_M2WPR2) . . . . .240
6.6.9RAMCFG memory 2 write protection register 3 (RAMCFG_M2WPR3) . . . . .241
6.6.10RAMCFG memory x ECC key register (RAMCFG_MxECCKEYR) . . . . .241
6.6.11RAMCFG memory x erase key register (RAMCFG_MxERKEYR) . . . . .242
6.6.12RAMCFG register map . . . . .243
7Embedded flash memory (FLASH) . . . . .246
7.1Introduction . . . . .246
7.2FLASH main features . . . . .246
7.3FLASH functional description . . . . .247
7.3.1FLASH block diagram . . . . .247
7.3.2FLASH signals . . . . .248
7.3.3Flash memory architecture and usage . . . . .249
7.3.4FLASH read operations . . . . .251
7.3.5FLASH program operations . . . . .253
7.3.6FLASH erase operations . . . . .256
7.3.7FLASH parallel operations . . . . .259
7.3.8FLASH error protections . . . . .260
7.3.9OTP and RO memory access . . . . .260
7.3.10Flash high-cycle data . . . . .262
7.3.11Flash bank swapping . . . . .264
7.3.12FLASH reset and clocks . . . . .267
7.4FLASH option bytes . . . . .269
7.4.1About option bytes . . . . .269
7.4.2Option bytes loading . . . . .269
7.4.3Option bytes modification . . . . .269
7.4.4Description of user and system option bytes . . . . .272
7.4.5Description of data protection option bytes . . . . .273
7.4.6Description of boot address option bytes . . . . .274
7.4.7Specific rules for modifying option bytes . . . . .274
7.5Option bytes key (OBK) management . . . . .276
7.5.1OBK loading . . . . .276
7.5.2OBK access per HDPL level . . . . .277
7.5.3OBK programming sequence . . . . .277
7.5.4OBK programming finite state machine . . . . .279
7.5.5OBK swap sector . . . . .280
7.5.6OBK alternate sector erase . . . . .282
7.6FLASH security and protections . . . . .282
7.6.1TrustZone security protection . . . . .283
7.6.2Hide protection (HDP) . . . . .285
7.6.3Block-based secure flash memory area protection . . . . .287
7.6.4Block-based privileged flash memory area protection . . . . .288
7.6.5Flash memory register privileged and unprivileged modes . . . . .289
7.6.6Flash memory banks attributes in case of bank swap . . . . .290
7.6.7Flash memory configuration protection . . . . .291
7.6.8Write protection . . . . .292
7.6.9Flash high-cycle data protections . . . . .292
7.6.10Life cycle management . . . . .294
7.6.11Product state transitions . . . . .295
7.6.12OBK protection . . . . .297
7.6.13One-time-programmable and read-only memory protections . . . . .298
7.7System memory . . . . .299
7.7.1Introduction . . . . .299
7.7.2RSS user functions . . . . .299
7.8FLASH low-power modes . . . . .306
7.9FLASH error management . . . . .307
7.9.1Introduction . . . . .307
7.9.2Non-secure write protection error (WRPERR) . . . . .307
7.9.3Secure write protection error (WRPERR) . . . . .308
7.9.4Non secure programming sequence error (PGSERR) . . . . .309
7.9.5Secure programming sequence error (PGSERR) . . . . .310
7.9.6Non-secure strobe error (STRBERR) . . . . .311
7.9.7Secure strobe error (STRBERR) . . . . .311
7.9.8Non-secure inconsistency error (INCERR) . . . . .311
7.9.9Secure inconsistency error (INCERR) . . . . .312
7.9.10Error correction code error (ECCC, ECCD) . . . . .313
7.9.11Illegal access (ILAFM/ILAP) . . . . .314
7.9.12Option byte change error (OPTCHANGEERR) . . . . .314
7.11.32FLASH privilege block based register for Bank1
(FLASH_PRIVBB1Rx) . . . . .		347
7.11.33FLASH security watermark for Bank1 (FLASH_SECWM1R_CUR) . .348
7.11.34FLASH security watermark for Bank1 (FLASH_SECWM1R_PRG) . .348
7.11.35FLASH write sector group protection for Bank1
(FLASH_WRP1R_CUR) . . . . .		349
7.11.36FLASH write sector group protection for Bank1
(FLASH_WRP1R_PRG) . . . . .		349
7.11.37FLASH data sector configuration Bank1 (FLASH_EDATA1R_CUR) . .350
7.11.38FLASH data sector configuration Bank1 (FLASH_EDATA1R_PRG) . .351
7.11.39FLASH HDP Bank1 configuration (FLASH_HDP1R_CUR) . . . . .351
7.11.40FLASH HDP Bank1 configuration (FLASH_HDP1R_PRG) . . . . .352
7.11.41FLASH ECC correction register (FLASH_ECCCORR) . . . . .352
7.11.42FLASH ECC detection register (FLASH_ECCDETR) . . . . .353
7.11.43FLASH ECC data (FLASH_ECCDR) . . . . .354
7.11.44FLASH secure block-based register for Bank2 (FLASH_SECB2Rx)355
7.11.45FLASH privilege block-based register for Bank2
(FLASH_PRIVBB2Rx) . . . . .		355
7.11.46FLASH security watermark for Bank2 (FLASH_SECWM2R_CUR) . .356
7.11.47FLASH security watermark for Bank2 (FLASH_SECWM2R_PRG) . .356
7.11.48FLASH write sector group protection for Bank2
(FLASH_WRP2R_CUR) . . . . .		357
7.11.49FLASH write sector group protection for Bank2
(FLASH_WRP2R_PRG) . . . . .		358
7.11.50FLASH data sectors configuration Bank2 (FLASH_EDATA2R_CUR) .358
7.11.51FLASH data sector configuration Bank2 (FLASH_EDATA2R_PRG) . .359
7.11.52FLASH HDP Bank2 configuration (FLASH_HDP2R_CUR) . . . . .359
7.11.53FLASH HDP Bank2 configuration (FLASH_HDP2R_PRG) . . . . .360
7.12FLASH register map and reset values . . . . .361
8Instruction cache (ICACHE) . . . . .366
8.1ICACHE introduction . . . . .366
8.2ICACHE main features . . . . .366
8.3ICACHE implementation . . . . .367
8.4ICACHE functional description . . . . .367
8.4.1ICACHE block diagram . . . . .368
8.4.2ICACHE reset and clocks . . . . .368
8.4.3ICACHE TAG memory . . . . .369
8.4.4Direct-mapped ICACHE (1-way cache) . . . . .370
8.4.5ICACHE enable . . . . .371
8.4.6Cacheable and noncacheable traffic . . . . .371
8.4.7Address remapping . . . . .372
8.4.8Cacheable accesses . . . . .374
8.4.9Dual-master cache . . . . .375
8.4.10ICACHE security . . . . .375
8.4.11ICACHE maintenance . . . . .375
8.4.12ICACHE performance monitoring . . . . .376
8.4.13ICACHE boot . . . . .376
8.5ICACHE low-power modes . . . . .376
8.6ICACHE error management and interrupts . . . . .377
8.7ICACHE registers . . . . .377
8.7.1ICACHE control register (ICACHE_CR) . . . . .377
8.7.2ICACHE status register (ICACHE_SR) . . . . .378
8.7.3ICACHE interrupt enable register (ICACHE_IER) . . . . .379
8.7.4ICACHE flag clear register (ICACHE_FCR) . . . . .379
8.7.5ICACHE hit monitor register (ICACHE_HMONR) . . . . .380
8.7.6ICACHE miss monitor register (ICACHE_MMONR) . . . . .380
8.7.7ICACHE region x configuration register (ICACHE_CRRx) . . . . .380
8.7.8ICACHE register map . . . . .382
9Data cache (DCACHE) . . . . .383
9.1DCACHE introduction . . . . .383
9.2DCACHE main features . . . . .383
9.3DCACHE implementation . . . . .384
9.4DCACHE functional description . . . . .384
9.4.1DCACHE block diagram . . . . .385
9.4.2DCACHE reset and clocks . . . . .385
9.4.3DCACHE TAG memory . . . . .386
9.4.4DCACHE enable . . . . .388
9.4.5Cacheable and noncacheable traffic . . . . .388
9.4.6Cacheable accesses . . . . .389
9.4.7DCACHE security . . . . .391
9.4.8DCACHE maintenance . . . . .391
9.4.9DCACHE performance monitoring . . . . .393
9.4.10DCACHE boot . . . . .393
9.5DCACHE low-power modes . . . . .394
9.6DCACHE error management and interrupts . . . . .394
9.7DCACHE registers . . . . .395
9.7.1DCACHE control register (DCACHE_CR) . . . . .395
9.7.2DCACHE status register (DCACHE_SR) . . . . .396
9.7.3DCACHE interrupt enable register (DCACHE_IER) . . . . .397
9.7.4DCACHE flag clear register (DCACHE_FCR) . . . . .398
9.7.5DCACHE read-hit monitor register (DCACHE_RHMONR) . . . . .398
9.7.6DCACHE read-miss monitor register (DCACHE_RMMONR) . . . . .399
9.7.7DCACHE write-hit monitor register (DCACHE_WHMONR) . . . . .399
9.7.8DCACHE write-miss monitor register (DCACHE_WMMONR) . . . . .399
9.7.9DCACHE command range start address register
(DCACHE_CMDRSADRR) . . . . .		400
9.7.10DCACHE command range end address register
(DCACHE_CMDREADRR) . . . . .		400
9.7.11DCACHE register map . . . . .400
10Power control (PWR) . . . . .402
10.1Introduction . . . . .402
10.2PWR main features . . . . .402
10.3PWR pins and internal signals . . . . .403
10.4PWR power supplies and supply domains . . . . .404
10.4.1External power supplies . . . . .405
10.4.2Internal regulators . . . . .406
10.4.3Power-up and power-down power sequences . . . . .408
10.4.4Independent analog peripherals supply . . . . .408
10.4.5Independent I/O supply rail . . . . .409
10.4.6Independent USB transceivers supply . . . . .409
10.4.7Backup domain . . . . .409
10.5PWR system supply voltage regulation . . . . .411
10.5.1SMPS and LDO embedded regulators . . . . .411
10.5.2V CORE supply versus reset, voltage scaling, and low-power modes . . . . .411
10.5.3Embedded voltage regulator operating modes . . . . .411
10.6PWR power supply and temperature supervision . . . . .412
10.6.1Power-on reset (POR)/power-down reset (PDR) . . . . .412
10.6.2Brownout reset (BOR) . . . . .413
10.6.3Programmable voltage detector (PVD) . . . . .414
10.6.4Analog voltage detector (AVD) . . . . .414
10.6.5VDDIO2 voltage monitor (IO2VM) . . . . .415
10.6.6Backup domain voltage monitoring . . . . .415
10.6.7Temperature monitoring . . . . .416
10.7PWR management . . . . .417
10.7.1Voltage scaling . . . . .417
10.7.2Power management examples . . . . .418
10.8Power modes . . . . .419
10.8.1Slowing down system clocks . . . . .423
10.8.2Peripheral clock gating . . . . .423
10.8.3Low-power modes . . . . .423
10.8.4Sleep mode . . . . .424
10.8.5Stop mode . . . . .425
10.8.6Standby mode . . . . .427
10.8.7Power modes output pins . . . . .430
10.9PWR security and privileged protection . . . . .431
10.9.1PWR security protection . . . . .431
10.9.2PWR privileged protection . . . . .432
10.10PWR interrupts . . . . .433
10.11PWR registers . . . . .434
10.11.1PWR power mode control register (PWR_PMCR) . . . . .434
10.11.2PWR power mode control register [alternate] (PWR_PMCR) . . . . .436
10.11.3PWR status register (PWR_PMSR) . . . . .437
10.11.4PWR voltage scaling control register (PWR_VOSCR) . . . . .438
10.11.5PWR voltage scaling status register (PWR_VOSSR) . . . . .439
10.11.6PWR Backup domain control register (PWR_BDCR) . . . . .439
10.11.7PWR Backup domain control register (PWR_DBPCR) . . . . .441
10.11.8PWR Backup domain status register (PWR_BDSR) . . . . .441
10.11.9PWR USB Type-C power delivery register (PWR_UCPDR) . . . . .442
10.11.10PWR supply configuration control register (PWR_SCCR) . . . . .442
10.11.11PWR voltage monitor control register (PWR_VMCR) . . . . .443
10.11.12PWR USB supply control register (PWR_USBSCR) . . . . .444
10.11.13PWR voltage monitor status register (PWR_VMSR) . . . . .445
10.11.14PWR wake-up status clear register (PWR_WUSCR) . . . . .446
10.11.15PWR wake-up status register (PWR_WUSR) . . . . .446
10.11.16PWR wake-up configuration register (PWR_WUCR) . . . . .447
10.11.17PWR I/O retention register (PWR_IORETR) . . . . .447
10.11.18PWR security configuration register (PWR_SECCFGR) . . . . .448
10.11.19PWR privilege configuration register (PWR_PRIVCFGR) . . . . .449
10.11.20PWR register map . . . . .450
11Reset and clock control (RCC) . . . . .452
11.1Introduction . . . . .452
11.2RCC pins and internal signals . . . . .452
11.3RCC reset functional description . . . . .452
11.3.1Power reset . . . . .452
11.3.2System reset . . . . .453
11.3.3Backup domain reset . . . . .454
11.3.4Reset source identification . . . . .454
11.4RCC clocks functional description . . . . .455
11.4.1HSE clock . . . . .457
11.4.2HSI clock . . . . .458
11.4.3CSI oscillator . . . . .459
11.4.4HSI48 clock . . . . .460
11.4.5PLL description . . . . .460
11.4.6LSE clock . . . . .464
11.4.7LSI clock . . . . .465
11.4.8System clock (SYSCLK) selection . . . . .465
11.4.9Handling clock generators in stop and standby modes . . . . .466
11.4.10Clock security system (CSS) . . . . .467
11.4.11Clock output generation (MCO1/MCO2) . . . . .468
11.4.12Kernel clock selection . . . . .468
11.4.13RTC and TAMP clock . . . . .472
11.4.14Timer clock . . . . .473
11.4.15Watchdog clock . . . . .473
11.4.16Peripherals clock gating and autonomous mode . . . . .473
11.5RCC security and privilege functional description . . . . .474
11.5.1RCC TrustZone security protection modes . . . . .474
11.5.2RCC privilege protection modes . . . . .477
11.6RCC low-power modes . . . . .477
11.7RCC interrupts . . . . .479
11.8RCC registers . . . . .481
11.8.1RCC clock control register (RCC_CR) . . . . .481
11.8.2RCC HSI calibration register (RCC_HSICFGR) . . . . .484
11.8.3RCC clock recovery RC register (RCC_CRRRCR) . . . . .484
11.8.4RCC CSI calibration register (RCC_CSICFGR) . . . . .485
11.8.5RCC clock configuration register1 (RCC_CFGR1) . . . . .485
11.8.6RCC CPU domain clock configuration register 2 (RCC_CFGR2) . . . . .488
11.8.7RCC PLL clock source selection register (RCC_PLL1CFGR) . . . . .490
11.8.8RCC PLL clock source selection register (RCC_PLL2CFGR) . . . . .492
11.8.9RCC PLL clock source selection register (RCC_PLL3CFGR) . . . . .494
11.8.10RCC PLL1 dividers register (RCC_PLL1DIVR) . . . . .495
11.8.11RCC PLL1 fractional divider register (RCC_PLL1FRACR) . . . . .497
11.8.12RCC PLL1 dividers register (RCC_PLL2DIVR) . . . . .497
11.8.13RCC PLL2 fractional divider register (RCC_PLL2FRACR) . . . . .498
11.8.14RCC PLL3 dividers register (RCC_PLL3DIVR) . . . . .499
11.8.15RCC PLL3 fractional divider register (RCC_PLL3FRACR) . . . . .500
11.8.16RCC clock source interrupt enable register (RCC_CIER) . . . . .501
11.8.17RCC clock source interrupt flag register (RCC_CIFR) . . . . .502
11.8.18RCC clock source interrupt clear register (RCC_CICR) . . . . .504
11.8.19RCC AHB1 reset register (RCC_AHB1RSTR) . . . . .505
11.8.20RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .506
11.8.21RCC AHB4 peripheral reset register (RCC_AHB4RSTR) . . . . .508
11.8.22RCC APB1 peripheral low reset register (RCC_APB1LRSTR) . . . . .509
11.8.23RCC APB1 peripheral high reset register (RCC_APB1HRSTR) . . . . .512
11.8.24RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .513
11.8.25RCC APB3 peripheral reset register (RCC_APB3RSTR) . . . . .515
11.8.26RCC AHB1 peripherals clock register (RCC_AHB1ENR) . . . . .516
11.8.27RCC AHB2 peripheral clock register (RCC_AHB2ENR) . . . . .518
11.8.28RCC AHB4 peripheral clock register (RCC_AHB4ENR) . . . . .520
11.8.29RCC APB1 peripheral clock register (RCC_APB1LENR) . . . . .521
11.8.30RCC APB1 peripheral clock register (RCC_APB1HENR) . . . . .524
11.8.31RCC APB2 peripheral clock register (RCC_APB2ENR) . . . . .525
11.8.32RCC APB3 peripheral clock register (RCC_APB3ENR) . . . . .526
11.8.33RCC AHB1 sleep clock register (RCC_AHB1LPENR) . . . . .528
11.8.34RCC AHB2 sleep clock register (RCC_AHB2LPENR) . . . . .530
11.8.35RCC AHB4 sleep clock register (RCC_AHB4LPENR) . . . . .532
11.8.36RCC APB1 sleep clock register (RCC_APB1LLPENR) . . . . .533
11.8.37RCC APB1 sleep clock register (RCC_APB1HLPENR) . . . . .536
11.8.38RCC APB2 sleep clock register (RCC_APB2LPENR) . . . . .537
11.8.39RCC APB3 sleep clock register (RCC_APB3LPENR) . . . . .539
11.8.40RCC kernel clock configuration register (RCC_CCIPR1) . . . . .541
11.8.41RCC kernel clock configuration register (RCC_CCIPR2) . . . . .543
11.8.42RCC kernel clock configuration register (RCC_CCIPR3) . . . . .546
11.8.43RCC kernel clock configuration register (RCC_CCIPR4) . . . . .547
11.8.44RCC kernel clock configuration register (RCC_CCIPR5) . . . . .549
11.8.45RCC Backup domain control register (RCC_BDCR) . . . . .551
11.8.46RCC reset status register (RCC_RSR) . . . . .553
11.8.47RCC secure configuration register (RCC_SECCFGR) . . . . .554
11.8.48RCC privilege configuration register (RCC_PRIVCFGR) . . . . .556
11.9RCC register map . . . . .557
12Clock recovery system (CRS) . . . . .563
12.1CRS introduction . . . . .563
12.2CRS main features . . . . .563
12.3CRS implementation . . . . .563
12.4CRS functional description . . . . .564
12.4.1CRS block diagram . . . . .564
12.4.2CRS internal signals . . . . .564
12.4.3Synchronization input . . . . .565
12.4.4Frequency error measurement . . . . .565
12.4.5Frequency error evaluation and automatic trimming . . . . .566
12.4.6CRS initialization and configuration . . . . .567
12.5CRS in low-power modes . . . . .568
12.6CRS interrupts . . . . .568
12.7CRS registers . . . . .568
12.7.1CRS control register (CRS_CR) . . . . .568
12.7.2CRS configuration register (CRS_CFGR) . . . . .570
12.7.3CRS interrupt and status register (CRS_ISR) . . . . .571
12.7.4CRS interrupt flag clear register (CRS_ICR) . . . . .573
12.7.5CRS register map . . . . .573
13General-purpose I/Os (GPIO) . . . . .575
13.1Introduction . . . . .575
13.2GPIO main features . . . . .575
13.3GPIO functional description . . . . .575
13.3.1General-purpose I/O (GPIO) . . . . .577
13.3.2I/O pin alternate function multiplexer and mapping . . . . .578
13.3.3I/O port control registers . . . . .578
13.3.4I/O port data registers . . . . .579
13.3.5I/O data bitwise handling . . . . .579
13.3.6GPIO locking mechanism . . . . .579
13.3.7I/O alternate function input/output . . . . .579
13.3.8External interrupt/wake-up lines . . . . .580
13.3.9Input configuration . . . . .580
13.3.10Output configuration . . . . .581
13.3.11Alternate function configuration . . . . .581
13.3.12Analog configuration . . . . .582
13.3.13Using the HSE or LSE oscillator pins as GPIOs . . . . .582
13.3.14Using the GPIO pins in the RTC supply domain . . . . .583
13.3.15I/Os state retention during standby mode . . . . .583
13.3.16TrustZone security . . . . .583
13.3.17Privileged and unprivileged modes . . . . .584
13.3.18High-speed low-voltage mode (HSLV) . . . . .584
13.3.19I/O compensation cell . . . . .585
13.4GPIO registers . . . . .586
13.4.1GPIO port mode register (GPIOx_MODER) (x = A to I) . . . . .586
13.4.2GPIO port output type register (GPIOx_OTYPER) (x = A to I) . . . . .586
13.4.3GPIO port output speed register (GPIOx_OSPEEDR) (x = A to I) . . . . .587
13.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to I) . . . . .587
13.4.5GPIO port input data register (GPIOx_IDR) (x = A to I) . . . . .588
13.4.6GPIO port output data register (GPIOx_ODR) (x = A to I) . . . . .588
13.4.7GPIO port bit set/reset register (GPIOx_BSRR) (x = A to I) . . . . .589
13.4.8GPIO port configuration lock register (GPIOx_LCKR) (x = A to I) . . . . .589
13.4.9GPIO alternate function low register (GPIOx_AFRL) (x = A to I) . . . . .590
13.4.10GPIO alternate function high register (GPIOx_AFRH) (x = A to H) . . . . .591
13.4.11GPIO port bit reset register (GPIOx_BRR) (x = A to I) . . . . .592
13.4.12GPIO high-speed low-voltage register (GPIOx_HSLVR) (x = A to I) . . . . .592
13.4.13GPIO secure configuration register (GPIOx_SECCFGR) (x = A to I) . . . . .593
13.4.14GPIO register map . . . . .594
14System configuration, boot, and security (SBS) . . . . .596
14.1SBS introduction . . . . .596
14.2SBS main features . . . . .596
14.3SBS functional description . . . . .597
14.3.1SBS block diagram . . . . .597
14.3.2SBS signals . . . . .598
14.3.3SBS reset and clocks . . . . .598
14.3.4SBS system configuration . . . . .599
14.3.5SBS boot control . . . . .600
14.3.6SBS debug control . . . . .603
14.3.7SBS hardware secure storage control . . . . .605
14.4SBS interrupts . . . . .607
14.5SBS registers . . . . .607
14.5.1SBS temporal isolation control register (SBS_HDPLCR) . . . . .607
14.5.2SBS temporal isolation status register (SBS_HDPLSR) . . . . .607
14.5.3SBS next HDPL control register (SBS_NEXTHDPLCR) . . . . .608
14.5.4SBS debug control register (SBS_DBGCR) . . . . .608
14.5.5SBS debug lock register (SBS_DBGLOCKR) . . . . .609
14.5.6SBS RSS command register (SBS_RSSCMDR) . . . . .610
14.5.7SBS EPOCH selection control register (SBS_EPOCHSELCCR) . . . . .610
14.5.8SBS security mode configuration control register (SBS_SECCFGR) . . . . .611
14.5.9SBS product mode and configuration register (SBS_PMCR) . . . . .611
14.5.10SBS FPU interrupt mask register (SBS_FPUIMR) . . . . .613
14.5.11SBS memory erase status register (SBS_MESR) . . . . .613
14.5.12SBS compensation cell for I/Os control and status register
(SBS_CCCSR) . . . . .		614
14.5.13SBS compensation cell for I/Os value register (SBS_CCVALR) . . . . .615
14.5.14SBS compensation cell for I/Os software code register
(SBS_CCSWCR) . . . . .		616
14.5.15SBS Class B register (SBS_CFGR2) . . . . .616
14.5.16SBS CPU nonsecure lock register (SBS_CNSLCKR) . . . . .617
14.5.17SBS CPU secure lock register (SBS_CSLCKR) . . . . .618
14.5.18SBS fiift ECC NMI mask register (SBS_ECCNMIR) . . . . .619
14.5.19SBS register map . . . . .620
15Peripherals interconnect matrix . . . . .622
15.1Interconnect matrix introduction . . . . .622
16.4.7GPDMA channel state and linked-list programming in run-to-completion mode . . . . .648
16.4.8GPDMA channel state and linked-list programming in link step mode651
16.4.9GPDMA channel state and linked-list programming . . . . .658
16.4.10GPDMA FIFO-based transfers . . . . .660
16.4.11GPDMA transfer request and arbitration . . . . .667
16.4.12GPDMA triggered transfer . . . . .671
16.4.13GPDMA circular buffering with linked-list programming . . . . .672
16.4.14GPDMA transfer in peripheral flow-control mode . . . . .674
16.4.15GPDMA secure/nonsecure channel . . . . .675
16.4.16GPDMA privileged/unprivileged channel . . . . .676
16.4.17GPDMA error management . . . . .676
16.5GPDMA in debug mode . . . . .678
16.6GPDMA in low-power modes . . . . .678
16.7GPDMA interrupts . . . . .679
16.8GPDMA registers . . . . .680
16.8.1GPDMA secure configuration register (GPDMA_SECCFGR) . . . . .680
16.8.2GPDMA privileged configuration register (GPDMA_PRIVCFGR) . . . . .681
16.8.3GPDMA configuration lock register (GPDMA_RCFGLOCKR) . . . . .681
16.8.4GPDMA nonsecure masked interrupt status register (GPDMA_MISR) . . . . .682
16.8.5GPDMA secure masked interrupt status register (GPDMA_SMISR) . . . . .683
16.8.6GPDMA channel x linked-list base address register (GPDMA_CxLBAR) . . . . .683
16.8.7GPDMA channel x flag clear register (GPDMA_CxFCR) . . . . .684
16.8.8GPDMA channel x status register (GPDMA_CxSR) . . . . .685
16.8.9GPDMA channel x control register (GPDMA_CxCR) . . . . .686
16.8.10GPDMA channel x transfer register 1 (GPDMA_CxTR1) . . . . .688
16.8.11GPDMA channel x transfer register 2 (GPDMA_CxTR2) . . . . .692
16.8.12GPDMA channel x block register 1 (GPDMA_CxBR1) . . . . .696
16.8.13GPDMA channel x alternate block register 1 (GPDMA_CxBR1) . . . . .697
16.8.14GPDMA channel x source address register (GPDMA_CxSAR) . . . . .700
16.8.15GPDMA channel x destination address register (GPDMA_CxDAR) . . . . .702
16.8.16GPDMA channel x transfer register 3 (GPDMA_CxTR3) . . . . .703
16.8.17GPDMA channel x block register 2 (GPDMA_CxBR2) . . . . .704
16.8.18GPDMA channel x linked-list address register (GPDMA_CxLLR) . . . . .705
16.8.19GPDMA channel x alternate linked-list address register (GPDMA_CxLLR) . . . . .707
16.8.20GPDMA register map . . . . .708
17Nested vectored interrupt controller (NVIC) . . . . .711
17.1NVIC main features . . . . .711
17.2SysTick calibration value register . . . . .711
17.3Interrupt and exception vectors . . . . .712
18Extended interrupts and event controller (EXTI) . . . . .722
18.1EXTI main features . . . . .722
18.2EXTI block diagram . . . . .722
18.2.1EXTI connections between peripherals and CPU . . . . .724
18.2.2EXTI interrupt/event mapping . . . . .724
18.3EXTI functional description . . . . .726
18.3.1EXTI configurable event input wake-up . . . . .726
18.3.2EXTI direct event input wake-up . . . . .727
18.3.3EXTI mux selection . . . . .728
18.4EXTI functional behavior . . . . .728
18.5EXTI event protection . . . . .729
18.5.1EXTI security protection . . . . .729
18.5.2EXTI privilege protection . . . . .730
18.6EXTI registers . . . . .731
18.6.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .731
18.6.2EXTI falling trigger selection register (EXTI_FTSR1) . . . . .731
18.6.3EXTI software interrupt event register (EXTI_SWIER1) . . . . .732
18.6.4EXTI rising edge pending register (EXTI_RPR1) . . . . .733
18.6.5EXTI falling edge pending register (EXTI_FPR1) . . . . .733
18.6.6EXTI security configuration register (EXTI_SECCFGR1) . . . . .734
18.6.7EXTI privilege configuration register (EXTI_PRIVCFGR1) . . . . .735
18.6.8EXTI rising trigger selection register 2 (EXTI_RTSR2) . . . . .735
18.6.9EXTI falling trigger selection register 2 (EXTI_FTSR2) . . . . .736
18.6.10EXTI software interrupt event register 2 (EXTI_SWIER2) . . . . .737
18.6.11EXTI rising edge pending register 2 (EXTI_RPR2) . . . . .739
18.6.12EXTI falling edge pending register 2 (EXTI_FPR2) . . . . .740
18.6.13EXTI security configuration register 2 (EXTI_SECCFGR2) . . . . .741
18.6.14EXTI privilege configuration register 2 (EXTI_PRIVCFGR2) . . . . .742
18.6.15EXTI external interrupt selection register (EXTI_EXTICR1) . . . . .742
18.6.16EXTI external interrupt selection register (EXTI_EXTICR2) . . . . .744
18.6.17EXTI external interrupt selection register (EXTI_EXTICR3) . . . . .746
18.6.18EXTI external interrupt selection register (EXTI_EXTICR4) . . . . .748
18.6.19EXTI lock register (EXTI_LOCKR) . . . . .750
18.6.20EXTI CPU wake-up with interrupt mask register (EXTI_IMR1) . . . . .751
18.6.21EXTI CPU wake-up with event mask register (EXTI_EM1) . . . . .751
18.6.22EXTI CPU wake-up with interrupt mask register 2 (EXTI_IMR2) . . . . .752
18.6.23EXTI CPU wake-up with event mask register 2 (EXTI_EM2) . . . . .753
18.6.24EXTI register map . . . . .754
19Cyclic redundancy check calculation unit (CRC) . . . . .756
19.1CRC introduction . . . . .756
19.2CRC main features . . . . .756
19.3CRC functional description . . . . .757
19.3.1CRC block diagram . . . . .757
19.3.2CRC internal signals . . . . .757
19.3.3CRC operation . . . . .757
19.4CRC registers . . . . .759
19.4.1CRC data register (CRC_DR) . . . . .759
19.4.2CRC independent data register (CRC_IDR) . . . . .759
19.4.3CRC control register (CRC_CR) . . . . .760
19.4.4CRC initial value (CRC_INIT) . . . . .761
19.4.5CRC polynomial (CRC_POL) . . . . .761
19.4.6CRC register map . . . . .762
20CORDIC coprocessor (CORDIC) . . . . .763
20.1CORDIC introduction . . . . .763
20.2CORDIC main features . . . . .763
20.3CORDIC functional description . . . . .763
20.3.1General description . . . . .763
20.3.2CORDIC functions . . . . .764
20.3.3Fixed point representation . . . . .770
20.3.4Scaling factor . . . . .771
20.3.5Precision . . . . .771
20.3.6Zero-overhead mode . . . . .774
20.3.7Polling mode . . . . .775
20.3.8Interrupt mode . . . . .776
20.3.9DMA mode . . . . .776
20.4CORDIC registers . . . . .777
20.4.1CORDIC control/status register (CORDIC_CSR) . . . . .777
20.4.2CORDIC argument register (CORDIC_WDATA) . . . . .779
20.4.3CORDIC result register (CORDIC_RDATA) . . . . .780
20.4.4CORDIC register map . . . . .780
21Filter math accelerator (FMAC) . . . . .781
21.1FMAC introduction . . . . .781
21.2FMAC main features . . . . .781
21.3FMAC functional description . . . . .782
21.3.1General description . . . . .782
21.3.2Local memory and buffers . . . . .783
21.3.3Input buffers . . . . .783
21.3.4Output buffer . . . . .786
21.3.5Initialization functions . . . . .788
21.3.6Filter functions . . . . .789
21.3.7Fixed point representation . . . . .793
21.3.8Implementing FIR filters with the FMAC . . . . .793
21.3.9Implementing IIR filters with the FMAC . . . . .795
21.3.10Examples of filter initialization . . . . .797
21.3.11Examples of filter operation . . . . .798
21.3.12Filter design tips . . . . .800
21.4FMAC registers . . . . .801
21.4.1FMAC X1 buffer configuration register (FMAC_X1BUFCFG) . . . . .801
21.4.2FMAC X2 buffer configuration register (FMAC_X2BUFCFG) . . . . .801
21.4.3FMAC Y buffer configuration register (FMAC_YBUFCFG) . . . . .802
21.4.4FMAC parameter register (FMAC_PARAM) . . . . .803
21.4.5FMAC control register (FMAC_CR) . . . . .804
21.4.6FMAC status register (FMAC_SR) . . . . .805
21.4.7FMAC write data register (FMAC_WDATA) . . . . .806
21.4.8FMAC read data register (FMAC_RDATA) . . . . .807
21.4.9FMAC register map . . . . .807
22Flexible memory controller (FMC) . . . . .809
22.1Introduction . . . . .809
22.2FMC main features . . . . .809
22.3FMC block diagram . . . . .810
22.4AHB interface . . . . .811
22.4.1Supported memories and transactions . . . . .812
22.5External device address mapping . . . . .813
22.5.1NOR/PSRAM address mapping . . . . .814
22.5.2NAND flash memory address mapping . . . . .814
22.5.3SDRAM address mapping . . . . .815
22.6NOR flash/PSRAM controller . . . . .817
22.6.1External memory interface signals . . . . .819
22.6.2Supported memories and transactions . . . . .821
22.6.3General timing rules . . . . .822
22.6.4NOR flash/PSRAM controller asynchronous transactions . . . . .822
22.6.5Synchronous transactions . . . . .840
22.6.6NOR/PSRAM controller registers . . . . .847
22.7NAND flash controller . . . . .855
22.7.1External memory interface signals . . . . .855
22.7.2NAND flash supported memories and transactions . . . . .856
22.7.3Timing diagrams for NAND flash memory . . . . .857
22.7.4NAND flash operations . . . . .858
22.7.5NAND flash prewait functionality . . . . .858
22.7.6Computation of the error correction code (ECC)
in NAND flash memory . . . . .		859
22.7.7NAND flash controller registers . . . . .860
22.8SDRAM controller . . . . .866
22.8.1SDRAM controller main features . . . . .866
22.8.2SDRAM External memory interface signals . . . . .866
22.8.3SDRAM controller functional description . . . . .867
22.8.4Low-power modes . . . . .873
22.8.5SDRAM controller registers . . . . .876
22.8.6FMC register map . . . . .882
23Octo-SPI interface (OCTOSPI) . . . . .885
23.1OCTOSPI introduction . . . . .885
23.2OCTOSPI main features . . . . .885
23.3OCTOSPI implementation . . . . .886
23.4OCTOSPI functional description . . . . .887
23.4.1OCTOSPI block diagram . . . . .887
23.4.2OCTOSPI pins and internal signals . . . . .888
23.4.3OCTOSPI interface to memory modes . . . . .889
23.4.4OCTOSPI regular-command protocol . . . . .889
23.4.5OCTOSPI regular-command protocol signal interface . . . . .893
23.4.6HyperBus protocol . . . . .896
23.4.7Specific features . . . . .900
23.4.8OCTOSPI operating mode introduction . . . . .901
23.4.9OCTOSPI indirect mode . . . . .901
23.4.10OCTOSPI automatic status-polling mode . . . . .903
23.4.11OCTOSPI memory-mapped mode . . . . .904
23.4.12OCTOSPI configuration introduction . . . . .905
23.4.13OCTOSPI system configuration . . . . .905
23.4.14OCTOSPI device configuration . . . . .905
23.4.15OCTOSPI regular-command mode configuration . . . . .908
23.4.16OCTOSPI HyperBus protocol configuration . . . . .910
23.4.17OCTOSPI error management . . . . .911
23.4.18OCTOSPI BUSY and ABORT . . . . .911
23.4.19OCTOSPI reconfiguration or deactivation . . . . .912
23.4.20NCS behavior . . . . .912
23.5Address alignment and data number . . . . .914
23.6OCTOSPI interrupts . . . . .915
23.7OCTOSPI registers . . . . .915
23.7.1OCTOSPI control register (OCTOSPI_CR) . . . . .915
23.7.2OCTOSPI device configuration register 1 (OCTOSPI_DCR1) . . . . .918
23.7.3OCTOSPI device configuration register 2 (OCTOSPI_DCR2) . . . . .920
23.7.4OCTOSPI device configuration register 3 (OCTOSPI_DCR3) . . . . .921
23.7.5OCTOSPI device configuration register 4 (OCTOSPI_DCR4) . . . . .921
23.7.6OCTOSPI status register (OCTOSPI_SR) . . . . .922
23.7.7OCTOSPI flag clear register (OCTOSPI_FCR) . . . . .923
23.7.8OCTOSPI data length register (OCTOSPI_DLR) . . . . .923
23.7.9OCTOSPI address register (OCTOSPI_AR) . . . . .924
23.7.10OCTOSPI data register (OCTOSPI_DR) . . . . .924
23.7.11OCTOSPI polling status mask register (OCTOSPI_PSMKR) . . . . .925
23.7.12OCTOSPI polling status match register (OCTOSPI_PSMAR) . . . . .926
23.7.13OCTOSPI polling interval register (OCTOSPI_PIR) . . . . .926
23.7.14OCTOSPI communication configuration register (OCTOSPI_CCR) . .926
23.7.15OCTOSPI timing configuration register (OCTOSPI_TCR) . . . . .928
23.7.16OCTOSPI instruction register (OCTOSPI_IR) . . . . .929
23.7.17OCTOSPI alternate bytes register (OCTOSPI_ABR) . . . . .929
23.7.18OCTOSPI low-power timeout register (OCTOSPI_LPTR) . . . . .930
23.7.19OCTOSPI wrap communication configuration register
(OCTOSPI_WPCCR) . . . . .		930
23.7.20OCTOSPI wrap timing configuration register (OCTOSPI_WPTCR) . .932
23.7.21OCTOSPI wrap instruction register (OCTOSPI_WPIR) . . . . .933
23.7.22OCTOSPI wrap alternate bytes register (OCTOSPI_WPABR) . . . . .933
23.7.23OCTOSPI write communication configuration register
(OCTOSPI_WCCR) . . . . .		934
23.7.24OCTOSPI write timing configuration register (OCTOSPI_WTCR) . . . .936
23.7.25OCTOSPI write instruction register (OCTOSPI_WIR) . . . . .936
23.7.26OCTOSPI write alternate bytes register (OCTOSPI_WABR) . . . . .937
23.7.27OCTOSPI HyperBus latency configuration register
(OCTOSPI_HLCR) . . . . .		937
23.7.28OCTOSPI register map . . . . .938
24Secure digital input/output MultiMediaCard interface (SDMMC) . . .941
24.1SDMMC main features . . . . .941
24.2SDMMC implementation . . . . .941
24.3SDMMC bus topology . . . . .942
24.4SDMMC operation modes . . . . .944
24.5SDMMC functional description . . . . .945
24.5.1SDMMC block diagram . . . . .945
24.5.2SDMMC pins and internal signals . . . . .945
24.5.3General description . . . . .946
24.5.4SDMMC adapter . . . . .948
24.5.5SDMMC AHB slave interface . . . . .970
24.5.6SDMMC AHB master interface . . . . .971
24.5.7AHB and SDMMC_CK clock relation . . . . .974
24.6Card functional description . . . . .974
24.6.1SD I/O mode . . . . .974
24.6.2CMD12 send timing . . . . .982
24.6.3Sleep (CMD5) . . . . .986
24.6.4Interrupt mode (Wait-IRQ) . . . . .987
24.6.5Boot operation . . . . .988
24.6.6Response R1b handling . . . . .991
24.6.7Reset and card cycle power . . . . .992
24.7Hardware flow control . . . . .993
24.8Ultra-high-speed phase I (UHS-I) voltage switch . . . . .993
24.9SDMMC interrupts . . . . .996
24.10SDMMC registers . . . . .998
24.10.1SDMMC power control register (SDMMC_POWER) . . . . .998
24.10.2SDMMC clock control register (SDMMC_CLKCR) . . . . .999
24.10.3SDMMC argument register (SDMMC_ARGR) . . . . .1001
24.10.4SDMMC command register (SDMMC_CMDR) . . . . .1001
24.10.5SDMMC command response register (SDMMC_RESPCMDR) . . . . .1003
24.10.6SDMMC response x register (SDMMC_RESPxR) . . . . .1004
24.10.7SDMMC data timer register (SDMMC_TIMER) . . . . .1004
24.10.8SDMMC data length register (SDMMC_DLENR) . . . . .1005
24.10.9SDMMC data control register (SDMMC_DCTRL) . . . . .1006
24.10.10SDMMC data counter register (SDMMC_DCNTR) . . . . .1007
24.10.11SDMMC status register (SDMMC_STAR) . . . . .1008
24.10.12SDMMC interrupt clear register (SDMMC_ICR) . . . . .1011
24.10.13SDMMC mask register (SDMMC_MASKR) . . . . .1013
24.10.14SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . . . .1016
24.10.15SDMMC DMA control register (SDMMC_IDMACTRLR) . . . . .1016
24.10.16SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . .1017
24.10.17SDMMC IDMA buffer base address register
(SDMMC_IDMABASER) . . . . .		1018
24.10.18SDMMC IDMA linked list address register (SDMMC_IDMALAR) . . . . .1018
24.10.19SDMMC IDMA linked list memory base register
(SDMMC_IDMABAR) . . . . .		1019
24.10.20SDMMC data FIFO registers x (SDMMC_FIFORx) . . . . .1020
24.10.21SDMMC register map . . . . .1020
25Delay block (DLYB) . . . . .1023
25.1DLYB introduction . . . . .1023
25.2DLYB main features . . . . .1023
25.3DLYB implementation . . . . .1023
25.4DLYB functional description . . . . .1023
25.4.1DLYB diagram . . . . .1023
25.4.2DLYB pins and internal signals . . . . .1024
25.4.3General description . . . . .1024
25.4.4Delay line length configuration procedure . . . . .1025
25.4.5Output clock phase configuration procedure . . . . .1026
25.5DLYB registers . . . . .1026
25.5.1DLYB control register (DLYB_CR) . . . . .1026
25.5.2DLYB configuration register (DLYB_CFGR) . . . . .1027
25.5.3DLYB register map . . . . .1028
26Analog-to-digital converters (ADC1/2) . . . . .1029
26.1ADC introduction . . . . .1029
26.2ADC main features . . . . .1029
26.3ADC implementation . . . . .1031
26.4ADC functional description . . . . .1032
26.4.1ADC block diagram . . . . .1032
26.4.2ADC pins and internal signals . . . . .1033
26.4.3ADC clocks . . . . .1036
26.4.4ADC connectivity . . . . .1038
26.4.5Slave AHB interface . . . . .1040
26.4.6ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . . . . .1040
26.4.7Single-ended and differential input channels . . . . .1041
26.4.8Calibration (ADCAL, ADCALDIF, ADC_CALFACT) . . . . .1041
26.4.9ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .1044
26.4.10Constraints when writing the ADC control bits . . . . .1045
26.4.11Channel selection (ADC_SQRy, ADC_JSQR) . . . . .1046
26.4.12Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .1047
26.4.13Single conversion mode (CONT = 0) . . . . .1049
26.4.14Continuous conversion mode (CONT = 1) . . . . .1049
26.4.15Starting conversions (ADSTART, JADSTART) . . . . .1050
26.4.16ADC timing . . . . .1051
26.4.17Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .1052
26.4.18Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .1053
26.4.19Injected channel management . . . . .1055
26.4.20Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .1056
26.4.21Queue of context for injected conversions . . . . .1057
26.4.22Programmable resolution (RES) - fast conversion mode . . . . .1065
26.4.23End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . . . .1066
26.4.24End of conversion sequence (EOS, JEOS) . . . . .1066
26.4.25Timing diagrams example (single/continuous modes,
hardware/software triggers) . . . . .		1067
26.4.26Data management . . . . .1069
26.4.27Dynamic low-power features . . . . .1075
26.4.28Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,
AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . .		1080
26.4.29Oversampler . . . . .1084
26.4.30Dual ADC modes . . . . .1091
26.4.31Temperature sensor . . . . .1104
26.4.32VBAT supply monitoring . . . . .1106
26.4.33Monitoring the internal voltage reference . . . . .1107
26.4.34Monitoring the supply voltage . . . . .1108
26.5ADC interrupts . . . . .1109
26.6ADC registers (for each ADC) . . . . .1110
26.6.1ADC interrupt and status register (ADC_ISR) . . . . .1110
26.6.2ADC interrupt enable register (ADC_IER) . . . . .1112
26.6.3ADC control register (ADC_CR) . . . . .1114
26.6.4ADC configuration register (ADC_CFGR) . . . . .1117
26.6.5ADC configuration register 2 (ADC_CFGR2) . . . . .1122
26.6.6ADC sample time register 1 (ADC_SMPR1) . . . . .1124
26.6.7ADC sample time register 2 (ADC_SMPR2) . . . . .1125
26.6.8ADC watchdog threshold register 1 (ADC_TR1) . . . . .1126
26.6.9ADC watchdog threshold register 2 (ADC_TR2) . . . . .1127
26.6.10ADC watchdog threshold register 3 (ADC_TR3) . . . . .1128
26.6.11ADC regular sequence register 1 (ADC_SQR1) . . . . .1128
26.6.12ADC regular sequence register 2 (ADC_SQR2) . . . . .1129
26.6.13ADC regular sequence register 3 (ADC_SQR3) . . . . .1130
26.6.14ADC regular sequence register 4 (ADC_SQR4) . . . . .1131
26.6.15ADC regular data register (ADC_DR) . . . . .1132
26.6.16ADC injected sequence register (ADC_JSQR) . . . . .1132
26.6.17ADC offset y register (ADC_OFRy) . . . . .1135
26.6.18ADC injected channel y data register (ADC_JDRy) . . . . .1136
26.6.19ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .1137
26.6.20ADC analog watchdog 3 configuration register (ADC_AWD3CR) . . . . .1137
26.6.21ADC Differential mode selection register (ADC_DIFSEL) . . . . .1138
26.6.22ADC calibration factors (ADC_CALFACT) . . . . .1139
26.6.23ADC option register (ADC_OR) . . . . .1139
26.7ADC common registers . . . . .1140
26.7.1ADC common status register (ADC_CSR) . . . . .1140
26.7.2ADC common control register (ADC_CCR) . . . . .1142
26.7.3ADC common regular data register for dual mode (ADC_CDR) . . . . .1145
26.8ADC register map . . . . .1146
27Digital temperature sensor (DTS) . . . . .1150
27.1DTS introduction . . . . .1150
27.2DTS main features . . . . .1150
27.3DTS functional description . . . . .1151
27.3.1DTS block diagram . . . . .1151
27.3.2DTS internal signals . . . . .1151
27.3.3DTS block operation . . . . .1152
27.3.4Operating modes . . . . .1152
27.3.5Calibration . . . . .1152
27.3.6Prescaler . . . . .1152
27.3.7Temperature measurement principles . . . . .1153
27.3.8Sampling time . . . . .1154
27.3.9Quick measurement mode . . . . .1154
27.3.10Trigger input . . . . .1155
27.3.11On-off control and ready flag . . . . .1155
27.3.12Temperature measurement sequence . . . . .1156
27.4DTS low-power modes . . . . .1157
27.5DTS interrupts . . . . .1157
27.5.1Temperature window comparator . . . . .1157
27.5.2Synchronous interrupt . . . . .1157
27.5.3Asynchronous wakeup . . . . .1157
27.6DTS registers . . . . .1158
27.6.1Temperature sensor configuration register 1 (DTS_CFGR1) . . . . .1158
27.6.2Temperature sensor T0 value register 1 (DTS_T0VALR1) . . . . .1160
27.6.3Temperature sensor ramp value register (DTS_RAMPVALR) . . . . .1160
27.6.4Temperature sensor interrupt threshold register 1 (DTS_ITR1) . . . . .1161
27.6.5Temperature sensor data register (DTS_DR) . . . . .1161

28 Digital-to-analog converter (DAC) . . . . . 1167

28.7.5DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . .1193
28.7.6DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . .1194
28.7.7DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . .1194
28.7.8DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .1195
28.7.9Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .1195
28.7.10Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . .1196
28.7.11Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . .1196
28.7.12DAC channel1 data output register (DAC_DOR1) . . . . .1197
28.7.13DAC channel2 data output register (DAC_DOR2) . . . . .1197
28.7.14DAC status register (DAC_SR) . . . . .1198
28.7.15DAC calibration control register (DAC_CCR) . . . . .1199
28.7.16DAC mode control register (DAC_MCR) . . . . .1200
28.7.17DAC channel1 sample and hold sample time register (DAC_SHSR1) . . . . .1201
28.7.18DAC channel2 sample and hold sample time register (DAC_SHSR2) . . . . .1202
28.7.19DAC sample and hold time register (DAC_SHHR) . . . . .1202
28.7.20DAC sample and hold refresh time register (DAC_SHRR) . . . . .1203
28.7.21DAC register map . . . . .1204
29Voltage reference buffer (VREFBUF) . . . . .1207
29.1VREFBUF introduction . . . . .1207
29.2VREFBUF implementation . . . . .1207
29.3VREFBUF functional description . . . . .1207
29.4VREFBUF trimming . . . . .1208
29.5VREFBUF registers . . . . .1209
29.5.1VREFBUF control and status register (VREFBUF_CSR) . . . . .1209
29.5.2VREFBUF calibration control register (VREFBUF_CCR) . . . . .1210
29.5.3VREFBUF register map . . . . .1210
30Digital camera interface (DCMI) . . . . .1211
30.1DCMI introduction . . . . .1211
30.2DCMI main features . . . . .1211
30.3DCMI functional description . . . . .1211
30.3.1DCMI block diagram . . . . .1212
30.3.2DCMI pins and internal signals . . . . .1212
30.3.3DCMI clocks . . . . .1213
30.3.4DCMI DMA interface . . . . .1213
30.3.5DCMI physical interface . . . . .1213
30.3.6DCMI synchronization . . . . .1215
30.3.7DCMI capture modes . . . . .1217
30.3.8DCMI crop feature . . . . .1218
30.3.9DCMI JPEG format . . . . .1219
30.3.10DCMI FIFO . . . . .1219
30.3.11DCMI data format description . . . . .1220
30.4DCMI interrupts . . . . .1222
30.5DCMI registers . . . . .1222
30.5.1DCMI control register (DCMI_CR) . . . . .1222
30.5.2DCMI status register (DCMI_SR) . . . . .1225
30.5.3DCMI raw interrupt status register (DCMI_RIS) . . . . .1225
30.5.4DCMI interrupt enable register (DCMI_IER) . . . . .1226
30.5.5DCMI masked interrupt status register (DCMI_MIS) . . . . .1227
30.5.6DCMI interrupt clear register (DCMI_ICR) . . . . .1228
30.5.7DCMI embedded synchronization code register (DCMI_ESCR) . . . . .1229
30.5.8DCMI embedded synchronization unmask register (DCMI_ESUR) . . . . .1229
30.5.9DCMI crop window start (DCMI_CWSTRT) . . . . .1230
30.5.10DCMI crop window size (DCMI_CWSIZE) . . . . .1231
30.5.11DCMI data register (DCMI_DR) . . . . .1231
30.5.12DCMI register map . . . . .1232
31Parallel synchronous slave interface (PSSI) . . . . .1233
31.1PSSI introduction . . . . .1233
31.2PSSI main features . . . . .1233
31.3PSSI functional description . . . . .1233
31.3.1PSSI block diagram . . . . .1234
31.3.2PSSI pins and internal signals . . . . .1234
31.3.3PSSI clock . . . . .1235
31.3.4PSSI data management . . . . .1235
31.3.5PSSI optional control signals . . . . .1237
31.4PSSI interrupts . . . . .1240
31.5PSSI registers . . . . .1241
31.5.1PSSI control register (PSSI_CR) . . . . .1241
31.5.2PSSI status register (PSSI_SR) . . . . .1242
31.5.3PSSI raw interrupt status register (PSSI_RIS) . . . . .1243
31.5.4PSSI interrupt enable register (PSSI_IER) . . . . .1244
31.5.5PSSI masked interrupt status register (PSSI_MIS) . . . . .1244
31.5.6PSSI interrupt clear register (PSSI_ICR) . . . . .1245
31.5.7PSSI data register (PSSI_DR) . . . . .1245
31.5.8PSSI register map . . . . .1246
32True random number generator (RNG) . . . . .1247
32.1RNG introduction . . . . .1247
32.2RNG main features . . . . .1247
32.3RNG functional description . . . . .1248
32.3.1RNG block diagram . . . . .1248
32.3.2RNG internal signals . . . . .1248
32.3.3Random number generation . . . . .1248
32.3.4RNG initialization . . . . .1251
32.3.5RNG operation . . . . .1252
32.3.6RNG clocking . . . . .1254
32.3.7Error management . . . . .1254
32.3.8RNG low-power use . . . . .1255
32.4RNG interrupts . . . . .1256
32.5RNG processing time . . . . .1256
32.6RNG entropy source validation . . . . .1257
32.6.1Introduction . . . . .1257
32.6.2Validation conditions . . . . .1257
32.7RNG registers . . . . .1258
32.7.1RNG control register (RNG_CR) . . . . .1258
32.7.2RNG status register (RNG_SR) . . . . .1260
32.7.3RNG data register (RNG_DR) . . . . .1261
32.7.4RNG noise source control register (RNG_NSCR) . . . . .1262
32.7.5RNG health test control register (RNG_HTCR) . . . . .1263
32.7.6RNG register map . . . . .1263
33AES hardware accelerator (AES) . . . . .1264
33.1AES introduction . . . . .1264
33.2AES main features . . . . .1264
33.3AES implementation . . . . .1265
33.4AES functional description . . . . .1265
33.4.1AES block diagram . . . . .1265
33.4.2AES internal signals . . . . .1266
33.4.3AES reset and clocks . . . . .1266
33.4.4AES symmetric cipher implementation . . . . .1266
33.4.5AES encryption or decryption typical usage . . . . .1267
33.4.6AES authenticated encryption, decryption, and cipher-based message authentication . . . . .1270
33.4.7AES ciphertext stealing and data padding . . . . .1270
33.4.8AES suspend and resume operations . . . . .1271
33.4.9AES basic chaining modes (ECB, CBC) . . . . .1271
33.4.10AES counter (CTR) mode . . . . .1275
33.4.11AES Galois/counter mode (GCM) . . . . .1277
33.4.12AES Galois message authentication code (GMAC) . . . . .1282
33.4.13AES counter with CBC-MAC (CCM) . . . . .1283
33.4.14AES key sharing with secure AES co-processor . . . . .1288
33.4.15AES data registers and data swapping . . . . .1289
33.4.16AES key registers . . . . .1291
33.4.17AES initialization vector registers . . . . .1291
33.4.18AES error management . . . . .1292
33.5AES interrupts . . . . .1293
33.6AES DMA requests . . . . .1293
33.7AES processing latency . . . . .1294
33.8AES registers . . . . .1296
33.8.1AES control register (AES_CR) . . . . .1296
33.8.2AES status register (AES_SR) . . . . .1298
33.8.3AES data input register (AES_DINR) . . . . .1299
33.8.4AES data output register (AES_DOUTR) . . . . .1300
33.8.5AES key register 0 (AES_KEYR0) . . . . .1300
33.8.6AES key register 1 (AES_KEYR1) . . . . .1301
33.8.7AES key register 2 (AES_KEYR2) . . . . .1301
33.8.8AES key register 3 (AES_KEYR3) . . . . .1301
33.8.9AES initialization vector register 0 (AES_IVR0) . . . . .1302
33.8.10AES initialization vector register 1 (AES_IVR1) . . . . .1302
33.8.11AES initialization vector register 2 (AES_IVR2) . . . . .1302
33.8.12AES initialization vector register 3 (AES_IVR3) . . . . .1303
33.8.13AES key register 4 (AES_KEYR4) . . . . .1303
33.8.14AES key register 5 (AES_KEYR5) . . . . .1303
33.8.15AES key register 6 (AES_KEYR6) . . . . .1304
33.8.16AES key register 7 (AES_KEYR7) . . . . .1304
33.8.17AES suspend registers (AES_SUSPRx) . . . . .1304
33.8.18AES interrupt enable register (AES_IER) . . . . .1305
33.8.19AES interrupt status register (AES_ISR) . . . . .1306
33.8.20AES interrupt clear register (AES_ICR) . . . . .1307
33.8.21AES register map . . . . .1307
34Secure AES coprocessor (SAES) . . . . .1310
34.1SAES introduction . . . . .1310
34.2SAES main features . . . . .1310
34.3SAES implementation . . . . .1311
34.4SAES functional description . . . . .1311
34.4.1SAES block diagram . . . . .1311
34.4.2SAES internal signals . . . . .1312
34.4.3SAES reset and clocks . . . . .1313
34.4.4SAES symmetric cipher implementation . . . . .1313
34.4.5SAES encryption or decryption typical usage . . . . .1314
34.4.6SAES authenticated encryption, decryption, and cipher-based message authentication . . . . .1316
34.4.7SAES ciphertext stealing and data padding . . . . .1317
34.4.8SAES suspend and resume operations . . . . .1317
34.4.9SAES basic chaining modes (ECB, CBC) . . . . .1318
34.4.10SAES counter (CTR) mode . . . . .1322
34.4.11SAES Galois/counter mode (GCM) . . . . .1324
34.4.12SAES Galois message authentication code (GMAC) . . . . .1328
34.4.13SAES counter with CBC-MAC (CCM) . . . . .1330
34.4.14SAES operation with wrapped keys . . . . .1335
34.4.15SAES operation with shared keys . . . . .1339
34.4.16SAES data registers and data swapping . . . . .1340
34.4.17SAES key registers . . . . .1343
34.4.18SAES initialization vector registers . . . . .1344
34.4.19SAES error management . . . . .1345
34.5SAES interrupts . . . . .1347
34.6SAES DMA requests . . . . .1347
34.7SAES processing latency . . . . .1348
34.8SAES registers . . . . .1350
34.8.1SAES control register (SAES_CR) . . . . .1350
34.8.2SAES status register (SAES_SR) . . . . .1353
34.8.3SAES data input register (SAES_DINR) . . . . .1354
34.8.4SAES data output register (SAES_DOUTR) . . . . .1355
34.8.5SAES key register 0 (SAES_KEYR0) . . . . .1355
34.8.6SAES key register 1 (SAES_KEYR1) . . . . .1356
34.8.7SAES key register 2 (SAES_KEYR2) . . . . .1356
34.8.8SAES key register 3 (SAES_KEYR3) . . . . .1356
34.8.9SAES initialization vector register 0 (SAES_IVR0) . . . . .1357
34.8.10SAES initialization vector register 1 (SAES_IVR1) . . . . .1357
34.8.11SAES initialization vector register 2 (SAES_IVR2) . . . . .1357
34.8.12SAES initialization vector register 3 (SAES_IVR3) . . . . .1358
34.8.13SAES key register 4 (SAES_KEYR4) . . . . .1358
34.8.14SAES key register 5 (SAES_KEYR5) . . . . .1358
34.8.15SAES key register 6 (SAES_KEYR6) . . . . .1359
34.8.16SAES key register 7 (SAES_KEYR7) . . . . .1359
34.8.17SAES suspend registers (SAES_SUSPRx) . . . . .1359
34.8.18SAES interrupt enable register (SAES_IER) . . . . .1360
34.8.19SAES interrupt status register (SAES_ISR) . . . . .1361
34.8.20SAES interrupt clear register (SAES_ICR) . . . . .1362
34.8.21SAES register map . . . . .1363
35Hash processor (HASH) . . . . .1365
35.1HASH introduction . . . . .1365
35.2HASH main features . . . . .1365
35.3HASH implementation . . . . .1366
35.4HASH functional description . . . . .1366
35.4.1HASH block diagram . . . . .1366
35.4.2HASH internal signals . . . . .1366
35.4.3About secure hash algorithms . . . . .1367
35.4.4Message data feeding . . . . .1367
35.4.5Message digest computing . . . . .1368
35.4.6Message padding . . . . .1370
35.4.7HMAC operation . . . . .1371
35.4.8HASH suspend/resume operations . . . . .1373
35.4.9HASH DMA interface . . . . .1375
35.4.10HASH error management . . . . .1376
35.4.11HASH processing time . . . . .1376
35.5HASH interrupts . . . . .1377
35.6HASH registers . . . . .1377
35.6.1HASH control register (HASH_CR) . . . . .1377
35.6.2HASH data input register (HASH_DIN) . . . . .1379
35.6.3HASH start register (HASH_STR) . . . . .1380
35.6.4HASH digest registers . . . . .1381
35.6.5HASH interrupt enable register (HASH_IMR) . . . . .1383
35.6.6HASH status register (HASH_SR) . . . . .1383
35.6.7HASH context swap registers . . . . .1384
35.6.8HASH register map . . . . .1385
36Public key accelerator (PKA) . . . . .1387
36.1PKA introduction . . . . .1387
36.2PKA main features . . . . .1387
36.3PKA implementation . . . . .1387
36.4PKA functional description . . . . .1388
36.4.1PKA block diagram . . . . .1388
36.4.2PKA internal signals . . . . .1388
36.4.3PKA reset and clocks . . . . .1388
36.4.4PKA public key acceleration . . . . .1389
36.4.5Typical applications for PKA . . . . .1391
36.4.6PKA procedure to perform an operation . . . . .1393
36.4.7PKA error management . . . . .1394
36.5PKA operating modes . . . . .1395
36.5.1Introduction . . . . .1395
36.5.2Montgomery parameter computation . . . . .1396
36.5.3Modular addition . . . . .1396
36.5.4Modular subtraction . . . . .1397

37 On-the-fly decryption engine (OTFDEC) . . . . . 1420

37.3.6OTFDEC error management . . . . .1424
37.4OTFDEC interrupts . . . . .1425
37.5OTFDEC application information . . . . .1425
37.5.1OTFDEC initialization process . . . . .1425
37.5.2OTFDEC and power management . . . . .1427
37.5.3Encrypting for OTFDEC . . . . .1427
37.5.4OTFDEC key CRC source code . . . . .1428
37.6OTFDEC registers . . . . .1429
37.6.1OTFDEC control register (OTFDEC_CR) . . . . .1429
37.6.2OTFDEC privileged access control configuration register
(OTFDEC_PRIVCFGGR) . . . . .		1430
37.6.3OTFDEC region x configuration register (OTFDEC_RxCFGR) . . . . .1430
37.6.4OTFDEC region x start address register
(OTFDEC_RxSTARTADDR) . . . . .		1432
37.6.5OTFDEC region x end address register (OTFDEC_RxENDADDR) . . . . .1432
37.6.6OTFDEC region x nonce register 0 (OTFDEC_RxNONCER0) . . . . .1433
37.6.7OTFDEC region x nonce register 1 (OTFDEC_RxNONCER1) . . . . .1434
37.6.8OTFDEC region x key register 0 (OTFDEC_RxKEYR0) . . . . .1434
37.6.9OTFDEC region x key register 1 (OTFDEC_RxKEYR1) . . . . .1435
37.6.10OTFDEC region x key register 2 (OTFDEC_RxKEYR2) . . . . .1435
37.6.11OTFDEC region x key register 3 (OTFDEC_RxKEYR3) . . . . .1436
37.6.12OTFDEC interrupt status register (OTFDEC_ISR) . . . . .1436
37.6.13OTFDEC interrupt clear register (OTFDEC_ICR) . . . . .1437
37.6.14OTFDEC interrupt enable register (OTFDEC_IER) . . . . .1438
37.6.15OTFDEC register map . . . . .1439
38Advanced-control timers (TIM1/TIM8) . . . . .1443
38.1TIM1/TIM8 introduction . . . . .1443
38.2TIM1/TIM8 main features . . . . .1443
38.3TIM1/TIM8 functional description . . . . .1444
38.3.1Block diagram . . . . .1444
38.3.2TIM1/TIM8 pins and internal signals . . . . .1445
38.3.3Time-base unit . . . . .1449
38.3.4Counter modes . . . . .1451
38.3.5Repetition counter . . . . .1463
38.3.6External trigger input . . . . .1464
38.3.7Clock selection . . . . .1465
38.6.7TIMx capture/compare mode register 1 (TIMx_CCMR1)
(x = 1, 8) . . . . .		1547
38.6.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . .		1549
38.6.9TIMx capture/compare mode register 2 (TIMx_CCMR2)
(x = 1, 8) . . . . .		1552
38.6.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . .		1553
38.6.11TIMx capture/compare enable register (TIMx_CCER)(x = 1, 8) . . . . .1556
38.6.12TIMx counter (TIMx_CNT)(x = 1, 8) . . . . .1560
38.6.13TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . .1560
38.6.14TIMx autoreload register (TIMx_ARR)(x = 1, 8) . . . . .1561
38.6.15TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . .1561
38.6.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 1, 8) . . . . .1562
38.6.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 1, 8) . . . . .1562
38.6.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 1, 8) . . . . .1563
38.6.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 1, 8) . . . . .1564
38.6.20TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) . . . . .1565
38.6.21TIMx capture/compare register 5 (TIMx_CCR5)(x = 1, 8) . . . . .1569
38.6.22TIMx capture/compare register 6 (TIMx_CCR6)(x = 1, 8) . . . . .1570
38.6.23TIMx capture/compare mode register 3 (TIMx_CCMR3)
(x = 1, 8) . . . . .		1571
38.6.24TIMx timer deadtime register 2 (TIMx_DTR2)(x = 1, 8) . . . . .1572
38.6.25TIMx timer encoder control register (TIMx_ECR)(x = 1, 8) . . . . .1573
38.6.26TIMx timer input selection register (TIMx_TISEL)(x = 1, 8) . . . . .1574
38.6.27TIMx alternate function option register 1 (TIMx_AF1)(x = 1, 8) . . . . .1575
38.6.28TIMx alternate function register 2 (TIMx_AF2)(x = 1, 8) . . . . .1578
38.6.29TIMx DMA control register (TIMx_DCR)(x = 1, 8) . . . . .1580
38.6.30TIMx DMA address for full transfer (TIMx_DMAR)(x = 1, 8) . . . . .1582
38.6.31TIMx register map . . . . .1582
39General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . .1585
39.1TIM2/TIM3/TIM4/TIM5 introduction . . . . .1585
39.2TIM2/TIM3/TIM4/TIM5 main features . . . . .1585
39.3TIM2/TIM3/TIM4/TIM5 implementation . . . . .1586
39.4TIM2/TIM3/TIM4/TIM5 functional description . . . . .1587
39.4.1Block diagram . . . . .1587
39.4.2TIM2/TIM3/TIM4/TIM5 pins and internal signals . . . . .1588
39.5.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) . . . . .1678
39.5.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 2 to 5) . . . . .		1679
39.5.11TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5) . . . . .1682
39.5.12TIMx counter (TIMx_CNT)(x = 3, 4) . . . . .1683
39.5.13TIMx counter (TIMx_CNT)(x = 2, 5) . . . . .1684
39.5.14TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . .1684
39.5.15TIMx autoreload register (TIMx_ARR)(x = 3, 4) . . . . .1685
39.5.16TIMx autoreload register (TIMx_ARR)(x = 2, 5) . . . . .1685
39.5.17TIMx capture/compare register 1 (TIMx_CCR1)(x = 3, 4) . . . . .1686
39.5.18TIMx capture/compare register 1 (TIMx_CCR1)(x = 2, 5) . . . . .1687
39.5.19TIMx capture/compare register 2 (TIMx_CCR2)(x = 3, 4) . . . . .1687
39.5.20TIMx capture/compare register 2 (TIMx_CCR2)(x = 2, 5) . . . . .1688
39.5.21TIMx capture/compare register 3 (TIMx_CCR3)(x = 3, 4) . . . . .1689
39.5.22TIMx capture/compare register 3 (TIMx_CCR3)(x = 2, 5) . . . . .1690
39.5.23TIMx capture/compare register 4 (TIMx_CCR4)(x = 3, 4) . . . . .1691
39.5.24TIMx capture/compare register 4 (TIMx_CCR4)(x = 2, 5) . . . . .1692
39.5.25TIMx timer encoder control register (TIMx_ECR)(x = 2 to 5) . . . . .1693
39.5.26TIMx timer input selection register (TIMx_TISEL)(x = 2 to 5) . . . . .1694
39.5.27TIMx alternate function register 1 (TIMx_AF1)(x = 2 to 5) . . . . .1695
39.5.28TIMx alternate function register 2 (TIMx_AF2)(x = 2 to 5) . . . . .1696
39.5.29TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . .1697
39.5.30TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . .1698
39.5.31TIMx register map . . . . .1699
40Basic timers (TIM6/TIM7) . . . . .1702
40.1TIM6/TIM7 introduction . . . . .1702
40.2TIM6/TIM7 main features . . . . .1702
40.3TIM6/TIM7 functional description . . . . .1703
40.3.1TIM6/TIM7 block diagram . . . . .1703
40.3.2TIM6/TIM7 internal signals . . . . .1703
40.3.3TIM6/TIM7 clocks . . . . .1704
40.3.4Time-base unit . . . . .1704
40.3.5Counting mode . . . . .1706
40.3.6UIF bit remapping . . . . .1713
40.3.7ADC triggers . . . . .1714
40.3.8TIM6/TIM7 DMA requests . . . . .1714
40.3.9Debug mode . . . . .1714
40.3.10TIM6/TIM7 low-power modes . . . . .1714
40.3.11TIM6/TIM7 interrupts . . . . .1714
40.4TIM6/TIM7 registers . . . . .1715
40.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . .1715
40.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . .1717
40.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . .1717
40.4.4TIMx status register (TIMx_SR)(x = 6 to 7) . . . . .1718
40.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . .1718
40.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . .1718
40.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . .1719
40.4.8TIMx autoreload register (TIMx_ARR)(x = 6 to 7) . . . . .1719
40.4.9TIMx register map . . . . .1720
41General-purpose timers (TIM12/TIM13/TIM14) . . . . .1721
41.1TIM12/TIM13/TIM14 introduction . . . . .1721
41.2TIM12 main features . . . . .1721
41.3TIM13/TIM14 main features . . . . .1722
41.4TIM12/TIM13/TIM14 functional description . . . . .1723
41.4.1Block diagram . . . . .1723
41.4.2TIM12/TIM13/TIM14 pins and internal signals . . . . .1724
41.4.3Time-base unit . . . . .1727
41.4.4Counter modes . . . . .1729
41.4.5Clock selection . . . . .1732
41.4.6Capture/compare channels . . . . .1734
41.4.7Input capture mode . . . . .1736
41.4.8PWM input mode (TIM12 only) . . . . .1737
41.4.9Forced output mode . . . . .1738
41.4.10Output compare mode . . . . .1739
41.4.11PWM mode . . . . .1740
41.4.12Combined PWM mode (TIM12 only) . . . . .1745
41.4.13One-pulse mode . . . . .1746
41.4.14Retriggerable one pulse mode (TIM12 only) . . . . .1748
41.4.15UIF bit remapping . . . . .1749
41.4.16Timer input XOR function . . . . .1749
41.4.17TIM12 external trigger synchronization . . . . .1749
41.4.18Slave mode – combined reset + trigger mode . . . . .1752
41.4.19Slave mode – combined reset + gated mode . . . . .1752
41.4.20Timer synchronization (TIM12 only) . . . . .1752
41.4.21Using timer output as trigger for other timers
(TIM13/TIM14 only) . . . . .		1752
41.4.22ADC triggers (TIM12 only) . . . . .1752
41.4.23Debug mode . . . . .1752
41.5TIM12/TIM13/TIM14 low-power modes . . . . .1753
41.6TIM12/TIM13/TIM14 interrupts . . . . .1753
41.7TIM12 registers . . . . .1753
41.7.1TIM12 control register 1 (TIM12_CR1) . . . . .1753
41.7.2TIM12 control register 2 (TIM12_CR2) . . . . .1755
41.7.3TIM12 slave mode control register (TIM12_SMCR) . . . . .1755
41.7.4TIM12 interrupt enable register (TIM12_DIER) . . . . .1758
41.7.5TIM12 status register (TIM12_SR) . . . . .1759
41.7.6TIM12 event generation register (TIM12_EGR) . . . . .1760
41.7.7TIM12 capture/compare mode register 1 (TIM12_CCMR1) . . . . .1761
41.7.8TIM12 capture/compare mode register 1 [alternate]
(TIM12_CCMR1) . . . . .		1762
41.7.9TIM12 capture/compare enable register (TIM12_CCER) . . . . .1765
41.7.10TIM12 counter (TIM12_CNT) . . . . .1766
41.7.11TIM12 prescaler (TIM12_PSC) . . . . .1767
41.7.12TIM12 autoreload register (TIM12_ARR) . . . . .1767
41.7.13TIM12 capture/compare register 1 (TIM12_CCR1) . . . . .1768
41.7.14TIM12 capture/compare register 2 (TIM12_CCR2) . . . . .1768
41.7.15TIM12 timer input selection register (TIM12_TISEL) . . . . .1769
41.7.16TIM12 register map . . . . .1770
41.8TIM13/TIM14 registers . . . . .1772
41.8.1TIMx control register 1 (TIMx_CR1)(x = 13, 14) . . . . .1772
41.8.2TIMx interrupt enable register (TIMx_DIER)(x = 13, 14) . . . . .1773
41.8.3TIMx status register (TIMx_SR)(x = 13, 14) . . . . .1773
41.8.4TIMx event generation register (TIMx_EGR)(x = 13, 14) . . . . .1774
41.8.5TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 13, 14) . . . . .		1775
41.8.6TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 13, 14) . . . . .		1776
41.8.7TIMx capture/compare enable register
(TIMx_CCER)(x = 13, 14) . . . . .		1778
41.8.8TIMx counter (TIMx_CNT)(x = 13, 14) . . . . .1779
41.8.9TIMx prescaler (TIMx_PSC)(x = 13, 14) . . . . .1780
41.8.10TIMx autoreload register (TIMx_ARR)(x = 13, 14) . . . . .1780
41.8.11TIMx capture/compare register 1 (TIMx_CCR1)(x = 13, 14) . . . . .1781
41.8.12TIMx timer input selection register (TIMx_TISEL)(x = 13, 14) . . . . .1781
41.8.13TIM13/TIM14 register map . . . . .1782
42General purpose timers (TIM15/TIM16/TIM17) . . . . .1784
42.1TIM15/TIM16/TIM17 introduction . . . . .1784
42.2TIM15 main features . . . . .1784
42.3TIM16/TIM17 main features . . . . .1785
42.4TIM15/TIM16/TIM17 functional description . . . . .1786
42.4.1Block diagram . . . . .1786
42.4.2TIM15/TIM16/TIM17 pins and internal signals . . . . .1787
42.4.3Time-base unit . . . . .1790
42.4.4Counter modes . . . . .1792
42.4.5Repetition counter . . . . .1796
42.4.6Clock selection . . . . .1797
42.4.7Capture/compare channels . . . . .1799
42.4.8Input capture mode . . . . .1801
42.4.9PWM input mode (only for TIM15) . . . . .1803
42.4.10Forced output mode . . . . .1804
42.4.11Output compare mode . . . . .1804
42.4.12PWM mode . . . . .1806
42.4.13Combined PWM mode (TIM15 only) . . . . .1811
42.4.14Complementary outputs and dead-time insertion . . . . .1812
42.4.15Using the break function . . . . .1815
42.4.16Bidirectional break input . . . . .1819
42.4.17Clearing the tim_ocxref signal on an external event . . . . .1820
42.4.186-step PWM generation . . . . .1821
42.4.19One-pulse mode . . . . .1823
42.4.20Retriggerable one pulse mode (TIM15 only) . . . . .1824
42.4.21UIF bit remapping . . . . .1825
42.4.22Timer input XOR function (TIM15 only) . . . . .1825
42.4.23External trigger synchronization (TIM15 only) . . . . .1825
42.4.24Slave mode – combined reset + trigger mode (TIM15 only) . . . . .1828
42.4.25Slave mode – combined reset + gated mode (TIM15 only) . . . . .1828
42.4.26Timer synchronization (TIM15 only) . . . . .1829
42.4.27Using timer output as trigger for other timers (TIM16/TIM17 only) . . .1829
42.4.28ADC triggers (TIM15 only) . . . . .1829
42.4.29DMA burst mode . . . . .1829
42.4.30TIM15/TIM16/TIM17 DMA requests . . . . .1830
42.4.31Debug mode . . . . .1830
42.5TIM15/TIM16/TIM17 low-power modes . . . . .1831
42.6TIM15/TIM16/TIM17 interrupts . . . . .1831
42.7TIM15 registers . . . . .1832
42.7.1TIM15 control register 1 (TIM15_CR1) . . . . .1832
42.7.2TIM15 control register 2 (TIM15_CR2) . . . . .1833
42.7.3TIM15 slave mode control register (TIM15_SMCR) . . . . .1835
42.7.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .1837
42.7.5TIM15 status register (TIM15_SR) . . . . .1838
42.7.6TIM15 event generation register (TIM15_EGR) . . . . .1840
42.7.7TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .1841
42.7.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		1842
42.7.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .1845
42.7.10TIM15 counter (TIM15_CNT) . . . . .1848
42.7.11TIM15 prescaler (TIM15_PSC) . . . . .1848
42.7.12TIM15 autoreload register (TIM15_ARR) . . . . .1849
42.7.13TIM15 repetition counter register (TIM15_RCR) . . . . .1849
42.7.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .1850
42.7.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .1851
42.7.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .1851
42.7.17TIM15 timer deadtime register 2 (TIM15_DTR2) . . . . .1854
42.7.18TIM15 input selection register (TIM15_TISEL) . . . . .1855
42.7.19TIM15 alternate function register 1 (TIM15_AF1) . . . . .1856
42.7.20TIM15 alternate function register 2 (TIM15_AF2) . . . . .1858
42.7.21TIM15 DMA control register (TIM15_DCR) . . . . .1859
42.7.22TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .1860
42.7.23TIM15 register map . . . . .1860
42.8TIM16/TIM17 registers . . . . .1863
42.8.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .1863
42.8.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .1864
42.8.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .1865
42.8.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .1866
42.8.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .1867
42.8.6TIMx capture/compare mode register 1 (TIMx_CCMR1)
(x = 16 to 17) . . . . .		1868
42.8.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1869
42.8.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .1871
42.8.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .1874
42.8.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .1874
42.8.11TIMx auto-reautoreload register (TIMx_ARR)(x = 16 to 17) . . . . .1875
42.8.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .1875
42.8.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .1876
42.8.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .1877
42.8.15TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16 to 17) . . . . .1880
42.8.16TIMx input selection register (TIMx_TISEL)(x = 16 to 17) . . . . .1881
42.8.17TIMx alternate function register 1 (TIMx_AF1)(x = 16 to 17) . . . . .1881
42.8.18TIMx alternate function register 2 (TIMx_AF2)(x = 16 to 17) . . . . .1884
42.8.19TIM17 option register 1 (TIM17_OR1) . . . . .1884
42.8.20TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .1885
42.8.21TIM16/TIM17 DMA address for full transfer
(TIMx_DMAR)(x = 16 to 17) . . . . .		1886
42.8.22TIM16/TIM17 register map . . . . .1887
43Low-power timer (LPTIM) . . . . .1890
43.1LPTIM introduction . . . . .1890
43.2LPTIM main features . . . . .1890
43.3LPTIM implementation . . . . .1890
43.4LPTIM functional description . . . . .1892
43.4.1LPTIM block diagram . . . . .1892
43.4.2LPTIM pins and internal signals . . . . .1893
43.4.3LPTIM input and trigger mapping . . . . .1895
43.4.4LPTIM reset and clocks . . . . .1896
43.4.5Glitch filter . . . . .1897
43.4.6Prescaler . . . . .1898
43.4.7Trigger multiplexer . . . . .1898
43.4.8Operating mode . . . . .1899
43.4.9Timeout function . . . . .1901
43.4.10Waveform generation . . . . .1901
43.4.11Register update . . . . .1902
43.4.12Counter mode .....1903
43.4.13Timer enable .....1903
43.4.14Timer counter reset .....1904
43.4.15Encoder mode .....1904
43.4.16Repetition counter .....1906
43.4.17Capture/compare channels .....1907
43.4.18Input capture mode .....1908
43.4.19PWM mode .....1910
43.4.20DMA requests .....1912
43.4.21Debug mode .....1913
43.5LPTIM low-power modes .....1913
43.6LPTIM interrupts .....1913
43.7LPTIM registers .....1914
43.7.1LPTIM4 interrupt and status register (LPTIM4_ISR) .....1915
43.7.2LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1 to 3, 5, 6) .....		1916
43.7.3LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1 to 3, 5, 6) .....		1918
43.7.4LPTIM4 interrupt clear register (LPTIM4_ICR) .....1920
43.7.5LPTIMx interrupt clear register [alternate] (LPTIMx_ICR)
(x = 1 to 3, 5, 6) .....		1921
43.7.6LPTIMx interrupt clear register [alternate] (LPTIMx_ICR)
(x = 1 to 3, 5, 6) .....		1922
43.7.7LPTIM4 interrupt enable register (LPTIM4_DIER) .....1923
43.7.8LPTIMx interrupt enable register [alternate] (LPTIMx_DIER)
(x = 1 to 3, 5, 6) .....		1925
43.7.9LPTIMx interrupt enable register [alternate] (LPTIMx_DIER)
(x = 1 to 3, 5, 6) .....		1926
43.7.10LPTIM configuration register (LPTIM_CFGR) .....1928
43.7.11LPTIM control register (LPTIM_CR) .....1931
43.7.12LPTIM compare register 1 (LPTIM_CCR1) .....1932
43.7.13LPTIM autoreload register (LPTIM_ARR) .....1933
43.7.14LPTIM counter register (LPTIM_CNT) .....1933
43.7.15LPTIM configuration register 2 (LPTIM_CFGR2) .....1934
43.7.16LPTIM repetition register (LPTIM_RCR) .....1935
43.7.17LPTIM capture/compare mode register 1 (LPTIM_CCMR1) .....1935
43.7.18LPTIM compare register 2 (LPTIM_CCR2) .....1938
43.7.19LPTIM register map .....1938
45.6.1WWDG control register (WWDG_CR) . . . . .1961
45.6.2WWDG configuration register (WWDG_CFR) . . . . .1962
45.6.3WWDG status register (WWDG_SR) . . . . .1963
45.6.4WWDG register map . . . . .1963
46Real-time clock (RTC) . . . . .1964
46.1RTC introduction . . . . .1964
46.2RTC main features . . . . .1964
46.3RTC functional description . . . . .1965
46.3.1RTC block diagram . . . . .1965
46.3.2RTC pins and internal signals . . . . .1967
46.3.3GPIOs controlled by the RTC and TAMP . . . . .1968
46.3.4RTC secure protection modes . . . . .1972
46.3.5RTC privilege protection modes . . . . .1974
46.3.6Clock and prescalers . . . . .1975
46.3.7Real-time clock and calendar . . . . .1976
46.3.8Calendar ultra-low power mode . . . . .1976
46.3.9Programmable alarms . . . . .1977
46.3.10Periodic auto-wake-up . . . . .1977
46.3.11RTC initialization and configuration . . . . .1978
46.3.12Reading the calendar . . . . .1980
46.3.13Resetting the RTC . . . . .1981
46.3.14RTC synchronization . . . . .1982
46.3.15RTC reference clock detection . . . . .1982
46.3.16RTC smooth digital calibration . . . . .1983
46.3.17Timestamp function . . . . .1985
46.3.18Calibration clock output . . . . .1986
46.3.19Tamper and alarm output . . . . .1986
46.4RTC low-power modes . . . . .1987
46.5RTC interrupts . . . . .1987
46.6RTC registers . . . . .1989
46.6.1RTC time register (RTC_TR) . . . . .1989
46.6.2RTC date register (RTC_DR) . . . . .1990
46.6.3RTC subsecond register (RTC_SSR) . . . . .1991
46.6.4RTC initialization control and status register (RTC_ICSR) . . . . .1992
46.6.5RTC prescaler register (RTC_PRER) . . . . .1994
46.6.6RTC wake-up timer register (RTC_WUTR) . . . . .1995
46.6.7RTC control register (RTC_CR) . . . . .1995
46.6.8RTC privilege mode control register (RTC_PRIVCFGR) . . . . .1999
46.6.9RTC secure configuration register (RTC_SECCFGR) . . . . .2001
46.6.10RTC write protection register (RTC_WPR) . . . . .2002
46.6.11RTC calibration register (RTC_CALR) . . . . .2003
46.6.12RTC shift control register (RTC_SHIFTR) . . . . .2004
46.6.13RTC timestamp time register (RTC_TSTR) . . . . .2005
46.6.14RTC timestamp date register (RTC_TSDR) . . . . .2006
46.6.15RTC timestamp subsecond register (RTC_TSSSR) . . . . .2007
46.6.16RTC alarm A register (RTC_ALRMAR) . . . . .2007
46.6.17RTC alarm A subsecond register (RTC_ALRMASSR) . . . . .2009
46.6.18RTC alarm B register (RTC_ALRMBR) . . . . .2010
46.6.19RTC alarm B subsecond register (RTC_ALRMBSSR) . . . . .2011
46.6.20RTC status register (RTC_SR) . . . . .2012
46.6.21RTC nonsecure masked interrupt status register (RTC_MISR) . . . . .2013
46.6.22RTC secure masked interrupt status register (RTC_SMISR) . . . . .2014
46.6.23RTC status clear register (RTC_SCR) . . . . .2015
46.6.24RTC option register (RTC_OR) . . . . .2016
46.6.25RTC alarm A binary mode register (RTC_ALRABINR) . . . . .2017
46.6.26RTC alarm B binary mode register (RTC_ALRBBINR) . . . . .2017
46.6.27RTC register map . . . . .2019
47Tamper and backup registers (TAMP) . . . . .2022
47.1TAMP introduction . . . . .2022
47.2TAMP main features . . . . .2023
47.3TAMP functional description . . . . .2024
47.3.1TAMP block diagram . . . . .2024
47.3.2TAMP pins and internal signals . . . . .2025
47.3.3GPIOs controlled by the RTC and TAMP . . . . .2028
47.3.4TAMP register write protection . . . . .2028
47.3.5TAMP secure protection modes . . . . .2028
47.3.6Backup registers protection zones . . . . .2029
47.3.7TAMP privilege protection modes . . . . .2029
47.3.8Boot hardware key (BHK) . . . . .2030
47.3.9Tamper detection . . . . .2030
47.3.10TAMP backup registers and other device secrets erase . . . . .2030
47.3.11Tamper detection configuration and initialization . . . . .2032
47.4TAMP low-power modes . . . . .2038
47.5TAMP interrupts . . . . .2039
47.6TAMP registers . . . . .2039
47.6.1TAMP control register 1 (TAMP_CR1) . . . . .2039
47.6.2TAMP control register 2 (TAMP_CR2) . . . . .2041
47.6.3TAMP control register 3 (TAMP_CR3) . . . . .2044
47.6.4TAMP filter control register (TAMP_FLTCR) . . . . .2045
47.6.5TAMP active tamper control register 1 (TAMP_ATCR1) . . . . .2047
47.6.6TAMP active tamper seed register (TAMP_ATSEEDR) . . . . .2049
47.6.7TAMP active tamper output register (TAMP_ATOR) . . . . .2050
47.6.8TAMP active tamper control register 2 (TAMP_ATCR2) . . . . .2051
47.6.9TAMP secure configuration register (TAMP_SECCFGR) . . . . .2054
47.6.10TAMP privilege configuration register (TAMP_PRIVCFGR) . . . . .2056
47.6.11TAMP interrupt enable register (TAMP_IER) . . . . .2057
47.6.12TAMP status register (TAMP_SR) . . . . .2059
47.6.13TAMP nonsecure masked interrupt status register (TAMP_MISR) . . . . .2061
47.6.14TAMP secure masked interrupt status register (TAMP_SMISR) . . . . .2062
47.6.15TAMP status clear register (TAMP_SCR) . . . . .2064
47.6.16TAMP monotonic counter 1 register (TAMP_COUNT1R) . . . . .2066
47.6.17TAMP option register (TAMP_OR) . . . . .2066
47.6.18TAMP resources protection configuration register (TAMP_RPCFGR) . . . . .2067
47.6.19TAMP backup x register (TAMP_BKPxR) . . . . .2068
47.6.20TAMP register map . . . . .2069
48Inter-integrated circuit interface (I2C) . . . . .2071
48.1I2C introduction . . . . .2071
48.2I2C main features . . . . .2071
48.3I2C implementation . . . . .2072
48.4I2C functional description . . . . .2072
48.4.1I2C block diagram . . . . .2073
48.4.2I2C pins and internal signals . . . . .2073
48.4.3I2C clock requirements . . . . .2074
48.4.4I2C mode selection . . . . .2074
48.4.5I2C initialization . . . . .2075
48.4.6I2C reset . . . . .2079
48.4.7I2C data transfer . . . . .2080
48.4.8I2C target mode . . . . .2082
48.4.9I2C controller mode . . . . .2091
48.4.10I2C_TIMINGR register configuration examples . . . . .2102
48.4.11SMBus specific features . . . . .2104
48.4.12SMBus initialization . . . . .2106
48.4.13SMBus I2C_TIMEOUTR register configuration examples . . . . .2108
48.4.14SMBus target mode . . . . .2109
48.4.15SMBus controller mode . . . . .2112
48.4.16Wake-up from Stop mode on address match . . . . .2115
48.4.17Error conditions . . . . .2116
48.5I2C in low-power modes . . . . .2118
48.6I2C interrupts . . . . .2118
48.7I2C DMA requests . . . . .2119
48.7.1Transmission using DMA . . . . .2119
48.7.2Reception using DMA . . . . .2119
48.8I2C debug modes . . . . .2119
48.9I2C registers . . . . .2120
48.9.1I2C control register 1 (I2C_CR1) . . . . .2120
48.9.2I2C control register 2 (I2C_CR2) . . . . .2123
48.9.3I2C own address 1 register (I2C_OAR1) . . . . .2125
48.9.4I2C own address 2 register (I2C_OAR2) . . . . .2125
48.9.5I2C timing register (I2C_TIMINGR) . . . . .2126
48.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .2127
48.9.7I2C interrupt and status register (I2C_ISR) . . . . .2128
48.9.8I2C interrupt clear register (I2C_ICR) . . . . .2131
48.9.9I2C PEC register (I2C_PECR) . . . . .2132
48.9.10I2C receive data register (I2C_RXDR) . . . . .2132
48.9.11I2C transmit data register (I2C_TXDR) . . . . .2133
48.9.12I2C register map . . . . .2134
49Improved inter-integrated circuit (I3C) . . . . .2135
49.1I3C introduction . . . . .2135
49.2I3C main features . . . . .2135
49.3I3C implementation . . . . .2137
49.3.1I3C instantiation . . . . .2137
49.3.2I3C wake-up from low-power mode(s) . . . . .2137
49.3.3I3C FIFOs . . . . .2137
49.3.4I3C triggers . . . . .2137
49.3.5I3C interrupt(s) . . . . .2137
49.3.6I3C MIPI ® support . . . . .2138
49.4I3C block diagram . . . . .2139
49.5I3C pins and internal signals . . . . .2139
49.6I3C reset and clocks . . . . .2140
49.6.1I3C reset . . . . .2140
49.6.2I3C clocks and requirements . . . . .2140
49.7I3C peripheral state and programming . . . . .2142
49.7.1I3C peripheral state . . . . .2142
49.7.2I3C controller state and programming sequence . . . . .2143
49.7.3I3C target state and programming sequence . . . . .2147
49.8I3C registers and programming . . . . .2151
49.8.1I3C register set, as controller/target . . . . .2151
49.8.2I3C registers and fields use versus peripheral state, as controller . . . . .2152
49.8.3I3C registers and fields usage versus peripheral state, as target . . . . .2155
49.9I3C bus transfers and programming . . . . .2157
49.9.1I3C command set (CCC)s, as controller/target . . . . .2157
49.9.2I3C broadcast/direct CCC transfer (except ENTDAA, RSTACT),
as controller . . . . .		2161
49.9.3I3C broadcast ENTDAA CCC transfer, as controller . . . . .2163
49.9.4I3C broadcast/direct RSTACT CCC transfer, as controller . . . . .2163
49.9.5I3C broadcast/direct CCC transfer
(except ENTDAA, DEFTGTS, DEFGRPA), as target . . . . .		2165
49.9.6I3C broadcast ENTDAA CCC transfer, as target . . . . .2167
49.9.7I3C broadcast DEFTGTS CCC transfer, as target . . . . .2168
49.9.8I3C broadcast DEFGRPA CCC transfer, as target . . . . .2169
49.9.9I3C direct GETSTATUS CCC response, as target . . . . .2170
49.9.10I3C private read/write transfer, as controller . . . . .2171
49.9.11I3C private read/write transfer, as target . . . . .2172
49.9.12Legacy I2C read/write transfer, as controller . . . . .2173
49.9.13I3C IBI transfer, as controller/target . . . . .2174
49.9.14I3C hot-join request transfer, as controller/target . . . . .2175
49.9.15I3C controller-role request transfer, as controller/target . . . . .2176
49.10I3C FIFOs management, as controller . . . . .2177
49.10.1C-FIFO management, as controller . . . . .2177
49.10.2TX-FIFO management, as controller . . . . .2178
49.10.3RX-FIFO management, as controller . . . . .2181
49.10.4S-FIFO management, as controller . . . . .2183
49.11I3C FIFOs management, as target . . . . .2185
49.11.1RX-FIFO management, as target . . . . .2185
49.11.2TX-FIFO management, as target . . . . .2186
49.12I3C error management . . . . .2189
49.12.1Controller error management . . . . .2189
49.12.2Target error management . . . . .2191
49.13I3C wake-up from low-power mode(s) . . . . .2192
49.13.1Wake-up from Stop . . . . .2192
49.14I3C in low-power modes . . . . .2195
49.15I3C interrupts . . . . .2196
49.16I3C registers . . . . .2197
49.16.1I3C message control register (I3C_CR) . . . . .2197
49.16.2I3C message control register [alternate] (I3C_CR) . . . . .2199
49.16.3I3C configuration register (I3C_CFGGR) . . . . .2201
49.16.4I3C receive data byte register (I3C_RDR) . . . . .2206
49.16.5I3C receive data word register (I3C_RDWR) . . . . .2206
49.16.6I3C transmit data byte register (I3C_TDR) . . . . .2207
49.16.7I3C transmit data word register (I3C_TDWR) . . . . .2208
49.16.8I3C IBI payload data register (I3C_IBIDR) . . . . .2210
49.16.9I3C target transmit configuration register (I3C_TGTDDR) . . . . .2211
49.16.10I3C status register (I3C_SR) . . . . .2212
49.16.11I3C status error register (I3C_SER) . . . . .2213
49.16.12I3C received message register (I3C_RMR) . . . . .2215
49.16.13I3C event register (I3C_EVR) . . . . .2216
49.16.14I3C interrupt enable register (I3C_IER) . . . . .2220
49.16.15I3C clear event register (I3C_CEVR) . . . . .2222
49.16.16I3C own device characteristics register (I3C_DEVR0) . . . . .2224
49.16.17I3C device x characteristics register (I3C_DEVRx) . . . . .2226
49.16.18I3C maximum read length register (I3C_MAXRLR) . . . . .2228
49.16.19I3C maximum write length register (I3C_MAXWLR) . . . . .2229
49.16.20I3C timing register 0 (I3C_TIMINGR0) . . . . .2230
49.16.21I3C timing register 1 (I3C_TIMINGR1) . . . . .2231
49.16.22I3C timing register 2 (I3C_TIMINGR2) . . . . .2233
49.16.23I3C bus characteristics register (I3C_BCR) . . . . .2234
49.16.24I3C device characteristics register (I3C_DCR) . . . . .2235
49.16.25I3C get capability register (I3C_GETCAPR) . . . . .2236
49.16.26I3C controller-role capability register (I3C_CRCAPR) . . . . .2237
49.16.27I3C get max data speed register (I3C_GETMXDSR) . . . . .2238
49.16.28I3C extended provisioned ID register (I3C_EPIDR) . . . . .2240
49.16.29I3C register map . . . . .2241
50Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .2244
50.1USART introduction . . . . .2244
50.2USART main features . . . . .2244
50.3USART extended features . . . . .2245
50.4USART implementation . . . . .2245
50.5USART functional description . . . . .2247
50.5.1USART block diagram . . . . .2247
50.5.2USART pins and internal signals . . . . .2247
50.5.3USART clocks . . . . .2249
50.5.4USART character description . . . . .2249
50.5.5USART FIFOs and thresholds . . . . .2252
50.5.6USART transmitter . . . . .2252
50.5.7USART receiver . . . . .2255
50.5.8USART baud rate generation . . . . .2262
50.5.9Tolerance of the USART receiver to clock deviation . . . . .2264
50.5.10USART auto baud rate detection . . . . .2265
50.5.11USART multiprocessor communication . . . . .2267
50.5.12USART Modbus communication . . . . .2269
50.5.13USART parity control . . . . .2270
50.5.14USART LIN (local interconnection network) mode . . . . .2271
50.5.15USART synchronous mode . . . . .2273
50.5.16USART single-wire half-duplex communication . . . . .2277
50.5.17USART receiver timeout . . . . .2277
50.5.18USART smartcard mode . . . . .2278
50.5.19USART IrDA SIR ENDEC block . . . . .2282
50.5.20Continuous communication using USART and DMA . . . . .2285
50.5.21RS232 hardware flow control and RS485 driver enable . . . . .2287
50.5.22USART low-power management . . . . .2290
50.6USART in low-power modes . . . . .2293
50.7USART interrupts . . . . .2293
50.8USART registers . . . . .2296
50.8.1USART control register 1 (USART_CR1) . . . . .2296
50.8.2USART control register 1 [alternate] (USART_CR1) . . . . .2300
50.8.3USART control register 2 (USART_CR2) . . . . .2303
50.8.4USART control register 3 (USART_CR3) . . . . .2307
50.8.5USART control register 3 [alternate] (USART_CR3) . . . . .2311
50.8.6USART baud rate register (USART_BRR) . . . . .2315
50.8.7USART guard time and prescaler register (USART_GTPR) . . . . .2315
50.8.8USART receiver timeout register (USART_RTOR) . . . . .2316
50.8.9USART request register (USART_RQR) . . . . .2317
50.8.10USART interrupt and status register (USART_ISR) . . . . .2318
50.8.11USART interrupt and status register [alternate] (USART_ISR) . . . . .2324
50.8.12USART interrupt flag clear register (USART_ICR) . . . . .2329
50.8.13USART receive data register (USART_RDR) . . . . .2330
50.8.14USART transmit data register (USART_TDR) . . . . .2331
50.8.15USART prescaler register (USART_PRESC) . . . . .2331
50.8.16USART register map . . . . .2332
51Low-power universal asynchronous receiver transmitter (LPUART) . . . . .2334
51.1LPUART introduction . . . . .2334
51.2LPUART main features . . . . .2334
51.3LPUART implementation . . . . .2335
51.4LPUART functional description . . . . .2337
51.4.1LPUART block diagram . . . . .2337
51.4.2LPUART pins and internal signals . . . . .2338
51.4.3LPUART clocks . . . . .2339
51.4.4LPUART character description . . . . .2339
51.4.5LPUART FIFOs and thresholds . . . . .2341
51.4.6LPUART transmitter . . . . .2341
51.4.7LPUART receiver . . . . .2345
51.4.8LPUART baud rate generation . . . . .2349
51.4.9Tolerance of the LPUART receiver to clock deviation . . . . .2350
51.4.10LPUART multiprocessor communication . . . . .2351
51.4.11LPUART parity control . . . . .2353
51.4.12LPUART single-wire half-duplex communication . . . . .2354
51.4.13Continuous communication using DMA and LPUART . . . . .2354
51.4.14RS232 hardware flow control and RS485 driver enable . . . . .2357
51.4.15LPUART low-power management . . . . .2359
51.5LPUART in low-power modes . . . . .2362
51.6LPUART interrupts . . . . .2363
51.7LPUART registers . . . . .2364
51.7.1LPUART control register 1 (LPUART_CR1) . . . . .2364
51.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .2367
51.7.3LPUART control register 2 (LPUART_CR2) . . . . .2370
51.7.4LPUART control register 3 (LPUART_CR3) . . . . .2372
51.7.5LPUART control register 3 [alternate] (LPUART_CR3) . . . . .2375
51.7.6LPUART baud rate register (LPUART_BRR) . . . . .2377
51.7.7LPUART request register (LPUART_RQR) . . . . .2377
51.7.8LPUART interrupt and status register (LPUART_ISR) . . . . .2378
51.7.9LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .2383
51.7.10LPUART interrupt flag clear register (LPUART_ICR) . . . . .2386
51.7.11LPUART receive data register (LPUART_RDR) . . . . .2387
51.7.12LPUART transmit data register (LPUART_TDR) . . . . .2387
51.7.13LPUART prescaler register (LPUART_PRESC) . . . . .2388
51.7.14LPUART register map . . . . .2389
52Serial peripheral interface (SPI) . . . . .2391
52.1SPI introduction . . . . .2391
52.2SPI main features . . . . .2391
52.3SPI implementation . . . . .2392
52.4SPI functional description . . . . .2393
52.4.1SPI block diagram . . . . .2393
52.4.2SPI pins and internal signals . . . . .2394
52.4.3SPI communication general aspects . . . . .2395
52.4.4Communications between one master and one slave . . . . .2395
52.4.5Standard multislave communication . . . . .2398
52.4.6Multimaster communication . . . . .2401
52.4.7Slave select (NSS pin) management . . . . .2402
52.4.8Ready pin (RDY) management . . . . .2406
52.4.9Communication formats . . . . .2406
52.4.10Configuring the SPI . . . . .2408
52.4.11Enabling the SPI . . . . .2409
52.4.12SPI data transmission and reception procedures . . . . .2410
52.4.13Disabling the SPI . . . . .2414
52.4.14Communication using DMA (direct memory addressing) . . . . .2415
52.5SPI specific modes and control . . . . .2417
52.5.1TI mode . . . . .2417
52.5.2SPI error flags . . . . .2417
52.5.3CRC computation . . . . .2421
52.6SPI in low-power modes . . . . .2422
52.7SPI interrupts . . . . .2422
52.8I2S main features . . . . .2424
52.9I2S functional description . . . . .2424
52.9.1I2S general description . . . . .2424
52.9.2Pin sharing with SPI function . . . . .2425
52.9.3Bitfields usable in I2S/PCM mode . . . . .2425
52.9.4Slave and master modes . . . . .2426
52.9.5Supported audio protocols . . . . .2426
52.9.6Additional serial interface flexibility . . . . .2432
52.9.7Startup sequence . . . . .2434
52.9.8Stop sequence . . . . .2436
52.9.9Clock generator . . . . .2437
52.9.10Internal FIFOs . . . . .2439
52.9.11FIFO status flags . . . . .2440
52.9.12Handling of underrun situation . . . . .2440
52.9.13Handling of overrun situation . . . . .2441
52.9.14Frame error detection . . . . .2442
52.9.15DMA interface . . . . .2444
52.9.16Programing examples . . . . .2444
52.10I2S interrupts . . . . .2447
52.11SPI/I2S registers . . . . .2447
52.11.1SPI/I2S control register 1 (SPI_CR1) . . . . .2447
52.11.2SPI/I2S control register 2 (SPI_CR2) . . . . .2449
52.11.3SPI/I2S configuration register 1 (SPI_CFG1) . . . . .2450
52.11.4SPI/I2S configuration register 2 (SPI_CFG2) . . . . .2453
52.11.5SPI/I2S interrupt enable register (SPI_IER) . . . . .2455
52.11.6SPI/I2S status register (SPI_SR) . . . . .2456
52.11.7SPI/I2S interrupt/status flags clear register (SPI_IFCR) . . . . .2459
52.11.8SPI/I2S transmit data register (SPI_TXDR) . . . . .2460
52.11.9SPI/I2S receive data register (SPI_RXDR) . . . . .2460
52.11.10SPI/I2S polynomial register (SPI_CRCPOLY) . . . . .2461
52.11.11SPI/I2S transmitter CRC register (SPI_TXCRC) . . . . .2461
52.11.12SPI/I2S receiver CRC register (SPI_RXCRC) . . . . .2462
52.11.13SPI/I2S underrun data register (SPI_UDRDR) . . . . .2463
52.11.14SPI/I2S configuration register (SPI_I2SCFGR) . . . . .2463
52.11.15SPI/I2S register map . . . . .2465
53Serial audio interface (SAI) . . . . .2467
53.1SAI introduction . . . . .2467
53.2SAI main features . . . . .2467
53.3SAI implementation . . . . .2468
53.4SAI functional description . . . . .2469
53.4.1SAI block diagram . . . . .2469
53.4.2SAI pins and internal signals . . . . .2470
53.4.3Main SAI modes . . . . .2471
53.4.4SAI synchronization mode . . . . .2472
53.4.5Audio data size . . . . .2473
53.4.6Frame synchronization . . . . .2473
53.4.7Slot configuration . . . . .2476
53.4.8SAI clock generator . . . . .2478
53.4.9Internal FIFOs . . . . .2481
53.4.10PDM interface . . . . .2483
53.4.11AC'97 link controller . . . . .2491
53.4.12SPDIF output . . . . .2493
53.4.13Specific features . . . . .2496
53.4.14Error flags . . . . .2500
53.4.15Disabling the SAI . . . . .2503
53.4.16SAI DMA interface . . . . .2503
53.5SAI interrupts . . . . .2504
53.6SAI registers . . . . .2506
53.6.1SAI global configuration register (SAI_GCR) . . . . .2506
53.6.2SAI configuration register 1 (SAI_ACR1) . . . . .2506
53.6.3SAI configuration register 2 (SAI_ACR2) . . . . .2509
53.6.4SAI frame configuration register (SAI_AFRCR) . . . . .2511
53.6.5SAI slot register (SAI_ASLOTR) . . . . .2512
53.6.6SAI interrupt mask register (SAI_AIM) . . . . .2513
53.6.7SAI status register (SAI_ASR) . . . . .2515
53.6.8SAI clear flag register (SAI_ACLRFR) . . . . .2517
53.6.9SAI data register (SAI_ADR) . . . . .2518
53.6.10SAI configuration register 1 (SAI_BCR1) . . . . .2518
53.6.11SAI configuration register 2 (SAI_BCR2) . . . . .2521
53.6.12SAI frame configuration register (SAI_BFRCR) . . . . .2523
53.6.13SAI slot register (SAI_BSLOTR) . . . . .2524
53.6.14SAI interrupt mask register (SAI_BIM) . . . . .2525
53.6.15SAI status register (SAI_BSR) . . . . .2526
53.6.16SAI clear flag register (SAI_BCLRFR) . . . . .2528
53.6.17SAI data register (SAI_BDR) . . . . .2529
53.6.18SAI PDM control register (SAI_PDMCR) . . . . .2530
53.6.19SAI PDM delay register (SAI_PDMDLY) . . . . .2531
53.6.20SAI register map . . . . .2533
54FD controller area network (FDCAN) . . . . .2535
54.1FDCAN introduction . . . . .2535
54.2FDCAN main features . . . . .2537
54.3FDCAN functional description . . . . .2538
54.3.1FDCAN block diagram . . . . .2538
54.3.2FDCAN pins and internal signals . . . . .2539
54.3.3Bit timing . . . . .2540
54.3.4Operating modes . . . . .2541
54.3.5Error management . . . . .2550
54.3.6Message RAM . . . . .2551
54.3.7FIFO acknowledge handling . . . . .2560
54.3.8FDCAN Rx FIFO element . . . . .2560
54.3.9FDCAN Tx buffer element . . . . .2562
54.3.10FDCAN Tx event FIFO element . . . . .2564
54.3.11FDCAN standard message ID filter element . . . . .2565
54.3.12FDCAN extended message ID filter element . . . . .2566
54.4FDCAN registers . . . . .2568
54.4.1FDCAN core release register (FDCAN_CREL) . . . . .2568
54.4.2FDCAN endian register (FDCAN_ENDN) . . . . .2568
54.4.3FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . . .2568
54.4.4FDCAN test register (FDCAN_TEST) . . . . .2569
54.4.5FDCAN RAM watchdog register (FDCAN_RWD) . . . . .2570
54.4.6FDCAN CC control register (FDCAN_CCCR) . . . . .2571
54.4.7FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . . . . .2572
54.4.8FDCAN timestamp counter configuration register (FDCAN_TSCC) . . . . .2574
54.4.9FDCAN timestamp counter value register (FDCAN_TSCV) . . . . .2574
54.4.10FDCAN timeout counter configuration register (FDCAN_TOCC) . . . . .2575
54.4.11FDCAN timeout counter value register (FDCAN_TOCV) . . . . .2576
54.4.12FDCAN error counter register (FDCAN_ECR) . . . . .2576
54.4.13FDCAN protocol status register (FDCAN_PSR) . . . . .2577
54.4.14FDCAN transmitter delay compensation register (FDCAN_TDCR) . . . . .2579
54.4.15FDCAN interrupt register (FDCAN_IR) . . . . .2579
54.4.16FDCAN interrupt enable register (FDCAN_IE) . . . . .2582
54.4.17FDCAN interrupt line select register (FDCAN_ILS) . . . . .2584
54.4.18FDCAN interrupt line enable register (FDCAN_ILE) . . . . .2585
54.4.19FDCAN global filter configuration register (FDCAN_RXGFC) . . . . .2585
54.4.20FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . .2587
54.4.21FDCAN high-priority message status register (FDCAN_HPMS) . . . . .2587
54.4.22FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . .2588
54.4.23CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . .2589
54.4.24FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . .2589
54.4.25FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . .2590
54.4.26FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . .2590
54.4.27FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . .2591
54.4.28FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . .2591
54.4.29FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . .2592
54.4.30FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . . . . .2593
54.4.31FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) . . . . .2593
54.4.32FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . . . . .2594
54.4.33FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . .		2594
54.4.34FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_TXBCIE) . . . . .		2595
54.4.35FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . .2595
54.4.36FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . .2596
54.4.37FDCAN CFG clock divider register (FDCAN_CKDIV) . . . . .2596
54.4.38FDCAN register map . . . . .2597
55Universal serial bus full-speed host/device interface (USB) . . . . .2601
55.1USB introduction . . . . .2601
55.2USB main features . . . . .2601
55.3USB implementation . . . . .2601
55.4USB functional description . . . . .2602
55.4.1USB block diagram . . . . .2602
55.4.2USB pins and internal signals . . . . .2602
55.4.3USB reset and clocks . . . . .2603
55.4.4General description and Device mode functionality . . . . .2603
55.4.5Description of USB blocks used in both Device and Host modes . . .2604
55.4.6Description of host frame scheduler (HFS) specific to Host mode . .2605
55.5Programming considerations for Device and Host modes . . . . .2606
55.5.1Generic USB Device programming . . . . .2606
55.5.2System and power-on reset . . . . .2606
55.5.3Double-buffered endpoints and usage in Device mode . . . . .2613
55.5.4Double buffered channels: usage in Host mode . . . . .2615
55.5.5Isochronous transfers in Device mode . . . . .2616
55.5.6Isochronous transfers in Host mode . . . . .2617
55.5.7Suspend/resume events . . . . .2618
55.6USB registers . . . . .2622
55.6.1USB control register (USB_CNTR) . . . . .2622
55.6.2USB interrupt status register (USB_ISTR) . . . . .2625
55.6.3USB frame number register (USB_FNR) . . . . .2629
55.6.4USB Device address (USB_DADDR) . . . . .2629
55.6.5USB LPM control and status register (USB_LPMCSR) . . . . .2630
55.6.6USB battery charging detector (USB_BCDR) . . . . .2631
55.6.7USB endpoint/channel n register (USB_CHEPnR) . . . . .2632
55.6.8USB register map . . . . .2641
55.7USB SRAM registers . . . . .2642
55.7.1Channel/endpoint transmit buffer descriptor n
(USB_CHEP_TXRXBD_n) . . . . .		2643
55.7.2Channel/endpoint receive buffer descriptor n [alternate]
(USB_CHEP_TXRXBD_n) . . . . .		2643
55.7.3Channel/endpoint receive buffer descriptor n
(USB_CHEP_RXTXBD_n)		2645
55.7.4Channel/endpoint transmit buffer descriptor n [alternate]
(USB_CHEP_RXTXBD_n)		2646
55.7.5USBSRAM register map2647
56USB Type-C ® /USB Power Delivery interface (UCPD)2648
56.1UCPD introduction2648
56.2UCPD main features2648
56.3UCPD implementation2649
56.4UCPD functional description2649
56.4.1UCPD block diagram2650
56.4.2UCPD reset and clocks2651
56.4.3Physical layer protocol2652
56.4.4UCPD BMC transmitter2658
56.4.5UCPD BMC receiver2660
56.4.6UCPD Type-C pull-ups (Rp) and pull-downs (Rd)2661
56.4.7UCPD Type-C voltage monitoring and de-bouncing2662
56.4.8UCPD fast role swap (FRS)2662
56.4.9UCPD DMA Interface2662
56.4.10Wake-up from Stop mode2662
56.5UCPD programming sequences2663
56.5.1Initialization phase2663
56.5.2Type-C state machine handling2663
56.5.3USB PD transmit2665
56.5.4USB PD receive2666
56.5.5UCPD software trimming2667
56.6UCPD low-power modes2667
56.7UCPD interrupts2668
56.8UCPD registers2669
56.8.1UCPD configuration register 1 (UCPD_CFGR1)2669
56.8.2UCPD configuration register 2 (UCPD_CFGR2)2671
56.8.3UCPD configuration register 3 (UCPD_CFGR3)2671
56.8.4UCPD control register (UCPD_CR)2672
56.8.5UCPD interrupt mask register (UCPD_IMR)2674
56.8.6UCPD status register (UCPD_SR)2676
56.8.7UCPD interrupt clear register (UCPD_ICR)2679
56.8.8UCPD Tx ordered set type register (UCPD_TX_ORDSETR) . . . . .2680
56.8.9UCPD Tx payload size register (UCPD_TX_PAYSZR) . . . . .2680
56.8.10UCPD Tx data register (UCPD_TXDR) . . . . .2681
56.8.11UCPD Rx ordered set register (UCPD_RX_ORDSETR) . . . . .2681
56.8.12UCPD Rx payload size register (UCPD_RX_PAYSZR) . . . . .2682
56.8.13UCPD receive data register (UCPD_RXDR) . . . . .2683
56.8.14UCPD Rx ordered set extension register 1
(UCPD_RX_ORDEXTR1) . . . . .		2683
56.8.15UCPD Rx ordered set extension register 2
(UCPD_RX_ORDEXTR2) . . . . .		2684
56.8.16UCPD register map . . . . .2684
57Ethernet (ETH): media access control
(MAC) with DMA controller . . . . .		2687
57.1Ethernet introduction . . . . .2687
57.2Ethernet main features . . . . .2687
57.2.1Standard compliance . . . . .2687
57.2.2MAC features . . . . .2687
57.2.3Transaction layer (MTL) features . . . . .2689
57.2.4DMA block features . . . . .2690
57.2.5Bus interface features . . . . .2690
57.3Ethernet pins and internal signals . . . . .2691
57.4Ethernet architecture . . . . .2692
57.4.1DMA controller . . . . .2693
57.4.2MTL . . . . .2701
57.4.3MAC . . . . .2702
57.5Ethernet functional description: MAC . . . . .2707
57.5.1Double VLAN processing . . . . .2707
57.5.2Source address and VLAN insertion, replacement, or deletion . . . . .2708
57.5.3Packet filtering . . . . .2710
57.5.4IEEE 1588 timestamp support . . . . .2716
57.5.5Checksum offload engine . . . . .2741
57.5.6TCP segmentation offload . . . . .2747
57.5.7IPv4 ARP offload . . . . .2753
57.5.8Loopback . . . . .2754
57.5.9Flow control . . . . .2755
57.5.10MAC management counters . . . . .2758
57.5.11Interrupts generated by the MAC . . . . .2760
57.5.12MAC and MMC register descriptions . . . . .2760
57.6Ethernet functional description: PHY interfaces . . . . .2761
57.6.1Station management agent (SMA) . . . . .2761
57.6.2Media independent interface (MII) . . . . .2768
57.6.3Reduced media independent interface (RMII) . . . . .2769
57.7Ethernet low-power modes . . . . .2772
57.7.1Low-power management . . . . .2772
57.7.2Energy Efficient Ethernet (EEE) . . . . .2778
57.8Ethernet interrupts . . . . .2784
57.8.1DMA interrupts . . . . .2784
57.8.2MTL interrupts . . . . .2786
57.8.3MAC Interrupts . . . . .2786
57.9Ethernet programming model . . . . .2787
57.9.1DMA initialization . . . . .2787
57.9.2MTL initialization . . . . .2788
57.9.3MAC initialization . . . . .2788
57.9.4Performing normal receive and transmit operation . . . . .2789
57.9.5Stopping and starting transmission . . . . .2790
57.9.6Programming guidelines for switching to new descriptor list
in RxDMA . . . . .		2790
57.9.7Programming guidelines for switching the AHB clock frequency . . . . .2790
57.9.8Programming guidelines for MII link state transitions . . . . .2791
57.9.9Programming guidelines for IEEE 1588 timestamping . . . . .2792
57.9.10Programming guidelines for PTP offload feature . . . . .2793
57.9.11Programming guidelines for Energy Efficient Ethernet (EEE) . . . . .2797
57.9.12Programming guidelines for flexible pulse-per-second (PPS) output . . . . .2799
57.9.13Programming guidelines for IEEE 1588 auxiliary snapshot . . . . .2801
57.9.14Programming guidelines for TSO . . . . .2801
57.9.15Programming guidelines to perform VLAN filtering on the receiver . . . . .2802
57.10Descriptors . . . . .2803
57.10.1Descriptor overview . . . . .2803
57.10.2Descriptor structure . . . . .2803
57.10.3Transmit descriptor . . . . .2807
57.10.4Receive descriptor . . . . .2820
57.11Ethernet registers . . . . .2832
57.11.1Ethernet register maps . . . . .2832
59.2.3DBG reset and clocks . . . . .2984
59.2.4DBG power domains . . . . .2984
59.2.5Debug and low-power modes . . . . .2984
59.2.6Security . . . . .2985
59.2.7Debug authentication . . . . .2987
59.3Serial-wire and JTAG debug port (SWJ-DP) . . . . .2990
59.3.1JTAG debug port . . . . .2991
59.3.2Serial-wire debug port . . . . .2993
59.3.3Debug port registers . . . . .2995
59.3.4Debug port register map and reset values . . . . .3001
59.4Access ports . . . . .3002
59.4.1Access port registers . . . . .3003
59.4.2Access port register map . . . . .3009
59.5ROM tables . . . . .3010
59.5.1System ROM table registers . . . . .3013
59.5.2System ROM table register map . . . . .3017
59.5.3MCU ROM table registers . . . . .3018
59.5.4MCU ROM table register map . . . . .3022
59.5.5Processor ROM table registers . . . . .3023
59.5.6Processor ROM table register map . . . . .3028
59.6Data watchpoint and trace unit (DWT) . . . . .3029
59.6.1DWT registers . . . . .3029
59.6.2DWT register map . . . . .3043
59.7Instrumentation trace macrocell (ITM) . . . . .3046
59.7.1ITM registers . . . . .3046
59.7.2ITM register map . . . . .3054
59.8Breakpoint unit (BPU) . . . . .3056
59.8.1BPU registers . . . . .3056
59.8.2BPU register map . . . . .3062
59.9Embedded Trace Macrocell (ETM) . . . . .3063
59.9.1ETM registers . . . . .3063
59.9.2ETM register map . . . . .3087
59.10Trace port interface unit (TPIU) . . . . .3091
59.10.1TPIU registers . . . . .3092
59.10.2TPIU register map . . . . .3101
59.11Cross-trigger interface (CTI) . . . . .3103

List of tables

Table 1.Implementation of masters . . . . .106
Table 2.Implementation of slaves . . . . .106
Table 3.Securable peripherals by TZSC . . . . .110
Table 4.TrustZone-aware peripherals . . . . .114
Table 5.Memory map and peripheral register addresses (STM32H562/563/573xx) . . . . .118
Table 6.Memory map and peripheral register addresses (STM32H523/533xx) . . . . .123
Table 7.Configuring security attributes with IDAU and SAU . . . . .136
Table 8.MPCWMx resources . . . . .138
Table 9.MPCBBx resources (STM32H562/63/73xx devices) . . . . .138
Table 10.MPCBBx resources (STM32H523/33xx devices) . . . . .138
Table 11.DMA channel use (security) . . . . .142
Table 12.Secure alternate function between peripherals and allocated I/Os . . . . .144
Table 13.Nonsecure peripheral functions that cannot be connected to secure I/Os . . . . .145
Table 14.Nonsecure peripheral functions that can be connected to secure I/Os . . . . .145
Table 15.TrustZone-aware DBGMCU nonsecure accesses management . . . . .146
Table 16.DMA channel use (privilege) . . . . .150
Table 17.Internal tampers in TAMP . . . . .154
Table 18.Effect of low-power modes on TAMP . . . . .155
Table 19.Accelerated cryptographic operations . . . . .158
Table 20.Main product life cycle transitions . . . . .160
Table 21.Typical product life cycle phases . . . . .161
Table 22.Software intellectual property protection with PRODUCT_STAT . . . . .166
Table 23.Boot mode when TrustZone is disabled (TZEN = 0xC3) - STM32H523/62/63xx devices . . . . .170
Table 24.Boot mode when TrustZone is enabled (TZEN = 0xB4) - STM32H523/62/63xx devices . . . . .170
Table 25.Boot mode when TrustZone is disabled (TZEN = 0xC3) - STM32H533/73xx . . . . .171
Table 26.Boot mode when TrustZone is enabled (TZEN = 0xB4) - STM32H533/73xx . . . . .171
Table 27.GTZC features . . . . .174
Table 28.GTZC1 sub-block address offset . . . . .175
Table 29.MPCWM resource assignment . . . . .175
Table 30.MPCWM3 and MPCWM4 (subregions A and B) . . . . .175
Table 31.MPCBB resource assignment (STM32H562/63/73xx devices) . . . . .175
Table 32.MPCBB resource assignment (STM32H523/33xx devices) . . . . .176
Table 33.Secure properties of subregions A and B . . . . .179
Table 34.Privileged properties of subregions A and B . . . . .179
Table 35.GTZC interrupt request . . . . .180
Table 36.GTZC1 TZSC register map and reset values . . . . .199
Table 37.GTZC1 TZIC register map and reset values . . . . .227
Table 38.GTZC1 MPCBBz register map and reset values (z = 1 to 3) . . . . .231
Table 39.SRAMs density (Kbytes) . . . . .232
Table 40.Internal SRAMs features . . . . .233
Table 41.SRAM2 features . . . . .235
Table 42.Effect of low-power modes on RAMCFG . . . . .236
Table 43.RAMCFG interrupt requests . . . . .236
Table 44.RAMCFG register map and reset values . . . . .243
Table 45.Recommended number of wait states and programming delay . . . . .252
Table 46.Flash memory OTP organization . . . . .261
Table 47.Read-only public data organization . . . . .262
Table 48.Memory map and swapping options (STM32H562/563/573xx devices) . . . . .265
Table 49.Memory map and swapping options (STM32H523/533xx devices) . . . . .265
Table 50.Recommended reactions to FLASH_OPSR contents . . . . .268
Table 51.Option bytes organization . . . . .271
Table 52.Specific modifying rules . . . . .275
Table 53.OB modifiable in closed product . . . . .275
Table 54.Option bytes key area . . . . .277
Table 55.Default secure watermark . . . . .283
Table 56.Flash memory TZ protection summary . . . . .283
Table 57.TZ protection and bank or mass erase summary . . . . .284
Table 58.Secure watermark-based area . . . . .285
Table 59.Secure hide protection . . . . .286
Table 60.HDP protections summary . . . . .287
Table 61.Secure configuration block-based registers access conditions . . . . .287
Table 62.Privilege protection summary . . . . .288
Table 63.Privilege and mass or bank erase . . . . .288
Table 64.Privilege configuration register access conditions (TZ enabled) . . . . .288
Table 65.Privilege configuration register access conditions (TZ disabled) . . . . .289
Table 66.Flash register accesses . . . . .289
Table 67.Flash interface register protection summary . . . . .292
Table 68.High-cycle area protection summary: access to data area address range . . . . .293
Table 69.HDP protected definition . . . . .293
Table 70.Privileged sectors and data area - Access to data area address range . . . . .293
Table 71.Product states, debug states and debug policy . . . . .294
Table 72.PRODUCT_STATE transitions . . . . .296
Table 73.TZ OBK protection summary . . . . .297
Table 74.OBK protection summary with TZ disabled . . . . .298
Table 75.Access conditions to secure control register . . . . .298
Table 76.Access conditions to non-secure control register . . . . .298
Table 77.OTP/RO access constraints . . . . .299
Table 78.RSSLIB/NSSLIB accesses . . . . .299
Table 79.RSSLIB/NSSLIB entry point access . . . . .300
Table 80.RSS lib interface functions . . . . .300
Table 81.NSS lib interface functions . . . . .304
Table 82.Effect of low-power modes on the embedded flash memory . . . . .306
Table 83.Locating ECC failure . . . . .313
Table 84.Flash interrupt request . . . . .316
Table 85.Register map and reset value table . . . . .361
Table 86.ICACHE features . . . . .367
Table 87.TAG memory dimensioning parameters
for n-way set associative operating mode (default) . . . . .		369
Table 88.TAG memory dimensioning parameters for direct-mapped cache mode . . . . .370
Table 89.ICACHE cacheability for AHB transaction . . . . .372
Table 90.Memory configurations . . . . .372
Table 91.ICACHE remap region size, base address, and remap address . . . . .373
Table 92.ICACHE interrupts . . . . .377
Table 93.ICACHE register map and reset values . . . . .382
Table 94.DCACHE features . . . . .384
Table 95.TAG memory dimensioning parameters . . . . .387
Table 96.DCACHE cacheability for AHB transaction . . . . .389
Table 97.DCACHE interrupts . . . . .394
Table 98.DCACHE register map and reset values . . . . .400
Table 99.PWR input/output pins . . . . .403
Table 100.PWR internal input/output signals . . . . .403
Table 101.Low-power mode summary . . . . .420
Table 102.Functionalities depending on the working mode . . . . .420
Table 103.Sleep mode . . . . .424
Table 104.Memory shut-off block selection . . . . .425
Table 105.Stop mode . . . . .427
Table 106.Standby mode . . . . .430
Table 107.Power modes output states versus MCU power modes . . . . .430
Table 108.PWR security configuration summary . . . . .431
Table 109.PWR interrupt requests . . . . .433
Table 110.PWR register map and reset values . . . . .450
Table 111.RCC input/output signals connected to package pins or balls . . . . .452
Table 112.Reset source identification (RCC_RSR) . . . . .454
Table 113.STOPWUCK and STOPKERWUCK description . . . . .466
Table 114.HSIKERON and CSIKERON behavior . . . . .467
Table 115.Kernel clock distribution overview . . . . .469
Table 116.RCC security configuration summary . . . . .475
Table 117.Interrupt sources and control . . . . .479
Table 118.RCC register map and reset values . . . . .557
Table 119.CRS features . . . . .563
Table 120.CRS internal input/output signals . . . . .564
Table 121.CRS interconnection . . . . .565
Table 122.Effect of low-power modes on CRS . . . . .568
Table 123.Interrupt control bits . . . . .568
Table 124.CRS register map and reset values . . . . .573
Table 125.Port bit configuration . . . . .576
Table 126.GPIO secured bits . . . . .584
Table 127.GPIO register map and reset values . . . . .594
Table 128.SBS internal input/output signals . . . . .598
Table 129.HDPL encoded values . . . . .602
Table 130.SBS boot logic . . . . .602
Table 131.OBK-HDPL logic . . . . .607
Table 132.SBS register map and reset values . . . . .620
Table 133.Peripherals interconnect matrix . . . . .622
Table 134.GPDMA1/2 channel implementation . . . . .633
Table 135.GPDMA1/2 wake-up in low-power modes . . . . .633
Table 136.Programmed GPDMA1/2 request . . . . .633
Table 137.Programmed GPDMA1/2 request as a block request . . . . .638
Table 138.GPDMA1/2 channel with peripheral early termination . . . . .638
Table 139.Programmed GPDMA1/2 request with peripheral early termination . . . . .638
Table 140.Programmed GPDMA1/2 trigger . . . . .639
Table 141.Programmed GPDMA source/destination burst . . . . .660
Table 142.Programmed data handling . . . . .665
Table 143.Effect of low-power modes on GPDMA . . . . .678
Table 144.GPDMA interrupt requests . . . . .679
Table 145.GPDMA register map and reset values . . . . .708
Table 146.STM32H562/563/573xx vector table . . . . .712
Table 147.STM32H523/533xx vector table . . . . .717
Table 148.EXTI signals . . . . .723
Table 149.EVG signals . . . . .724
Table 150.EXTI line connections . . . . .724
Table 151.Masking functionality . . . . .728
Table 152.Register protection overview . . . . .729
Table 153.EXTI register map sections. . . . .731
Table 154.EXTI register map and reset values . . . . .754
Table 155.CRC internal input/output signals . . . . .757
Table 156.CRC register map and reset values . . . . .762
Table 157.CORDIC functions . . . . .764
Table 158.Cosine parameters . . . . .765
Table 159.Sine parameters . . . . .765
Table 160.Phase parameters . . . . .766
Table 161.Modulus parameters . . . . .766
Table 162.Arctangent parameters . . . . .767
Table 163.Hyperbolic cosine parameters . . . . .767
Table 164.Hyperbolic sine parameters . . . . .768
Table 165.Hyperbolic arctangent parameters . . . . .768
Table 166.Natural logarithm parameters . . . . .769
Table 167.Natural log scaling factors and corresponding ranges . . . . .769
Table 168.Square root parameters . . . . .770
Table 169.Square root scaling factors and corresponding ranges . . . . .770
Table 170.Precision vs. number of iterations. . . . .773
Table 171.CORDIC register map and reset value . . . . .780
Table 172.Valid combinations for read and write methods . . . . .794
Table 173.FMAC register map and reset values . . . . .807
Table 174.NOR/PSRAM bank selection . . . . .814
Table 175.NOR/PSRAM External memory address . . . . .814
Table 176.NAND memory mapping and timing registers. . . . .814
Table 177.NAND bank selection . . . . .815
Table 178.SDRAM bank selection. . . . .815
Table 179.SDRAM address mapping . . . . .815
Table 180.SDRAM address mapping with 8-bit data bus width. . . . .816
Table 181.SDRAM address mapping with 16-bit data bus width. . . . .817
Table 182.Programmable NOR/PSRAM access parameters . . . . .818
Table 183.Non-multiplexed I/O NOR flash memory. . . . .819
Table 184.16-bit multiplexed I/O NOR flash memory . . . . .819
Table 185.Non-multiplexed I/Os PSRAM/SRAM . . . . .820
Table 186.16-Bit multiplexed I/O PSRAM . . . . .820
Table 187.NOR flash/PSRAM: example of supported memories
and transactions . . . . .		821
Table 188.FMC_BCRx bitfields (mode 1) . . . . .824
Table 189.FMC_BTRx bitfields (mode 1) . . . . .824
Table 190.FMC_BCRx bitfields (mode A) . . . . .826
Table 191.FMC_BTRx bitfields (mode A) . . . . .826
Table 192.FMC_BWTRx bitfields (mode A). . . . .827
Table 193.FMC_BCRx bitfields (mode 2/B). . . . .829
Table 194.FMC_BTRx bitfields (mode 2/B). . . . .829
Table 195.FMC_BWTRx bitfields (mode 2/B) . . . . .830
Table 196.FMC_BCRx bitfields (mode C) . . . . .831
Table 197.FMC_BTRx bitfields (mode C) . . . . .832
Table 198.FMC_BWTRx bitfields (mode C). . . . .832
Table 199.FMC_BCRx bitfields (mode D) . . . . .834
Table 200.FMC_BTRx bitfields (mode D) . . . . .835
Table 201.FMC_BWTRx bitfields (mode D). . . . .835
Table 202.FMC_BCRx bitfields (Muxed mode) . . . . .837
Table 203.FMC_BTRx bitfields (Muxed mode) . . . . .838
Table 204.FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .843
Table 205.FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .844
Table 206.FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .845
Table 207.FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .846
Table 208.Programmable NAND flash access parameters . . . . .855
Table 209.8-bit NAND flash . . . . .855
Table 210.16-bit NAND flash . . . . .856
Table 211.Supported memories and transactions . . . . .856
Table 212.ECC result relevant bits . . . . .865
Table 213.SDRAM signals . . . . .866
Table 214.FMC register map and reset values . . . . .882
Table 215.OCTOSPI implementation . . . . .886
Table 216.OCTOSPI input/output pins . . . . .888
Table 217.OCTOSPI internal signals . . . . .888
Table 218.Command/address phase description . . . . .897
Table 219.OctaRAM command address bit assignment
(based on 64-Mbyte OctaRAM) . . . . .		907
Table 220.Address alignment cases . . . . .914
Table 221.OCTOSPI interrupt requests . . . . .915
Table 222.OCTOSPI register map and reset values . . . . .938
Table 223.SDMMC instances on device . . . . .941
Table 224.SDMMC features . . . . .942
Table 225.SDMMC operation modes SD and SDIO . . . . .944
Table 226.SDMMC operation modes e•MMC . . . . .944
Table 227.SDMMC internal input/output signals . . . . .945
Table 228.SDMMC pins . . . . .946
Table 229.SDMMC Command and data phase selection . . . . .947
Table 230.Command token format . . . . .953
Table 231.Short response with CRC token format . . . . .954
Table 232.Short response without CRC token format . . . . .954
Table 233.Long response with CRC token format . . . . .954
Table 234.Specific Commands overview . . . . .955
Table 235.Command path status flags . . . . .956
Table 236.Command path error handling . . . . .956
Table 237.Data token format . . . . .964
Table 238.Data path status flags and clear bits . . . . .964
Table 239.Data path error handling . . . . .966
Table 240.Data FIFO access . . . . .967
Table 241.Transmit FIFO status flags . . . . .968
Table 242.Receive FIFO status flags . . . . .969
Table 243.AHB and SDMMC_CK clock frequency relation . . . . .974
Table 244.SDIO special operation control . . . . .974
Table 245.4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . .978
Table 246.CMD12 use cases . . . . .983
Table 247.SDMMC interrupts . . . . .997
Table 248.Response type and SDMMC_RESPxR registers . . . . .1004
Table 249.SDMMC register map . . . . .1020
Table 250.STM32H5 features . . . . .1023
Table 251.DLYB internal input/output signals . . . . .1024
Table 252.Delay block control . . . . .1025
Table 253.DLYB register map and reset values . . . . .1028
Table 254.ADC features . . . . .1031
Table 255.ADC input/output pins . . . . .1033
Table 256.ADC internal input/output signals . . . . .1033
Table 257.ADC interconnection . . . . .1033
Table 258.Configuring the trigger polarity for regular external triggers . . . . .1053
Table 259.Configuring the trigger polarity for injected external triggers . . . . .1054
Table 260.TSAR timings depending on resolution . . . . .1066
Table 261.Offset computation versus data resolution . . . . .1069
Table 262.Analog watchdog channel selection . . . . .1080
Table 263.Analog watchdog 1 comparison . . . . .1081
Table 264.Analog watchdog 2 and 3 comparison . . . . .1081
Table 265.Maximum output results versus N and M (gray cells indicate truncation) . . . . .1085
Table 266.Oversampler operating modes summary . . . . .1090
Table 267.ADC interrupts . . . . .1109
Table 268.DELAY bits versus ADC resolution. . . . .1144
Table 269.ADC global register map. . . . .1146
Table 270.ADC register map and reset values for each ADC (offset = 0x000 for master ADC, 0x100 for slave ADC). . . . .1146
Table 271.ADC register map and reset values (master and slave ADC common registers) . . . . .1148
Table 272.DTS internal input/output signals . . . . .1151
Table 273.Sampling time configuration . . . . .1154
Table 274.Trigger configuration . . . . .1155
Table 275.Temperature sensor behavior in low-power modes . . . . .1157
Table 276.Interrupt control bits . . . . .1158
Table 277.DTS register map and reset values . . . . .1166
Table 278.DAC features . . . . .1168
Table 279.DAC input/output pins . . . . .1170
Table 280.DAC internal input/output signals . . . . .1170
Table 281.DAC interconnection . . . . .1170
Table 282.Data format (case of 12-bit data) . . . . .1173
Table 283.HFSEL description . . . . .1173
Table 284.Sample and refresh timings . . . . .1179
Table 285.Channel output modes summary . . . . .1181
Table 286.Effect of low-power modes on DAC . . . . .1187
Table 287.DAC interrupts . . . . .1188
Table 288.DAC register map and reset values . . . . .1204
Table 289.VREFBUF typical values . . . . .1207
Table 290.VREF buffer modes . . . . .1208
Table 291.VREFBUF register map and reset values. . . . .1210
Table 292.DCMI input/output pins . . . . .1212
Table 293.DCMI internal input/output signals . . . . .1212
Table 294.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .1214
Table 295.Positioning of captured data bytes in 32-bit words (10-bit width) . . . . .1214
Table 296.Positioning of captured data bytes in 32-bit words (12-bit width) . . . . .1214
Table 297.Positioning of captured data bytes in 32-bit words (14-bit width) . . . . .1215
Table 298.Data storage in monochrome progressive video format . . . . .1220
Table 299.Data storage in RGB progressive video format . . . . .1221
Table 300.Data storage in YCbCr progressive video format . . . . .1221
Table 301.Data storage in YCbCr progressive video format - Y extraction mode . . . . .1221
Table 302.DCMI interrupts. . . . .1222
Table 303.DCMI register map and reset values . . . . .1232
Table 304.PSSI input/output pins . . . . .1235
Table 305.PSSI internal input/output signals . . . . .1235
Table 306.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .1236
Table 307.Positioning of captured data bytes in 32-bit words (16-bit width) . . . . .1237
Table 308.PSSI interrupt requests . . . . .1240
Table 309.PSSI register map and reset values . . . . .1246
Table 310.RNG internal input/output signals . . . . .1248
Table 311.RNG interrupt requests . . . . .1256
Table 312.RNG initialization times . . . . .1257
Table 313.RNG configurations . . . . .1257
Table 314.Configuration selection . . . . .1258
Table 315.RNG register map and reset map . . . . .1263
Table 316.AES versus SAES features . . . . .1265
Table 317.AES internal input/output signals . . . . .1266
Table 318.AES approved symmetric key functions . . . . .1267
Table 319.Counter mode initialization vector definition . . . . .1276
Table 320.Initialization of IV registers in GCM mode . . . . .1279
Table 321.GCM last block definition . . . . .1279
Table 322.Initialization of IV registers in CCM mode . . . . .1286
Table 323.AES data swapping example . . . . .1289
Table 324.Key endianness in AES_KEYRx registers (128/256-bit keys) . . . . .1291
Table 325.IVI bitfield spread over AES_IVRx registers . . . . .1292
Table 326.AES interrupt requests . . . . .1293
Table 327.Processing latency for ECB, CBC and CTR . . . . .1294
Table 328.Processing latency for GCM and CCM (in clock cycles) . . . . .1295
Table 329.AES register map and reset values . . . . .1307
Table 330.AES versus SAES features . . . . .1311
Table 331.SAES internal input/output signals . . . . .1312
Table 332.SAES approved symmetric key functions . . . . .1313
Table 333.Counter mode initialization vector definition . . . . .1323
Table 334.Initialization of IV registers in GCM mode . . . . .1326
Table 335.GCM last block definition . . . . .1326
Table 336.Initialization of IV registers in CCM mode . . . . .1332
Table 337.AES data swapping example . . . . .1341
Table 338.Key endianness in SAES_KEYRx registers (128/256-bit keys) . . . . .1343
Table 339.IVI bitfield spread over SAES_IVRx registers . . . . .1345
Table 340.SAES interrupt requests . . . . .1347
Table 341.Processing latency for ECB, CBC and CTR . . . . .1348
Table 342.Processing latency for GCM and CCM (in SAES kernel clock cycles) . . . . .1348
Table 343.SAES register map and reset values . . . . .1363
Table 344.HASH internal input/output signals . . . . .1366
Table 345.Information on supported hash algorithms . . . . .1367
Table 346.Hash processor outputs . . . . .1370
Table 347.Processing time (in clock cycle) . . . . .1376
Table 348.HASH interrupt requests . . . . .1377
Table 349.HASH1 register map and reset values . . . . .1385
Table 350.Internal input/output signals . . . . .1388
Table 351.PKA integer arithmetic functions list . . . . .1389
Table 352.PKA prime field (Fp) elliptic curve functions list . . . . .1390
Table 353.Montgomery parameter computation . . . . .1396
Table 354.Modular addition . . . . .1397
Table 355.Modular subtraction . . . . .1397
Table 356.Montgomery multiplication . . . . .1398
Table 357.Modular exponentiation (normal mode) . . . . .1399
Table 358.Modular exponentiation (fast mode) . . . . .1399
Table 359.Modular exponentiation (protected mode) . . . . .1400
Table 360.Modular inversion . . . . .1400
Table 361.Modular reduction . . . . .1401
Table 362.Arithmetic addition . . . . .1401
Table 363.Arithmetic subtraction . . . . .1401
Table 364.Arithmetic multiplication . . . . .1402
Table 365.Arithmetic comparison . . . . .1402
Table 366.CRT exponentiation . . . . .1403
Table 367.Point on elliptic curve Fp check . . . . .1404
Table 368.ECC Fp scalar multiplication . . . . .1404
Table 369.ECDSA sign - Inputs . . . . .1406
Table 370.ECDSA sign - Outputs . . . . .1406
Table 371.Extended ECDSA sign - Extra outputs . . . . .1407
Table 372.ECDSA verification - Inputs . . . . .1407
Table 373.ECDSA verification - Outputs . . . . .1408
Table 374.ECC complete addition . . . . .1408
Table 375.ECC double base ladder . . . . .1409
Table 376.ECC projective to affine . . . . .1410
Table 377.Family of supported curves for ECC operations . . . . .1411
Table 378.Modular exponentiation . . . . .1412
Table 379.ECC scalar multiplication . . . . .1412
Table 380.ECDSA signature average computation time . . . . .1413
Table 381.ECDSA verification average computation times . . . . .1413
Table 382.ECC double base ladder average computation times . . . . .1413
Table 383.ECC projective to affine average computation times . . . . .1413
Table 384.ECC complete addition average computation times . . . . .1413
Table 385.Point on elliptic curve Fp check average computation times . . . . .1413
Table 386.Montgomery parameters average computation times . . . . .1414
Table 387.PKA interrupt requests . . . . .1414
Table 388.PKA register map and reset values . . . . .1419
Table 389.OTFDEC internal input/output signals . . . . .1421
Table 390.OTFDEC interrupt requests . . . . .1425
Table 391.OTFDEC register map and reset values . . . . .1439
Table 392.TIM input/output pins . . . . .1445
Table 393.TIM internal input/output signals . . . . .1445
Table 394.Interconnect to the tim_ti1 input multiplexer . . . . .1447
Table 395.Interconnect to the tim_ti2 input multiplexer . . . . .1447
Table 396.Interconnect to the tim_ti3 input multiplexer . . . . .1447
Table 397.Interconnect to the tim_ti4 input multiplexer . . . . .1447
Table 398.Internal trigger connection . . . . .1447
Table 399.Interconnect to the tim_etr input multiplexer . . . . .1448
Table 400.Timer break interconnect . . . . .1448
Table 401.Timer break2 interconnect . . . . .1448
Table 402.System break interconnect . . . . .1449
Table 403.CCR and ARR register change dithering pattern . . . . .1482
Table 404.CCR register change dithering pattern in center-aligned PWM mode . . . . .1483
Table 405.Behavior of timer outputs versus tim_brk/tim_brk2 inputs . . . . .1495
Table 406.Break protection disarming conditions . . . . .1497
Table 407.Counting direction versus encoder signals (CC1P = CC2P = 0) . . . . .1506
Table 408.Counting direction versus encoder signals and polarity settings . . . . .1510
Table 409.DMA request . . . . .1531
Table 410.Effect of low-power modes on TIM1/TIM8 . . . . .1532
Table 411.Interrupt requests . . . . .1532
Table 412.Output control bits for complementary tim_ocx and tim_ocxn channels
with break feature . . . . .		1559
Table 413.TIMx register map and reset values . . . . .1582
Table 414.STM32H5 general purpose timers . . . . .1586
Table 415.TIM input/output pins . . . . .1588
Table 416.TIM internal input/output signals . . . . .1588
Table 417.Interconnect to the tim_ti1 input multiplexer . . . . .1589
Table 418.Interconnect to the tim_ti2 input multiplexer . . . . .1589
Table 419.Interconnect to the tim_ti3 input multiplexer . . . . .1589
Table 420.Interconnect to the tim_ti4 input multiplexer . . . . .1590
Table 421.TIMx internal trigger connection . . . . .1590
Table 422.Interconnect to the tim_etr input multiplexer . . . . .1590
Table 423.CCR and ARR register change dithering pattern . . . . .1622
Table 424.CCR register change dithering pattern in center-aligned PWM mode . . . . .1623
Table 425.Counting direction versus encoder signals(CC1P = CC2P = 0) . . . . .1632
Table 426.Counting direction versus encoder signals and polarity settings . . . . .1637
Table 427.DMA request . . . . .1661
Table 428.Effect of low-power modes on TIM2/TIM3/TIM4/TIM5 . . . . .1661
Table 429.Interrupt requests . . . . .1662
Table 430.Output control bit for standard tim_ocx channels . . . . .1683
Table 431.TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . .1699
Table 432.TIM internal input/output signals . . . . .1703
Table 433.TIMx_ARR register change dithering pattern . . . . .1713
Table 434.DMA request . . . . .1714
Table 435.Effect of low-power modes on TIM6/TIM7 . . . . .1714
Table 436.Interrupt request . . . . .1714
Table 437.TIMx register map and reset values . . . . .1720
Table 438.TIM input/output pins . . . . .1724
Table 439.TIM internal input/output signals . . . . .1724
Table 440.Interconnect to the tim_ti1 input multiplexer . . . . .1726
Table 441.Interconnect to the tim_ti2 input multiplexer . . . . .1726
Table 442.TIMx internal trigger connection . . . . .1726
Table 443.CCR and ARR register change dithering pattern . . . . .1744
Table 444.Effect of low-power modes on TIM12/TIM13/TIM14 . . . . .1753
Table 445.Interrupt requests . . . . .1753
Table 446.Output control bit for standard tim_ocx channels . . . . .1766
Table 447.TIM12 register map and reset values . . . . .1770
Table 448.Output control bit for standard tim_ocx channels . . . . .1779
Table 449.TIM13/TIM14 register map and reset values . . . . .1782
Table 450.TIM input/output pins . . . . .1787
Table 451.TIM internal input/output signals . . . . .1788
Table 452.Interconnect to the tim_ti1 input multiplexer . . . . .1789
Table 453.Interconnect to the tim_ti2 input multiplexer . . . . .1789
Table 454.TIMx internal trigger connection . . . . .1789
Table 455.Timer break interconnect . . . . .1790
Table 456.System break interconnect . . . . .1790
Table 457.CCR and ARR register change dithering pattern . . . . .1810
Table 458.Break protection disarming conditions . . . . .1819
Table 459.DMA request . . . . .1830
Table 460.Effect of low-power modes on TIM15/TIM16/TIM17 . . . . .1831
Table 461.Interrupt requests . . . . .1831
Table 462.Output control bits for complementary tim_ocx and tim_ocxn channels with break feature (TIM15). . . . .1847
Table 463.TIM15 register map and reset values . . . . .1860
Table 464.Output control bits for complementary tim_oc1 and tim_oc1n channels with break feature (TIM16/TIM17) . . . . .1873
Table 465.TIM16/TIM17 register map and reset values . . . . .1887
Table 466.STM32H5 LPTIM features . . . . .1891
Table 467.LPTIM1/2/3/5/6 input/output pins . . . . .1893
Table 468.LPTIM4 input/output pins . . . . .1893
Table 469.LPTIM1/2/3/5/6 internal signals . . . . .1894
Table 470.LPTIM4 internal signals . . . . .1894
Table 471.LPTIM1/2/3/4/5/6 external trigger connections . . . . .1895
Table 472.LPTIM1/2/3/5/6 input 1 connections . . . . .1895
Table 473.LPTIM1/2/3/5/6 input 2 connections . . . . .1895
Table 474.LPTIM1/2/3/5/6 input capture 1 connections . . . . .1895
Table 475.LPTIM1 input capture 2 connections . . . . .1896
Table 476.LPTIM2 input capture 2 connections . . . . .1896
Table 477.LPTIM3/5/6 input capture 2 connections . . . . .1896
Table 478.Prescaler division ratios . . . . .1898
Table 479.Encoder counting scenarios . . . . .1905
Table 480.Input capture Glitch filter latency (in counter step unit). . . . .1909
Table 481.Effect of low-power modes on the LPTIM . . . . .1913
Table 482.Interrupt events . . . . .1914
Table 483.LPTIM register map and reset values . . . . .1938
Table 484.IWDG features . . . . .1941
Table 485.IWDG delays versus actions . . . . .1942
Table 486.IWDG internal input/output signals . . . . .1943
Table 487.Effect of low power modes on IWDG . . . . .1948
Table 488.IWDG interrupt request . . . . .1950
Table 489.IWDG register map and reset values . . . . .1956
Table 490.WWDG features . . . . .1957
Table 491.WWDG internal input/output signals . . . . .1958
Table 492.WWDG interrupt requests . . . . .1961
Table 493.WWDG register map and reset values . . . . .1963
Table 494.RTC input/output pins . . . . .1967
Table 495.RTC internal input/output signals . . . . .1967
Table 496.RTC interconnection . . . . .1968
Table 497.RTC pin PC13 configuration . . . . .1969
Table 498.PI8 configuration . . . . .1971
Table 499.RTC_OUT mapping . . . . .1972
Table 500.Effect of low-power modes on RTC . . . . .1987
Table 501.RTC pins functionality over modes . . . . .1987
Table 502.Nonsecure interrupt requests . . . . .1988
Table 503.Secure interrupt requests . . . . .1988
Table 504.RTC register map and reset values . . . . .2019
Table 505.TAMP input/output pins . . . . .2025
Table 506.TAMP internal input/output signals . . . . .2025
Table 507.TAMP interconnection . . . . .2026
Table 508.Device resource x tamper protection . . . . .2032
Table 509.Active tamper output change period . . . . .2035
Table 510.Minimum ATPER value. . . . .2036
Table 511.Active tamper filtered pulse duration . . . . .2037
Table 512.Effect of low-power modes on TAMP . . . . .2038
Table 513.TAMP pins functionality over modes . . . . .2039
Table 514.Interrupt requests . . . . .2039
Table 515.TAMP register map and reset values . . . . .2069
Table 516.I2C implementation. . . . .2072
Table 517.I2C input/output pins. . . . .2073
Table 518.I2C internal input/output signals . . . . .2074
Table 519.Comparison of analog and digital filters . . . . .2076
Table 520.I 2 C-bus and SMBus specification data setup and hold times . . . . .2078
Table 521.I2C configuration. . . . .2082
Table 522.I 2 C-bus and SMBus specification clock timings . . . . .2093
Table 523.Timing settings for f I2CCLK of 8 MHz. . . . .2103
Table 524.Timing settings for f I2CCLK of 16 MHz. . . . .2103
Table 525.SMBus timeout specifications. . . . .2105
Table 526.SMBus with PEC configuration. . . . .2107
Table 527.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms. . . . .2108
Table 528.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .2108
Table 529.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .2108
Table 530.Effect of low-power modes to I2C. . . . .2118
Table 531.I2C interrupt requests . . . . .2118
Table 532.I2C register map and reset values . . . . .2134
Table 533.I3C wake-up . . . . .2137
Table 534.I3C FIFOs implementation . . . . .2137
Table 535.I3C interrupt(s) . . . . .2137
Table 536.I3C peripheral controller/target features versus MIPI v1.1 . . . . .2138
Table 537.I3C input/output pins. . . . .2139
Table 538.I3C internal input/output signals . . . . .2139
Table 539.I3C register usage . . . . .2151
Table 540.I3C registers/fields usage versus controller state . . . . .2152
Table 541.I3C registers/fields usage versus target state. . . . .2155
Table 542.List of supported I3C CCCs, as controller/target . . . . .2158
Table 543.I3C controller error management . . . . .2189
Table 544.I3C target error management . . . . .2191
Table 545.Effect of low-power modes . . . . .2195
Table 546.I3C interrupt requests . . . . .2196
Table 547.I3C register map and reset values . . . . .2241
Table 548.Instance implementation. . . . .2245
Table 549.USART/LPUART features . . . . .2246
Table 550.USART/UART input/output pins . . . . .2248
Table 551.USART internal input/output signals. . . . .2249
Table 552.Noise detection from sampled data . . . . .2261
Table 553.Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .2265
Table 554.Tolerance of the USART receiver when BRR[3:0] is different from 0000. . . . .2265
Table 555.USART frame formats . . . . .2270
Table 556.Effect of low-power modes on the USART . . . . .2293
Table 557.USART interrupt requests. . . . .2294
Table 558.USART register map and reset values . . . . .2332
Table 559.Instance implementation on STM32H5 . . . . .2335
Table 560.USART/LPUART features . . . . .2335
Table 561.LPUART input/output pins . . . . .2338
Table 562.LPUART internal input/output signals . . . . .2338
Table 563.Error calculation for programmed baud rates at lpuart_ker_ck_pres= 32.768 kHz . . . . .2349
Table 564.Tolerance of the LPUART receiver . . . . .2350
Table 566.Effect of low-power modes on the LPUART . . . . .2362
Table 567.LPUART interrupt requests . . . . .2363
Table 568.LPUART register map and reset values . . . . .2389
Table 569.SPI features . . . . .2392
Table 570.SPI/I2S input/output pins . . . . .2395
Table 571.SPI internal input/output signals . . . . .2395
Table 572.Effect of low-power modes on the SPI . . . . .2422
Table 573.SPI wake-up and interrupt requests . . . . .2423
Table 574.Bitfields usable in PCM/I2S mode . . . . .2425
Table 575.WS and CK level before SPI/I2S is enabled when AFCNTR = 1 . . . . .2434
Table 576.Serial data line swapping . . . . .2434
Table 577.CLKGEN programming examples for usual I2S frequencies . . . . .2438
Table 578.I2S interrupt requests . . . . .2447
Table 579.SPI register map and reset values . . . . .2465
Table 580.STM32H5 SAI features . . . . .2468
Table 581.SAI internal input/output signals . . . . .2470
Table 582.SAI input/output pins . . . . .2470
Table 583.External synchronization selection . . . . .2473
Table 584.MCLK_x activation conditions . . . . .2478
Table 585.Clock generator programming examples . . . . .2481
Table 586.SAI_A configuration for TDM mode . . . . .2488
Table 587.TDM frame configuration examples . . . . .2490
Table 588.SOPD pattern . . . . .2494
Table 589.Parity bit calculation . . . . .2494
Table 590.Audio sampling frequency versus symbol rates . . . . .2495
Table 591.SAI interrupt sources . . . . .2504
Table 592.SAI register map and reset values . . . . .2533
Table 593.CAN subsystem I/O signals . . . . .2539
Table 594.CAN subsystem I/O pins . . . . .2539
Table 595.DLC coding in FDCAN . . . . .2543
Table 596.Possible configurations for frame transmission . . . . .2557
Table 597.Rx FIFO element . . . . .2560
Table 598.Rx FIFO element description . . . . .2560
Table 599.Tx buffer and FIFO element . . . . .2562
Table 600.Tx buffer element description . . . . .2562
Table 601.Tx event FIFO element . . . . .2564
Table 602.Tx event FIFO element description . . . . .2564
Table 603.Standard message ID filter element . . . . .2565
Table 604.Standard message ID filter element field description . . . . .2566
Table 605.Extended message ID filter element . . . . .2566
Table 606.Extended message ID filter element field description . . . . .2567
Table 607.FDCAN register map and reset values . . . . .2597
Table 608.STM32H5 USB implementation . . . . .2601
Table 609.USB input/output pins . . . . .2602
Table 610.Double-buffering buffer flag definition . . . . .2614
Table 611.Bulk double-buffering memory buffers usage (Device mode) . . . . .2614
Table 612.Bulk double-buffering memory buffers usage (Host mode) . . . . .2616
Table 613.Isochronous memory buffers usage . . . . .2617
Table 614.Isochronous memory buffers usage . . . . .2618
Table 615.Resume event detection . . . . .2620
Table 616.Resume event detection for host . . . . .2621
Table 617.Reception status encoding . . . . .2639
Table 618.Endpoint/channel type encoding . . . . .2639
Table 619.Endpoint/channel kind meaning . . . . .2639
Table 620.Transmission status encoding . . . . .2639
Table 621.USB register map and reset values . . . . .2641
Table 622.Definition of allocated buffer memory . . . . .2644
Table 623.USB SRAM register map and reset values . . . . .2647
Table 624.UCPD implementation . . . . .2649
Table 625.UCPD software trim data . . . . .2649
Table 626.UCPD signals on pins . . . . .2650
Table 627.UCPD internal signals . . . . .2651
Table 628.4b5b symbol encoding table . . . . .2653
Table 629.Ordered sets . . . . .2654
Table 630.Validation of ordered sets . . . . .2654
Table 631.Data size . . . . .2655
Table 632.Coding for ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx . . . . .2663
Table 633.Type-C sequence (source: 3A); cable/sink connected (Rd on CC1; Ra on CC2) . . . . .2665
Table 634.Effect of low power modes on the UCPD . . . . .2667
Table 635.UCPD interrupt requests . . . . .2668
Table 636.UCPD register map and reset values . . . . .2684
Table 637.Ethernet peripheral pins . . . . .2691
Table 638.Ethernet internal input/output signals . . . . .2692
Table 639.Priority scheme for Tx DMA and Rx DMA . . . . .2701
Table 640.Double VLAN processing features in Tx path . . . . .2707
Table 641.Double VLAN processing in Rx path . . . . .2708
Table 642.VLAN insertion or replacement based on VLTi bit . . . . .2709
Table 643.Destination address filtering . . . . .2712
Table 644.Source address filtering . . . . .2713
Table 645.VLAN match status . . . . .2714
Table 646.Ordinary clock: PTP messages for snapshot . . . . .2717
Table 647.End-to-end transparent clock: PTP messages for snapshot . . . . .2718
Table 648.Peer-to-peer transparent clock: PTP messages for snapshot . . . . .2719
Table 649.Egress and ingress latency for PHY interfaces . . . . .2722
Table 650.Minimum PTP clock frequency example . . . . .2723
Table 651.Message format defined in IEEE 1588-2008 . . . . .2724
Table 652.Message format defined in IEEE 1588-2008 . . . . .2724
Table 653.IPv6-UDP PTP packet fields required for control and status . . . . .2725
Table 654.Ethernet PTP packet fields required for control and status . . . . .2726
Table 655.Timestamp Snapshot Dependency on ETH_MACTSCR bits . . . . .2728
Table 656.PTP message generation criteria . . . . .2734
Table 657.Common PTP message header fields . . . . .2736
Table 658.MAC Transmit PTP mode and one-step timestamping operation . . . . .2739
Table 659.Transmit checksum offload engine functions for different packet types . . . . .2744
Table 660.Receive checksum offload engine functions for different packet types . . . . .2746
Table 661.TSO: TCP and IP header fields . . . . .2750
Table 662.Pause packet fields . . . . .2755
Table 663.Tx MAC flow control . . . . .2756
Table 664.Rx MAC flow control . . . . .2756
Table 665.Size of the maximum receive packet . . . . .2759
Table 666.MCD clock selection . . . . .2762
Table 667.MDIO Clause 45 frame structure . . . . .2763
Table 668.MDIO Clause 22 frame structure . . . . .2764
Table 669.Remote wake-up packet filter register . . . . .2775
Table 670.Description of the remote wake-up filter fields . . . . .2775
Table 671.Remote wake-up packet and PMT interrupt generation . . . . .2777
Table 672.Transfer complete interrupt behavior . . . . .2785
Table 673.TDES0 normal descriptor (read format) . . . . .2807
Table 674.TDES1 normal descriptor (read format) . . . . .2808
Table 675.TDES2 normal descriptor (read format) . . . . .2808
Table 676.TDES3 normal descriptor (read format) . . . . .2809
Table 677.TDES0 normal descriptor (write-back format). . . . .2812
Table 678.TDES1 normal descriptor (write-back format). . . . .2812
Table 679.TDES2 normal descriptor (write-back format). . . . .2813
Table 680.TDES3 normal descriptor (write-back format). . . . .2813
Table 681.TDES0 context descriptor. . . . .2816
Table 682.TDES1 context descriptor. . . . .2817
Table 683.TDES2 context descriptor. . . . .2817
Table 684.TDES3 context descriptor. . . . .2817
Table 685.RDES0 normal descriptor (read format) . . . . .2821
Table 686.RDES1 normal descriptor (read format) . . . . .2821
Table 687.RDES2 normal descriptor (read format) . . . . .2821
Table 688.RDES3 normal descriptor (read format) . . . . .2821
Table 689.RDES0 normal descriptor (write-back format) . . . . .2823
Table 690.RDES1 normal descriptor (write-back format) . . . . .2823
Table 691.RDES2 normal descriptor (write-back format) . . . . .2825
Table 692.RDES3 normal descriptor (write-back format) . . . . .2827
Table 693.RDES0 context descriptor . . . . .2830
Table 694.RDES1 context descriptor . . . . .2831
Table 695.RDES2 context descriptor . . . . .2831
Table 696.RDES3 context descriptor . . . . .2831
Table 697.ETH_DMA common register map and reset values . . . . .2853
Table 698.ETH_DMA_CH register map and reset values . . . . .2853
Table 699.ETH_MTL register map and reset values . . . . .2866
Table 700.Giant Packet Status based on S2KP and JE Bits . . . . .2872
Table 701.Packet Length based on the CST and ACS bits . . . . .2872
Table 702.Ethernet MAC register map and reset values . . . . .2953
Table 703.HDMI pin . . . . .2965
Table 704.HDMI-CEC internal input/output signals . . . . .2965
Table 705.Error handling timing parameters . . . . .2971
Table 706.TXERR timing parameters . . . . .2972
Table 707.HDMI-CEC interrupts . . . . .2973
Table 708.HDMI-CEC register map and reset values . . . . .2981
Table 709.JTAG/Serial-wire debug port pins . . . . .2983
Table 710.Trace port pins . . . . .2983
Table 711.Single-wire trace port pins . . . . .2984
Table 712.Authentication signal states with TrustZone enabled (TZEN = 0xB4) . . . . .2986
Table 713.Authentication signal states with TrustZone disabled (TZEN = 0xC3) . . . . .2986
Table 714.Life cycle state and debug states . . . . .2986
Table 715.Definition of data to provision . . . . .2989
Table 716.Permission mask (Endianness: Little Endian) . . . . .2989
Table 717.JTAG-DP data registers . . . . .2992
Table 718.Packet request . . . . .2994
Table 719.ACK response . . . . .2994
Table 720.Data transfer . . . . .2994
Table 721.Debug port registers . . . . .2995
Table 722.Debug port register map and reset values . . . . .3001
Table 723.MEM-AP registers . . . . .3003
Table 724.Access port register map and reset values . . . . .3009
Table 725.System ROM table . . . . .3010
Table 726.MCU ROM table . . . . .3011
Table 727.Processor ROM table . . . . .3011
Table 728.System ROM table register map and reset values . . . . .3017
Table 729.MCU ROM table register map and reset values . . . . .3022
Table 730.CPU ROM table register map and reset values . . . . .3028
Table 731.DWT register map and reset values . . . . .3043
Table 732.ITM register map and reset values . . . . .3054
Table 733.BPU register map and reset values . . . . .3062
Table 734.ETM register map and reset values . . . . .3087
Table 735.TPIU register map and reset values . . . . .3101
Table 736.CTI inputs . . . . .3103
Table 737.CTI outputs . . . . .3103
Table 738.CTI register map and reset values . . . . .3114
Table 739.Peripheral clock freeze control bits . . . . .3117
Table 740.Peripheral behaviour in debug mode . . . . .3118
Table 741.DBGMCU register map and reset values . . . . .3132
Table 742.Document revision history . . . . .3140

List of figures

Figure 1. System architecture . . . . . 107

Figure 2. Memory map based on IDAU mapping (STM32H562/563/573xx devices) . . . . . 116

Figure 3. Memory map based on IDAU mapping (STM32H523/533xx devices) . . . . . 117

Figure 4. Secure/nonsecure partitioning using TrustZone technology. . . . . 133

Figure 5. Sharing memory map between CPU in secure and nonsecure state . . . . . 135

Figure 6. Secure world transition and memory partitioning . . . . . 135

Figure 7. Global TrustZone framework and TrustZone awareness . . . . . 137

Figure 8. Flash memory TrustZone protections . . . . . 141

Figure 9. Flash memory secure HDP area . . . . . 148

Figure 10. Key management principle . . . . . 156

Figure 11. Device life cycle security. . . . . 159

Figure 12. PRODUCT_STATES (simplified TrustZone activated view) . . . . . 162

Figure 13. PRODUCT_STATES (full TrustZone activated view) . . . . . 163

Figure 14. Collaborative development principle . . . . . 165

Figure 15. External flash memory protection using SFI. . . . . 167

Figure 16. GTZC in Armv8-M subsystem block diagram. . . . . 174

Figure 17. GTZC block diagram. . . . . 177

Figure 18. Watermark memory protection controller (region x/subregions A and B) . . . . . 178

Figure 19. MPCBB block diagram . . . . . 179

Figure 20. Memory map: SRAM1, SRAM2/3 with ECC (STM32H562/72/73xx devices). . . . . 234

Figure 21. Memory map: SRAM1/3, SRAM2 with ECC (STM32H523/33xx devices) . . . . . 235

Figure 22. FLASH block diagram (simplified) . . . . . 247

Figure 23. Embedded flash memory organization (2-Mbyte devices) . . . . . 249

Figure 24. Embedded flash memory usage . . . . . 250

Figure 25. Flash high-cycle data memory map on 2-Mbyte devices . . . . . 263

Figure 26. Flash high-cycle data memory map on 1-Mbyte devices . . . . . 263

Figure 27. Flash high-cycle data memory map on 512-Kbyte devices . . . . . 264

Figure 28. Flash high-cycle data memory map on 256-Kbyte devices . . . . . 264

Figure 29. Flash bank swapping sequence . . . . . 267

Figure 30. OBK protection checks . . . . . 279

Figure 31. Key writing flow. . . . . 280

Figure 32. Swap workflow . . . . . 281

Figure 33. HDP in user flash memory (STM32H563/573xx devices). . . . . 286

Figure 34. Protection attributes in case of bank swap illustration . . . . . 291

Figure 35. ICACHE block diagram . . . . . 368

Figure 36. ICACHE TAG and data memories functional view . . . . . 370

Figure 37. ICACHE remapping address mechanism . . . . . 373

Figure 38. DCACHE block diagram . . . . . 385

Figure 39. DCACHE TAG and data memories functional view . . . . . 388

Figure 40. Power supply with SMPS (STM32H563/573xx devices only). . . . . 404

Figure 41. Power supply with LDO . . . . . 405

Figure 42. System supply configurations . . . . . 407

Figure 43. Power-on (POR) / power-down (PDR) reset waveform . . . . . 412

Figure 44. BOR thresholds . . . . . 413

Figure 45. PVD thresholds. . . . . 414

Figure 46. AVD thresholds. . . . . 415

Figure 47. VBAT thresholds. . . . . 416

Figure 48. Temperature thresholds . . . . . 417

Figure 49.Dynamic voltage scaling in Run mode . . . . .418
Figure 50.I/O states in Standby mode . . . . .428
Figure 51.Simplified diagram of the reset circuit. . . . .453
Figure 52.Clock tree . . . . .456
Figure 53.HSE/LSE clock sources . . . . .457
Figure 54.CSI calibration flow . . . . .460
Figure 55.PLL block diagram . . . . .461
Figure 56.PLLs initialization flow. . . . .464
Figure 57.CRS block diagram. . . . .564
Figure 58.CRS counter behavior . . . . .566
Figure 59.Structure of 3- or 5-V tolerant GPIO (TT or FT) . . . . .576
Figure 60.Input floating/pull-up/pull-down configurations . . . . .580
Figure 61.Output configuration . . . . .581
Figure 62.Alternate function configuration . . . . .582
Figure 63.High-impedance analog configuration . . . . .582
Figure 64.SBS block diagram . . . . .597
Figure 65.Compensation cell management . . . . .599
Figure 66.Compensation cell usage . . . . .600
Figure 67.SBS boot control. . . . .601
Figure 68.SBS debug control . . . . .604
Figure 69.SBS hardware secure storage control . . . . .606
Figure 70.GPDMA block diagram . . . . .641
Figure 71.GPDMA channel direct programming without linked-list (GPDMA_CxLLR = 0). . . . .642
Figure 72.GPDMA channel suspend and resume sequence . . . . .643
Figure 73.GPDMA channel abort and restart sequence. . . . .644
Figure 74.Static linked-list data structure (all Uxx = 1)
of a linear addressing channel x . . . . .		645
Figure 75.Static linked-list data structure (all Uxx = 1)
of a 2D addressing channel x . . . . .		646
Figure 76.GPDMA dynamic linked-list data structure
of a linear addressing channel x . . . . .		647
Figure 77.GPDMA dynamic linked-list data structure
of a 2D addressing channel x . . . . .		647
Figure 78.GPDMA channel execution and linked-list programming
in run-to-completion mode (GPDMA_CxCR.LSM = 0). . . . .		649
Figure 79.Inserting a LLI n with an auxiliary GPDMA channel y . . . . .651
Figure 80.GPDMA channel execution and linked-list programming
in link step mode (GPDMA_CxCR.LSM = 1) . . . . .		653
Figure 81.Building LLI n+1 : GPDMA dynamic linked-lists in link step mode . . . . .654
Figure 82.Replace with a new LLI n in register file in link step mode . . . . .655
Figure 83.Replace with a new LLI n and LLI n+1 in memory in link step mode (option 1) . . . . .656
Figure 84.Replace with a new LLI n and LLI n+1 in memory in link step mode (option 2) . . . . .657
Figure 85.GPDMA channel execution and linked-list programming . . . . .659
Figure 86.Programmed 2D addressing. . . . .662
Figure 87.GPDMA arbitration policy . . . . .669
Figure 88.Trigger hit, memorization, and overrun waveform . . . . .672
Figure 89.GPDMA circular buffer programming: update of the memory start address
with a linear addressing channel . . . . .		673
Figure 90.Shared GPDMA channel with circular buffering: update of the memory
start address with a linear addressing channel. . . . .		674
Figure 91.EXTI block diagram . . . . .723
Figure 92.Configurable event trigger logic CPU wake-up. . . . .726
Figure 93.EXTI direct events . . . . .727
Figure 94.EXTI mux GPIO selection. . . . .728
Figure 95.CRC calculation unit block diagram . . . . .757
Figure 96.CORDIC convergence for trigonometric functions . . . . .771
Figure 97.CORDIC convergence for hyperbolic functions . . . . .772
Figure 98.CORDIC convergence for square root . . . . .773
Figure 99.Block diagram . . . . .782
Figure 100.Input buffer areas . . . . .784
Figure 101.Circular input buffer . . . . .785
Figure 102.Circular input buffer operation . . . . .786
Figure 103.Circular output buffer . . . . .787
Figure 104.Circular output buffer operation . . . . .788
Figure 105.FIR filter structure . . . . .790
Figure 106.IIR filter structure (direct form 1) . . . . .792
Figure 107.X1 buffer initialization . . . . .797
Figure 108.Filtering example 1 . . . . .798
Figure 109.Filtering example 2 . . . . .799
Figure 110.FMC block diagram. . . . .811
Figure 111.FMC memory banks . . . . .813
Figure 112.Mode 1 read access waveforms . . . . .823
Figure 113.Mode 1 write access waveforms. . . . .823
Figure 114.Mode A read access waveforms. . . . .825
Figure 115.Mode A write access waveforms . . . . .825
Figure 116.Mode 2 and mode B read access waveforms. . . . .827
Figure 117.Mode 2 write access waveforms. . . . .828
Figure 118.Mode B write access waveforms . . . . .828
Figure 119.Mode C read access waveforms . . . . .830
Figure 120.Mode C write access waveforms . . . . .831
Figure 121.Mode D read access waveforms . . . . .833
Figure 122.Mode D write access waveforms . . . . .834
Figure 123.Muxed read access waveforms . . . . .836
Figure 124.Muxed write access waveforms . . . . .837
Figure 125.Asynchronous wait during a read access waveforms. . . . .839
Figure 126.Asynchronous wait during a write access waveforms. . . . .840
Figure 127.Wait configuration waveforms. . . . .842
Figure 128.Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM). . . . .843
Figure 129.Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . .845
Figure 130.NAND flash controller waveforms for common memory access. . . . .857
Figure 131.Access to non 'CE don't care' NAND-flash. . . . .859
Figure 132.Burst write SDRAM access waveforms . . . . .868
Figure 133.Burst read SDRAM access . . . . .869
Figure 134.Logic diagram of Read access with RBURST bit set (CAS=1, RPIPE=0) . . . . .870
Figure 135.Read access crossing row boundary . . . . .872
Figure 136.Write access crossing row boundary . . . . .872
Figure 137.Self-refresh mode . . . . .874
Figure 138.Power-down mode . . . . .875
Figure 139.OCTOSPI block diagram in octal configuration . . . . .887
Figure 140.OCTOSPI block diagram in quad configuration . . . . .887
Figure 141.OCTOSPI block diagram in dual-quad configuration . . . . .888
Figure 142.SDR read command in octal configuration . . . . .889
Figure 143.DTR read in octal-SPI mode with DQS (Macronix mode) example . . . . .892
Figure 144.SDR write command in octo-SPI mode example . . . . .894
Figure 145. DTR write in octal-SPI mode (Macronix mode) example . . . . .895
Figure 146. Example of HyperBus read operation. . . . .896
Figure 147. HyperBus write operation with initial latency . . . . .898
Figure 148. HyperBus read operation with additional latency . . . . .898
Figure 149. HyperBus write operation with additional latency . . . . .899
Figure 150. HyperBus write operation with no latency (register write). . . . .899
Figure 151. HyperBus read operation page crossing with latency. . . . .900
Figure 152. D0/D1 data ordering in octal-SPI DTR mode (Micron) - Read access . . . . .906
Figure 153. OctaRAM read operation with reverse data ordering D1/D0 . . . . .907
Figure 154. NCS when CKMODE = 0 (T = CLK period) . . . . .912
Figure 155. NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .913
Figure 156. NCS when CKMODE = 1 in DTR mode (T = CLK period) . . . . .913
Figure 157. NCS when CKMODE = 1 with an abort (T = CLK period). . . . .913
Figure 158. SDMMC “no response” and “no data” operations. . . . .942
Figure 159. SDMMC (multiple) block read operation. . . . .942
Figure 160. SDMMC (multiple) block write operation. . . . .943
Figure 161. SDMMC (sequential) stream read operation . . . . .943
Figure 162. SDMMC (sequential) stream write operation . . . . .943
Figure 163. SDMMC block diagram. . . . .945
Figure 164. SDMMC Command and data phase relation . . . . .947
Figure 165. Control unit . . . . .949
Figure 166. Command/response path . . . . .950
Figure 167. Command path state machine (CPSM) . . . . .951
Figure 168. Data path . . . . .957
Figure 169. DDR mode data packet clocking . . . . .958
Figure 170. DDR mode CRC status / boot acknowledgment clocking. . . . .958
Figure 171. Data path state machine (DPSM). . . . .959
Figure 172. CLKMUX unit . . . . .970
Figure 173. Linked list structures . . . . .972
Figure 174. Asynchronous interrupt generation. . . . .975
Figure 175. Synchronous interrupt period data read . . . . .976
Figure 176. Synchronous interrupt period data write . . . . .976
Figure 177. Asynchronous interrupt period data read . . . . .977
Figure 178. Asynchronous interrupt period data write . . . . .978
Figure 179. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25. . . . .981
Figure 180. Clock stop with SDMMC_CK for DDR50, SDR50, SDR104. . . . .981
Figure 181. Read Wait with SDMMC_CK < 50 MHz . . . . .982
Figure 182. Read Wait with SDMMC_CK > 50 MHz . . . . .982
Figure 183. CMD12 stream timing . . . . .985
Figure 184. CMD5 Sleep Awake procedure . . . . .987
Figure 185. Normal boot mode operation . . . . .989
Figure 186. Alternative boot mode operation. . . . .990
Figure 187. Command response R1b busy signaling . . . . .991
Figure 188. SDMMC state control . . . . .992
Figure 189. Card cycle power / power up diagram . . . . .993
Figure 190. CMD11 signal voltage switch sequence . . . . .994
Figure 191. Voltage switch transceiver typical application. . . . .996
Figure 192. DLYB block diagram. . . . .1024
Figure 193. ADC block diagram . . . . .1032
Figure 194. ADC clock scheme . . . . .1037
Figure 195. ADC1 connectivity . . . . .1038
Figure 196. ADC2 connectivity . . . . .1039
Figure 197. ADC calibration. . . . .1042
Figure 198. Updating the ADC calibration factor . . . . .1043
Figure 199. Mixing single-ended and differential channels . . . . .1044
Figure 200. Enabling / disabling the ADC . . . . .1045
Figure 201. Bulb mode timing diagram . . . . .1048
Figure 202. Analog-to-digital conversion time . . . . .1051
Figure 203. Stopping ongoing regular conversions . . . . .1052
Figure 204. Stopping ongoing regular and injected conversions . . . . .1053
Figure 205. Triggers shared between ADC master and slave . . . . .1054
Figure 206. Injected conversion latency . . . . .1056
Figure 207. Example of ADC_JSQR queue of context (sequence change) . . . . .1059
Figure 208. Example of ADC_JSQR queue of context (trigger change) . . . . .1059
Figure 209. Example of ADC_JSQR queue of context with overflow before conversion. . . . .1060
Figure 210. Example of ADC_JSQR queue of context with overflow during conversion . . . . .1060
Figure 211. Example of ADC_JSQR queue of context with empty queue (case JQM = 0). . . . .1061
Figure 212. Example of ADC_JSQR queue of context with empty queue (JQM = 1) . . . . .1062
Figure 213. Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0) -
JADSTP occurs during an ongoing conversion. . . . .		1062
Figure 214. Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0) -
JADSTP occurs during an ongoing conversion and a new
trigger occurs . . . . .		1063
Figure 215. Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0) -
JADSTP occurs outside an ongoing conversion. . . . .		1063
Figure 216. Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 1) . . . . .1064
Figure 217. Flushing ADC_JSQR queue of context by setting ADDIS = 1 (JQM = 0). . . . .1064
Figure 218. Flushing ADC_JSQR queue of context by setting ADDIS = 1 (JQM = 1). . . . .1065
Figure 219. Single conversions of a sequence, software trigger . . . . .1067
Figure 220. Continuous conversion of a sequence, software trigger. . . . .1067
Figure 221. Single conversions of a sequence, hardware trigger . . . . .1068
Figure 222. Continuous conversions of a sequence, hardware trigger . . . . .1068
Figure 223. Right alignment (offset disabled, unsigned value) . . . . .1070
Figure 224. Right alignment (offset enabled, signed value). . . . .1071
Figure 225. Left alignment (offset disabled, unsigned value) . . . . .1071
Figure 226. Left alignment (offset enabled, signed value). . . . .1072
Figure 227. Example of overrun (OVRMOD = 0). . . . .1073
Figure 228. Example of overrun (OVRMOD = 1). . . . .1074
Figure 229. AUTODLY = 1, regular conversion in continuous mode, software trigger . . . . .1077
Figure 230. AUTODLY = 1, regular HW conversions interrupted by injected conversions
(DISCEN = 0; JDISCEN = 0) . . . . .		1077
Figure 231. AUTODLY = 1, regular HW conversions interrupted by injected conversions . . . . .
(DISCEN = 1, JDISCEN = 1) . . . . .		1078
Figure 232. AUTODLY = 1, regular continuous conversions interrupted by injected conversions . . . . .1079
Figure 233. AUTODLY = 1 in auto- injected mode (JAUTO = 1). . . . .1079
Figure 234. Analog watchdog guarded area . . . . .1080
Figure 235. ADC y _AWD x _OUT signal generation (on all regular channels). . . . .1082
Figure 236. ADC y _AWD x _OUT signal generation (AWD x flag not cleared by software) . . . . .1083
Figure 237. ADC y _AWD x _OUT signal generation (on a single regular channel) . . . . .1083
Figure 238. ADC y _AWD x _OUT signal generation (on all injected channels) . . . . .1083
Figure 239. 20-bit to 16-bit result truncation . . . . .1085
Figure 240. Numerical example with 5-bit shift and rounding . . . . .1085
Figure 241. Triggered regular oversampling mode (TROVS bit = 1). . . . .1087
Figure 242. Regular oversampling modes (4x ratio) . . . . .1088
Figure 243. Regular and injected oversampling modes used simultaneously . . . . .1089
Figure 244. Triggered regular oversampling with injection . . . . .1089
Figure 245. Oversampling in auto-injected mode . . . . .1090
Figure 246. Dual ADC block diagram (1) . . . . .1092
Figure 247. Injected simultaneous mode on 4 channels: dual ADC mode . . . . .1093
Figure 248. Regular simultaneous mode on 16 channels: dual ADC mode . . . . .1095
Figure 249. Interleaved mode on one channel in continuous conversion mode: dual ADC mode. . . . .1096
Figure 250. Interleaved mode on 1 channel in single conversion mode: dual ADC mode. . . . .1097
Figure 251. Interleaved conversion with injection . . . . .1097
Figure 252. Alternate trigger: injected group of each ADC . . . . .1098
Figure 253. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode. . . . .1099
Figure 254. Alternate + regular simultaneous . . . . .1100
Figure 255. Case of trigger occurring during injected conversion . . . . .1100
Figure 256. Interleaved single channel CH0 with injected sequence CH11, CH12. . . . .1101
Figure 257. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first. . . . .		1101
Figure 258. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first. . . . .		1101
Figure 259. DMA Requests in regular simultaneous mode when MDMA = 0b00 . . . . .1102
Figure 260. DMA requests in regular simultaneous mode when MDMA = 0b10 . . . . .1103
Figure 261. DMA requests in interleaved mode when MDMA = 0b10. . . . .1103
Figure 262. Temperature sensor channel block diagram . . . . .1105
Figure 263. VBAT channel block diagram . . . . .1107
Figure 264. VREFINT channel block diagram . . . . .1107
Figure 265. Temperature sensor functional block diagram . . . . .1151
Figure 266. Method for low REF_CLK frequencies . . . . .1153
Figure 267. Method for high REF_CLK frequencies . . . . .1153
Figure 268. Temperature sensor sequence. . . . .1156
Figure 269. Dual-channel DAC block diagram . . . . .1169
Figure 270. Data registers in single DAC channel mode. . . . .1172
Figure 271. Data registers in dual DAC channel mode . . . . .1172
Figure 272. Timing diagram for conversion with trigger disabled TEN = 0 . . . . .1174
Figure 273. DAC LFSR register calculation algorithm . . . . .1176
Figure 274. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . .1177
Figure 275. DAC triangle wave generation . . . . .1177
Figure 276. DAC conversion (SW trigger enabled) with triangle wave generation . . . . .1178
Figure 277. DAC sample and hold mode phase diagram . . . . .1180
Figure 278. VREFBUF block diagram . . . . .1207
Figure 279. DCMI block diagram . . . . .1212
Figure 280. DCMI signal waveforms . . . . .1213
Figure 281. Timing diagram. . . . .1215
Figure 282. Frame capture waveforms in snapshot mode. . . . .1217
Figure 283. Frame capture waveforms in continuous grab mode . . . . .1218
Figure 284. Coordinates and size of the window after cropping . . . . .1218
Figure 285. Data capture waveforms. . . . .1219
Figure 286. Pixel raster scan order . . . . .1220
Figure 287. PSSI block diagram . . . . .1234
Figure 288. Top-level block diagram . . . . .1234
Figure 289. Data enable in receive mode waveform diagram (CKPOL=0) . . . . .1238
Figure 290. Data enable waveform diagram in transmit mode (CKPOL=1). . . . .1238
Figure 291. Ready in receive mode waveform diagram (CKPOL=0). . . . .1239
Figure 292. Bidirectional PSSI_DE/PSSI_RDY waveform . . . . .1240
Figure 293. Bidirectional PSSI_DE/PSSI_RDY connection diagram . . . . .1240
Figure 294. RNG block diagram . . . . .1248
Figure 295. NIST SP800-90B entropy source model. . . . .1249
Figure 296. RNG initialization overview . . . . .1252
Figure 297. AES block diagram . . . . .1266
Figure 298. Encryption/ decryption typical usage . . . . .1267
Figure 299. Typical operation with authentication . . . . .1270
Figure 300. Example of suspend mode management . . . . .1271
Figure 301. ECB encryption . . . . .1272
Figure 302. ECB decryption . . . . .1272
Figure 303. CBC encryption . . . . .1272
Figure 304. CBC decryption . . . . .1273
Figure 305. Message construction in CTR mode . . . . .1275
Figure 306. CTR encryption . . . . .1276
Figure 307. Message construction in GCM . . . . .1277
Figure 308. GCM authenticated encryption . . . . .1279
Figure 309. Message construction in GMAC mode . . . . .1282
Figure 310. GMAC authentication mode . . . . .1283
Figure 311. Message construction in CCM mode . . . . .1284
Figure 312. CCM mode authenticated encryption . . . . .1285
Figure 313. 128-bit block construction according to the data type. . . . .1290
Figure 314. SAES block diagram . . . . .1312
Figure 315. Encryption/ decryption typical usage . . . . .1314
Figure 316. Typical operation with authentication . . . . .1316
Figure 317. Example of suspend mode management . . . . .1317
Figure 318. ECB encryption . . . . .1318
Figure 319. ECB decryption . . . . .1318
Figure 320. CBC encryption . . . . .1319
Figure 321. CBC decryption . . . . .1319
Figure 322. Message construction in CTR mode . . . . .1322
Figure 323. CTR encryption . . . . .1323
Figure 324. Message construction in GCM . . . . .1324
Figure 325. GCM authenticated encryption . . . . .1326
Figure 326. Message construction in GMAC mode . . . . .1329
Figure 327. GMAC authentication mode . . . . .1329
Figure 328. Message construction in CCM mode . . . . .1330
Figure 329. CCM mode authenticated encryption . . . . .1332
Figure 330. Operation with wrapped keys for SAES in ECB and CBC modes . . . . .1335
Figure 331. Operation with wrapped keys for SAES in CTR mode . . . . .1338
Figure 332. Usage of Shared-key mode . . . . .1339
Figure 333. 128-bit block construction according to the data type. . . . .1342
Figure 334. Key protection mechanisms . . . . .1344
Figure 335. HASH block diagram . . . . .1366
Figure 336. Message data swapping feature. . . . .1368
Figure 337. HASH suspend/resume mechanism. . . . .1374
Figure 338. PKA block diagram . . . . .1388
Figure 339. OTFDEC block diagram . . . . .1421
Figure 340. Typical OTFDEC use in a SoC . . . . .1422
Figure 341. AES CTR decryption flow . . . . .1423
Figure 342. OTFDEC flow control overview (dual burst read request) . . . . .1424
Figure 343. Advanced-control timer block diagram . . . . .1444
Figure 344. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1450
Figure 345.Counter timing diagram with prescaler division change from 1 to 4 . . . . .1450
Figure 346.Counter timing diagram, internal clock divided by 1 . . . . .1452
Figure 347.Counter timing diagram, internal clock divided by 2 . . . . .1452
Figure 348.Counter timing diagram, internal clock divided by 4 . . . . .1453
Figure 349.Counter timing diagram, internal clock divided by N . . . . .1453
Figure 350.Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded). . . . .		1454
Figure 351.Counter timing diagram, update event when ARPE = 1
(TIMx_ARR preloaded). . . . .		1455
Figure 352.Counter timing diagram, internal clock divided by 1 . . . . .1456
Figure 353.Counter timing diagram, internal clock divided by 2 . . . . .1457
Figure 354.Counter timing diagram, internal clock divided by 4 . . . . .1457
Figure 355.Counter timing diagram, internal clock divided by N . . . . .1458
Figure 356.Counter timing diagram, update event when repetition counter is not used. . . . .1458
Figure 357.Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1460
Figure 358.Counter timing diagram, internal clock divided by 2 . . . . .1460
Figure 359.Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .1461
Figure 360.Counter timing diagram, internal clock divided by N . . . . .1461
Figure 361.Counter timing diagram, update event with ARPE = 1 (counter underflow) . . . . .1462
Figure 362.Counter timing diagram, Update event with ARPE = 1 (counter overflow) . . . . .1463
Figure 363.Update rate examples depending on mode and TIMx_RCR register settings . . . . .1464
Figure 365.Control circuit in normal mode, internal clock divided by 1 . . . . .1466
Figure 366.tim_ti2 external clock connection example . . . . .1466
Figure 367.Control circuit in external clock mode 1 . . . . .1467
Figure 368.External trigger input block . . . . .1468
Figure 369.Control circuit in external clock mode 2 . . . . .1469
Figure 370.Capture/compare channel (example: channel 1 input stage) . . . . .1469
Figure 371.Capture/compare channel 1 main circuit . . . . .1470
Figure 372.Output stage of capture/compare channel (channel 1, idem ch. 2, 3 and 4) . . . . .1471
Figure 373.Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .1471
Figure 374.PWM input mode timing . . . . .1474
Figure 375.Output compare mode, toggle on tim_oc1 . . . . .1476
Figure 376.Edge-aligned PWM waveforms (ARR = 8) . . . . .1477
Figure 377.Center-aligned PWM waveforms (ARR = 8). . . . .1478
Figure 378.Dithering principle . . . . .1479
Figure 379.Data format and register coding in dithering mode. . . . .1480
Figure 380.PWM resolution vs frequency . . . . .1481
Figure 381.PWM dithering pattern . . . . .1482
Figure 382.Dithering effect on duty cycle in center-aligned PWM mode . . . . .1483
Figure 383.Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1485
Figure 384.Combined PWM mode on channel 1 and 3 . . . . .1486
Figure 385.3-phase combined PWM signals with multiple trigger pulses per period . . . . .1487
Figure 386.Complementary output with symmetrical dead-time insertion . . . . .1488
Figure 387.Asymmetrical deadtime . . . . .1489
Figure 388.Dead-time waveforms with delay greater than the negative pulse . . . . .1489
Figure 389.Dead-time waveforms with delay greater than the positive pulse. . . . .1489
Figure 390.Break and Break2 circuitry overview . . . . .1492
Figure 391.Various output behavior in response to a break event on tim_brk (OSSI = 1) . . . . .1494
Figure 392.PWM output state following tim_brk and tim_brk2 assertion (OSSI = 1) . . . . .1495
Figure 393.PWM output state following tim_brk assertion (OSSI = 0) . . . . .1496
Figure 394.Output redirection (tim_brk2 request not represented). . . . .1497
Figure 395.tim_ocref_clr input selection multiplexer. . . . .1498
Figure 396. Clearing TIMx tim_ocxref . . . . .1499
Figure 397. 6-step generation, COM example (OSSR = 1) . . . . .1500
Figure 398. Example of one pulse mode. . . . .1501
Figure 399. Retriggerable one-pulse mode . . . . .1502
Figure 400. Pulse generator circuitry . . . . .1503
Figure 401. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .1504
Figure 402. Extended pulsewidth in case of concurrent triggers . . . . .1505
Figure 403. Example of counter operation in encoder interface mode. . . . .1507
Figure 404. Example of encoder interface mode with tim_ti1fp1 polarity inverted. . . . .1507
Figure 405. Quadrature encoder counting modes . . . . .1508
Figure 406. Direction plus clock encoder mode. . . . .1509
Figure 407. Directional clock encoder mode (CC1P = CC2P = 0). . . . .1509
Figure 408. Directional clock encoder mode (CC1P = CC2P = 1). . . . .1510
Figure 409. Index gating options . . . . .1511
Figure 410. Jittered Index signals . . . . .1511
Figure 411. Index generation for IPOS[1:0] = 11 . . . . .1512
Figure 412. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .1512
Figure 413. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .1513
Figure 414. Counter reading with index gated on channel A and B. . . . .1513
Figure 415. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11). . . . .1514
Figure 416. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .1515
Figure 417. Index behavior in x1 and x2 mode (IPOS[1:0] = 01). . . . .1516
Figure 418. Directional index sensitivity. . . . .1516
Figure 419. Counter reset as function of FIDX bit setting . . . . .1517
Figure 420. Index blanking. . . . .1517
Figure 421. Index behavior in clock + direction mode, IPOS[0] = 1. . . . .1518
Figure 422. Index behavior in directional clock mode, IPOS[0] = 1 . . . . .1518
Figure 423. State diagram for quadrature encoded signals. . . . .1519
Figure 424. Up-counting encoder error detection . . . . .1520
Figure 425. Down-counting encode error detection. . . . .1521
Figure 426. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .1522
Figure 427. Measuring time interval between edges on three signals. . . . .1523
Figure 428. Example of Hall sensor interface . . . . .1525
Figure 429. Control circuit in reset mode . . . . .1526
Figure 430. Control circuit in Gated mode . . . . .1527
Figure 431. Control circuit in trigger mode. . . . .1528
Figure 432. Control circuit in external clock mode 2 + trigger mode . . . . .1529
Figure 433. General-purpose timer block diagram . . . . .1587
Figure 434. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1592
Figure 435. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1593
Figure 436. Counter timing diagram, internal clock divided by 1 . . . . .1594
Figure 437. Counter timing diagram, internal clock divided by 2 . . . . .1594
Figure 438. Counter timing diagram, internal clock divided by 4 . . . . .1595
Figure 439. Counter timing diagram, internal clock divided by N. . . . .1595
Figure 440. Counter timing diagram, Update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .1596
Figure 441. Counter timing diagram, Update event when ARPE = 1 (TIMx_ARR preloaded). . . . .1597
Figure 442. Counter timing diagram, internal clock divided by 1 . . . . .1598
Figure 443. Counter timing diagram, internal clock divided by 2 . . . . .1599
Figure 444. Counter timing diagram, internal clock divided by 4 . . . . .1599
Figure 445. Counter timing diagram, internal clock divided by N. . . . .1600
Figure 446. Counter timing diagram, Update event. . . . .1600
Figure 447. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1602
Figure 448. Counter timing diagram, internal clock divided by 2 . . . . .1602
Figure 449. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .1603
Figure 450. Counter timing diagram, internal clock divided by N . . . . .1603
Figure 451. Counter timing diagram, Update event with ARPE = 1 (counter underflow). . . . .1604
Figure 452. Counter timing diagram, Update event with ARPE = 1 (counter overflow). . . . .1605
Figure 453. Control circuit in normal mode, internal clock divided by 1 . . . . .1606
Figure 454. tim_ti2 external clock connection example . . . . .1606
Figure 455. Control circuit in external clock mode 1 . . . . .1607
Figure 456. External trigger input block . . . . .1608
Figure 457. Control circuit in external clock mode 2 . . . . .1609
Figure 458. Capture/compare channel (example: channel 1 input stage). . . . .1609
Figure 459. Capture/compare channel 1 main circuit . . . . .1610
Figure 460. Output stage of capture/compare channel (channel 1, idem ch.2, 3 and 4). . . . .1610
Figure 461. PWM input mode timing . . . . .1613
Figure 462. Output compare mode, toggle on tim_oc1 . . . . .1615
Figure 463. Edge-aligned PWM waveforms (ARR = 8). . . . .1616
Figure 464. Center-aligned PWM waveforms (ARR = 8). . . . .1617
Figure 465. Dithering principle . . . . .1618
Figure 466. Data format and register coding in dithering mode . . . . .1619
Figure 467. PWM resolution vs frequency (16-bit mode). . . . .1620
Figure 468. PWM resolution vs frequency (32-bit mode). . . . .1620
Figure 469. PWM dithering pattern . . . . .1621
Figure 470. Dithering effect on duty cycle in center-aligned PWM mode . . . . .1622
Figure 471. Generation of two phase-shifted PWM signals with 50% duty cycle . . . . .1624
Figure 472. Combined PWM mode on channels 1 and 3 . . . . .1625
Figure 473. OCREF_CLR input selection multiplexer . . . . .1626
Figure 474. Clearing TIMx tim_ocxref . . . . .1626
Figure 475. Example of One-pulse mode . . . . .1627
Figure 476. Retriggerable one-pulse mode . . . . .1629
Figure 477. Pulse generator circuitry . . . . .1630
Figure 478. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .1630
Figure 479. Extended pulse width in case of concurrent triggers . . . . .1631
Figure 480. Example of counter operation in encoder interface mode . . . . .1633
Figure 481. Example of encoder interface mode with tim_ti1fp1 polarity inverted . . . . .1633
Figure 482. Quadrature encoder counting modes . . . . .1634
Figure 483. Direction plus clock encoder mode . . . . .1635
Figure 484. Directional clock encoder mode (CC1P = CC2P = 0). . . . .1636
Figure 485. Directional clock encoder mode (CC1P = CC2P = 1). . . . .1636
Figure 486. Index gating options . . . . .1638
Figure 487. Jittered Index signals . . . . .1638
Figure 488. Index generation for IPOS[1:0] = 11 . . . . .1639
Figure 489. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .1639
Figure 490. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .1640
Figure 491. Counter reading with index gated on channel A and B . . . . .1640
Figure 492. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11). . . . .1641
Figure 493. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .1642
Figure 494. Index behavior in x1 and x2 mode (IPOS[1:0] = 01). . . . .1643
Figure 495. Directional index sensitivity . . . . .1643
Figure 496. Counter reset as function of FIDX bit setting . . . . .1644
Figure 497. Index blanking . . . . .1644
Figure 498. Index behavior in clock + direction mode, IPOS[0] = 1. . . . .1645
Figure 499. Index behavior in directional clock mode, IPOS[0] = 1 . . . . .1645
Figure 500. State diagram for quadrature encoded signals . . . . .1646
Figure 501. Up-counting encoder error detection . . . . .1647
Figure 502. Down-counting encode error detection . . . . .1648
Figure 503. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .1649
Figure 504. Control circuit in reset mode . . . . .1651
Figure 505. Control circuit in gated mode . . . . .1652
Figure 506. Control circuit in trigger mode . . . . .1652
Figure 507. Control circuit in external clock mode 2 + trigger mode . . . . .1654
Figure 508. Master/Slave timer example . . . . .1654
Figure 509. Master/slave connection example with 1 channel only timers . . . . .1655
Figure 510. Gating TIM_slv with tim_oc1ref of TIM_mstr . . . . .1656
Figure 511. Gating TIM_slv with Enable of TIM_mstr . . . . .1657
Figure 512. Triggering TIM_slv with update of TIM_mstr. . . . .1658
Figure 513. Triggering TIM_slv with Enable of TIM_mstr . . . . .1658
Figure 514. Triggering TIM_mstr and TIM_slv with TIM_mstr tim_ti1 input. . . . .1659
Figure 515. Basic timer block diagram. . . . .1703
Figure 516. Control circuit in normal mode, internal clock divided by 1 . . . . .1704
Figure 517. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1705
Figure 518. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1706
Figure 519. Counter timing diagram, internal clock divided by 1 . . . . .1707
Figure 520. Counter timing diagram, internal clock divided by 2 . . . . .1707
Figure 521. Counter timing diagram, internal clock divided by 4 . . . . .1708
Figure 522. Counter timing diagram, internal clock divided by N . . . . .1708
Figure 523. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .1709
Figure 524. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR preloaded). . . . .1710
Figure 525. Dithering principle . . . . .1711
Figure 526. Data format and register coding in dithering mode . . . . .1711
Figure 527. FCnt resolution vs frequency . . . . .1712
Figure 528. PWM dithering pattern . . . . .1712
Figure 529. General-purpose timer block diagram (TIM12). . . . .1723
Figure 530. General-purpose timer block diagram (TIM13/TIM14) (2) . . . . .1724
Figure 531. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1728
Figure 532. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1728
Figure 533. Counter timing diagram, internal clock divided by 1 . . . . .1729
Figure 534. Counter timing diagram, internal clock divided by 2 . . . . .1730
Figure 535. Counter timing diagram, internal clock divided by 4 . . . . .1730
Figure 536. Counter timing diagram, internal clock divided by N . . . . .1731
Figure 537. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .1731
Figure 538. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR preloaded). . . . .1732
Figure 539. Control circuit in normal mode, internal clock divided by 1 . . . . .1733
Figure 540. tim_ti2 external clock connection example . . . . .1733
Figure 541. Control circuit in external clock mode 1 . . . . .1734
Figure 542. Capture/compare channel 1 input stage (TIM13/TIM14) . . . . .1735
Figure 543. Capture/compare channel 1 input stage (TIM12). . . . .1735
Figure 544. Capture/compare channel 1 main circuit . . . . .1736
Figure 545. Output stage of capture/compare channel 1 . . . . .1736
Figure 546. PWM input mode timing . . . . .1738
Figure 547. Output compare mode, toggle on tim_oc1. . . . .1740
Figure 548. Edge-aligned PWM waveforms (ARR = 8) . . . . .1741
Figure 549. Dithering principle . . . . .1742
Figure 550. Data format and register coding in dithering mode . . . . .1742
Figure 551. PWM resolution vs frequency . . . . .1743
Figure 552. PWM dithering pattern . . . . .1744
Figure 553. Combined PWM mode on channel 1 and 2 . . . . .1746
Figure 554. Example of one pulse mode . . . . .1747
Figure 555. Retriggerable one pulse mode . . . . .1748
Figure 556. Measuring time interval between edges on 2 signals . . . . .1749
Figure 557. Control circuit in reset mode . . . . .1750
Figure 558. Control circuit in gated mode . . . . .1751
Figure 559. Control circuit in trigger mode . . . . .1751
Figure 560. TIM15 block diagram . . . . .1786
Figure 561. TIM16/TIM17 block diagram (3) . . . . .1787
Figure 562. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1791
Figure 563. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1792
Figure 564. Counter timing diagram, internal clock divided by 1 . . . . .1793
Figure 565. Counter timing diagram, internal clock divided by 2 . . . . .1794
Figure 566. Counter timing diagram, internal clock divided by 4 . . . . .1794
Figure 567. Counter timing diagram, internal clock divided by N . . . . .1795
Figure 568. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded) . . . . .		1795
Figure 569. Counter timing diagram, update event when ARPE = 1
(TIMx_ARR preloaded) . . . . .		1796
Figure 570. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1797
Figure 571. Control circuit in normal mode, internal clock divided by 1 . . . . .1798
Figure 572. tim_ti2 external clock connection example . . . . .1798
Figure 573. Control circuit in external clock mode 1 . . . . .1799
Figure 574. Capture/compare channel (example: channel 1 input stage) . . . . .1800
Figure 575. Capture/compare channel 1 main circuit . . . . .1800
Figure 576. Output stage of capture/compare channel (channel 1) . . . . .1801
Figure 577. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .1801
Figure 578. PWM input mode timing . . . . .1804
Figure 579. Output compare mode, toggle on tim_oc1 . . . . .1806
Figure 580. Edge-aligned PWM waveforms (ARR = 8) . . . . .1807
Figure 581. Dithering principle . . . . .1808
Figure 582. Data format and register coding in dithering mode . . . . .1808
Figure 583. PWM resolution vs frequency . . . . .1809
Figure 584. PWM dithering pattern . . . . .1810
Figure 585. Combined PWM mode on channel 1 and 2 . . . . .1812
Figure 586. Complementary output with symmetrical dead-time insertion . . . . .1813
Figure 587. Asymmetrical deadtime . . . . .1814
Figure 588. Dead-time waveforms with delay greater than the negative pulse . . . . .1814
Figure 589. Dead-time waveforms with delay greater than the positive pulse . . . . .1814
Figure 590. Break circuitry overview . . . . .1816
Figure 591. Output behavior in response to a break event on tim_brk . . . . .1818
Figure 592. Output redirection . . . . .1820
Figure 593. tim_ocref_clr input selection multiplexer . . . . .1821
Figure 594. 6-step generation, COM example (OSSR = 1) . . . . .1822
Figure 595. Example of one pulse mode . . . . .1823
Figure 596. Retriggerable one pulse mode . . . . .1825
Figure 597. Measuring time interval between edges on 2 signals . . . . .1825
Figure 598. Control circuit in reset mode . . . . .1826
Figure 599. Control circuit in gated mode . . . . .1827
Figure 600. Control circuit in trigger mode . . . . .1828
Figure 601. LPTIM1/2/3/5/6 block diagram (1) . . . . .1892
Figure 602. LPTIM4 block diagram(1) . . . . .1893
Figure 603. Glitch filter timing diagram . . . . .1897
Figure 604. LPTIM output waveform, single-counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . .		1899
Figure 605. LPTIM output waveform, single-counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . .		1900
Figure 606. LPTIM output waveform, Continuous counting mode configuration . . . . .1900
Figure 607. Waveform generation . . . . .1902
Figure 608. Encoder mode counting sequence . . . . .1906
Figure 609. Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . .		1907
Figure 610. Capture/compare input stage (channel 1) . . . . .1908
Figure 611. Capture/compare output stage (channel 1) . . . . .1908
Figure 612. Edge-aligned PWM mode (PRELOAD = 1) . . . . .1910
Figure 613. Edge-aligned PWM waveforms (ARR=8 and CCxP = 0) . . . . .1911
Figure 614. PWM mode with immediate update versus preloaded update . . . . .1912
Figure 615. Independent watchdog block diagram . . . . .1942
Figure 616. Reset timing due to timeout . . . . .1944
Figure 617. Reset timing due to refresh in the not allowed area . . . . .1945
Figure 618. Changing PR, RL, and performing a refresh (1) . . . . .1946
Figure 619. Window comparator update (1) . . . . .1947
Figure 620. Independent watchdog interrupt timing diagram. . . . .1949
Figure 621. Early wake-up comparator update (1) . . . . .1950
Figure 622. Watchdog block diagram . . . . .1958
Figure 623. Window watchdog timing diagram . . . . .1960
Figure 624. RTC block diagram . . . . .1966
Figure 625. TAMP block diagram . . . . .2024
Figure 626. Backup registers protection zones . . . . .2029
Figure 627. Tamper sampling with precharge pulse . . . . .2034
Figure 628. Low level detection with precharge and filtering . . . . .2034
Figure 629. Active tamper filtering . . . . .2036
Figure 630. Block diagram . . . . .2073
Figure 631. I 2 C-bus protocol . . . . .2075
Figure 632. Setup and hold timings . . . . .2077
Figure 633. I2C initialization flow . . . . .2079
Figure 634. Data reception . . . . .2080
Figure 635. Data transmission . . . . .2081
Figure 636. Target initialization flow . . . . .2084
Figure 637. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .2086
Figure 638. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .2087
Figure 639. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .2088
Figure 640. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .2089
Figure 641. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .2090
Figure 642. Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . .		2090
Figure 643. Controller clock generation . . . . .2092
Figure 644. Controller initialization flow . . . . .2094
Figure 645. 10-bit address read access with HEAD10R = 0 . . . . .2094
Figure 646.10-bit address read access with HEAD10R = 1 . . . . .2095
Figure 647.Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .2096
Figure 648.Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .2097
Figure 649.Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		2098
Figure 650.Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .2100
Figure 651.Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .2101
Figure 652.Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		2102
Figure 653.Timeout intervals for t LOW:SEXT , t LOW:MEXT . . . . .2106
Figure 654.Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .2109
Figure 655.Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .2110
Figure 656.Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .2111
Figure 657.Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .2112
Figure 658.Bus transfer diagrams for SMBus controller transmitter . . . . .2113
Figure 659.Bus transfer diagrams for SMBus controller receiver . . . . .2115
Figure 660.I3C block diagram. . . . .2139
Figure 661.I3C (primary) controller state and programming sequence diagram. . . . .2143
Figure 662.I3C target state and programing sequence diagram . . . . .2148
Figure 663.I3C CCC messages, as controller . . . . .2162
Figure 664.I3C broadcast ENTDAA CCC, as controller . . . . .2163
Figure 665.I3C broadcast, direct read and direct write RSTACT CCC, as controller . . . . .2164
Figure 666.I3C CCC messages, as target . . . . .2166
Figure 667.I3C broadcast ENTDAA CCC, as target. . . . .2167
Figure 668.I3C broadcast DEFTGTS CCC, as target. . . . .2168
Figure 669.I3C broadcast DEFGRPA CCC, as target . . . . .2169
Figure 670.I3C private read/write messages, as controller. . . . .2171
Figure 671.I3C private read/write messages, as target . . . . .2172
Figure 672.Legacy I2C read/write messages, as controller . . . . .2173
Figure 673.IBI transfer, as controller/target . . . . .2174
Figure 674.Hot-join request transfer, as controller/target . . . . .2175
Figure 675.Controller-role request transfer, as controller/target . . . . .2176
Figure 676.C-FIFO management, as controller . . . . .2177
Figure 677.TX-FIFO management, as controller . . . . .2179
Figure 678.RX-FIFO management, as controller . . . . .2181
Figure 679.S-FIFO management, as controller . . . . .2184
Figure 680.RX-FIFO management, as target on the I3C bus. . . . .2185
Figure 681.TX-FIFO management with I3C_TGTTDR, as target on the I3C bus. . . . .2187
Figure 682.TX-FIFO management by software without I3C_TGTTDR
if reading less bytes than TX-FIFO size, as target. . . . .		2189
Figure 683.USART block diagram . . . . .2247
Figure 684.Word length programming . . . . .2251
Figure 685.Configurable stop bits . . . . .2253
Figure 686.TC/TXE behavior when transmitting . . . . .2255
Figure 687.Start bit detection when oversampling by 16 or 8. . . . .2256
Figure 688.usart_ker_ck clock divider block diagram. . . . .2259
Figure 689.Data sampling when oversampling by 16. . . . .2260
Figure 690.Data sampling when oversampling by 8. . . . .2261
Figure 691.Mute mode using Idle line detection . . . . .2268
Figure 692.Mute mode using address mark detection . . . . .2269
Figure 693.Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .2272
Figure 694.Break detection in LIN mode vs. Framing error detection. . . . .2273
Figure 695.USART example of synchronous master transmission. . . . .2274
Figure 696.USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		2274
Figure 697.USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		2275
Figure 698.USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		2276
Figure 699.ISO 7816-3 asynchronous protocol . . . . .2278
Figure 700.Parity error detection using the 1.5 stop bits . . . . .2280
Figure 701.IrDA SIR ENDEC block diagram. . . . .2284
Figure 702.IrDA data modulation (3/16) - normal mode . . . . .2284
Figure 703.Transmission using DMA . . . . .2286
Figure 704.Reception using DMA . . . . .2287
Figure 705.Hardware flow control between two USARTs. . . . .2287
Figure 706.RS232 RTS flow control . . . . .2288
Figure 707.RS232 CTS flow control . . . . .2289
Figure 708.Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .2292
Figure 709.Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		2292
Figure 710.LPUART block diagram . . . . .2337
Figure 711.LPUART word length programming . . . . .2340
Figure 712.Configurable stop bits . . . . .2342
Figure 713.TC/TXE behavior when transmitting . . . . .2344
Figure 714.lpuart_ker_ck clock divider block diagram . . . . .2348
Figure 715.Mute mode using Idle line detection . . . . .2352
Figure 716.Mute mode using address mark detection . . . . .2353
Figure 717.Transmission using DMA . . . . .2355
Figure 718.Reception using DMA . . . . .2356
Figure 719.Hardware flow control between two LPUARTs. . . . .2357
Figure 720.RS232 RTS flow control . . . . .2357
Figure 721.RS232 CTS flow control . . . . .2358
Figure 722.Wake-up event verified (wake-up event = address match,
FIFO disabled) . . . . .		2361
Figure 723.Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		2361
Figure 724.SPI/I2S block diagram . . . . .2393
Figure 725.Full-duplex single master/ single slave application. . . . .2396
Figure 726.Half-duplex single master/ single slave application . . . . .2397
Figure 727.Simplex single master / single slave application
(master in transmit-only / slave in receive-only mode) . . . . .		2398
Figure 728.Master and three independent slaves connected in star topology . . . . .2399
Figure 729.Master and three slaves connected in circular (daisy chain) topology . . . . .2401
Figure 730.Multimaster application . . . . .2402
Figure 731.Scheme of NSS control logic . . . . .2404
Figure 732.Data flow timing control (SSOE = 1, SSOM = 0, SSM = 0) . . . . .2404
Figure 733.NSS interleaving pulses between data (SSOE = 1, SSOM = 1, SSM = 0). . . . .2405
Figure 734.Data clock timing diagram . . . . .2407
Figure 735.Data alignment when data size is not equal to 8, 16 or 32 bits . . . . .2408
Figure 736.TI mode transfer . . . . .2417
Figure 737.Optional configurations of the slave behavior when an underrun condition is detected . . . . .2419
Figure 738.Waveform examples . . . . .2427
Figure 739.Master I2S Philips protocol waveforms (16/32-bit full accuracy) . . . . .2428
Figure 740. I2S Philips standard waveforms . . . . .2428
Figure 741. Master MSB-justified 16- or 32-bit full-accuracy length . . . . .2429
Figure 742. Master MSB-justified 16- or 24-bit data length . . . . .2429
Figure 743. Slave MSB-justified 16-, 24- or 32-bit data length . . . . .2430
Figure 744. LSB-justified 16 or 24-bit data length . . . . .2430
Figure 745. Master PCM when the frame length is equal the data length . . . . .2431
Figure 746. Master PCM standard waveforms (16 or 24-bit data length) . . . . .2431
Figure 747. Slave PCM waveforms . . . . .2432
Figure 748. Startup sequence, I2S Philips standard, master . . . . .2435
Figure 749. Startup sequence, I2S Philips standard, slave . . . . .2436
Figure 750. Stop sequence, I2S Philips standard, master . . . . .2436
Figure 751. I 2 S clock generator architecture . . . . .2437
Figure 752. Data Format . . . . .2439
Figure 753. Handling of underrun situation . . . . .2441
Figure 754. Handling of overrun situation . . . . .2442
Figure 755. Frame error detection, with FIXCH = 0 . . . . .2443
Figure 756. Frame error detection, with FIXCH = 1 . . . . .2443
Figure 757. SAI functional block diagram . . . . .2469
Figure 758. Audio frame . . . . .2473
Figure 759. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .2475
Figure 760. FS role is start of frame (FSDEF = 0) . . . . .2476
Figure 761. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .2477
Figure 762. First bit offset . . . . .2477
Figure 763. Audio block clock generator overview . . . . .2479
Figure 764. PDM typical connection and timing . . . . .2483
Figure 765. Detailed PDM interface block diagram . . . . .2484
Figure 766. Start-up sequence . . . . .2485
Figure 767. SAI_ADR format in TDM mode, 32-bit slot width . . . . .2486
Figure 768. SAI_ADR format in TDM mode, 16-bit slot width . . . . .2487
Figure 769. SAI_ADR format in TDM mode, 8-bit slot width . . . . .2488
Figure 770. AC'97 audio frame . . . . .2491
Figure 771. Example of typical AC'97 configuration on devices featuring at least two embedded SAIs (three external AC'97 decoders) . . . . .2492
Figure 772. SPDIF format . . . . .2493
Figure 773. SAI_xDR register ordering . . . . .2494
Figure 774. Data companding hardware in an audio block in the SAI . . . . .2497
Figure 775. Tristate strategy on SD output line on an inactive slot . . . . .2499
Figure 776. Tristate on output data line in a protocol like I2S . . . . .2500
Figure 777. Overrun detection error . . . . .2501
Figure 778. FIFO underrun event . . . . .2501
Figure 779. CAN subsystem . . . . .2536
Figure 780. FDCAN block diagram . . . . .2538
Figure 781. Bit timing . . . . .2540
Figure 782. Transceiver delay measurement . . . . .2545
Figure 783. Pin control in bus monitoring mode . . . . .2546
Figure 784. Pin control in loop-back mode . . . . .2549
Figure 785. CAN error state diagram . . . . .2550
Figure 786. Message RAM configuration . . . . .2551
Figure 787. Standard message ID filter path . . . . .2554
Figure 788. Extended message ID filter path . . . . .2555
Figure 789. USB peripheral block diagram . . . . .2602
Figure 790. Packet buffer areas with examples of buffer description table locations . . . . .2608
Figure 791. UCPD block diagram . . . . .2650
Figure 792. Clock division and timing elements. . . . .2652
Figure 793. K-code transmission . . . . .2654
Figure 794. Transmit order for various sizes of data . . . . .2655
Figure 795. Packet format . . . . .2656
Figure 796. Line format of Hard Reset. . . . .2656
Figure 797. Line format of Cable Reset. . . . .2657
Figure 798. BIST test data frame. . . . .2658
Figure 799. BIST Carrier Mode 2 frame. . . . .2658
Figure 800. UCPD BMC transmitter architecture. . . . .2659
Figure 801. UCPD BMC receiver architecture . . . . .2660
Figure 802. Ethernet high-level block diagram . . . . .2693
Figure 803. DMA transmission flow (standard mode) . . . . .2696
Figure 804. DMA transmission flow (OSP mode) . . . . .2698
Figure 805. Receive DMA flow . . . . .2700
Figure 806. Overview of MAC transmission flow . . . . .2704
Figure 807. MAC reception flow . . . . .2706
Figure 808. Packet filtering sequence . . . . .2710
Figure 809. Networked time synchronization. . . . .2719
Figure 810. Propagation delay calculation in clocks supporting
peer-to-peer path correction . . . . .		2720
Figure 811. System time update using fine correction method . . . . .2730
Figure 812. TCP segmentation offload overview. . . . .2747
Figure 813. TCP segmentation offload flow. . . . .2748
Figure 814. Header and payload fields of segmented packets . . . . .2751
Figure 815. Supported PHY interfaces . . . . .2761
Figure 816. SMA Interface block . . . . .2761
Figure 817. MDIO packet structure (Clause 45) . . . . .2762
Figure 818. MDIO packet structure (Clause 22) . . . . .2763
Figure 819. SMA write operation flow . . . . .2765
Figure 820. Write data packet . . . . .2766
Figure 821. Read data packet . . . . .2766
Figure 822. Media independent interface (MII) signals . . . . .2768
Figure 823. RMII block diagram. . . . .2770
Figure 824. Transmission bit order . . . . .2771
Figure 825. Receive bit order. . . . .2772
Figure 826. LPI transitions (Transmit, 100 Mbds) . . . . .2780
Figure 827. LPI Tx clock gating (when LPITCSE = 1) . . . . .2781
Figure 828. LPI transitions (receive, 100 Mbps) . . . . .2782
Figure 829. Descriptor ring structure . . . . .2803
Figure 830. DMA descriptor ring . . . . .2805
Figure 831. Descriptor tail pointer example 1 . . . . .2805
Figure 832. Descriptor tail pointer example 2 . . . . .2806
Figure 833. Transmit descriptor (read format) . . . . .2807
Figure 834. Transmit descriptor write-back format. . . . .2812
Figure 835. Transmit context descriptor format. . . . .2816
Figure 836. Receive normal descriptor (read format) . . . . .2820
Figure 837. Receive normal descriptor (write-back format). . . . .2822
Figure 838. Receive context descriptor . . . . .2830
Figure 839. Generation of ETH_DMAISR flags . . . . .2846
Figure 840. HDMI-CEC block diagram . . . . .2966
Figure 841. Message structure . . . . .2966
Figure 842. Blocks . . . . .2967
Figure 843. Bit timings . . . . .2967
Figure 844. Signal free time . . . . .2968
Figure 845. Arbitration phase . . . . .2968
Figure 846. SFT of three nominal bit periods . . . . .2968
Figure 847. Error bit timing . . . . .2969
Figure 848. Error handling . . . . .2971
Figure 849. TXERR detection . . . . .2972
Figure 850. Block diagram of debug support infrastructure . . . . .2983
Figure 851. Product life cycle states and debug authentication . . . . .2987
Figure 852. JTAG TAP state machine . . . . .2991
Figure 853. CoreSight topology . . . . .3012
Figure 854. Trace port interface unit (TPIU) . . . . .3091
Figure 855. Embedded cross trigger . . . . .3103

Chapters