34. Revision history

Updated document title, Introduction , Section 4.1: Introduction , Section 4.2: Main features , Section 12.4.4: DMAMUX request line multiplexer , Section 15.7.1: Description of the analog watchdog , Section 19.3.4: PKA public key acceleration , Section 19.4.5: Modular and Montgomery multiplication and Section 19.5.1: Supported elliptic curves .

Updated Figure 2: Memory map and Figure 56: Surface charge transfer analog I/O group structure .

Updated Table 1: Memory map and peripheral register boundary addresses , Figure 72: Acquisition sequence summary , Table 83: CTR mode initialization vector definition , Table 85: Initialization of AES_IVRx registers in GCM mode , Table 86: Initialization of AES_IVRx registers in CCM mode , Table 117: Modular exponentiation computation times and Table 122: Montgomery parameters average computation times .

Added Table 121: Point on elliptic curve Fp check average computation times .

Added Note in Section 22.4.6: Trigger multiplexer and footnote to Table 98: Montgomery multiplication .

Minor text edits across the whole document.

Updated Related documents , User and read protection option bytes , reset values in sections 3.10.7 to 3.10.14 , Section 4.2: Main features , Section 5.2: CRC main features , Polynomial programmability , Section 5.4: CRC registers , Section 6.4: Low-power modes , Section 6.4.4: Exiting Low-power mode , Section 8.2: Clocks , Section 8.2.6: LSI1 clock , Section 8.2.7: LSI2 clock , Section 8.4.1: RCC clock control register (RCC_CR) , Section 8.4.29: RCC control/status register (RCC_CSR) , Section 15.3.2: ADC voltage regulator (ADVREGEN) , Section 15.3.12: Starting conversions (ADSTART) , Section 21.4.8: TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) , Section 22.7.4: LPTIM configuration register (LPTIM_CFGGR) , Section 23.3.14: Calibration clock output , Section 23.3.15: Alarm output , Section 27.8.3: USART control register 2 (USART_CR2) and Section 31.8.1: DBGMCU identity code register (DBGMCU_IDCODE) .

Updated Table 21: Sub-system low power wake-up sources , Table 23: Functionalities depending on system operating mode , Table 62: ADC input/output pins , Table 72: Acquisition sequence summary and Table 200: DBGMCU register map and reset values .

Updated Figure 6: CRC calculation unit block diagram , Figure 11: Low-power modes possible transitions and added footnote to it, Figure 30: ADC block diagram , Figure 56: Surface charge transfer analog I/O group structure and Figure 91: Advanced-control timer block diagram .

Minor text edits across the whole document.

Updated Section 3.5: FLASH UID64 , Section 6.4: Low-power modes , Section 6.4.4: Exiting Low-power mode , Section 6.6.2: PWR control register 2 (PWR_CR2) , Section 8.2: Clocks , Section 8.2.6: LSI1 clock , Section 8.2.11: Clock security system on LSE (LSECSS) , Section 9.3.2: I/O pin alternate function multiplexer and mapping , Section 15.3.3: Calibration (ADCAL) , Section 15.3.7: Configuring the ADC , Section 15.8: Temperature sensor and internal reference voltage , Section 15.11.3: ADC control register (ADC_CR) , Section 15.11.4: ADC configuration register 1 (ADC_CFGR1) , Section 15.11.5: ADC configuration register 2 (ADC_CFGR2) , Section 15.11.11: ADC calibration factor (ADC_CALFACT) , Section 17.2: RNG main features , DMA operation in different operating modes , Section 20.3.16: Using the break function , Section 20.4.8: TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) , Section 27.5.20: RS232 hardware flow control and RS485 Driver Enable , Section 27.8.4: USART control register 3 (USART_CR3) , Communication using DMA (direct memory addressing) , Section 31.7.15: CTI lock access register (CTI_LAR) , and Section 31.8.1: DBGMCU identity code register (DBGMCU_IDCODE) .

Added Section 32.4: Part number codification register .

Updated Table 21: Sub-system low power wake-up sources and Table 23: Functionalities depending on system operating mode .

Updated Figure 11: Low-power modes possible transitions , Figure 82: GCM authenticated encryption and Figure 114: Control circuit in normal mode, internal clock divided by 1 .

Rename \( t_{ADCVREG\_SETUP} \) into \( t_{ADCVREG\_STUP} \) throughout Section 15: Analog-to-digital converter (ADC) .

Minor text edits across the whole document.

Updated document title, Introduction , Section 3.3.1: Flash memory organization , CPU2 secure SRAM2 areas , Section 4.1: Introduction , Section 4.2: Main features , Section 8.4.28: RCC backup domain control register (RCC_BDCR) , Section 8.4.29: RCC control/status register (RCC_CSR) , Section 8.4.31: RCC extended clock recovery register (RCC_EXTCFGR) , Section 30.4.8: HSEM clear semaphore key register (HSEM_KEYR) , and Section 31.8.2: DBGMCU configuration register (DBGMCU_CR) .

Updated Figure 220: Transfer bus diagrams for I2C target transmitter (mandatory events only) , Figure 223: Transfer bus diagrams for I2C target receiver (mandatory events only) , and Figure 230: Transfer bus diagrams for I2C controller transmitter (mandatory events only) .

Updated Table 178: SPI register map and reset values .

Added Section 33: Important security notice .

Minor text edits across the whole document.

Added Empty check and Caution in Section 3.3.6: Flash memory program and erase operations .

Updated Section 3.3.7: Flash main memory erase sequences , Section 3.3.8: Flash main memory programming sequences , note in Section 3.6.1: Read protection (RDP) , Section 3.10.4: Flash memory status register (FLASH_SR) , Section 3.10.5: Flash memory control register (FLASH_CR) , Section 3.10.19: Flash memory secure SRAM2 start address and CPU2 reset vector register (FLASH_SRRVR) , Section 6.2.2: Programmable voltage detector (PVD) , Section 8.1.2: System reset , Section 8.4.30: RCC clock HSE register (RCC_HSECR) , Converting a supply-relative ADC measurement to an absolute voltage value , Section 20.4.7: TIM1 capture/compare mode register 1 (TIM1_CCMR1) , Section 21.4.7: TIM2 capture/compare mode register 1 (TIM2_CCMR1) , Section 25.4: WWDG interrupts , Section 25.5.2: WWDG configuration register (WWDG_CFR) , Section 31.4.11: DP access port select register (DP_SELECTR) , and Section 31.7.3: CTI application trigger set register (CTI_APPSETR) .

Updated Figure 56: Surface charge transfer analog I/O group structure , Figure 57: Sampling capacitor voltage variation , and Figure 209: Watchdog block diagram .

Updated Table 193: Debug port register map and reset values .

Minor text edits across the whole document.

Updated document title, Section 3.5: FLASH UID64 , Section 3.10.16: Flash memory CPU2 status register (FLASH_C2SR) , Section 4.1: Introduction , Section 4.2: Main features , Entering Stop0 mode , Section 6.4.8: Stop1 mode , Section 8.2.18: Clock-out capability , Section 16.3.4: Charge transfer acquisition sequence , Section 20.3.22: Encoder interface mode , and Section 21.3.15: Encoder interface mode .

Updated Figure 2: Memory map , Figure 208: Independent watchdog block diagram , Figure 214: I2C initialization flow , and Figure 217: Target initialization flow .

Minor text edits across the whole document.

Updated Figure 2: Memory map , Figure 14: Clock tree , and Figure 207: RTC block diagram .

Updated Section 8.2.3: MSI clock , Temperature sensor , V _REFINT and V _BAT internal channels , Section 21.3.18: Timers and external trigger synchronization , Section 23.6.4: RTC initialization and status register (RTC_ISR) , and Section 26.9.1: I2C control register 1 (I2C_CR1) .

Added Section 26.4.15: SMBus controller mode .

Added Table 80: RNG configurations , Table 167: USART/UART input/output pins , and Table 168: USART internal input/output signals .

Minor text edits across the whole document.