14. Extended interrupt and event controller (EXTI)

The Extended interrupt and event controller (EXTI) manages the individual CPU and system wakeup through configurable and direct event inputs. It provides wakeup requests to the power control, and generates an interrupt request to the CPUs interrupt controller and events to the CPUs event input. For each CPU an additional event generation block (EVG) is needed to generate the CPU event signal.

The EXTI wakeup requests allow the system to be woken up from STOP modes, and the CPU to be woken up from the CSTOP and CSTANDBY modes.

The interrupt request and event request generation can also be used in RUN modes.

14.1 EXTI main features

The EXTI main features are the following:

• • 49 input events supported
• • Two CPUs supported
• • All event inputs allow to wake up the system
• • Events which do not have an associated wakeup flag in the peripheral, have a flag in the EXTI and generate an interrupt to the CPU from the EXTI
• • Some events can be used to generate a CPU wakeup event

The asynchronous event inputs are classified in two groups:

• • Configurable events (signals from I/Os or peripherals able to generate a pulse)
  • – Configurable events have the following features:
    • - Selectable active trigger edge
    • - Interrupt pending status register bit.
    • - Individual interrupt and event generation mask, used for conditioning the CPU wakeup, interrupt and event generation
    • - SW trigger possibility
• • Direct events (interrupt and wakeup sources from peripherals having an associated flag which requiring to be cleared in the peripheral)
  • – Direct events have the following features:
    • - Fixed rising edge active trigger
    • - No interrupt pending status register bit in the EXTI (the interrupt pending status flag is provided by the peripheral generating the event)
    • - Individual interrupt and event generation mask, used for conditioning the CPU wakeup and event generation
    • - No SW trigger possibility

14.2 EXTI block diagram

The EXTI consists of a register block accessed via an AHB interface, the event input Trigger block, and the masking block as shown in Figure 27 .

The register block contains all the EXTI registers.

The event input trigger block provides event input edge trigger logic.

The masking block provides the event input distribution to the different wakeup, interrupt and event outputs, and the masking of these.

Figure 27. EXTI block diagram

Table 56. EXTI pin overview

Table 57. EVG pin overview

14.2.1 EXTI connections between peripherals and CPU

The peripherals able to generate wakeup or interrupt events when the system is in STOP mode or a CPU is in CSTOP mode are connected to the EXTI.

• • Peripheral wakeup signals that generate a pulse or which do not have an interrupt status bits in the peripheral, are connected to an EXTI configurable event input. For these events the EXTI provides a status pending bit that has to be cleared. It is the EXTI interrupt associated with the status bit that will interrupt the CPU.
• • Peripheral interrupt and wakeup signals that have a status bit in the peripheral that has to be cleared in the peripheral, are connected to an EXTI direct event input. There is no status pending bit within the EXTI. The interrupt or wakeup is cleared by the CPU in the peripheral. It is the peripheral interrupt that will interrupt the CPU directly.

The EXTI configurable event interrupts are connected to the respective interrupt controller of each CPU(m).

The dedicated EXTI/EVG CPU(m) event is connected to the respective CPU(m) rxev input.

The EXTI CPU(m) wakeup signals are connected to the PWR block, and are used to wake up the system and CPU(m) sub-system bus clocks.

14.3 EXTI functional description

Depending on the EXTI event input type and wakeup target(s), different logic implementations are used. The applicable features are controlled from register bits:

• • Active trigger edge enable, by rising edge selection
  EXTI rising trigger selection register (EXTI_RTSR1) ,
  EXTI rising trigger selection register (EXTI_RTSR2) ,
  and falling edge selection
  EXTI falling trigger selection register (EXTI_FTSR1) ,
  EXTI falling trigger selection register (EXTI_FTSR2) .
• • Software trigger, by
  EXTI software interrupt event register (EXTI_SWIER1) ,
  EXTI software interrupt event register (EXTI_SWIER2) .
• • Interrupt pending flag, by
  EXTI pending register (EXTI_PR1) ,
  EXTI pending register (EXTI_PR2) .
• • CPU wakeup and interrupt enable, by
  EXTI CPU wakeup with interrupt mask register (EXTI_IMR1) ,
  EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR1) ,
  EXTI CPU wakeup with interrupt mask register (EXTI_IMR2) ,
  EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR2) .
• • CPU wakeup and event enable, by
  EXTI CPU wakeup with event mask register (EXTI_EMR1) ,
  EXTI CPU2 wakeup with event mask register (EXTI_C2EMR1)
  EXTI CPU wakeup with event mask register (EXTI_EMR2) ,
  EXTI CPU2 wakeup with event mask register (EXTI_C2EMR2) .

Table 58. EXTI event input configurations and register control

1. Only for input events with configuration “rxev generation” enabled.

14.3.1 EXTI configurable event input wakeup

Figure 28 is a detailed representation of the logic associated with configurable event inputs which will wake up the CPU(m) sub-system bus clocks and generated an EXTI pending flag and interrupt to the CPU(m) and or a CPU(m) wakeup event.

Figure 28. Configurable event trigger logic CPU wakeup

1. 1. Only for the input events that support CPU rxeu generation \( c(n)\_event \) .

The software interrupt event register allows to trigger configurable events by software, writing the corresponding register bit, irrespective of the edge selection setting.

The rising edge and falling edge selection registers allow to enable and select the configurable event active trigger edge or both edges.

Each CPU has its dedicated interrupt mask register and a dedicated event mask registers. The enabled event allows to generate an event on the CPU. All events for a CPU are OR-ed together into a single CPU event signal. The event pending register (EXTI_PR) is not set for an unmasked CPU event.

The configurable events have unique interrupt pending request registers, shared by the CPUs. The pending register is only set for an unmasked interrupt. Each configurable event provides a common interrupt to all CPUs. The configurable event interrupts need to be acknowledged by software in the EXTI_PR register.

When a CPU(m) interrupt or CPU(m) event is enabled the asynchronous edge detection circuit is reset by the clocked delay and rising edge detect pulse generator. This guarantees that the EXTI hclk clock is woken up before the asynchronous edge detection circuit is reset.

Note: A detected configurable event interrupt pending request, may be cleared by any CPU. The system is unable to enter into Low-power modes as long as an interrupt pending request is active.

14.3.2 EXTI direct event input wakeup

Figure 29 is a detailed representation of the logic associated with direct event inputs waking up the system.

The direct events do not have an associated EXTI interrupt. The EXTI only wakes up the system and CPU sub-system clocks and may generate a CPU wakeup event. The peripheral synchronous interrupt, associated with the direct wakeup event wakes up the CPU.

The EXTI direct event is able to generate a CPU event. This CPU event wakes up the CPU. The CPU event may occur before the associated Peripheral interrupt flag is set.

Note: The direct events are cleared in the peripheral generating the event. When a direct event input enabled by CPU(m) is cleared by another CPU before the CPU(m) clock is running, the CPU(m) no longer receives a CPU(m) interrupt nor a CPU(m) event and does not wake up. However the system stays in RUN mode, generating the CPU(m) clock. For this reason CPU(m) direct events must NOT be cleared by the other CPU.

Figure 29. Direct event trigger logic CPU wakeup

1. 1. Only for the input events that support CPU rxev generation c(n)_event.

14.4 EXTI functional behavior

The direct event inputs are enabled in the respective peripheral generating the wakeup event. The configurable events are enabled by enabling at least one of the trigger edges.

Once an event input is enabled, the generation of a CPU(m) wakeup is conditioned by the CPU(m) interrupt mask and CPU(m) event mask.

Table 59. Masking functionality

1. The single exti(n) interrupt goes to all CPUs. If no interrupt is required for CPU(m), the exti(n) interrupt must be masked in the CPU(m) interrupt controller.

2. Only if CPU(m) interrupt is enabled in EXTI_CmIMR.IMn.

For configurable event inputs, when the enabled edge(s) occur on the event input, an event request is generated. When the associated CPU(m) interrupt is unmasked the corresponding pending bit EXTI_PR.PIFn is set and the CPU(m) sub-system is woken up and CPU interrupt signal is activated. The EXTI_PR.PIFn pending bit must be cleared by software writing, it to '1'. This clears the CPU interrupt.

For direct event inputs, when enabled in the associated peripheral, an event request is generated on the rising edge only. There is no corresponding CPU pending bit in the EXTI. When the associated CPU(m) interrupt is unmasked the corresponding CPU sub-system is woken up. The CPU is woken up (interrupted) by the peripheral synchronous interrupt.

The CPU(m) event must be unmasked to generate an event. When the enabled edge(s) occur on the event input a CPU(m) event pulse is generated. There is no event pending bit.

For the configurable event inputs an event request can be generated by software when writing a '1' in the software interrupt/event register EXTI_SWIER, generating a rising edge on the event. The edge event pending bit is set in EXTI_PR, irrespective of the setting in EXTI_RTSR.

14.5 EXTI registers

The EXTI register map is divided as detailed in Table 60 .

Table 60. EXTI register map sections

All the registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit) access.

14.5.1 EXTI rising trigger selection register (EXTI_RTSR1)

Address offset: 0x000

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:0 RT[20:0] : Rising trigger event configuration bit of configurable event input x (x = 20 to 0) ⁽¹⁾ .

0: Rising trigger disabled (for event and Interrupt) for input line

1: Rising trigger enabled (for event and Interrupt) for input line

1. 1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a rising edge on the configurable event input occurs during writing of the register, the associated pending bit is not set. Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

14.5.2 EXTI falling trigger selection register (EXTI_FTSR1)

Address offset: 0x004

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:0 FT[20:0] : Falling trigger event configuration bit of configurable event input x (x = 20 to 0) ⁽¹⁾ .

0: Falling trigger disabled (for event and Interrupt) for input line

1: Falling trigger enabled (for event and Interrupt) for input line.

1. 1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a falling edge on the configurable event input occurs during writing of the register, the associated pending bit is not set. Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

14.5.3 EXTI software interrupt event register (EXTI_SWIER1)

Address offset: 0x008

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:0 SWI[20:0] : Software interrupt on event x (x = 20 to 0)

A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. Will always return 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger a rising edge event on event x.

This bit is auto cleared by HW.

14.5.4 EXTI pending register (EXTI_PR1)

Address offset: 0x00C

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:0 PIF[20:0] : configurable event inputs x (x = 20 to 0) Pending bit.

0: No trigger request occurred

1: Selected trigger request occurred

This bit is set when the selected edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing a 1 into the bit.

14.5.5 EXTI rising trigger selection register (EXTI_RTSR2)

Address offset: 0x020

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 RT41 : Rising trigger event configuration bit of configurable event input 41 ⁽¹⁾

0: Rising trigger disabled (for event and interrupt) for input line

1: Rising trigger enabled (for event and interrupt) for input line

Bit 8 RT40 : Rising trigger event configuration bit of configurable event input 40 ⁽¹⁾

0: Rising trigger disabled (for event and interrupt) for input line

1: Rising trigger enabled (for event and interrupt) for input line

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 RT33 : Rising trigger event configuration bit of configurable event input 33 ⁽¹⁾

0: Rising trigger disabled (for event and interrupt) for input line

1: Rising trigger enabled (for event and interrupt) for input line

Bit 0 Reserved, must be kept at reset value.

1. 1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a rising edge on the configurable event input occurs during writing of the register, the associated pending bit is not set. Rising and falling edge triggers can be set for the same configurable Event input. In this case, both edges generate a trigger.

14.5.6 EXTI falling trigger selection register (EXTI_FTSR2)

Address offset: 0x024

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 FT41 : Falling trigger event configuration bit of configurable event input 41 ⁽¹⁾

0: Falling trigger disabled (for event and interrupt) for input line

1: Falling trigger enabled (for event and interrupt) for input line

Bit 8 FT40 : Falling trigger event configuration bit of configurable event input 40 ⁽¹⁾

0: Falling trigger disabled (for event and interrupt) for input line

1: Falling trigger enabled (for event and interrupt) for input line

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 FT33 : Falling trigger event configuration bit of configurable event input 33 ⁽¹⁾

0: Falling trigger disabled (for event and interrupt) for input line

1: Falling trigger enabled (for event and interrupt) for input line

Bit 0 Reserved, must be kept at reset value.

1. 1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a falling edge on the configurable event input occurs during writing of the register, the associated pending bit is not set. Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

14.5.7 EXTI software interrupt event register (EXTI_SWIER2)

Address offset: 0x028

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 SWI41 : Software interrupt on event 41

A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. Will always return 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger a rising edge event on event 41.

This bit is auto cleared by HW.

Bit 8 SWI40 : Software interrupt on event 40

A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. Will always return 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger a rising edge event on event 40.

This bit is auto cleared by HW.

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 SWI33 : Software interrupt on event 33

A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. Will always return 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger a rising edge event on event 33.

This bit is auto cleared by HW.

Bit 0 Reserved, must be kept at reset value.

14.5.8 EXTI pending register (EXTI_PR2)

Address offset: 0x02C

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 PIF41 : configurable event inputs 41 pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing a 1 into the bit.

Bit 8 PIF40 : configurable event inputs 40 pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing a 1 into the bit.

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 PIF33 : configurable event inputs 33 pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing a 1 into the bit.

Bit 0 Reserved, must be kept at reset value.

14.5.9 EXTI CPU wakeup with interrupt mask register (EXTI_IMR1)

Address offset: 0x080

Reset value: 0x7FC0 0000

Contains register bits for configurable events and direct events.

Bits 31, 28:25, 23, Reserved, must be kept at reset value.
21:20

Bits 30:29, 24, 22, IM[30:29, 24, 22, 19:0] : CPU wakeup with interrupt mask on event input x (x = 30:29, 24, 22, 19:0) ⁽¹⁾⁽²⁾ .

0: Wakeup with interrupt request from Line x is masked

1: Wakeup with interrupt request from Line x is unmasked

1. 1. The reset value for configurable event inputs is set to '0' in order to disable the interrupt by default.
2. 2. The reset value for direct event inputs is set to '1' in order to enable the interrupt by default.

14.5.10 EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR1)

Address offset: 0x0C0

Reset value: 0x7FC0 0000

Contains register bits for configurable events and direct events.

Bits 31, 28:25, 23, Reserved, must be kept at reset value.
21:20

Bits 30:29, 24, 22, IM[30:29, 24, 22, 19:0] : CPU2 wakeup with interrupt mask on event input x (x = 30:29, 24, 22, 19:0 19 to 0) ⁽¹⁾⁽²⁾ .

0: Wakeup with interrupt request from Line x is masked

1: Wakeup with interrupt request from Line x is unmasked

1. 1. The reset value for configurable event inputs is set to '0' in order to disable the interrupt by default.
2. 2. The reset value for direct event inputs is set to '1' in order to enable the interrupt by default.

14.5.11 EXTI CPU wakeup with event mask register (EXTI_EMR1)

Address offset: 0x084

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:17 EM[19:17] : CPU wakeup with event generation mask on event input x (x = 19 to 17)

0: Wakeup with event generation from Line x is masked

1: Wakeup with event generation from Line x is unmasked

Bit 16 Reserved, must be kept at reset value.

Bits 15:0 EM[15:0] : CPU wakeup with event generation mask on event input x (x = 15 to 0)

0: Wakeup with event generation from Line x is masked

1: Wakeup with event generation from Line x is unmasked

14.5.12 EXTI CPU2 wakeup with event mask register (EXTI_C2EMR1)

Address offset: 0x0C4

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:17 EM[19:17] : CPU2 wakeup with event generation mask on event input x (x = 19 to 17)

0: Wakeup with event generation from Line x is masked

1: Wakeup with event generation from Line x is unmasked

Bit 16 Reserved, must be kept at reset value.

Bits 15:0 EM[15:0] : CPU2 wakeup with event generation mask on event input x (x = 15 to 0)

0: Wakeup with event generation from Line x is masked

1: Wakeup with event generation from Line x is unmasked

14.5.13 EXTI CPU wakeup with interrupt mask register (EXTI_IMR2)

Address offset: 0x090

Reset value: 0x0001 FCFD

Contains register bits for configurable events and direct events.

Bits 31:17, 15:14, Reserved, must be kept at reset value.

11, 3:0

Bits 16, 13:12, 10:4 IM[48, 45:44, 42:36] : CPU wakeup with interrupt mask on event input x (x = 48, 45 to 44, 42 to 36) ⁽¹⁾⁽²⁾

0: Wakeup with interrupt request from Line x is masked

1: Wakeup with interrupt request from Line x is unmasked

1. 1. The reset value for configurable event inputs is set to '0' in order to disable the interrupt by default.
2. 2. The reset value for direct event inputs is set to '1' in order to enable the interrupt by default.

14.5.14 EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR2)

Address offset: 0x0D0

Reset value: 0x0001 FCFD

Contains register bits for configurable events and direct events.

Bits 31:17, 15:14, Reserved, must be kept at reset value.

11, 3:0

Bits 16, 13:12, 10:4 IM[48, 45:44, 42:36] : CPU wakeup with interrupt mask on event input x (x = 48, 45 to 44, 42 to 36) ⁽¹⁾⁽²⁾

0: Wakeup with interrupt request from Line x is masked

1: Wakeup with interrupt request from Line x is unmasked

1. 1. The reset value for configurable event inputs is set to '0' in order to disable the interrupt by default.
2. 2. The reset value for direct event inputs is set to '1' in order to enable the interrupt by default.

14.5.15 EXTI CPU wakeup with event mask register (EXTI_EMR2)

Address offset: 0x094

Reset value: 0x0000 0000

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 EM41 : CPU wakeup with event generation mask on event input 41

• 0: Wakeup with event generation from Line 41 is masked
• 1: Wakeup with event generation from Line 41 is unmasked

Bit 8 EM40 : CPU wakeup with event generation mask on event input 40.

• 0: Wakeup with event generation from Line 40 is masked
• 1: Wakeup with event generation from Line 40 is unmasked

Bits 7:0 Reserved, must be kept at reset value.

14.5.16 EXTI CPU2 wakeup with event mask register (EXTI_C2EMR2)

Address offset: 0x0D4

Reset value: 0x0000 0000

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 EM41 : CPU2 wakeup with event generation mask on event input 41

• 0: Wakeup with event generation from Line 41 is masked
• 1: Wakeup with event generation from Line 41 is unmasked

Bit 8 EM40 : CPU2 wakeup with event generation mask on event input 40.

• 0: Wakeup with event generation from Line 40 is masked
• 1: Wakeup with event generation from Line 40 is unmasked

Bits 7:0 Reserved, must be kept at reset value.

14.5.17 EXTI register map

The following table gives the EXTI register map and the reset values.

Table 61. EXTI register map and reset values

Table 61. EXTI register map and reset values (continued)

Refer to Section 2.2 on page 54 for the register boundary addresses.