13. Nested vectored interrupt controller (NVIC)

13.1 NVIC main features

The CPU1 NVIC features:

• • 63 maskable interrupt channels (not including the sixteen Cortex ^® -M4 with FPU interrupt lines)
• • 16 programmable priority levels (four bits of interrupt priority are used)
• • Low-latency exception interrupt handling
• • Power management control
• • Implementation of System control registers

The CPU2 NVIC features:

• • 32 maskable interrupt channels (not including the sixteen Cortex ^® -M0+ interrupt lines)
• • Four programmable priority levels (two bits of interrupt priority are used)
• • Low-latency exception interrupt handling
• • Power management control

The NVICs and the processor cores interfaces are closely coupled, resulting in low latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming refer to STM32 Cortex ^® -M4 MCUs and MPUs programming manual (PM0214) for Cortex ^® -M4, and Cortex ^® -M0+ programming manual for STM32L0, STM32G0, STM32WL and STM32WB Series (PM0223) for Cortex ^® -M0+.

13.2 Interrupt block diagram

The different peripheral interrupts are connected in different ways, depending on the sharing between the two CPUs. To prevent a peripheral or EXTI interrupt to trigger both CPUs, they can be masked either in the NVIC, or, for the NVIC vector sharing multiple peripheral interrupts, by a pre-mask in the SYSCFG registers, see Section 10: System configuration controller (SYSCFG) .

The interrupt block diagram is shown in Figure 26 .

Figure 26. Interrupt block diagram

13.3 Interrupt and exception vectors

Each of the CPU1 and CPU2 has its own vector table, see, respectively, Table 53 and Table 54 , where shaded cells indicate the processor exceptions.

Table 53. CPU1 vector table

Table 53. CPU1 vector table (continued)

Table 53. CPU1 vector table (continued)

Table 54. CPU2 vector table

Table 54. CPU2 vector table (continued)

13.4 Interrupt list

The device wakeup sources are listed in Table 55 . Depending on its origin, the wakeup is handled according to different types, see Section 14.4: EXTI functional behavior for more information.

Some wakeup sources are able to generate an event to the CPUs. see Event column.

The wakeup source capability to wakeup CPU1 and or CPU2 is listed in Wakeup column.

For CPUs interrupt handling see Section 13: Nested vectored interrupt controller (NVIC) .

For Wakeup handling see Section 14: Extended interrupt and event controller (EXTI) .

Table 55. Wakeup interrupt table

Table 55. Wakeup interrupt table (continued)

1. 1. For correct operation the EXTI direct event C2IMRx.IMn bit must be set to 0 before CPU1 uses this direct event.
2. 2. For correct operation the EXTI direct event C1IMRx.IMn bit must be set to 0 before CPU2 uses this direct event.
3. 3. For correct operation the EXTI configurable event both C2IMRx.IMn and C2EMRx.EMn bits must be set to 0 before CPU1 uses this configurable event.
4. 4. For correct operation the EXTI configurable event both C1IMRx.IMn and C1EMRx.EMn bits must be set to 0 before CPU2 uses this configurable event.