7. Peripherals interconnect matrix
7.1 Introduction
Several peripherals have direct connections, enabling autonomous communication and/or synchronization between them. This saves CPU resources and, consequently, reduces power consumption. In addition, these hardware connections remove software latency and result in more predictable system design.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and sleep, Stop 0 and Stop 1 modes.
7.2 Connection summary
Table 33. STM32WB10CC peripherals interconnect matrix (1) (2)
| Source | Destination | ||||
|---|---|---|---|---|---|
| TIM1 | TIM2 | LPTIM1 | LPTIM2 | ADC1 | |
| TIM1 | - | 1 | - | - | 2 |
| TIM2 | 1 | - | - | - | 2 |
| LPTIM1 | - | - | - | - | - |
| LPTIM2 | - | - | - | - | - |
| ADC1 | 3 | - | - | - | - |
| T. Sensor | - | - | - | - | 6 |
| VBAT | - | - | - | - | 6 |
| VREFINT | - | - | - | - | 6 |
| HSE | - | - | - | - | - |
| LSE | - | 4 | - | - | - |
| MSI | - | - | - | - | - |
| LSI | - | - | - | - | - |
| MCO | - | - | - | - | - |
| EXTI | - | - | - | - | 2 |
| RTC | - | - | 5 | 5 | - |
| SYST ERR | 7 | - | - | - | - |
1. Numbers in table are links to corresponding subsections of Section 7.3: Interconnection details .
2. The “-” symbol in grayed cells means no interconnect.
7.3 Interconnection details
7.3.1 From timer (TIM1/TIM2) to timer (TIM1/TIM2)
Purpose
Some of the timers are linked together internally for synchronization or chaining.
When one timer is configured in Master Mode, it can reset, start, stop or clock the counter of another timer configured in Slave Mode. A description of the feature is provided in Section 20.3.26: Timer synchronization .
The modes of synchronization are detailed in:
- • Section 20.3.26: Timer synchronization for advanced-control timers (TIM1)
- • Section 21.3.18: Timers and external trigger synchronization for general-purpose timers (TIM2)
Triggering signals
The output (from Master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1) following a configurable timer event. The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.
The input and output signals for TIM1 are shown in Figure 91: Advanced-control timer block diagram .
The possible master/slave connections are given in:
Active power mode(s)
Run, Sleep, Low-power run, Low-power sleep.
7.3.2 From timer (TIM1/TIM2) and EXTI to ADC (ADC1)
Purpose
General-purpose timer TIM2, advanced-control timer TIM1 and EXTI can be used to generate an ADC triggering event.
TIMx synchronization is described in Section 20.3.27: ADC synchronization .
ADC synchronization is described in Section 15.4: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) .
Triggering signals
The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.
The input (to ADC) is on signals EXT[15:0] and JEXT[15:0].
The connection between timers and ADC is provided in:
Active power mode(s)
Run, Sleep, Low-power run, Low-power sleep.
7.3.3 From ADC (ADC1) to timer (TIM1)
Purpose
ADC1 can provide trigger event through watchdog signals to advanced-control timers (TIM1).
A description of the ADC analog watchdog setting is provided in Section 16.4.30: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) .
Trigger settings on the timer are provided in Section 20.3.4: External trigger input .
Triggering signals
The output (from ADC) is on signal ADC_AWD1_OUT (for ADC1) (one watchdog on ADC) and the input (to timer) on signal TIM1_ETR (external trigger).
Active power mode(s)
Run, Sleep, Low-power run, Low-power sleep.
7.3.4 From LSE to timer (TIM2)
Purpose
External clock LSE can be used as input to general-purpose timer (TIM2) on TIM2_ETR pin.
Active power mode(s)
Run, Sleep, Low-power run, Low-power sleep.
7.3.5 From RTC to low-power timers (LPTIM1/LPTIM2)
Purpose
RTC alarm A/B, RTC_TAMP2 input detection can be used as trigger to start LPTIM counters (LPTIM1/2).
Triggering signals
This trigger feature is described in Section 22.4.6: Trigger multiplexer (and following sections).
The input selection is described in Table 136: LPTIM1 external trigger connection and Table 137: LPTIM2 external trigger connection .
Active power mode(s)
Run, Sleep, Low-power run, Low-power sleep, Stop 0, Stop 1.
7.3.6 From internal analog to ADC1
Purpose
Internal temperature sensor (VTS), internal reference voltage (VREFINT) and VBAT monitoring channel are connected to ADC1 input channel.
This is according to:
- • Section 15.2: ADC main features
- • Section 15.3.8: Channel selection (CHSEL, SCANDIR, CHSELRMOD)
- • Section 15.8: Temperature sensor and internal reference voltage
- • Section 15.9: Battery voltage monitoring
Active power mode(s)
Run, Sleep, low-power run, Low-power sleep.
7.3.7 From system errors to timer (TIM1)
Purpose
CSS, CPU hard fault, RAM parity error, FLASH ECC double error detection, PVD can generate system errors in the form of timer break toward timer TIM1.
The purpose of the break function is to protect power switches driven by PWM signals generated by the timer.
List(s) of possible break source(s) are described in:
Active power mode(s)
Run, Sleep, Low-power run, Low-power sleep.