6. Power control (PWR)

6.1 Power supplies

The devices require a \( V_{DD} \) operating voltage supply between 2.00 V and 3.6 V. Several independent supplies ( \( V_{DDA} \) , \( V_{DDRF} \) ) can be provided for specific peripherals:

• • \( V_{DD} = 2.00 \text{ V to } 3.6 \text{ V} \)

\( V_{DD} \) is the external power supply for the I/Os, the system analog blocks such as reset, power management, internal clocks and low power regulator. It is provided externally through VDD pins.

• • \( V_{DDA} = 2.00 \text{ V to } 3.6 \text{ V} \)

\( V_{DDA} \) is the external analog power supply for A/D converters, D/A converters, voltage reference buffer, and operational amplifiers. The \( V_{DDA} \) voltage level is independent from the \( V_{DD} \) voltage and must preferably be connected to \( V_{DD} \) when these peripherals are not used.

• • \( V_{DDRF} = 2.00 \text{ V to } 3.6 \text{ V} \)

\( V_{DDRF} \) is the external power supply for the Radio. It is provided externally through the VDDRF pin, and must be connected to the same supply as \( V_{DD} \) .

• • \( V_{BAT} = 1.55 \text{ V to } 3.6 \text{ V} \)

\( V_{BAT} \) is the power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when \( V_{DD} \) is not present.

During power up and power down, the following power sequence is required:

• • When \( V_{DD} < 1 \text{ V} \) the other power supply ( \( V_{DDA} \) ) must remain below \( V_{DD} + 0.3 \text{ V} \) . During the power down \( V_{DD} \) can temporarily become lower than the other supplies only if the energy provided to the MCU remains below 1 mJ. This allows the external decoupling capacitors to discharge with different time constants.
• • When \( V_{DD} \geq 1 \text{ V} \) all power supplies become independent.

An embedded linear voltage regulator is used to supply the internal digital power \( V_{CORE} \) . \( V_{CORE} \) is the power supply for digital peripherals, SRAM1 and SRAM2. The flash memory is supplied by \( V_{CORE} \) and \( V_{DD} \) .

Figure 7. Power supply overview

6.1.1 Independent analog peripherals supply

To improve ADC conversion accuracy and to extend the supply flexibility, the analog peripherals have an independent power supply that can be separately filtered and shielded from noise on the PCB.

• • The analog peripherals voltage supply input is available on a separate \( V_{DDA} \) pin.
• • An isolated supply ground connection is provided on \( V_{SSA} \) pin.

The \( V_{DDA} \) supply voltage can be different from \( V_{DD} \) . The presence of \( V_{DDA} \) must be checked before enabling any of the analog peripherals supplied by \( V_{DDA} \) (A/D converter, voltage reference buffer).

When a single supply is used, \( V_{DDA} \) can be externally connected to \( V_{DD} \) through the external filtering circuit in order to ensure a noise-free \( V_{DDA} \) reference voltage.

6.1.2 Battery backup domain

To retain the content of the Backup registers and supply the RTC function when \( V_{DD} \) is turned off, the \( V_{BAT} \) pin can be connected to an optional backup voltage supplied by a battery or by another source.

The \( V_{BAT} \) pin powers the RTC unit, the LSE oscillator and the PC14 to PC15 I/Os, allowing the RTC to operate even when the main power supply is turned off. The switch to the \( V_{BAT} \) supply is controlled by the power-down reset embedded in the Reset block.

Warning: During \( t_{RSTTEMPO} \) (temporization at \( V_{DD} \) startup) or after a PDR has been detected, the power switch between \( V_{BAT} \) and \( V_{DD} \) remains connected to \( V_{BAT} \) .

During the startup phase, if \( V_{DD} \) is established in less than \( t_{RSTTEMPO} \) (refer to the datasheet for its value) and \( V_{DD} > V_{BAT} + 0.6\text{ V} \) , a current may be injected into \( V_{BAT} \) through an internal diode connected between \( V_{DD} \) and the power switch ( \( V_{BAT} \) ).

If the power supply / battery connected to the \( V_{BAT} \) pin cannot support this current injection, it is recommended to connect an external low-drop diode between this power supply and the \( V_{BAT} \) pin.

If no external battery is used in the application, it is recommended to connect \( V_{BAT} \) to \( V_{DD} \) supply, and add a 100 nF external ceramic decoupling capacitor on \( V_{BAT} \) pin.

When the backup domain is supplied by \( V_{DD} \) (analog switch connected to \( V_{DD} \) ), the following pins are available:

• • PC14 and PC15, which can be used as GPIO pins
• • PC14 and PC15, which can be configured by LSE
• • PA0/RTC_TAMP2 when configured by the RTC as tamper pin

Note: As the analog switch can transfer only a limited amount of current (3 mA), the use of GPIO PC14 to PC15 in output mode is restricted: the speed must be limited to 2 MHz with a maximum load of 30 pF, and these I/Os cannot be used as current sources (e.g. to drive a LED).

When the backup domain is supplied by \( V_{BAT} \) (analog switch connected to \( V_{BAT} \) because \( V_{DD} \) is not present), the following functions are available:

• • PC14 and PC15 can be controlled only by LSE
• • PA0/RTC_TAMP2 when configured by the RTC as tamper pin

Backup domain access

After a system reset, the backup domain (RTC registers and backup registers) is protected against possible unwanted write accesses. To enable access to the backup domain, set the DBP bit in the PWR control register 1 (PWR_CR1) to enable access to the backup domain.

VBAT battery charging

When \( V_{DD} \) is present, it is possible to charge the external battery on \( V_{BAT} \) through an internal resistance.

The \( V_{BAT} \) charging is done either through a 5 k \( \Omega \) resistor or through a 1.5 k \( \Omega \) resistor, depending upon the VBRS bit value in the PWR control register 4 (PWR_CR4) .

The battery charging is enabled by setting VBE bit in the PWR control register 4 (PWR_CR4) , and automatically disabled in \( V_{BAT} \) mode.

6.1.3 Voltage regulator

Two embedded linear voltage regulators supply all the digital circuitries, except for the Standby circuitry and the backup domain.

The voltage regulators are always enabled after a reset. Depending on the application modes, the \( V_{CORE} \) supply is provided either by the main regulator (MR) or by the low-power regulator (LPR).

• • In Run, Sleep and Stop0 modes, both regulators are enabled and the main regulator (MR) supplies full power to the \( V_{CORE} \) domain (core, memories and digital peripherals).
• • In low-power run and low-power sleep modes, the main regulator is off and the low-power regulator (LPR) supplies low power to the \( V_{CORE} \) domain, preserving the contents of the registers and internal SRAM1 and SRAM2.
• • In Stop1 mode the main regulator is off and the low-power regulator (LPR) supplies low power to the \( V_{CORE} \) domain, preserving the contents of the registers and of internal SRAM1 and SRAM2.
• • In Standby mode with SRAM1, SRAM2a and SRAM2b content preserved (RRS bit is set in the PWR control register 3 (PWR_CR3) ), the main regulator (MR) is off and the low-power regulator (LPR) provides the supply to SRAM1, SRAM2a and SRAM2b. The core and digital peripherals (except Standby circuitry and backup domain) are powered off.
• • In Standby mode, both regulators are powered off. The contents of the registers is lost except for the Standby circuitry and the backup domain.
• • In Shutdown mode, both regulators are powered off. When exiting from Shutdown mode, a power-on reset is generated. Consequently, the contents of the registers and of both SRAM1 and SRAM2 is lost, except for the backup domain.

6.2 Power supply supervisor

6.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR)

The device has an integrated power-on reset / power-down reset, coupled with a brown-out reset circuitry.

Five BOR thresholds can be selected through option bytes.

The BOR is active in all power modes except Shutdown mode, and cannot be disabled. The BOR mechanism needs to be enabled, and can be disabled at any time if needed.

Reset mode

During power-on, the BOR keeps the device under reset until the supply voltage \( V_{DD} \) reaches the specified \( V_{BORx} \) threshold. When \( V_{DD} \) drops below the selected threshold, a device reset is generated. When \( V_{DD} \) is above the \( V_{BORx} \) upper limit, the device reset is released and the system can start.

For more details on the brown-out reset thresholds refer to the electrical characteristics section in the datasheet.

Figure 8. Brown-out reset waveform

1. The reset temporization \( t_{RSTTEMPO} \) is present only for the BOR lowest threshold ( \( V_{BOR0} \) ).

6.2.2 Programmable voltage detector (PVD)

The PVD can be used to monitor the \( V_{DD} \) power supply by comparing it to a threshold selected by the PLS[2:0] bits in the PWR control register 2 (PWR_CR2) .

The PVD can also be used to monitor a voltage level on the PVD_IN pin. In this case the voltage level on PVD_IN is compared to the internal VREFINT level.

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the PWR status register 2 (PWR_SR2) , to indicate if \( V_{DD} \) or the voltage level on PVD_IN is higher or lower than the PVD threshold. This event is internally connected to the EXTI Line16 and can generate an interrupt if enabled through the EXTI registers.

The PVD output interrupt can be generated when \( V_{DD} \) or the voltage level on PVD_IN drops below the PVD threshold, and/or when \( V_{DD} \) or the voltage level on PVD_IN rises above the PVD threshold, depending on EXTI Line16 rising/falling edge configuration. If the EXTI Line16 is configured to rising/falling edge sensitivity (rising/falling edge of PVDO), the interrupt is generated when \( V_{DD} \) or the voltage level on PVD_IN drops below/rises above the PVD threshold. As an example, the service routine can perform emergency shutdown tasks.

Figure 9. PVD thresholds

6.3 CPU2 boot

Booting of the CPU2 is controlled by the C2BOOT bit in PWR control register 4 (PWR_CR4) register. This allows the CPU1 to initialize the system after a reset or wake-up from system Low-power mode, before booting the CPU2.

• • Following reset the CPU2 is prevented from booting by the C2BOOT bit. The CPU2 boots only once the CPU1 has set the C2BOOT bit.
• • When exiting from system low power modes STOP0, STOP1 or STANDBY the C2BOOT bit controls the CPU2 booting.
  • – When \( C2BOOT = 1 \) , after a system low power mode the CPU2 boots when it is woken up via a wake-up source.
  • – When \( C2BOOT = 0 \) , after a system low power mode the CPU2 is prevented from booting. Instead on a CPU2 wake-up source the CPU1 is woken up via a C2HF. It is up to the CPU1 to boot the CPU2 by setting the C2BOOT bit.

Figure 10. CPU2 boot options

When the CPU2 is prevented from booting, the wake-up from Low-power mode boot procedure is the following:

• • Before the CPU1 enters CSTOP mode it clears the C2BOOT bit.
• • When CPU1 exits CSTOP :
  • – When the system remains in Run mode, it sets the C2BOOT bit, and subsequently processes the wake-up event.
  • – When the system exits from a low power mode from a CPU1 wake-up source, it initializes the system and sets the C2BOOT bit, and subsequently processes the wake-up event.
  • – When the system exits from a low power mode from the C2HF wake-up source, it initializes the system and set the C2BOOT bit, and subsequently goes back to CSTOP .

• • There is no special wake-up procedure for the CPU2. When the CPU2 wakes up, the system has been initialized by the CPU1. So the CPU2 can directly process the wake-up event.

When the system remains in Run mode (due to the Radio system) the CPU2 wakes up from CSTOP mode independently from the C2BOOT setting.

6.4 Low-power modes

By default, the microcontroller is in Run mode after a system or a power Reset and at least one CPU is in CRun mode executing code. Low-power modes are available to save power when the CPU does not need to be kept running, for example when it is waiting for an external event. The user has to select the mode that gives the best compromise between consumption, startup time and available wake-up sources.

The individual CPUs feature two low power modes, entered by the CPU when executing WFI, WFE or on return from an exception handler when SLEEPONEXIT is enabled.

• • CSleep mode: when the CPU enters low power mode and SLEEPDEEP is disabled, Arm® “sleep mode”.
• • CStop mode: when the CPU enters low power mode and SLEEPDEEP is enabled, Arm® “sleepdeep mode”.

The device features several low-power modes:

• • Sleep mode : CPU clock off, all peripherals including CPU core peripherals (among them NVIC, SysTick) can run and wake up the CPU when an interrupt or an event occurs.
• • Low-power run mode (LP run) : This mode is achieved when the system clock frequency is reduced below 2 MHz. The code is executed from the SRAM or from the flash memory. The regulator is in low-power mode to minimize the operating current.
• • Low-power sleep mode (LP sleep) : This mode is entered from the Low-power run mode: CPU is off.
• • Stop0 mode and Stop1 mode : the content of SRAM1, SRAM2 and of all registers is retained. All clocks in the \( V_{CORE} \) domain are stopped, the PLL, the MSI, the HSI16 and the HSE are disabled. The LSI and the LSE can be kept running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with the wake-up capability can enable the HSI16 RC during Stop mode to detect their wake-up condition.

In Stop0 mode, the main regulator remains ON, resulting in the fastest wake-up time, but with much higher consumption. The active peripherals and wake-up sources are the same as in Stop1 mode.

The system clock, when exiting from Stop0 or Stop1 mode, can be either MSI up to 48 MHz or HSI16, depending on the software configuration.

• • Standby mode : \( V_{CORE} \) domain is powered off. However, it is possible to preserve the SRAM1, SRAM2a and SRAM2b contents:
  • – Standby mode with SRAM1, SRAM2a and SRAM2b retention when bit RRS is set in the PWR control register 3 (PWR_CR3) . In this case, SRAM1, SRAM2a and SRAM2b are supplied by the low-power regulator.
  • – Standby mode when bit RRS is cleared in the PWR control register 3 (PWR_CR3) .

In this case the main regulator and the low-power regulator are powered off.

All clocks in the \( V_{CORE} \) domain are stopped, the PLL, the MSI, the HSI16 and the HSE are disabled. The LSI and the LSE can be kept running.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The system clock, when exiting Standby modes, is HSI16.

The radio must be disabled before entering Standby mode.

• • Shutdown mode: \( V_{CORE} \) domain is powered off. All clocks in the \( V_{CORE} \) domain are stopped, the PLL, the MSI, the HSI16, the LSI and the HSE are disabled. The LSE can be kept running. The system clock, when exiting Shutdown mode, is MSI at 4 MHz. In this mode, the supply voltage monitoring is disabled and the product behavior is not guaranteed in case of a power voltage drop.

Note: Stop, Standby, and Shutdown modes are only entered when both CPUs are in CStop mode.

In addition, the power consumption in Run mode can be reduced by slowing down the system clocks, and/or by gating the clocks to the APB and AHB peripherals when they are unused.

The system operation mode depend on the CPU1, the CPU2 and the Radio sub-system operating mode. The system enters a low power mode only when all three sub-systems allow it to do so.

After a system reset the CPU1 is in CRUN mode. The CPU2 boots only if enabled by the CPU1 via the C2BOOT register bit. As long as the CPU1 does not boot the CPU2, the device operates as a single CPU system. The CPU1 can enter and wake up from system low power modes on its own.

When CPU2 has boot, the CPU1, CPU2 and Radio sub-systems can enter and wake up from system low power modes on their own. The different wake-up sources for the different sub-systems are detailed in Table 21 .

Table 21. Sub-system low power wake-up sources

The system low power mode to enter depends on the allowed mode selected by both CPUs in the LPMS bits of PWR control register 1 (PWR_CR1) and PWR CPU2 control register 1 (PWR_C2CR1) . This is also valid when CPU2 is kept in hold by C2BOOT.

Figure 11 shows the operating modes state diagram. The CPU1, CPU2 and Radio sub-systems operate interdependently, according to their own sub-system states. Each sub-system has its own wake-up sources, to wake up from Stop and Standby modes. For the device to be in Stop, Standby or Shutdown mode, all three sub-systems need to be in CStop. When one sub-system enters CRun mode, the device enters Run mode.

Figure 11. Low-power modes possible transitions

Table 22. Low-power mode summary

1. Refer to Table 23 .

Table 23. Functionalities depending on system operating mode ⁽¹⁾

1. Legend: Y = Yes (enabled). O = Optional (disabled by default, can be enabled by software). R = data retained. - = Not available. Gray cells indicate Wakeup capability.
2. The content of SRAM1, SRAM2a and SRAM2b needs to be retained via the PWR_CR3.RRS bit.
3. The SRAM clock can be gated on or off.
4. The SRAM1, SRAM2a and SRAM2b content can optionally be retained when the PWR_CR3.RRS bit is set.
5. Some peripherals with wake-up from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore.
6. UART reception is functional in Stop mode, and generates a wake-up interrupt on Start, address match or received frame event.
7. I2C address detection is functional in Stop mode, and generates a wake-up interrupt in case of address match.
8. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
9. The I/Os with wake-up from Standby/Shutdown capability are PA0 and PA2.
10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop0, Stop1, Standby or Shutdown mode while the debug features are used. This is because the CPU1 core is no longer clocked.

However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details refer to Section 31.3.5: Debug and low power modes .

6.4.1 Run mode

Slowing down system clocks

In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down the peripherals before entering Sleep mode.

For more details, refer to Section 8.4.3: RCC clock configuration register (RCC_CFGR) .

Peripheral clock gating

In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped at any time to reduce the power consumption.

To further reduce the power consumption in Sleep mode, the peripheral clocks can be disabled prior to executing WFI or WFE instructions.

The peripheral clock gating is controlled by the RCC_AHBxENR and RCC_APBxENR registers.

Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in the RCC_AHBxSMENR and RCC_APBxSMENR registers.

6.4.2 Low-power run mode (LP run)

To further reduce the consumption when the system is in Run mode, the regulator can be configured in low-power mode. In this mode, the system frequency must not exceed 2 MHz. The Radio sub-system cannot be used in low-power Run mode.

Refer to the product datasheet for more details on voltage regulator and peripherals operating conditions.

I/O states in Low-power run mode

In Low-power run mode, all I/O pins keep the same state as in Run mode.

Entering Low-power run mode

To enter the Low-power run mode, proceed as follows:

1. 1. Optional: Jump into the SRAM and power-down the flash memory by setting the FPDR bit in PWR control register 1 (PWR_CR1) and PWR CPU2 control register 1 (PWR_C2CR1) .
2. 2. Decrease the system clock frequency below 2 MHz.
3. 3. Force the regulator in low-power mode by setting the LPR bit in the PWR control register 1 (PWR_CR1) .

Refer to Table 24 on how to enter the Low-power run mode.

Exiting Low-power run mode

To exit the Low-power run mode, proceed as follows (refer to Table 24 ):

1. 1. Force the regulator in main mode by clearing the LPR bit in the PWR control register 1 (PWR_CR1) .
2. 2. Wait until REGLPF bit is cleared in the PWR status register 2 (PWR_SR2) .
3. 3. Increase the system clock frequency.

6.4.3 Entering Low-power mode

Low power modes are entered by the MCU by executing WFI (Wait for Interrupt), or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the CPU1 System control register is set on Return from ISR.

Entering Low-power mode through WFI or WFE is executed only if no interrupt is pending or no event is pending.

6.4.4 Exiting Low-power mode

From Sleep modes, and Stop modes the MCU exit Low-power mode depending on the way the mode was entered:

• • If the WFI instruction or Return from ISR was used to enter the Low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device.
• • If the WFE instruction is used to enter the Low-power mode, the MCU exits the Low-power mode as soon as an event occurs. The wake-up event can be generated either by an NVIC IRQ interrupt, or by an event.

• – In the first case, when SEVONPEND = 0 in the CPU System control register, enabling an interrupt in the peripheral control register and in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. Only NVIC interrupts with sufficient priority wake-up and interrupt the MCU.

When SEVONPEND = 1 in the CPU System control register, enabling an interrupt in the peripheral control register and optionally in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. All NVIC interrupts wake up the MCU, even the disabled ones. Only enabled NVIC interrupts with sufficient priority wake up and interrupt the MCU.

• – In the second case, configuring an EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It may be necessary to clear the interrupt flag in the peripheral.

From Standby and Shutdown modes the MCU exits Low-power mode through an external reset (NRST pin), an IWDG reset, a rising/falling edge on one of the enabled WKUPx pins,

or an RTC event (see Section 23: Real-time clock (RTC) ), or a Radio event (for Standby only).

After waking up from Standby or Shutdown mode, program execution restarts in the same way as after a Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).

The system mode when the CPU wakes up from CStop mode can be determined from the CnSTOPF and CnSBF in PWR extended status and status clear register (PWR_EXTSCR) .

Table 25. CPU CSTOP wake-up vs. system operating mode

6.4.5 Sleep mode

I/O states in Sleep mode

In Sleep mode, all I/O pins keep the same state as in Run mode.

Entering Sleep mode

Sleep mode is entered according to Entering Low-power mode , when the SLEEPDEEP bit in the CPU System control register is cleared (see Table 26 ).

Exiting Sleep mode

The MCU exits from Sleep mode (see Table 26 ) as indicated in Exiting Low-power mode .

Table 26. Sleep mode

6.4.6 Low-power sleep mode (LP sleep)

Refer to the product datasheet for more details on voltage regulator and peripherals operating conditions.

I/O states in Low-power sleep mode

In Low-power sleep mode, all I/O pins keep the same state as in Run mode.

Entering Low-power sleep mode

Low-power sleep mode is entered from Low-power run mode as described in Section 6.4.3 , when the SLEEPDEEP bit in the Cortex® System control register is cleared.

Refer to Table 27 for details on how to enter the Low-power sleep mode.

Exiting Low-power sleep mode

The low-power Sleep mode is exited as described in Section 6.4.4 . When exiting Low-power sleep mode by issuing an interrupt or an event, the MCU is in Low-power run mode.

Refer to Table 27 for details on how to exit the Low-power sleep mode.

Table 27. Low-power sleep

6.4.7 Stop0 mode

The Stop0 mode is based on the CPU deep sleep mode combined with the peripheral clock gating. The voltage regulator is configured in main regulator mode. In Stop0 mode, all clocks in the V _CORE domain are stopped; the PLL, the MSI, the HSI16 and the HSE oscillators are disabled. Some peripherals with wake-up capability (I2Cx (x=1), and USART1) can switch on the HSI16 to receive a frame, and switch off the HSI16 after receiving the frame if it is not a wake-up frame. In this case, the HSI16 clock is propagated only to the peripheral requesting it.

SRAM1, SRAM2 and register contents are preserved.

The BOR is always available in Stop0 mode. The consumption increases when thresholds higher than V _BOR0 are used.

I/O states in Stop0 mode

In the Stop0 mode, all I/O pins keep the same state as in the Run mode.

Entering Stop0 mode

The Stop0 mode is entered according to Section 6.4.3 , when the SLEEPDEEP bit in the

Cortex System control register is set (see Table 28 ). Before entering the mode, the system clock must be set to HSI16 clock.

If flash memory programming is ongoing, the Stop0 mode entry is delayed until the operation is completed.

If an access to the APB domain is ongoing, the Stop0 mode entry is delayed until the APB access is finished.

In Stop0 mode, the following features can be selected by programming individual control bits:

• • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started, it cannot be stopped except by a reset. See Section 24.3: IWDG functional description .
• • Real-time clock (RTC): this is configured by the RTCEN bit in the RCC backup domain control register (RCC_BDCR) .
• • Internal RC oscillator (LSI): this is configured by the LSIxON bit in the RCC control/status register (RCC_CSR) .
• • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RCC backup domain control register (RCC_BDCR) .

Some peripherals can be used in Stop0 mode and add consumption if they are enabled and clocked by LSI or LSE, or when they request the HSI16 clock, namely LPTIM1, LPTIM2, I2Cx (x=1), USART1.

The PVD can be used in Stop0 mode. If not needed, it must be disabled by software to reduce power consumption.

The ADC and the temperature sensor can consume power during the Stop0 mode, unless they are disabled before entering this mode.

Exiting Stop0 mode

The Stop0 mode is exited according to what indicated in Section 6.4.4 .

Refer to Table 28 for details on how to exit Stop0 mode.

When exiting Stop0 mode by issuing an interrupt or a wake-up event, the HSI16 oscillator is selected as system clock if the bit STOPWUCK is set in RCC clock configuration register (RCC_CFGR) . The MSI oscillator is selected as system clock if the bit STOPWUCK is cleared. The wake-up time is shorter when HSI16 is selected as wake-up system clock. The MSI selection enables wake-up at higher frequency, up to 48 MHz.

When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop0 mode with HSI16. By keeping the internal regulator ON during Stop0 mode, the consumption is higher but the startup time is reduced.

When exiting Stop0 mode, the MCU is either in Run mode or in Low-power run mode if the bit LPR is set in the same register.

Table 28. Stop0 mode

6.4.8 Stop1 mode

The Stop1 mode is the same as Stop0 mode except that the main regulator is OFF, and only the low-power regulator is ON. Stop1 mode can be entered from Run mode and from Low-power run mode. Before entering the mode, the system clock must be set to HSI16 clock.

Refer to Table 29 for details on how to enter and exit Stop1 mode.

Table 29. Stop1 mode

6.4.9 Standby mode

Standby mode makes it possible to achieve the lowest power consumption with BOR. It is based on the CPU deepsleep mode, with the voltage regulators disabled (except when SRAM2 content is preserved). The PLL, the HSI16, the MSI and the HSE oscillators are also switched off.

Register contents are lost except for registers in the Backup domain and Standby circuitry (see Figure 7 ). SRAM1 and SRAM2 content can be preserved if the bit RRS is set in the PWR control register 3 (PWR_CR3) . In this case the Low-power regulator is ON and provides the supply to SRAM1 and SRAM2.

The BOR is always available in Standby mode. The consumption is increased when thresholds higher than \( V_{BOR0} \) are used.

I/O states in Standby mode

In Standby mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx registers (x=A,B,C,D,E,F,G,H)), or with a pull-down (refer to PWR_PDCRx registers (x=A,B,C,D,E,F,G,H)), or can be kept in analog state.

The RTC outputs on PC14 and PC15 used for LSE are functional. Two wake-up pins (WKUPx, x=1,4) and the RTC tamper are available.

Entering Standby mode

Standby mode is entered according to Section 6.4.3 , when the SLEEPDEEP bit in the Cortex System control register is set.

Refer to Table 30 for details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control bits:

• • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See Section 24.3: IWDG functional description .
• • Real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR).
• • Internal RC oscillator (LSI): this is configured by the LSIxON bit in the Control/status register (RCC_CSR).
• • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR)

Exiting Standby mode

Standby mode is exited according to Section 6.4.4 . The SBF status flag in the PWR extended status and status clear register (PWR_EXTSCR) indicates that the MCU was in Standby mode. All registers are reset after wake-up from Standby except for PWR control register 3 (PWR_CR3) .

Refer to Table 30 for more details on how to exit Standby mode.

6.4.10 Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. It is based on the deepsleep mode, with the voltage regulator disabled. The V _CORE domain is consequently powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off.

SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain. The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.

I/O states in Shutdown mode

In the Shutdown mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx registers (x=A,B,C,D,E,F,G,H)), or with a pull-down (refer to PWR_PDCRx registers (x=A,B,C,D,E,F,G,H)), or can be kept in analog state.

However this configuration is lost when exiting Shutdown mode due to the power-on reset.

PC14 and PC15 used for LSE are also functional. Two wake-up pins (WKUPx, x=1,4) and the RTC tamper are available.

Entering Shutdown mode

The Shutdown mode is entered according to Entering Low-power mode , when the SLEEPDEEP bit in the Cortex System control register is set.

Refer to Table 31 for details on how to enter Shutdown mode.

In Shutdown mode, the following features can be selected by programming individual control bits:

• • Real-time clock (RTC): this is configured by the RTCEN bit in the RCC backup domain

control register (RCC_BDCR) . Caution: in case of \( V_{DD} \) power-down the RTC content is lost.

• • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RCC backup domain control register (RCC_BDCR) .

Exiting Shutdown mode

The Shutdown mode is exited according to Exiting Low-power mode . A power-on reset occurs when exiting from Shutdown mode. All registers (except for the ones in the Backup domain) are reset after wake-up from Shutdown.

Refer to Table 31 for more details on how to exit Shutdown mode.

Table 31. Shutdown mode

6.4.11 Auto wake-up from Low-power mode

The RTC can be used to wake up the MCU from Low-power mode without depending on an external interrupt (Auto-wake-up mode). The RTC provides a programmable time base for waking up from Stop (0, 1 or 2) or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the RCC backup domain control register (RCC_BDCR) :

• • Low-power 32.768 kHz external crystal oscillator (LSE OSC)
  This clock source provides a precise time base with very low power consumption.
• • Low-power internal RC oscillator (LSI)
  This oscillator is designed to add minimum power consumption.

To wake up from Stop mode with an RTC alarm event, it is necessary to:

• • Configure the EXTI Line 17 to be sensitive to rising edge
• • Configure the RTC to generate the RTC alarm

To wake up from Standby mode, there is no need to configure the EXTI Line 17.

To wake up from Stop mode with an RTC wake-up event, it is necessary to:

• • Configure the EXTI Line 19 to be sensitive to rising edge
• • Configure the RTC to generate the RTC alarm

To wake up from Standby mode, there is no need to configure the EXTI Line 19.

6.5 Real-time radio information

The PWR provides flags indicating the real time operation on the radio:

• • BLE radio activity end interrupt flag
• • Critical radio phase flag
• • Critical radio phase end interrupt flag

These flags may be used by the CPU1 to determine the radio activity.

The basic timing relation for the different flags is shown in Figure 11 .

Figure 12. Real-time radio activity flags

When enabled, the radio activity end interrupt flag BLEAF indicates the end of a BLE radio activity period, and is generated when the radio enters Cstop mode.

The critical radio phase flag indicates the critical real time phase of the radio, where access to the flash memory must not be blocked by erase or program operations (all erase and program operations are suspended by the CPU2 in the flash memory interface). The end of the critical radio phase may be triggered by the CPU2 clearing the critical radio phase flag CRPF, and is eventually cleared at the end of the BLE radio activity.

When enabled, the critical radio phase end interrupt flag CRPEF indicates the end of a radio critical phase, and is generated when the radio critical phase ends.

6.6 PWR registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

6.6.1 PWR control register 1 (PWR_CR1)

Address offset: 0x000

Reset value: 0x0000 0200. This register is reset after wake-up from Standby mode, except for bits [2:0].

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 LPR : Low-power run

Note: When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR).

Bits 13:9 Reserved, must be kept at reset value.

Bit 8 DBP : Disable backup domain write protection

In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers.

0: Access to RTC and Backup registers disabled

1: Access to RTC and Backup registers enabled

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 FPDS : Flash memory power down mode during LPSleep for CPU1

This bit selects whether the flash memory is in power down mode or idle mode when both CPUs are in Sleep mode. flash memory is set in power down mode only when the system is in LPSleep mode and the PWR_C2CR1.FPDS bit from CPU2 also allows this.

0: Flash memory in Idle mode when system is in LPSleep mode

1: Flash memory in power down mode when system is in LPSleep mode

Bit 4 FPDR : Flash memory power down mode during LPRun for CPU1

This bit can only be written to 1 after unlocking this register bit, by first writing (code 0xC1B0) into this register (when writing the code, the register bits are not updated). Selects whether the flash memory is in power down mode or idle mode when in LPRun mode. (flash memory can only be in power down mode when code is executed from SRAM). Flash memory is set in power down mode only when the system is in LPRun mode, and the PWR_C2CR1.FPDR bit from CPU2 too allows so.

0: Flash memory in Idle mode when system is in LPRun mode

1: Flash memory in power down mode when system is in LPRun mode

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 LPMS[2:0] : Low-power mode selection for CPU1

These bits are not reset when exiting Standby mode.

These bits select the low-power mode allowed when CPU1 enters the deepsleep mode. The entered system low-power mode depends also upon the PWR_C2CR1.LPMS allowed low-power mode from CPU2.

000: Stop0 mode
001: Stop1 mode
010: Reserved
011: Standby mode
1xx: Shutdown mode

Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3.

6.6.2 PWR control register 2 (PWR_CR2)

Address offset: 0x004

Reset value: 0x0000 0000. This register is reset when exiting Standby mode.

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:1 PLS[2:0] : Programmable voltage detector level selection.

These bits select the voltage threshold detected by the Programmable voltage detector:

000: \( V_{PVD0} \sim 2.0\text{ V} \)
001: \( V_{PVD1} \sim 2.2\text{ V} \)
010: \( V_{PVD2} \sim 2.4\text{ V} \)
011: \( V_{PVD3} \sim 2.5\text{ V} \)
100: \( V_{PVD4} \sim 2.6\text{ V} \)
101: \( V_{PVD5} \sim 2.8\text{ V} \)
110: \( V_{PVD6} \sim 2.9\text{ V} \)
111: External input analog voltage PVD_IN (compared internally to \( V_{DDA} \) ). The I/O used as PVD_IN input must be configured in analog mode in the GPIO register.

Note: These bits are write-protected when the bit PVDL (PVD lock) is set in the SYSCFG_CBR register, they are reset only by a system reset.

Bit 0 PVDE : Programmable voltage detector enable

0: Programmable voltage detector disabled
1: Programmable voltage detector enabled

Note: This bit is write-protected when bit PVDL (PVD lock) is set in the SYSCFG_CBR register. This bit is reset only by a system reset.

6.6.3 PWR control register 3 (PWR_CR3)

Address offset: 0x008

Reset value: 0x0000 8000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 EIWUL : Enable internal wake-up line for CPU1

0: Internal wake-up line interrupt to CPU1 disabled

1: Internal wake-up line interrupt to CPU1 enabled

Bit 14 EC2H : Enable CPU2 Hold interrupt for CPU1

Enable CPU2 kept in hold, due to C2BOOT, interrupt to CPU1.

0: Interrupt to CPU1 disabled

1: interrupt to CPU1 enabled

Bit 13 Reserved, must be kept at reset value.

Bit 12 EBLEA : Enable BLE end of activity interrupt for CPU1

0: Interrupt to CPU1 disabled

1: interrupt to CPU1 enabled

Bit 11 ECRPE : Enable critical radio phase end of activity interrupt for CPU1

0: Interrupt to CPU1 disabled

1: interrupt to CPU1 enabled

Bit 10 APC : Apply pull-up and pull-down configuration from CPU1

When this bit for CPU1 or the PWR_C2CR3.APC bit for CPU2 is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When both bits are cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os.

Bit 9 RRS : SRAM1, SRAM2a and SRAM2b retention in Standby mode

0: SRAM1, SRAM2a and SRAM2b powered off in Standby mode (content is lost).

1: SRAM1, SRAM2a and SRAM2b powered by the low-power regulator in Standby mode (content is kept).

Bit 8 EBORHSMPSFB : Enable BORH interrupts for CPU1

0: Interrupts BORHF to CPU1 disabled

1: interrupts BORHF to CPU1 enabled

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 EWUP4 : Enable wake-up pin WKUP4 for CPU1

When this bit is set, the external wake-up pin WKUP4 is enabled and triggers an interrupt and wake-up from Stop, Standby or Shutdown event when a rising or a falling edge occurs to CPU1. The active edge is configured via the WP4 bit in the PWR control register 4 (PWR_CR4) .

Bits 2:1 Reserved, must be kept at reset value.

Bit 0 EWUP1 : Enable wake-up pin WKUP1 for CPU1

When this bit is set, the external wake-up pin WKUP1 is enabled and triggers an interrupt and wake-up from Stop, Standby or Shutdown event when a rising or a falling edge occurs to CPU1. The active edge is configured via the WP1 bit in the PWR control register 4 (PWR_CR4) .

6.6.4 PWR control register 4 (PWR_CR4)

Address offset: 0x00C

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 C2BOOT : Boot CPU2 after reset or wake-up from Stop or Standby modes.

• 0: CPU2 does not boot after reset or wake-up from Stop or Standby modes.
• 1: CPU2 boots after wake-up from Stop or Standby modes.

Bits 14:10 Reserved, must be kept at reset value.

Bit 9 VBRS : V _BAT battery charging resistor selection

• 0: Charge V _BAT through a 5 k \( \Omega \) resistor
• 1: Charge V _BAT through a 1.5 k \( \Omega \) resistor

Bit 8 VBE : V _BAT battery charging enable

• 0: V _BAT battery charging disabled
• 1: V _BAT battery charging enabled

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 WP4 : Wakeup pin WKUP4 polarity

This bit defines the polarity used for an event detection on external wake-up pin, WKUP4

• 0: Detection on high level (rising edge)
• 1: Detection on low level (falling edge)

Bits 2:1 Reserved, must be kept at reset value.

Bit 0 WP1 : Wakeup pin WKUP1 polarity

This bit defines the polarity used for an event detection on external wake-up pin, WKUP1

• 0: Detection on high level (rising edge)
• 1: Detection on low level (falling edge)

6.6.5 PWR status register 1 (PWR_SR1)

Address offset: 0x010

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Two additional APB cycles are needed to read this register vs. a standard APB read.

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 WUFI : Internal wake-up interrupt flag

This bit is set when a wake-up is detected on the internal wake-up line. It is cleared when all internal wake-up sources are cleared.

Bit 14 C2HF : CPU2 Hold interrupt flag

This bit is set when a CPU2 wake-up is detected when C2BOOT = 0. It is cleared by PWR_SCR.CC2HF.

Bit 13 Reserved, must be kept at reset value.

Bit 12 BLEAF : BLE end of activity interrupt flag

This bit is set when a BLE activity ends. It is cleared by PWR_SCR.CBLEAF.

Bit 11 CRPEF : Enable critical radio phase end of activity interrupt flag

This bit is set when Radio phase activity ends. It is cleared by PWR_SCR.CCRPEF.

Bit 10 Reserved, must be kept at reset value.

Bit 9 BLEWUF : BLE wake-up interrupt flag

This bit is set when a wake-up is detected on the BLE line. It is cleared by PWR_SCR.CBLEWUF.

Bit 8 BORHF : BORH interrupt flag

This bit is set when the V _DD rises above the BORH threshold. It is cleared by PWR_SCR.CBORHF.

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 WUF4 : Wakeup flag 4

This bit is set when a wake-up event is detected on wake-up pin, WKUP4. It is cleared by writing '1' in the CWUF4 bit of the PWR status clear register (PWR_SCR) .

Bits 2:1 Reserved, must be kept at reset value.

Bit 0 WUF1 : Wakeup flag 1

This bit is set when a wake-up event is detected on wake-up pin, WKUP1. It is cleared by writing '1' in the CWUF1 bit of the PWR status clear register (PWR_SCR) .

6.6.6 PWR status register 2 (PWR_SR2)

Address offset: 0x014

Reset value: 0x0000 0002. This register is partially reset when exiting Standby/Shutdown modes.

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 PVDO : Programmable voltage detector output

0: \( V_{DD} \) or voltage level on PVD_IN is above the selected PVD threshold

1: \( V_{DD} \) or voltage level on PVD_IN is below the selected PVD threshold

Bit 10 Reserved, must be kept at reset value.

Bit 9 REGLPF : Low-power regulator flag

This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency.

This bit is cleared by hardware when the regulator is ready.

0: The regulator is ready in main mode (MR)

1: The regulator is in low-power mode (LPR)

Bit 8 REGLPS : Low-power regulator started

This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wake-up from Standby mode time may be increased.

0: The low-power regulator is not ready

1: The low-power regulator is ready

Bits 7:0 Reserved, must be kept at reset value.

6.6.7 PWR status clear register (PWR_SCR)

Address offset: 0x018

Reset value: 0x0000 0000

Access: Three additional APB cycles are needed to write this register vs. a standard APB write.

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 CC2HF : Clear CPU2 Hold interrupt flag

Setting this bit clears the C2HF flag in the PWR_SR1 . This bit is always read 0.

1. Bit 13 Reserved, must be kept at reset value.
2. Bit 12 CBLEAF : Clear BLE end of activity interrupt flag
   Setting this bit clears the BLEAF flag in the PWR_SR1. This bit is always read 0.
3. Bit 11 CCRPEF : Clear critical radio phase end of activity interrupt flag
   Setting this bit clears the CRPEF flag in the PWR_SR1. This bit is always read 0.
4. Bit 10 Reserved, must be kept at reset value.
5. Bit 9 CBLEWUF Clear BLE wake-up interrupt flag
   Setting this bit clears the BLEWUF flag in the PWR_SR1. This bit is always read 0.
6. Bit 8 CBORHF : Clear BORH interrupt flag
   Setting this bit clears the SBORHF flag in the PWR_SR1. This bit is always read 0.
7. Bits 7:4 Reserved, must be kept at reset value.
8. Bit 3 CWUF4 : Clear wake-up flag 4
   Setting this bit clears the WUF4 flag in the PWR_SR1 register.
9. Bits 2:1 Reserved, must be kept at reset value.
10. Bit 0 CWUF1 : Clear wake-up flag 1
    Setting this bit clears the WUF1 flag in the PWR_SR1 register.

6.6.8 PWR Port A pull-up control register (PWR_PUCRA)

Address offset: 0x020

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port A pull-up bit y (y=0...15)

When set, this bit activates the pull-up on Px[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3) . The pull-up is not activated if the corresponding PDy bit is also set.

6.6.9 PWR Port A pull-down control register (PWR_PDCRA)

Address offset: 0x024

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port A pull-down bit y (y=0...15)

When set, this bit activates the pull-down on PA[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3) .

6.6.10 PWR Port B pull-up control register (PWR_PUCRB)

Address offset: 0x028

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 PU11 : Port B pull-up bit 11

When set, this bit activates the pull-up on Px[11] when one of the APC bits is set in PWR control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3) . The pull-up is not activated if the corresponding PD11 bit is also set.

Bit 10 Reserved, must be kept at reset value.

Bits 9:0 PUy : Port B pull-up bit y (y=0...9)

When set, this bit activates the pull-up on Px[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3) . The pull-up is not activated if the corresponding PDy bit is also set.

6.6.11 PWR Port B pull-down control register (PWR_PDCRB)

Address offset: 0x02C

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 PD11 : Port B pull-down bit 11

When set, this bit activates the pull-down on PB11 when one of the APC bits is set in PWR control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3) .

Bit 10 Reserved, must be kept at reset value.

Bits 9:0 PDy : Port B pull-down bit y (y=0...9)

When set, this bit activates the pull-down on PB[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3) .

6.6.12 PWR Port C pull-up control register (PWR_PUCRC)

Address offset: 0x030

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:14 PUy : Port C pull-up bit y (y=14,15)

When set, this bit activates the pull-up on Px[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3) . The pull-up is not activated if the corresponding PDy bit is also set.

Bits 13:0 Reserved, must be kept at reset value.

6.6.13 PWR Port C pull-down control register (PWR_PDCRC)

Address offset: 0x034

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:14 PDy : Port C pull-down bit y (y=14,15)

When set, this bit activates the pull-down on PC[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3) .

Bits 13:0 Reserved, must be kept at reset value.

6.6.14 PWR Port E pull-up control register (PWR_PUCRE)

Address offset: 0x040

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 PU4 : Port E pull-up bit 4

When set, this bit activates the pull-up on Px[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3) . The pull-up is not activated if the corresponding PD4 bit is also set.

Bits 3:0 Reserved, must be kept at reset value.

6.6.15 PWR Port E pull-down control register (PWR_PDCRE)

Address offset: 0x044

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 PD4 : Port E pull-down bit 4

When set, this bit activates the pull-down on PE4 when one of the APC bits is set in PWR control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3) .

Bits 3:0 Reserved, must be kept at reset value.

6.6.16 PWR Port H pull-up control register (PWR_PUCRH)

Address offset: 0x058

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 PU3 : Port H pull-up bit 3

When set, this bit activates the pull-up on PH[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3) .

The pull-up is not activated if the corresponding PDy bit is also set.

Bits 2:0 Reserved, must be kept at reset value.

6.6.17 PWR Port H pull-down control register (PWR_PDCRH)

Address offset: 0x05C

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 PD3 : Port H pull-down bit 3

When set, this bit activates the pull-down on PH[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3) .

Bits 2:0 Reserved, must be kept at reset value.

6.6.18 PWR CPU2 control register 1 (PWR_C2CR1)

Address offset: 0x080

Reset value: 0x0000 0000. This register is reset after wake-up from Standby mode, except for bits [2:0].

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 BLEEWKUP : BLE external wake-up

When set this bit forces a wake-up of the BLE controller. It is automatically reset when BLE controller exits its sleep mode.

0: No action

1: Wakeup BLE controller from its sleep mode

Bits 13:6 Reserved, must be kept at reset value.

Bit 5 FPDS : Flash memory power down mode during LPSleep for CPU2

This bit selects whether the flash memory is in power down mode or idle mode when both CPUs are in Sleep mode. flash memory is set in power down mode only when the system is in LPSleep mode and the PWR_CR1.FPDS bit from CPU1 also allows so.

0: Flash memory in Idle mode when system is in LPSleep mode

1: Flash memory in power down mode when system is in LPSleep mode

Bit 4 FPDR : Flash memory power down mode during LPRun for CPU2

This bit can only be written to 1 after unlocking this register bit, by first writing (code 0xC1B0) into this register (when writing the code register bits are not updated). Selects whether the flash memory is in power down mode or idle mode when in LPRun mode. (flash memory can only be in power down mode when code is executed from SRAM). Flash memory is set in power down mode only when the system is in LPRun mode, and the PWR_CR1.FPDR bit from CPU1 also allows so.

0: Flash memory in Idle mode when system is in LPRun mode

1: Flash memory in power down mode when system is in LPRun mode

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 LPMS[2:0] : Low-power mode selection for CPU2

These bits are not reset when exiting Standby mode.

These bits select the low-power mode entered when CPU2 enters the deepsleep mode. The system low-power mode entered depend also on the PWR_CR1.LPMS allowed low-power mode from CPU1.

000: Stop0 mode

001: Stop1 mode

010: Reserved

011: Standby mode

1xx: Shutdown mode

Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR control register 3 (PWR_CR3).

6.6.19 PWR CPU2 control register 3 (PWR_C2CR3)

Address offset: 0x084

Reset value: 0x0000 8000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 EIWUL : Enable internal wake-up line for CPU2

0: Internal wake-up line to CPU2 disabled

1: Internal wake-up line to CPU2 enabled

Bits 14:13 Reserved, must be kept at reset value.

Bit 12 APC : Apply pull-up and pull-down configuration for CPU2

When this bit for CPU2 or the PWR_CR3.APC bit for CPU1 is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied.

When both bits are cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os.

Bits 11:10 Reserved, must be kept at reset value.

Bit 9 EBLEWUP Enable BLE host wake-up interrupt for CPU2

0: Interrupt to CPU2 disabled

1: interrupt to CPU2 enabled

Bits 8:4 Reserved, must be kept at reset value.

Bit 3 EWUP4 : Enable wake-up pin WKUP4 for CPU2

When this bit is set, the external wake-up pin WKUP4 is enabled and triggers an interrupt and wake-up from Stop, Standby or Shutdown event when a rising or a falling edge occurs to CPU2. The active edge is configured via the WP4 bit in the PWR control register 4 (PWR_CR4) .

Bits 2:1 Reserved, must be kept at reset value.

Bit 0 EWUP1 : Enable wake-up pin WKUP1 for CPU2

When this bit is set, the external wake-up pin WKUP1 is enabled and triggers an interrupt and wake-up from Stop, Standby or Shutdown event when a rising or a falling edge occurs to CPU2. The active edge is configured via the WP1 bit in the PWR control register 4 (PWR_CR4) .

6.6.20 PWR extended status and status clear register (PWR_EXTSCR)

Address offset: 0x088

Reset value: 0x0000 0000

Access: Three additional APB cycles are needed to write this register vs. a standard APB write.

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 C2DS : CPU2 deepsleep mode

This bit is set by hardware when CPU2 enters deepsleep mode or is hold by C2BOOT.

0: CPU2 is running or in sleep

1: CPU2 is in deepsleep or hold by C2BOOT

Bit 14 C1DS : CPU1 deepsleep mode

This bit is set by hardware when CPU1 enters deepsleep mode.

0: CPU1 is running or in sleep

1: CPU1 is in deepsleep

Bit 13 CRPF : Critical Radio system phase

This bit is set by hardware when the Radio system wakes up. It is reset either by hardware when the Radio system enters Low-power mode or by software when writing CCRPF.

0: Not a critical Radio system phase

1: Critical Radio system phase ongoing

Bit 12 Reserved, must be kept at reset value.

Bit 11 C2STOPF : System Stop flag for CPU2.

This bit is set by hardware and cleared only by any reset or by setting C2CSSF bit.

0: System has not been in Stop mode

1: System has been in Stop mode

Bit 10 C2SBF : System Standby flag for CPU2.

This bit is set by hardware and cleared only by a POR reset or by setting C2CSSF bit.

0: System has not been in Standby mode

1: System has been in Standby mode

Bit 9 C1STOPF : System Stop flag for CPU1.

This bit is set by hardware and cleared only by any reset or by setting C1CSSF bit.

0: System has not been in Stop mode

1: System has been in Stop mode

Bit 8 C1SBF : System Standby flag for CPU1.

This bit is set by hardware and cleared only by a POR reset or by setting C1CSSF bit.

0: System has not been in Standby mode

1: System has been in Standby mode

Bits 7:3 Reserved, must be kept at reset value.

Bit 2 CCRPF : Clear critical Radio system phase

Setting this bit clears the CRPF bit.

Bit 1 C2CSSF : Clear CPU2 Stop Standby flags

Setting this bit clears the C2STOPF and C2SBF bits.

Bit 0 C1CSSF : Clear CPU1 Stop Standby flags

Setting this bit clears the C1STOPF and C1SBF bits.

h3. 6.6.21 PWR register map and reset value table

Table 32. PWR register map and reset values

Table 32. PWR register map and reset values (continued)

Refer to Section 2.2 on page 54 for the register boundary addresses.