RM0478-STM32WB10CC

Introduction

This document is addressed to application developers. It provides complete information on how to use the STM32WB10CC microcontroller memory and peripherals.

The STM32WB10CC multiprotocol wireless and ultra-low-power devices embed a powerful and ultra-low-power radio compliant with the Bluetooth ® Low Energy SIG specification 5.4. They contain a dedicated Arm ® Cortex ® -M0+ for performing all the real-time low layer operation.

The STM32WB10CC microcontrollers feature 320 Kbyte flash memory and 48 Kbytes SRAM, and include state of the art patented technology.

Available from STMicroelectronics web site www.st.com :

For information on the Arm ® Cortex ® -M4 and Cortex ® -M0+ cores, refer to the corresponding Technical Reference Manuals, available from the www.arm.com website.

For information on Bluetooth ® refer to www.bluetooth.com .

Contents

1Documentation conventions . . . . .49
1.1General information . . . . .49
1.2List of abbreviations for registers . . . . .49
1.3Register reset value . . . . .50
1.4Glossary . . . . .50
1.5Availability of peripherals . . . . .50
2System and memory overview . . . . .51
2.1System architecture . . . . .51
2.1.1S0: CPU1 (CPU1 Cortex®-M4) I-bus . . . . .52
2.1.2S1: CPU1 (CPU1 Cortex®-M4) D-bus . . . . .52
2.1.3S2: CPU1 (CPU1 Cortex®-M4) S-bus . . . . .52
2.1.4S3: CPU2 (Cortex®-M0+) S-bus . . . . .52
2.1.5S4: DMA-bus . . . . .53
2.1.6S5: Radio system-bus . . . . .53
2.1.7BusMatrix . . . . .53
2.2Memory organization . . . . .54
2.2.1Introduction . . . . .54
2.2.2Memory map and register boundary addresses . . . . .55
2.2.3Bit banding . . . . .59
2.3Boot configuration . . . . .59
2.4CPU2 boot . . . . .61
2.5CPU2 SRAM fetch disable . . . . .61
3Embedded flash memory (FLASH) . . . . .62
3.1Introduction . . . . .62
3.2FLASH main features . . . . .62
3.3FLASH functional description . . . . .63
3.3.1Flash memory organization . . . . .63
3.3.2Empty check . . . . .63
3.3.3Error code correction (ECC) . . . . .64
3.3.4Read access latency . . . . .64
3.3.5Adaptive real-time memory accelerator (ART Accelerator) . . . . .66
3.3.6Flash memory program and erase operations . . . . .69
3.3.7Flash main memory erase sequences . . . . .70
3.3.8Flash main memory programming sequences . . . . .72
3.4FLASH option bytes . . . . .77
3.4.1Option bytes description . . . . .77
3.4.2Option bytes programming . . . . .84
3.5FLASH UID64 . . . . .87
3.6Flash memory protection . . . . .88
3.6.1Read protection (RDP) . . . . .88
3.6.2Proprietary code readout protection (PCROP) . . . . .92
3.6.3Write protection (WRP) . . . . .93
3.6.4CPU2 security (ESE) . . . . .94
3.7FLASH program/erase suspension . . . . .95
3.8FLASH interrupts . . . . .96
3.9Register access protection . . . . .96
3.10FLASH registers . . . . .97
3.10.1Flash memory access control register (FLASH_ACR) . . . . .97
3.10.2Flash memory key register (FLASH_KEYR) . . . . .98
3.10.3Flash memory option key register (FLASH_OPTKEYR) . . . . .98
3.10.4Flash memory status register (FLASH_SR) . . . . .99
3.10.5Flash memory control register (FLASH_CR) . . . . .100
3.10.6Flash memory ECC register (FLASH_ECCR) . . . . .102
3.10.7Flash memory option register (FLASH_OPTR) . . . . .103
3.10.8Flash memory PCROP zone A start address register
(FLASH_PCROP1ASR) . . . . .		106
3.10.9Flash memory PCROP zone A end address register
(FLASH_PCROP1AER) . . . . .		106
3.10.10Flash memory WRP area A address register (FLASH_WRP1AR) . . . . .107
3.10.11Flash memory WRP area B address register (FLASH_WRP1BR) . . . . .107
3.10.12Flash memory PCROP zone B start address register
(FLASH_PCROP1BSR) . . . . .		108
3.10.13Flash memory PCROP zone B end address register
(FLASH_PCROP1BER) . . . . .		108
3.10.14Flash memory IPCC mailbox data buffer address register
(FLASH_IPCCBR) . . . . .		109
3.10.15Flash memory CPU2 access control register (FLASH_C2ACR) . . . . .109
3.10.16Flash memory CPU2 status register (FLASH_C2SR) . . . . .110
3.10.17Flash memory CPU2 control register (FLASH_C2CR) . . . . .112

3.10.18 Secure flash memory start address register (FLASH_SFR) . . . . . 113

3.10.19 Flash memory secure SRAM2 start address and CPU2 reset vector register (FLASH_SRRVR) . . . . . 114

3.10.20 FLASH register map . . . . . 116

4 Radio system . . . . . 118

4.1 Introduction . . . . . 118

4.2 Main features . . . . . 118

4.3 Radio system functional description . . . . . 119

4.3.1 General description . . . . . 119

5 Cyclic redundancy check calculation unit (CRC) . . . . . 120

5.1 Introduction . . . . . 120

5.2 CRC main features . . . . . 120

5.3 CRC functional description . . . . . 121

5.3.1 CRC block diagram . . . . . 121

5.3.2 CRC internal signals . . . . . 121

5.3.3 CRC operation . . . . . 121

5.4 CRC registers . . . . . 123

5.4.1 CRC data register (CRC_DR) . . . . . 123

5.4.2 CRC independent data register (CRC_IDR) . . . . . 123

5.4.3 CRC control register (CRC_CR) . . . . . 124

5.4.4 CRC initial value (CRC_INIT) . . . . . 125

5.4.5 CRC polynomial (CRC_POL) . . . . . 125

5.4.6 CRC register map . . . . . 126

6 Power control (PWR) . . . . . 127

6.1 Power supplies . . . . . 127

6.1.1 Independent analog peripherals supply . . . . . 128

6.1.2 Battery backup domain . . . . . 128

6.1.3 Voltage regulator . . . . . 129

6.2 Power supply supervisor . . . . . 130

6.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) . . . . . 130

6.2.2 Programmable voltage detector (PVD) . . . . . 131

6.3 CPU2 boot . . . . . 132

6.4 Low-power modes . . . . . 134

6.4.1Run mode .....140
6.4.2Low-power run mode (LP run) .....140
6.4.3Entering Low-power mode .....141
6.4.4Exiting Low-power mode .....141
6.4.5Sleep mode .....142
6.4.6Low-power sleep mode (LP sleep) .....143
6.4.7Stop0 mode .....144
6.4.8Stop1 mode .....146
6.4.9Standby mode .....147
6.4.10Shutdown mode .....149
6.4.11Auto wake-up from Low-power mode .....150
6.5Real-time radio information .....151
6.6PWR registers .....152
6.6.1PWR control register 1 (PWR_CR1) .....152
6.6.2PWR control register 2 (PWR_CR2) .....153
6.6.3PWR control register 3 (PWR_CR3) .....153
6.6.4PWR control register 4 (PWR_CR4) .....155
6.6.5PWR status register 1 (PWR_SR1) .....155
6.6.6PWR status register 2 (PWR_SR2) .....156
6.6.7PWR status clear register (PWR_SCR) .....157
6.6.8PWR Port A pull-up control register (PWR_PUCRA) .....158
6.6.9PWR Port A pull-down control register (PWR_PDCRA) .....158
6.6.10PWR Port B pull-up control register (PWR_PUCRB) .....159
6.6.11PWR Port B pull-down control register (PWR_PDCRB) .....159
6.6.12PWR Port C pull-up control register (PWR_PUCRC) .....160
6.6.13PWR Port C pull-down control register (PWR_PDCRC) .....160
6.6.14PWR Port E pull-up control register (PWR_PUCRE) .....161
6.6.15PWR Port E pull-down control register (PWR_PDCRE) .....161
6.6.16PWR Port H pull-up control register (PWR_PUCRH) .....162
6.6.17PWR Port H pull-down control register (PWR_PDCRH) .....162
6.6.18PWR CPU2 control register 1 (PWR_C2CR1) .....163
6.6.19PWR CPU2 control register 3 (PWR_C2CR3) .....164
6.6.20PWR extended status and status clear register (PWR_EXTSCR) .....165
6.6.21PWR register map and reset value table .....167
7Peripherals interconnect matrix .....169
7.1Introduction .....169
8.4RCC registers . . . . .191
8.4.1RCC clock control register (RCC_CR) . . . . .191
8.4.2RCC internal clock sources calibration register (RCC_ICSCR) . . . . .194
8.4.3RCC clock configuration register (RCC_CFGR) . . . . .195
8.4.4RCC PLL configuration register (RCC_PLLCFGR) . . . . .197
8.4.5RCC clock interrupt enable register (RCC_CIER) . . . . .200
8.4.6RCC clock interrupt flag register (RCC_CIFR) . . . . .201
8.4.7RCC clock interrupt clear register (RCC_CICR) . . . . .203
8.4.8RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .204
8.4.9RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .205
8.4.10RCC AHB4 peripheral reset register (RCC_AHB4RSTR) . . . . .206
8.4.11RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . .207
8.4.12RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . .207
8.4.13RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .208
8.4.14RCC APB3 peripheral reset register (RCC_APB3RSTR) . . . . .209
8.4.15RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .209
8.4.16RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .210
8.4.17RCC AHB4 peripheral clock enable register (RCC_AHB4ENR) . . . . .211
8.4.18RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . .212
8.4.19RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . .213
8.4.20RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .213
8.4.21RCC AHB1 peripheral clocks enable in Sleep modes register
(RCC_AHB1SMENR) . . . . .		214
8.4.22RCC AHB2 peripheral clocks enable in Sleep modes register
(RCC_AHB2SMENR) . . . . .		215
8.4.23RCC AHB4 peripheral clocks enable in Sleep and Stop
modes register (RCC_AHB4SMENR) . . . . .		216
8.4.24RCC APB1 peripheral clocks enable in Sleep mode register 1
(RCC_APB1SMENR1) . . . . .		217
8.4.25RCC APB1 peripheral clocks enable in Sleep mode register 2
(RCC_APB1SMENR2) . . . . .		218
8.4.26RCC APB2 peripheral clocks enable in Sleep mode register
(RCC_APB2SMENR) . . . . .		219
8.4.27RCC peripherals independent clock configuration register
(RCC_CCIPR) . . . . .		220
8.4.28RCC backup domain control register (RCC_BDCR) . . . . .221
8.4.29RCC control/status register (RCC_CSR) . . . . .223
8.4.30RCC clock HSE register (RCC_HSECR) . . . . .225
8.4.31RCC extended clock recovery register (RCC_EXTCFGR) . . . . .226
8.4.32RCC CPU2 AHB1 peripheral clock enable register (RCC_C2AHB1ENR) . . . . .228
8.4.33RCC CPU2 AHB2 peripheral clock enable register (RCC_C2AHB2ENR) . . . . .229
8.4.34RCC CPU2 AHB4 peripheral clock enable register (RCC_C2AHB4ENR) . . . . .230
8.4.35RCC CPU2 APB1 peripheral clock enable register 1 (RCC_C2APB1ENR1) . . . . .231
8.4.36RCC CPU2 APB1 peripheral clock enable register 2 (RCC_C2APB1ENR2) . . . . .232
8.4.37RCC CPU2 APB2 peripheral clock enable register (RCC_C2APB2ENR) . . . . .232
8.4.38RCC CPU2 APB3 peripheral clock enable register (RCC_C2APB3ENR) . . . . .233
8.4.39RCC CPU2 AHB1 peripheral clocks enable in Sleep modes register (RCC_C2AHB1SMENR) . . . . .234
8.4.40RCC CPU2 AHB2 peripheral clocks enable in Sleep modes register (RCC_C2AHB2SMENR) . . . . .235
8.4.41RCC CPU2 AHB4 peripheral clocks enable in Sleep mode register (RCC_C2AHB4SMENR) . . . . .236
8.4.42RCC CPU2 APB1 peripheral clocks enable in Sleep mode register 1 (RCC_C2APB1SMENR1) . . . . .237
8.4.43RCC CPU2 APB1 peripheral clocks enable in Sleep mode register 2 (RCC_C2APB1SMENR2) . . . . .238
8.4.44RCC CPU2 APB2 peripheral clocks enable in Sleep mode register (RCC_C2APB2SMENR) . . . . .238
8.4.45RCC CPU2 APB3 peripheral clock enable in Sleep mode register (RCC_C2APB3SMENR) . . . . .239
8.4.46RCC register map . . . . .240
9General-purpose I/Os (GPIO) . . . . .246
9.1Introduction . . . . .246
9.2GPIO main features . . . . .246
9.3GPIO functional description . . . . .246
9.3.1General-purpose I/O (GPIO) . . . . .249
9.3.2I/O pin alternate function multiplexer and mapping . . . . .249
9.3.3I/O port control registers . . . . .250
9.3.4I/O port data registers . . . . .250
9.3.5I/O data bitwise handling . . . . .250
9.3.6GPIO locking mechanism . . . . .251
9.3.7I/O alternate function input/output . . . . .251
9.3.8External interrupt/wakeup lines . . . . .251
9.3.9Input configuration . . . . .251
9.3.10Output configuration . . . . .252
9.3.11Alternate function configuration . . . . .253
9.3.12Analog configuration . . . . .253
9.3.13Using the LSE oscillator pins as GPIOs . . . . .254
9.3.14Using the GPIO pins in the RTC supply domain . . . . .254
9.3.15Using PH3 as GPIO . . . . .254
9.4GPIO registers . . . . .255
9.4.1GPIO port mode register (GPIOx_MODER)
(x = A to C and E, H) . . . . .		255
9.4.2GPIO port output type register (GPIOx_OTYPER)
(x = A to C and E, H) . . . . .		256
9.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to C and E, H) . . . . .		256
9.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to C and E, H) . . . . .		257
9.4.5GPIO port input data register (GPIOx_IDR)
(x = A to C and E, H) . . . . .		257
9.4.6GPIO port output data register (GPIOx_ODR)
(x = A to C and E, H) . . . . .		258
9.4.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to C and E, H) . . . . .		258
9.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to C and E, H) . . . . .		259
9.4.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to C and E, H) . . . . .		260
9.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to C and E, H) . . . . .		261
9.4.11GPIO port bit reset register (GPIOx_BRR) (x = A to C and E, H) . . . . .262
9.4.12GPIO register map . . . . .263
10System configuration controller (SYSCFG) . . . . .268
10.1SYSCFG main features . . . . .268
10.2SYSCFG registers . . . . .268
10.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .268
10.2.2SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .269
10.2.3SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		270
10.2.4SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) .....271
10.2.5SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) .....272
10.2.6SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) .....274
10.2.7SYSCFG SRAM2 control and status register (SYSCFG_SCSR) .....275
10.2.8SYSCFG configuration register 2 (SYSCFG_CFGR2) .....276
10.2.9SYSCFG SRAM2 write protection register (SYSCFG_SWPR1) .....277
10.2.10SYSCFG SRAM2 key register (SYSCFG_SKR) .....277
10.2.11SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2) .....277
10.2.12SYSCFG CPU1 interrupt mask register 1 (SYSCFG_IMR1) .....278
10.2.13SYSCFG CPU1 interrupt mask register 2 (SYSCFG_IMR2) .....278
10.2.14SYSCFG CPU2 interrupt mask register 1 (SYSCFG_C2IMR1) .....279
10.2.15SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2) .....279
10.2.16SYSCFG secure IP control register (SYSCFG_SIPCR) .....280
10.2.17SYSCFG register map .....282
11Direct memory access controller (DMA) .....284
11.1Introduction .....284
11.2DMA main features .....284
11.3DMA implementation .....285
11.3.1DMA1 .....285
11.3.2DMA request mapping .....285
11.4DMA functional description .....285
11.4.1DMA block diagram .....285
11.4.2DMA pins and internal signals .....286
11.4.3DMA transfers .....286
11.4.4DMA arbitration .....287
11.4.5DMA channels .....287
11.4.6DMA data width, alignment, and endianness .....291
11.4.7DMA error management .....292
11.5DMA interrupts .....293
11.6DMA registers .....293
11.6.1DMA interrupt status register (DMA_ISR) .....293
11.6.2DMA interrupt flag clear register (DMA_IFCR) .....295
11.6.3DMA channel x configuration register (DMA_CCRx) .....297
11.6.4DMA channel x number of data to transfer register (DMA_CNDTRx)299
11.6.5DMA channel x peripheral address register (DMA_CPARx)300
11.6.6DMA channel x memory address register (DMA_CMARx)301
11.6.7DMA register map301
12DMA request multiplexer (DMAMUX)304
12.1Introduction304
12.2DMAMUX main features305
12.3DMAMUX implementation305
12.3.1DMAMUX instantiation305
12.3.2DMAMUX mapping305
12.4DMAMUX functional description308
12.4.1DMAMUX block diagram308
12.4.2DMAMUX signals309
12.4.3DMAMUX channels309
12.4.4DMAMUX request line multiplexer309
12.4.5DMAMUX request generator312
12.5DMAMUX interrupts313
12.6DMAMUX registers314
12.6.1DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR)314
12.6.2DMAMUX request line multiplexer interrupt channel status register (DMAMUX_CSR)315
12.6.3DMAMUX request line multiplexer interrupt clear flag register (DMAMUX_CFR)315
12.6.4DMAMUX request generator channel x configuration register (DMAMUX_RGxCR)316
12.6.5DMAMUX request generator interrupt status register (DMAMUX_RGSR)317
12.6.6DMAMUX request generator interrupt clear flag register (DMAMUX_RGCFR)317
12.6.7DMAMUX register map318
13Nested vectored interrupt controller (NVIC)320
13.1NVIC main features320
13.2Interrupt block diagram320
13.3Interrupt and exception vectors321
13.4Interrupt list326
14Extended interrupt and event controller (EXTI) . . . . .329
14.1EXTI main features . . . . .329
14.2EXTI block diagram . . . . .329
14.2.1EXTI connections between peripherals and CPU . . . . .331
14.3EXTI functional description . . . . .332
14.3.1EXTI configurable event input wakeup . . . . .332
14.3.2EXTI direct event input wakeup . . . . .334
14.4EXTI functional behavior . . . . .334
14.5EXTI registers . . . . .336
14.5.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .336
14.5.2EXTI falling trigger selection register (EXTI_FTSR1) . . . . .337
14.5.3EXTI software interrupt event register (EXTI_SWIER1) . . . . .337
14.5.4EXTI pending register (EXTI_PR1) . . . . .338
14.5.5EXTI rising trigger selection register (EXTI_RTSR2) . . . . .338
14.5.6EXTI falling trigger selection register (EXTI_FTSR2) . . . . .339
14.5.7EXTI software interrupt event register (EXTI_SWIER2) . . . . .339
14.5.8EXTI pending register (EXTI_PR2) . . . . .340
14.5.9EXTI CPU wakeup with interrupt mask register (EXTI_IMR1) . . . . .341
14.5.10EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR1) . . . . .341
14.5.11EXTI CPU wakeup with event mask register (EXTI_EM1) . . . . .342
14.5.12EXTI CPU2 wakeup with event mask register (EXTI_C2EM1) . . . . .342
14.5.13EXTI CPU wakeup with interrupt mask register (EXTI_IMR2) . . . . .343
14.5.14EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR2) . . . . .343
14.5.15EXTI CPU wakeup with event mask register (EXTI_EM2) . . . . .344
14.5.16EXTI CPU2 wakeup with event mask register (EXTI_C2EM2) . . . . .344
14.5.17EXTI register map . . . . .345
15Analog-to-digital converter (ADC) . . . . .347
15.1Introduction . . . . .347
15.2ADC main features . . . . .348
15.3ADC functional description . . . . .349
15.3.1ADC pins and internal signals . . . . .349
15.3.2ADC voltage regulator (ADVREGEN) . . . . .350
15.3.3Calibration (ADCAL) . . . . .351
15.3.4ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .353
15.3.5ADC clock (CKMODE, PRESC[3:0]) . . . . .354
15.3.6ADC connectivity . . . . .356
15.3.7Configuring the ADC . . . . .357
15.3.8Channel selection (CHSEL, SCANDIR, CHSELRMOD) . . . . .357
15.3.9Programmable sampling time (SMPx[2:0]) . . . . .358
15.3.10Single conversion mode (CONT = 0) . . . . .359
15.3.11Continuous conversion mode (CONT = 1) . . . . .359
15.3.12Starting conversions (ADSTART) . . . . .360
15.3.13Timings . . . . .361
15.3.14Stopping an ongoing conversion (ADSTP) . . . . .362
15.4Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . . . . .362
15.4.1Discontinuous mode (DISCEN) . . . . .363
15.4.2Programmable resolution (RES) - Fast conversion mode . . . . .363
15.4.3End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . .364
15.4.4End of conversion sequence (EOS flag) . . . . .364
15.4.5Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . .		365
15.4.6Low frequency trigger mode . . . . .367
15.5Data management . . . . .367
15.5.1Data register and data alignment (ADC_DR, ALIGN) . . . . .367
15.5.2ADC overrun (OVR, OVRMOD) . . . . .367
15.5.3Managing a sequence of data converted without using the DMA . . . . .369
15.5.4Managing converted data without using the DMA without overrun . . . . .369
15.5.5Managing converted data using the DMA . . . . .369
15.6Low-power features . . . . .370
15.6.1Wait mode conversion . . . . .370
15.6.2Auto-off mode (AUTOFF) . . . . .371
15.7Analog window watchdog . . . . .373
15.7.1Description of the analog watchdog . . . . .373
15.7.2ADC_AWD1_OUT output signal generation . . . . .374
15.7.3Analog watchdog threshold control . . . . .376
15.8Temperature sensor and internal reference voltage . . . . .376
15.9Battery voltage monitoring . . . . .379
15.10ADC interrupts . . . . .380
15.11ADC registers . . . . .381
15.11.1ADC interrupt and status register (ADC_ISR) . . . . .381
15.11.2ADC interrupt enable register (ADC_IER) . . . . .382
15.11.3ADC control register (ADC_CR) . . . . .383
15.11.4ADC configuration register 1 (ADC_CFGR1) . . . . .385
15.11.5ADC configuration register 2 (ADC_CFGR2) . . . . .388
15.11.6ADC sampling time register (ADC_SMPR) . . . . .389
15.11.7ADC watchdog threshold register (ADC_TR) . . . . .390
15.11.8ADC channel selection register (ADC_CHSELR) . . . . .391
15.11.9ADC channel selection register [alternate] (ADC_CHSELR) . . . . .391
15.11.10ADC data register (ADC_DR) . . . . .393
15.11.11ADC calibration factor (ADC_CALFACT) . . . . .394
15.11.12ADC common configuration register (ADC_CCR) . . . . .394
15.12ADC register map . . . . .395
16Touch sensing controller (TSC) . . . . .398
16.1Introduction . . . . .398
16.2TSC main features . . . . .398
16.3TSC functional description . . . . .399
16.3.1TSC block diagram . . . . .399
16.3.2Surface charge transfer acquisition overview . . . . .399
16.3.3Reset and clocks . . . . .402
16.3.4Charge transfer acquisition sequence . . . . .402
16.3.5Spread spectrum feature . . . . .403
16.3.6Max count error . . . . .404
16.3.7Sampling capacitor I/O and channel I/O mode selection . . . . .404
16.3.8Acquisition mode . . . . .405
16.3.9I/O hysteresis and analog switch control . . . . .405
16.4TSC low-power modes . . . . .406
16.5TSC interrupts . . . . .406
16.6TSC registers . . . . .406
16.6.1TSC control register (TSC_CR) . . . . .406
16.6.2TSC interrupt enable register (TSC_IER) . . . . .409
16.6.3TSC interrupt clear register (TSC_ICR) . . . . .410
16.6.4TSC interrupt status register (TSC_ISR) . . . . .410
16.6.5TSC I/O hysteresis control register (TSC_IOHCR) . . . . .411
16.6.6TSC I/O analog switch control register
(TSC_IOASCR) . . . . .		411
16.6.7TSC I/O sampling control register (TSC_IOSCR) . . . . .412
16.6.8TSC I/O channel control register (TSC_IOCCR) . . . . .412
16.6.9TSC I/O group control status register (TSC_IOGCSR) . . . . .413
16.6.10TSC I/O group x counter register (TSC_IOGxCR) . . . . .413
16.6.11TSC register map . . . . .414
17True random number generator (RNG) . . . . .416
17.1Introduction . . . . .416
17.2RNG main features . . . . .416
17.3RNG functional description . . . . .417
17.3.1RNG block diagram . . . . .417
17.3.2RNG internal signals . . . . .417
17.3.3Random number generation . . . . .418
17.3.4RNG initialization . . . . .420
17.3.5RNG operation . . . . .421
17.3.6RNG clocking . . . . .422
17.3.7Error management . . . . .422
17.3.8RNG low-power use . . . . .423
17.4RNG interrupts . . . . .423
17.5RNG processing time . . . . .423
17.6RNG entropy source validation . . . . .424
17.6.1Introduction . . . . .424
17.6.2Validation conditions . . . . .424
17.7RNG registers . . . . .425
17.7.1RNG control register (RNG_CR) . . . . .425
17.7.2RNG status register (RNG_SR) . . . . .425
17.7.3RNG data register (RNG_DR) . . . . .426
17.7.4RNG register map . . . . .427
18AES hardware accelerator (AES) . . . . .428
18.1Introduction . . . . .428
18.2AES main features . . . . .428
18.3AES implementation . . . . .428
18.4AES functional description . . . . .429
18.4.1AES block diagram . . . . .429
18.4.2AES internal signals . . . . .429
18.4.3AES cryptographic core . . . . .429
18.4.4AES procedure to perform a cipher operation . . . . .435

19 Public key accelerator (PKA) . . . . . 477

19.2PKA main features . . . . .477
19.3PKA functional description . . . . .477
19.3.1PKA block diagram . . . . .477
19.3.2PKA internal signals . . . . .478
19.3.3PKA reset and clocks . . . . .478
19.3.4PKA public key acceleration . . . . .478
19.3.5Typical applications for PKA . . . . .480
19.3.6PKA procedure to perform an operation . . . . .482
19.3.7PKA error management . . . . .483
19.4PKA operating modes . . . . .483
19.4.1Introduction . . . . .483
19.4.2Montgomery parameter computation . . . . .484
19.4.3Modular addition . . . . .484
19.4.4Modular subtraction . . . . .485
19.4.5Modular and Montgomery multiplication . . . . .485
19.4.6Modular exponentiation . . . . .486
19.4.7Modular inversion . . . . .487
19.4.8Modular reduction . . . . .488
19.4.9Arithmetic addition . . . . .488
19.4.10Arithmetic subtraction . . . . .488
19.4.11Arithmetic multiplication . . . . .489
19.4.12Arithmetic comparison . . . . .489
19.4.13RSA CRT exponentiation . . . . .489
19.4.14Point on elliptic curve Fp check . . . . .490
19.4.15ECC Fp scalar multiplication . . . . .491
19.4.16ECDSA sign . . . . .492
19.4.17ECDSA verification . . . . .494
19.5Example of configurations and processing times . . . . .495
19.5.1Supported elliptic curves . . . . .495
19.5.2Computation times . . . . .497
19.6PKA interrupts . . . . .498
19.7PKA registers . . . . .499
19.7.1PKA control register (PKA_CR) . . . . .499
19.7.2PKA status register (PKA_SR) . . . . .500
19.7.3PKA clear flag register (PKA_CLRFR) . . . . .501
19.7.4PKA RAM . . . . .501

19.7.5 PKA register map . . . . . 502

20 Advanced-control timer (TIM1) . . . . . 503

20.1 TIM1 introduction . . . . . 503

20.2 TIM1 main features . . . . . 504

20.3 TIM1 functional description . . . . . 506

20.3.1 Time-base unit . . . . . 506

20.3.2 Counter modes . . . . . 508

20.3.3 Repetition counter . . . . . 519

20.3.4 External trigger input . . . . . 521

20.3.5 Clock selection . . . . . 522

20.3.6 Capture/compare channels . . . . . 526

20.3.7 Input capture mode . . . . . 528

20.3.8 PWM input mode . . . . . 529

20.3.9 Forced output mode . . . . . 530

20.3.10 Output compare mode . . . . . 531

20.3.11 PWM mode . . . . . 532

20.3.12 Asymmetric PWM mode . . . . . 535

20.3.13 Combined PWM mode . . . . . 536

20.3.14 Combined 3-phase PWM mode . . . . . 537

20.3.15 Complementary outputs and dead-time insertion . . . . . 538

20.3.16 Using the break function . . . . . 540

20.3.17 Bidirectional break inputs . . . . . 546

20.3.18 Clearing the OCxREF signal on an external event . . . . . 548

20.3.19 6-step PWM generation . . . . . 549

20.3.20 One-pulse mode . . . . . 550

20.3.21 Retriggerable one pulse mode . . . . . 551

20.3.22 Encoder interface mode . . . . . 552

20.3.23 UIF bit remapping . . . . . 554

20.3.24 Timer input XOR function . . . . . 555

20.3.25 Interfacing with Hall sensors . . . . . 555

20.3.26 Timer synchronization . . . . . 558

20.3.27 ADC synchronization . . . . . 562

20.3.28 DMA burst mode . . . . . 562

20.3.29 Debug mode . . . . . 563

20.4 TIM1 registers . . . . . 564

20.4.1 TIM1 control register 1 (TIM1_CR1) . . . . . 564

20.4.2TIM1 control register 2 (TIM1_CR2) . . . . .565
20.4.3TIM1 slave mode control register
(TIM1_SMCR) . . . . .		568
20.4.4TIM1 DMA/interrupt enable register
(TIM1_DIER) . . . . .		570
20.4.5TIM1 status register (TIM1_SR) . . . . .572
20.4.6TIM1 event generation register (TIM1_EGR) . . . . .574
20.4.7TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . .575
20.4.8TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . .		576
20.4.9TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . .579
20.4.10TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . .		580
20.4.11TIM1 capture/compare enable register
(TIM1_CCER) . . . . .		581
20.4.12TIM1 counter (TIM1_CNT) . . . . .585
20.4.13TIM1 prescaler (TIM1_PSC) . . . . .585
20.4.14TIM1 auto-reload register (TIM1_ARR) . . . . .585
20.4.15TIM1 repetition counter register (TIM1_RCR) . . . . .586
20.4.16TIM1 capture/compare register 1
(TIM1_CCR1) . . . . .		586
20.4.17TIM1 capture/compare register 2
(TIM1_CCR2) . . . . .		587
20.4.18TIM1 capture/compare register 3
(TIM1_CCR3) . . . . .		587
20.4.19TIM1 capture/compare register 4
(TIM1_CCR4) . . . . .		588
20.4.20TIM1 break and dead-time register
(TIM1_BDTR) . . . . .		588
20.4.21TIM1 DMA control register
(TIM1_DCR) . . . . .		592
20.4.22TIM1 DMA address for full transfer
(TIM1_DMAR) . . . . .		593
20.4.23TIM1 option register 1 (TIM1_OR1) . . . . .594
20.4.24TIM1 capture/compare mode register 3
(TIM1_CCMR3) . . . . .		594
20.4.25TIM1 capture/compare register 5
(TIM1_CCR5) . . . . .		595
20.4.26TIM1 capture/compare register 6
(TIM1_CCR6) . . . . .		596
20.4.27TIM1 alternate function option register 1 (TIM1_AF1) . . . . .597

20.4.28 TIM1 Alternate function register 2 (TIM1_AF2) . . . . . 597

20.4.29 TIM1 timer input selection register (TIM1_TISEL) . . . . . 598

20.4.30 TIM1 register map . . . . . 599

21 General-purpose timer (TIM2) . . . . . 602

21.1 TIM2 introduction . . . . . 602

21.2 TIM2 main features . . . . . 602

21.3 TIM2 functional description . . . . . 604

21.3.1 Time-base unit . . . . . 604

21.3.2 Counter modes . . . . . 606

21.3.3 Clock selection . . . . . 616

21.3.4 Capture/Compare channels . . . . . 620

21.3.5 Input capture mode . . . . . 622

21.3.6 PWM input mode . . . . . 623

21.3.7 Forced output mode . . . . . 624

21.3.8 Output compare mode . . . . . 624

21.3.9 PWM mode . . . . . 625

21.3.10 Asymmetric PWM mode . . . . . 629

21.3.11 Combined PWM mode . . . . . 629

21.3.12 Clearing the OCxREF signal on an external event . . . . . 630

21.3.13 One-pulse mode . . . . . 632

21.3.14 Retriggerable one pulse mode . . . . . 633

21.3.15 Encoder interface mode . . . . . 634

21.3.16 UIF bit remapping . . . . . 636

21.3.17 Timer input XOR function . . . . . 636

21.3.18 Timers and external trigger synchronization . . . . . 637

21.3.19 Timer synchronization . . . . . 640

21.3.20 DMA burst mode . . . . . 645

21.3.21 Debug mode . . . . . 646

21.4 TIM2 registers . . . . . 647

21.4.1 TIM2 control register 1 (TIM2_CR1) . . . . . 647

21.4.2 TIM2 control register 2 (TIM2_CR2) . . . . . 648

21.4.3 TIM2 slave mode control register (TIM2_SMCR) . . . . . 650

21.4.4 TIM2 DMA/Interrupt enable register (TIM2_DIER) . . . . . 653

21.4.5 TIM2 status register (TIM2_SR) . . . . . 654

21.4.6 TIM2 event generation register (TIM2_EGR) . . . . . 656

21.4.7 TIM2 capture/compare mode register 1 (TIM2_CCMR1) . . . . . 657

21.4.8TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) . . .658
21.4.9TIM2 capture/compare mode register 2 (TIM2_CCMR2) . . . . .661
21.4.10TIM2 capture/compare mode register 2 [alternate] (TIM2_CCMR2) . . .662
21.4.11TIM2 capture/compare enable register
(TIM2_CCER) . . . . .		663
21.4.12TIM2 counter (TIM2_CNT) . . . . .664
21.4.13TIM2 counter [alternate] (TIM2_CNT) . . . . .665
21.4.14TIM2 prescaler (TIM2_PSC) . . . . .665
21.4.15TIM2 auto-reload register (TIM2_ARR) . . . . .665
21.4.16TIM2 capture/compare register 1 (TIM2_CCR1) . . . . .666
21.4.17TIM2 capture/compare register 2 (TIM2_CCR2) . . . . .666
21.4.18TIM2 capture/compare register 3 (TIM2_CCR3) . . . . .667
21.4.19TIM2 capture/compare register 4 (TIM2_CCR4) . . . . .667
21.4.20TIM2 DMA control register (TIM2_DCR) . . . . .668
21.4.21TIM2 DMA address for full transfer (TIM2_DMAR) . . . . .668
21.4.22TIM2 option register 1 (TIM2_OR1) . . . . .669
21.4.23TIM2 alternate function option register 1 (TIM2_AF1) . . . . .669
21.4.24TIM2 timer input selection register (TIM2_TISEL) . . . . .670
21.4.25TIMx register map . . . . .671
22Low-power timer (LPTIM) . . . . .674
22.1Introduction . . . . .674
22.2LPTIM main features . . . . .674
22.3LPTIM implementation . . . . .675
22.4LPTIM functional description . . . . .675
22.4.1LPTIM block diagram . . . . .675
22.4.2LPTIM trigger mapping . . . . .676
22.4.3LPTIM reset and clocks . . . . .676
22.4.4Glitch filter . . . . .677
22.4.5Prescaler . . . . .678
22.4.6Trigger multiplexer . . . . .678
22.4.7Operating mode . . . . .679
22.4.8Timeout function . . . . .680
22.4.9Waveform generation . . . . .680
22.4.10Register update . . . . .682
22.4.11Counter mode . . . . .682
22.4.12Timer enable . . . . .683
22.4.13Timer counter reset . . . . .683
22.4.14Encoder mode . . . . .684
22.4.15Debug mode . . . . .685
22.5LPTIM low-power modes . . . . .685
22.6LPTIM interrupts . . . . .686
22.7LPTIM registers . . . . .686
22.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .687
22.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .688
22.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .688
22.7.4LPTIM configuration register (LPTIM_CFGR) . . . . .689
22.7.5LPTIM control register (LPTIM_CR) . . . . .692
22.7.6LPTIM compare register (LPTIM_CMP) . . . . .694
22.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .694
22.7.8LPTIM counter register (LPTIM_CNT) . . . . .695
22.7.9LPTIM register map . . . . .696
23Real-time clock (RTC) . . . . .697
23.1Introduction . . . . .697
23.2RTC main features . . . . .698
23.3RTC functional description . . . . .699
23.3.1RTC block diagram . . . . .699
23.3.2Clock and prescalers . . . . .700
23.3.3Real-time clock and calendar . . . . .700
23.3.4Programmable alarms . . . . .701
23.3.5Periodic auto-wake-up . . . . .701
23.3.6RTC initialization and configuration . . . . .702
23.3.7Reading the calendar . . . . .703
23.3.8Resetting the RTC . . . . .704
23.3.9RTC synchronization . . . . .705
23.3.10RTC reference clock detection . . . . .705
23.3.11RTC smooth digital calibration . . . . .706
23.3.12Time-stamp function . . . . .708
23.3.13Tamper detection . . . . .709
23.3.14Calibration clock output . . . . .711
23.3.15Alarm output . . . . .711
23.4RTC low-power modes . . . . .712
23.5RTC interrupts .....712
23.6RTC registers .....713
23.6.1RTC time register (RTC_TR) .....713
23.6.2RTC date register (RTC_DR) .....714
23.6.3RTC control register (RTC_CR) .....715
23.6.4RTC initialization and status register (RTC_ISR) .....718
23.6.5RTC prescaler register (RTC_PRER) .....721
23.6.6RTC wake-up timer register (RTC_WUTR) .....722
23.6.7RTC alarm A register (RTC_ALRMAR) .....723
23.6.8RTC alarm B register (RTC_ALRMBR) .....724
23.6.9RTC write protection register (RTC_WPR) .....725
23.6.10RTC sub second register (RTC_SSR) .....725
23.6.11RTC shift control register (RTC_SHIFTR) .....726
23.6.12RTC timestamp time register (RTC_TSTR) .....727
23.6.13RTC timestamp date register (RTC_TSDR) .....728
23.6.14RTC time-stamp sub second register (RTC_TSSSR) .....729
23.6.15RTC calibration register (RTC_CALR) .....730
23.6.16RTC tamper configuration register (RTC_TAMPCR) .....731
23.6.17RTC alarm A sub second register (RTC_ALRMASSR) .....733
23.6.18RTC alarm B sub second register (RTC_ALRMBSSR) .....734
23.6.19RTC option register (RTC_OR) .....735
23.6.20RTC backup registers (RTC_BKPxR) .....735
23.6.21RTC register map .....736
24Independent watchdog (IWDG) .....738
24.1Introduction .....738
24.2IWDG main features .....738
24.3IWDG functional description .....738
24.3.1IWDG block diagram .....738
24.3.2Window option .....739
24.3.3Hardware watchdog .....740
24.3.4Low-power freeze .....740
24.3.5Register access protection .....740
24.3.6Debug mode .....740
24.4IWDG registers .....741
24.4.1IWDG key register (IWDG_KR) .....741
26.4.9I2C controller mode .....773
26.4.10I2C_TIMINGR register configuration examples .....784
26.4.11SMBus specific features .....786
26.4.12SMBus initialization .....788
26.4.13SMBus I2C_TIMEOUTR register configuration examples .....790
26.4.14SMBus target mode .....791
26.4.15SMBus controller mode .....794
26.4.16Wake-up from Stop mode on address match .....797
26.4.17Error conditions .....798
26.5I2C in low-power modes .....800
26.6I2C interrupts .....800
26.7I2C DMA requests .....801
26.7.1Transmission using DMA .....801
26.7.2Reception using DMA .....801
26.8I2C debug modes .....801
26.9I2C registers .....802
26.9.1I2C control register 1 (I2C_CR1) .....802
26.9.2I2C control register 2 (I2C_CR2) .....804
26.9.3I2C own address 1 register (I2C_OAR1) .....806
26.9.4I2C own address 2 register (I2C_OAR2) .....807
26.9.5I2C timing register (I2C_TIMINGR) .....808
26.9.6I2C timeout register (I2C_TIMEOUTR) .....809
26.9.7I2C interrupt and status register (I2C_ISR) .....810
26.9.8I2C interrupt clear register (I2C_ICR) .....812
26.9.9I2C PEC register (I2C_PECR) .....813
26.9.10I2C receive data register (I2C_RXDR) .....813
26.9.11I2C transmit data register (I2C_TXDR) .....814
26.9.12I2C register map .....815
27Universal synchronous/asynchronous receiver transmitter (USART/UART) .....816
27.1USART introduction .....816
27.2USART main features .....817
27.3USART extended features .....818
27.4USART implementation .....818
27.5USART functional description .....819
27.5.1USART block diagram . . . . .819
27.5.2USART signals . . . . .820
27.5.3USART character description . . . . .821
27.5.4USART FIFOs and thresholds . . . . .823
27.5.5USART transmitter . . . . .823
27.5.6USART receiver . . . . .827
27.5.7USART baud rate generation . . . . .834
27.5.8Tolerance of the USART receiver to clock deviation . . . . .835
27.5.9USART auto baud rate detection . . . . .837
27.5.10USART multiprocessor communication . . . . .839
27.5.11USART Modbus communication . . . . .841
27.5.12USART parity control . . . . .842
27.5.13USART LIN (local interconnection network) mode . . . . .843
27.5.14USART synchronous mode . . . . .845
27.5.15USART single-wire half-duplex communication . . . . .849
27.5.16USART receiver timeout . . . . .849
27.5.17USART smartcard mode . . . . .850
27.5.18USART IrDA SIR ENDEC block . . . . .854
27.5.19Continuous communication using USART and DMA . . . . .857
27.5.20RS232 hardware flow control and RS485 Driver Enable . . . . .859
27.5.21USART low-power management . . . . .862
27.6USART in low-power modes . . . . .865
27.7USART interrupts . . . . .866
27.8USART registers . . . . .867
27.8.1USART control register 1 (USART_CR1) . . . . .867
27.8.2USART control register 1 [alternate] (USART_CR1) . . . . .870
27.8.3USART control register 2 (USART_CR2) . . . . .874
27.8.4USART control register 3 (USART_CR3) . . . . .878
27.8.5USART baud rate register (USART_BRR) . . . . .882
27.8.6USART guard time and prescaler register (USART_GTPR) . . . . .882
27.8.7USART receiver timeout register (USART_RTOR) . . . . .883
27.8.8USART request register (USART_RQR) . . . . .884
27.8.9USART interrupt and status register (USART_ISR) . . . . .885
27.8.10USART interrupt and status register [alternate] (USART_ISR) . . . . .891
27.8.11USART interrupt flag clear register (USART_ICR) . . . . .896
27.8.12USART receive data register (USART_RDR) . . . . .898
27.8.13USART transmit data register (USART_TDR) . . . . .898
27.8.14USART prescaler register (USART_PRESC) .....899
27.8.15USART register map .....900
28Serial peripheral interface (SPI) .....902
28.1Introduction .....902
28.2SPI main features .....902
28.3SPI implementation .....903
28.4SPI functional description .....903
28.4.1General description .....903
28.4.2Communications between one master and one slave .....904
28.4.3Standard multislave communication .....906
28.4.4Multimaster communication .....907
28.4.5Slave select (NSS) pin management .....908
28.4.6Communication formats .....909
28.4.7Configuration of SPI .....911
28.4.8Procedure for enabling SPI .....912
28.4.9Data transmission and reception procedures .....912
28.4.10SPI status flags .....922
28.4.11SPI error flags .....923
28.4.12NSS pulse mode .....924
28.4.13TI mode .....924
28.4.14CRC calculation .....925
28.5SPI interrupts .....927
28.6SPI registers .....928
28.6.1SPI control register 1 (SPIx_CR1) .....928
28.6.2SPI control register 2 (SPIx_CR2) .....930
28.6.3SPI status register (SPIx_SR) .....932
28.6.4SPI data register (SPIx_DR) .....933
28.6.5SPI CRC polynomial register (SPIx_CRCPR) .....934
28.6.6SPI Rx CRC register (SPIx_RXCRCR) .....934
28.6.7SPI Tx CRC register (SPIx_TXCRCR) .....934
28.6.8SPI register map .....936
29Inter-processor communication controller (IPCC) .....937
29.1Introduction .....937
29.2IPCC main features .....937
29.3IPCC functional description . . . . .937
29.3.1IPCC block diagram . . . . .938
29.3.2IPCC Simplex channel mode . . . . .938
29.3.3IPCC Half-duplex channel mode . . . . .941
29.3.4IPCC interrupts . . . . .944
29.4IPCC registers . . . . .945
29.4.1IPCC processor 1 control register (IPCC_C1CR) . . . . .945
29.4.2IPCC processor 1 mask register (IPCC_C1MR) . . . . .945
29.4.3IPCC processor 1 status set clear register (IPCC_C1SCR) . . . . .946
29.4.4IPCC processor 1 to processor 2 status register
(IPCC_C1TOC2SR) . . . . .		946
29.4.5IPCC processor 2 control register (IPCC_C2CR) . . . . .947
29.4.6IPCC processor 2 mask register (IPCC_C2MR) . . . . .947
29.4.7IPCC processor 2 status set clear register (IPCC_C2SCR) . . . . .948
29.4.8IPCC processor 2 to processor 1 status register
(IPCC_C2TOC1SR) . . . . .		949
29.4.9IPCC register map . . . . .950
30Hardware semaphore (HSEM) . . . . .951
30.1Introduction . . . . .951
30.2Main features . . . . .951
30.3Functional description . . . . .952
30.3.1HSEM block diagram . . . . .952
30.3.2HSEM internal signals . . . . .952
30.3.3HSEM lock procedures . . . . .952
30.3.4HSEM write/read/read lock register address . . . . .954
30.3.5HSEM unlock procedures . . . . .954
30.3.6HSEM COREID semaphore clear . . . . .955
30.3.7HSEM interrupts . . . . .955
30.3.8AHB bus master ID verification . . . . .957
30.4HSEM registers . . . . .958
30.4.1HSEM register semaphore x (HSEM_Rx) . . . . .958
30.4.2HSEM read lock register semaphore x (HSEM_RLRx) . . . . .959
30.4.3HSEM interrupt enable register (HSEM_CnIER) . . . . .960
30.4.4HSEM interrupt clear register (HSEM_CnICR) . . . . .960
30.4.5HSEM interrupt status register (HSEM_CnISR) . . . . .960
30.4.6HSEM interrupt status register (HSEM_CnMISR) . . . . .961
30.4.7HSEM clear register (HSEM_CR) .....961
30.4.8HSEM clear semaphore key register (HSEM_KEYR) .....962
30.4.9HSEM register map .....963
31Debug support (DBG) .....965
31.1Introduction .....965
31.2Debug use cases .....965
31.3DBG functional description .....967
31.3.1DBG block diagram .....967
31.3.2DBG pins and internal signals .....967
31.3.3DBG power domains .....968
31.3.4DBG clocks .....968
31.3.5Debug and low power modes .....969
31.3.6DBG reset .....969
31.4Serial wire and JTAG debug port (SWJ-DP) .....969
31.4.1JTAG debug port .....969
31.4.2SW debug port .....972
31.4.3Debug port registers .....973
31.4.4DP debug port identification register (DP_PIDR) .....974
31.4.5DP abort register (DP_ABORTR) .....974
31.4.6DP control and status register (DP_CTRL/STATR) .....975
31.4.7DP data link control register (DP_DLCR) .....977
31.4.8DP target identification register (DP_TARGETIDR) .....977
31.4.9DP data link protocol identification register (DP_DLPIDR) .....978
31.4.10DP resend register (DP_RESENR) .....978
31.4.11DP access port select register (DP_SELECTR) .....979
31.4.12DP read buffer register (DP_BUFFR) .....979
31.4.13DP target selection register (DP_TARGETSEL) .....980
31.4.14Debug port register map and reset values .....981
31.5Access ports .....982
31.5.1AP control/status word register (AP_CSWR) .....984
31.5.2AP transfer address register (AP_TAR) .....985
31.5.3AP data read/write register (AP_DRWR) .....985
31.5.4AP banked data registers (AP_BD0-3R) .....985
31.5.5AP base address register (AP_BASER) .....986
31.5.6AP identification register (AP_IDR) .....986
31.5.7Access port register map and reset values .....988
31.6Cross trigger interface (CTI) and matrix (CTM) . . . . .989
31.7Cross trigger interface registers . . . . .993
31.7.1CTI control register (CTI_CONTROLR) . . . . .993
31.7.2CTI trigger acknowledge register (CTI_INTACKR) . . . . .993
31.7.3CTI application trigger set register (CTI_APPSETR) . . . . .993
31.7.4CTI application trigger clear register (CTI_APPCLEAR) . . . . .994
31.7.5CTI application pulse register (CTI_APPPULSER) . . . . .995
31.7.6CTI trigger In x enable register (CTI_INENRx) . . . . .995
31.7.7CTI trigger out x enable register (CTI_OUTENRx) . . . . .996
31.7.8CTI trigger in status register (CTI_TRGISTSR) . . . . .996
31.7.9CTI trigger out status register (CTI_TRGOSTSR) . . . . .997
31.7.10CTI channel in status register (CTI_CHINSTSR) . . . . .997
31.7.11CTI channel out status register (CTI_CHOUTSTSR) . . . . .997
31.7.12CTI channel gate register (CTI_GATER) . . . . .998
31.7.13CTI claim tag set register (CTI_CLAIMSETR) . . . . .998
31.7.14CTI claim tag clear register (CTI_CLAIMCLR) . . . . .999
31.7.15CTI lock access register (CTI_LAR) . . . . .999
31.7.16CTI lock status register (CTI_LSR) . . . . .1000
31.7.17CTI authentication status register (CTI_AUTHSTATR) . . . . .1000
31.7.18CTI device configuration register (CTI_DEVIDR) . . . . .1001
31.7.19CTI device type identifier register (CTI_DEVTYPE) . . . . .1001
31.7.20CTI CoreSight peripheral identity register 4 (CTI_PIDR4) . . . . .1002
31.7.21CTI CoreSight peripheral identity register 0 (CTI_PIDR0) . . . . .1002
31.7.22CTI CoreSight peripheral identity register 1 (CTI_PIDR1) . . . . .1002
31.7.23CTI CoreSight peripheral identity register 2 (CTI_PIDR2) . . . . .1003
31.7.24CTI CoreSight peripheral identity register 3 (CTI_PIDR3) . . . . .1003
31.7.25CTI CoreSight component identity register 0 (CTI_CIDR0) . . . . .1004
31.7.26CTI CoreSight peripheral identity register 1 (CTI_CIDR1) . . . . .1004
31.7.27CTI CoreSight component identity register 2 (CTI_CIDR2) . . . . .1005
31.7.28CTI CoreSight component identity register 3 (CTI_CIDR3) . . . . .1005
31.7.29CTI register map and reset values . . . . .1006
31.8Microcontroller debug unit (DBGMCU) . . . . .1009
31.8.1DBGMCU identity code register (DBGMCU_IDCODE) . . . . .1009
31.8.2DBGMCU configuration register (DBGMCU_CR) . . . . .1009
31.8.3DBGMCU CPU1 APB1 peripheral freeze register 1
(DBGMCU_APB1FZR1) . . . . .		1010
31.8.4DBGMCU CPU2 APB1 peripheral freeze register 1 (DBGMCU_C2APB1FZR1) .....1011
31.8.5DBGMCU CPU1 APB1 peripheral freeze register 2 (DBGMCU_APB1FZR2) .....1012
31.8.6DBGMCU CPU2 APB1 peripheral freeze register 2 (DBGMCU_C2APB1FZR2) .....1013
31.8.7DBGMCU CPU1 APB2 peripheral freeze register (DBGMCU_APB2FZR) .....1013
31.8.8DBGMCU CPU2 APB2 peripheral freeze register (DBGMCU_C2APB2FZR) .....1014
31.8.9DBGMCU register map and reset values .....1015
31.9CPU2 ROM tables .....1017
31.9.1CPU2 ROM1 memory type register (C2ROM1_MEMTYPER) .....1019
31.9.2CPU2 ROM1 CoreSight peripheral identity register 4 (C2ROM1_PIDR4) .....1019
31.9.3CPU2 ROM1 CoreSight peripheral identity register 0 (C2ROM1_PIDR0) .....1019
31.9.4CPU2 ROM1 CoreSight peripheral identity register 1 (C2ROM1_PIDR1) .....1020
31.9.5CPU2 ROM1 CoreSight peripheral identity register 2 (C2ROM1_PIDR2) .....1020
31.9.6CPU2 ROM1 CoreSight peripheral identity register 3 (C2ROM1_PIDR3) .....1021
31.9.7CPU2 ROM1 CoreSight component identity register 0 (C2ROM1_CIDR0) .....1021
31.9.8CPU2 ROM1 CoreSight peripheral identity register 1 (C2ROM1_CIDR1) .....1022
31.9.9CPU2 ROM1 CoreSight component identity register 2 (C2ROM1_CIDR2) .....1022
31.9.10CPU2 ROM1 CoreSight component identity register 3 (C2ROM1_CIDR3) .....1022
31.9.11CPU2 processor ROM table registers and reset values .....1024
31.9.12CPU2 ROM2 memory type register (C2ROM2_MEMTYPER) .....1025
31.9.13CPU2 ROM2 CoreSight peripheral identity register 4 (C2ROM2_PIDR4) .....1025
31.9.14CPU2 ROM2 CoreSight peripheral identity register 0 (C2ROM2_PIDR0) .....1025
31.9.15CPU2 ROM2 CoreSight peripheral identity register 1 (C2ROM2_PIDR1) .....1026
31.9.16CPU2 ROM2 CoreSight peripheral identity register 2 (C2ROM2_PIDR2) .....1026
31.9.17CPU2 ROM2 CoreSight peripheral identity register 3 (C2ROM2_PIDR3) .....1027
31.9.18CPU2 ROM2 CoreSight component identity register 0 (C2ROM2_CIDR0) .....1027
31.9.19CPU2 ROM2 CoreSight peripheral identity register 1 (C2ROM2_CIDR1) .....1028
31.9.20CPU2 ROM2 CoreSight component identity register 2 (C2ROM2_CIDR2) .....1028
31.9.21CPU2 ROM2 CoreSight component identity register 3 (C2ROM2_CIDR3) .....1028
31.9.22CPU2 ROM table register map and reset values .....1030
31.10CPU2 data watchpoint and trace unit (DWT) .....1031
31.10.1DWT control register (DWT_CTRLR) .....1031
31.10.2DWT cycle count register (DWT_CYCCNTR) .....1033
31.10.3DWT CPI count register (DWT_CPICNTR) .....1033
31.10.4DWT exception count register (DWT_EXCCNTR) .....1034
31.10.5DWT sleep count register (DWT_SLP CNTR) .....1034
31.10.6DWT LSU count register (DWT_LSUCNTR) .....1035
31.10.7DWT fold count register (DWT_FOLDCNTR) .....1035
31.10.8DWT program counter sample register (DWT_PCSR) .....1035
31.10.9DWT comparator register x (DWT_COMPxR) .....1036
31.10.10DWT mask register x (DWT_MASKxR) .....1036
31.10.11DWT function register x (DWT_FUNCTxR) .....1036
31.10.12DWT CoreSight peripheral identity register 4 (DWT_PIDR4) .....1037
31.10.13DWT CoreSight peripheral identity register 0 (DWT_PIDR0) .....1038
31.10.14DWT CoreSight peripheral identity register 1 (DWT_PIDR1) .....1038
31.10.15DWT CoreSight peripheral identity register 2 (DWT_PIDR2) .....1039
31.10.16DWT CoreSight peripheral identity register 3 (DWT_PIDR3) .....1039
31.10.17DWT CoreSight component identity register 0 (DWT_CIDR0) .....1040
31.10.18DWT CoreSight peripheral identity register 1 (DWT_CIDR1) .....1040
31.10.19DWT CoreSight component identity register 2 (DWT_CIDR2) .....1040
31.10.20DWT CoreSight component identity register 3 (DWT_CIDR3) .....1041
31.10.21CPU2 DWT registers .....1042
31.11CPU2 breakpoint unit (PBU) .....1045
31.11.1BPU control register (BPU_CTRLR) .....1045
31.11.2BPU remap register (BPU_REMAPR) .....1045
31.11.3BPU comparator registers (BPU_COMPxR) .....1046
31.11.4BPU CoreSight peripheral identity register 4 (BPU_PIDR4) .....1046
31.11.5BPU CoreSight peripheral identity register 0 (BPU_PIDR0) . . . . .1047
31.11.6BPU CoreSight peripheral identity register 1 (BPU_PIDR1) . . . . .1047
31.11.7BPU CoreSight peripheral identity register 2 (BPU_PIDR2) . . . . .1047
31.11.8BPU CoreSight peripheral identity register 3 (BPU_PIDR3) . . . . .1048
31.11.9BPU CoreSight component identity register 0 (BPU_CIDR0) . . . . .1048
31.11.10BPU CoreSight peripheral identity register 1 (BPU_CIDR1) . . . . .1049
31.11.11BPU CoreSight component identity register 2 (BPU_CIDR2) . . . . .1049
31.11.12BPU CoreSight component identity register 3 (BPU_CIDR3) . . . . .1050
31.11.13CPU2 BPU register map and reset values . . . . .1051
31.12CPU2 cross trigger interface (CTI) . . . . .1052
31.13CPU1 ROM table . . . . .1052
31.13.1CPU1 ROM memory type register (C1ROM_MEMTYPER) . . . . .1053
31.13.2CPU1 ROM CoreSight peripheral identity register 4
(C1ROM_PIDR4) . . . . .		1054
31.13.3CPU1 ROM CoreSight peripheral identity register 0
(C1ROM_PIDR0) . . . . .		1054
31.13.4CPU1 ROM CoreSight peripheral identity register 1
(C1ROM_PIDR1) . . . . .		1055
31.13.5CPU1 ROM CoreSight peripheral identity register 2
(C1ROM_PIDR2) . . . . .		1055
31.13.6CPU1 ROM CoreSight peripheral identity register 3
(C1ROM_PIDR3) . . . . .		1056
31.13.7CPU1 ROM CoreSight component identity register 0
(C1ROM_CIDR0) . . . . .		1056
31.13.8CPU1 ROM CoreSight peripheral identity register 1
(C1ROM_CIDR1) . . . . .		1056
31.13.9CPU1 ROM CoreSight component identity register 2
(C1ROM_CIDR2) . . . . .		1057
31.13.10CPU1 ROM CoreSight component identity register 3
(C1ROM_CIDR3) . . . . .		1057
31.13.11CPU1 ROM table register map and reset values . . . . .1059
31.14CPU1 data watchpoint and trace unit (DWT) . . . . .1060
31.14.1DWT control register (DWT_CTRLR) . . . . .1060
31.14.2DWT cycle count register (DWT_CYCCNTR) . . . . .1062
31.14.3DWT CPI count register (DWT_CPICNTR) . . . . .1062
31.14.4DWT exception count register (DWT_EXCCNTR) . . . . .1063
31.14.5DWT sleep count register (DWT_SLPNCNTR) . . . . .1063
31.14.6DWT LSU count register (DWT_LSUCNTR) . . . . .1064
31.14.7DWT fold count register (DWT_FOLDCNTR) . . . . .1064
31.14.8DWT program counter sample register (DWT_PCSR) . . . . .1064
31.14.9DWT comparator register x (DWT_COMPxR) . . . . .1065
31.14.10DWT mask register x (DWT_MASKxR) . . . . .1065
31.14.11DWT function register x (DWT_FUNCTxR) . . . . .1065
31.14.12DWT CoreSight peripheral identity register 4 (DWT_PIDR4) . . . . .1066
31.14.13DWT CoreSight peripheral identity register 0 (DWT_PIDR0) . . . . .1067
31.14.14DWT CoreSight peripheral identity register 1 (DWT_PIDR1) . . . . .1067
31.14.15DWT CoreSight peripheral identity register 2 (DWT_PIDR2) . . . . .1068
31.14.16DWT CoreSight peripheral identity register 3 (DWT_PIDR3) . . . . .1068
31.14.17DWT CoreSight component identity register 0 (DWT_CIDR0) . . . . .1069
31.14.18DWT CoreSight peripheral identity register 1 (DWT_CIDR1) . . . . .1069
31.14.19DWT CoreSight component identity register 2 (DWT_CIDR2) . . . . .1069
31.14.20DWT CoreSight component identity register 3 (DWT_CIDR3) . . . . .1070
31.14.21CPU1 DWT register map and reset values . . . . .1071
31.15CPU1 instrumentation trace macrocell (ITM) . . . . .1073
31.15.1ITM stimulus register x (ITM_STIMRx) . . . . .1073
31.15.2ITM trace enable register (ITM_TER) . . . . .1073
31.15.3ITM trace privilege register (ITM_TPR) . . . . .1074
31.15.4ITM trace control register (ITM_TCR) . . . . .1074
31.15.5ITM CoreSight peripheral identity register 4 (ITM_PIDR4) . . . . .1075
31.15.6ITM CoreSight peripheral identity register 0 (ITM_PIDR0) . . . . .1076
31.15.7ITM CoreSight peripheral identity register 1 (ITM_PIDR1) . . . . .1076
31.15.8ITM CoreSight peripheral identity register 2 (ITM_PIDR2) . . . . .1077
31.15.9ITM CoreSight peripheral identity register 3 (ITM_PIDR3) . . . . .1077
31.15.10ITM CoreSight component identity register 0 (ITM_CIDR0) . . . . .1078
31.15.11ITM CoreSight peripheral identity register 1 (ITM_CIDR1) . . . . .1078
31.15.12ITM CoreSight component identity register 2 (ITM_CIDR2) . . . . .1078
31.15.13ITM CoreSight component identity register 3 (ITM_CIDR3) . . . . .1079
31.15.14ITM register map and reset values . . . . .1080
31.16CPU1 breakpoint unit (FPB) . . . . .1081
31.16.1FPB control register (FPB_CTRLR) . . . . .1081
31.16.2FPB remap register (FPB_REMAPR) . . . . .1081
31.16.3FPB comparator registers (FPB_COMPxR) . . . . .1082
31.16.4FPB CoreSight peripheral identity register 4 (FPB_PIDR4) . . . . .1082
31.16.5FPB CoreSight peripheral identity register 0 (FPB_PIDR0) . . . . .1083
31.16.6FPB CoreSight peripheral identity register 1 (FPB_PIDR1) . . . . .1083
31.16.7FPB CoreSight peripheral identity register 2 (FPB_PIDR2) . . . . .1084
31.16.8FPB CoreSight peripheral identity register 3 (FPB_PIDR3) . . . . .1084
31.16.9FPB CoreSight component identity register 0 (FPB_CIDR0) . . . . .1085
31.16.10FPB CoreSight peripheral identity register 1 (FPB_CIDR1) . . . . .1085
31.16.11FPB CoreSight component identity register 2 (FPB_CIDR2) . . . . .1085
31.16.12FPB CoreSight component identity register 3 (FPB_CIDR3) . . . . .1086
31.16.13FPB register map and reset values . . . . .1087
31.17CPU1 trace port interface unit (TPIU) . . . . .1088
31.17.1TPIU supported port size register (TPIU_SSPSR) . . . . .1088
31.17.2TPIU current port size register (TPIU_CSPSR) . . . . .1088
31.17.3TPIU asynchronous clock presecaler register (TPIU_ACPR) . . . . .1089
31.17.4TPIU selected pin protocol register (TPIU_SPPR) . . . . .1089
31.17.5TPIU formatter and flush status register (TPIU_FFSR) . . . . .1090
31.17.6TPIU formatter and flush control register (TPIU_FFCR) . . . . .1090
31.17.7TPIU formatter synchronization counter register (TPIU_FSCR) . . . . .1091
31.17.8TPIU claim tag set register (TPIU_CLAIMSETR) . . . . .1091
31.17.9TPIU claim tag clear register (TPIU_CLAIMCLR) . . . . .1092
31.17.10TPIU device configuration register (TPIU_DEVIDR) . . . . .1092
31.17.11TPIU device type identifier register (TPIU_DEVTYPE) . . . . .1093
31.17.12TPIU CoreSight peripheral identity register 4 (TPIU_PIDR4) . . . . .1093
31.17.13TPIU CoreSight peripheral identity register 0 (TPIU_PIDR0) . . . . .1094
31.17.14TPIU CoreSight peripheral identity register 1 (TPIU_PIDR1) . . . . .1094
31.17.15TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) . . . . .1094
31.17.16TPIU CoreSight peripheral identity register 3 (TPIU_PIDR3) . . . . .1095
31.17.17TPIU CoreSight component identity register 0 (TPIU_CIDR0) . . . . .1095
31.17.18TPIU CoreSight peripheral identity register 1 (TPIU_CIDR1) . . . . .1096
31.17.19TPIU CoreSight component identity register 2 (TPIU_CIDR2) . . . . .1096
31.17.20TPIU CoreSight component identity register 3 (TPIU_CIDR3) . . . . .1097
31.17.21CPU1 TPIU register map and reset values . . . . .1098
31.18CPU1 cross trigger interface (CTI) . . . . .1100
31.19References . . . . .1100
32Device electronic signature . . . . .1101
32.1Unique device ID register (96 bits) . . . . .1101
32.2Memory size data register . . . . .1102
32.2.1Flash size data register . . . . .1102
32.3Package data register . . . . .1102
32.4Part number codification register . . . . .1103
33Important security notice . . . . .1104
34Revision history . . . . .1105

List of tables

Table 1.Memory map and peripheral register boundary addresses . . . . .56
Table 2.Boot modes. . . . .59
Table 3.Flash memory - Single bank organization . . . . .63
Table 4.Number of wait states vs, flash memory clock (HCLK4) frequency . . . . .65
Table 5.Page erase overview . . . . .70
Table 6.Mass erase overview . . . . .71
Table 7.Errors in page-based row programming . . . . .76
Table 8.Option bytes format . . . . .77
Table 9.Option bytes organization . . . . .77
Table 10.Option loading control. . . . .86
Table 11.UID64 organization . . . . .87
Table 12.Flash memory read protection status . . . . .88
Table 13.RDP regression from Level 1 to Level 0 and memory erase . . . . .90
Table 14.Access status vs. protection level and execution modes . . . . .91
Table 17.Flash memory interrupt requests . . . . .96
Table 18.Flash interface register map and reset values . . . . .116
Table 19.CRC internal input/output signals . . . . .121
Table 20.CRC register map and reset values . . . . .126
Table 21.Sub-system low power wake-up sources . . . . .135
Table 22.Low-power mode summary . . . . .137
Table 23.Functionalities depending on system operating mode . . . . .138
Table 24.Low-power run . . . . .141
Table 25.CPU CSTOP wake-up vs. system operating mode . . . . .142
Table 26.Sleep mode. . . . .143
Table 27.Low-power sleep. . . . .144
Table 28.Stop0 mode . . . . .146
Table 29.Stop1 mode . . . . .147
Table 30.Standby mode. . . . .149
Table 31.Shutdown mode . . . . .150
Table 32.PWR register map and reset values . . . . .167
Table 33.STM32WB10CC peripherals interconnect matrix . . . . .169
Table 34.Maximum clock source frequency . . . . .185
Table 35.Peripheral clock enable . . . . .188
Table 36.Single core Low power debug configurations . . . . .189
Table 37.RCC register map and reset values . . . . .240
Table 38.Port bit configuration table . . . . .248
Table 39.GPIO register map and reset values . . . . .263
Table 40.SYSCFG register map and reset values. . . . .282
Table 41.DMA implementation . . . . .285
Table 42.DMA internal input/output signals . . . . .286
Table 43.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .291
Table 44.DMA interrupt requests. . . . .293
Table 45.DMA register map and reset values . . . . .301
Table 46.DMAMUX instantiation . . . . .305
Table 47.DMAMUX: assignment of multiplexer inputs to resources . . . . .306
Table 48.DMAMUX: assignment of trigger inputs to resources. . . . .306
Table 49.DMAMUX: assignment of synchronization inputs to resources . . . . .307
Table 50.DMAMUX signals . . . . .309
Table 51.DMAMUX interrupts . . . . .313
Table 52.DMAMUX register map and reset values . . . . .318
Table 53.CPU1 vector table. . . . .322
Table 54.CPU2 vector table. . . . .325
Table 55.Wakeup interrupt table . . . . .327
Table 56.EXTI pin overview. . . . .330
Table 57.EVG pin overview . . . . .330
Table 58.EXTI event input configurations and register control . . . . .332
Table 59.Masking functionality . . . . .335
Table 60.EXTI register map sections. . . . .336
Table 61.EXTI register map and reset values . . . . .345
Table 62.ADC input/output pins. . . . .349
Table 63.ADC internal input/output signals . . . . .350
Table 64.External triggers . . . . .350
Table 65.Latency between trigger and start of conversion . . . . .355
Table 66.Configuring the trigger polarity . . . . .362
Table 67.tSAR timings depending on resolution . . . . .364
Table 68.Analog watchdog comparison. . . . .373
Table 69.Analog watchdog channel selection . . . . .374
Table 70.ADC interrupts . . . . .380
Table 71.ADC register map and reset values . . . . .396
Table 72.Acquisition sequence summary . . . . .401
Table 73.Spread spectrum deviation versus AHB clock frequency. . . . .403
Table 74.I/O state depending on its mode and IODEF bit value . . . . .404
Table 75.Effect of low-power modes on TSC . . . . .406
Table 76.Interrupt control bits . . . . .406
Table 77.TSC register map and reset values . . . . .414
Table 78.RNG internal input/output signals . . . . .417
Table 79.RNG interrupt requests. . . . .423
Table 80.RNG configurations . . . . .424
Table 81.RNG register map and reset map. . . . .427
Table 82.AES internal input/output signals . . . . .429
Table 83.CTR mode initialization vector definition. . . . .446
Table 84.GCM last block definition . . . . .448
Table 85.Initialization of AES_IVRx registers in GCM mode. . . . .449
Table 86.Initialization of AES_IVRx registers in CCM mode . . . . .456
Table 87.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .461
Table 88.AES interrupt requests . . . . .464
Table 89.Processing latency for ECB, CBC and CTR. . . . .464
Table 90.Processing latency for GCM and CCM (in clock cycles). . . . .465
Table 91.AES register map and reset values . . . . .475
Table 92.Internal input/output signals . . . . .478
Table 93.PKA integer arithmetic functions list . . . . .479
Table 94.PKA prime field (Fp) elliptic curve functions list . . . . .479
Table 95.Montgomery parameter computation . . . . .484
Table 96.Modular addition . . . . .485
Table 97.Modular subtraction . . . . .485
Table 98.Montgomery multiplication . . . . .486
Table 99.Modular exponentiation (normal mode) . . . . .487
Table 100.Modular exponentiation (fast mode) . . . . .487
Table 101.Modular inversion . . . . .487
Table 102.Modular reduction . . . . .488
Table 103.Arithmetic addition . . . . .488
Table 104.Arithmetic subtraction . . . . .488
Table 105.Arithmetic multiplication . . . . .489
Table 106.Arithmetic comparison . . . . .489
Table 107.CRT exponentiation . . . . .490
Table 108.Point on elliptic curve Fp check . . . . .491
Table 109.ECC Fp scalar multiplication . . . . .491
Table 110.ECC Fp scalar multiplication (Fast Mode) . . . . .492
Table 111.ECDSA sign - Inputs . . . . .493
Table 112.ECDSA sign - Outputs . . . . .493
Table 113.Extended ECDSA sign (extra outputs) . . . . .494
Table 114.ECDSA verification (inputs) . . . . .494
Table 115.ECDSA verification (outputs) . . . . .494
Table 116.Family of supported curves for ECC operations . . . . .495
Table 117.Modular exponentiation computation times . . . . .497
Table 118.ECC scalar multiplication computation times . . . . .497
Table 119.ECDSA signature average computation times . . . . .497
Table 120.ECDSA verification average computation times . . . . .498
Table 121.Point on elliptic curve Fp check average computation times . . . . .498
Table 122.Montgomery parameters average computation times . . . . .498
Table 123.PKA interrupt requests . . . . .498
Table 124.PKA register map and reset values . . . . .502
Table 125.Behavior of timer outputs versus BRK/BRK2 inputs . . . . .545
Table 126.Break protection disarming conditions . . . . .547
Table 127.Counting direction versus encoder signals . . . . .553
Table 128.TIM1 internal trigger connection . . . . .570
Table 129.Output control bits for complementary OCx and OCxN channels with break feature . . . . .584
Table 130.TIM1 register map and reset values . . . . .599
Table 131.Counting direction versus encoder signals . . . . .635
Table 132.TIM2 internal trigger connection . . . . .653
Table 133.Output control bit for standard OCx channels . . . . .664
Table 134.TIM2 register map and reset values . . . . .671
Table 135.LPTIM features . . . . .675
Table 136.LPTIM1 external trigger connection . . . . .676
Table 137.LPTIM2 external trigger connection . . . . .676
Table 138.Prescaler division ratios . . . . .678
Table 139.Encoder counting scenarios . . . . .684
Table 140.Effect of low-power modes on the LPTIM . . . . .685
Table 141.Interrupt events . . . . .686
Table 142.LPTIM register map and reset values . . . . .696
Table 143.Effect of low-power modes on RTC . . . . .712
Table 144.Interrupt control bits . . . . .712
Table 145.RTC register map and reset values . . . . .736
Table 146.IWDG register map and reset values . . . . .746
Table 147.WWDG internal input/output signals . . . . .748
Table 148.WWDG register map and reset values . . . . .752
Table 149.I2C implementation . . . . .754
Table 150.I2C input/output pins . . . . .755
Table 151.I2C internal input/output signals . . . . .756
Table 152.Comparison of analog and digital filters . . . . .758
Table 153.I 2 C-bus and SMBus specification data setup and hold times . . . . .760
Table 154.I2C configuration . . . . .764
Table 155.I 2 C-bus and SMBus specification clock timings . . . . .775
Table 156.Timing settings for f I2CCLK of 8 MHz. . . . .785
Table 157.Timing settings for f I2CCLK of 16 MHz. . . . .785
Table 158.SMBus timeout specifications . . . . .787
Table 159.SMBus with PEC configuration . . . . .789
Table 160.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms. . . . .790
Table 161.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .790
Table 162.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .790
Table 163.Effect of low-power modes to I2C. . . . .800
Table 164.I2C interrupt requests . . . . .800
Table 165.I2C register map and reset values . . . . .815
Table 166.USART features . . . . .818
Table 167.USART/UART input/output pins . . . . .821
Table 168.USART internal input/output signals. . . . .821
Table 169.Noise detection from sampled data . . . . .833
Table 170.Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .836
Table 171.Tolerance of the USART receiver when BRR[3:0] is different from 0000. . . . .837
Table 172.USART frame formats . . . . .842
Table 173.Effect of low-power modes on the USART . . . . .865
Table 174.USART interrupt requests. . . . .866
Table 175.USART register map and reset values . . . . .900
Table 176.STM32WB10CC SPI implementation . . . . .903
Table 177.SPI interrupt requests . . . . .927
Table 178.SPI register map and reset values . . . . .936
Table 179.IPCC interface signals . . . . .938
Table 180.Bits used for the communication. . . . .939
Table 181.IPCC register map and reset values. . . . .950
Table 182.HSEM internal input/output signals. . . . .952
Table 183.Authorized AHB bus master IDs . . . . .957
Table 184.HSEM register map and reset values . . . . .963
Table 185.JTAG/Serial-wire debug port pins. . . . .967
Table 186.Trace port pins . . . . .968
Table 187.Single Wire Trace port pins . . . . .968
Table 188.Trigger pins . . . . .968
Table 189.JTAG-DP data registers . . . . .971
Table 190.Packet request . . . . .972
Table 191.ACK response. . . . .973
Table 192.Data transfer. . . . .973
Table 193.Debug port register map and reset values . . . . .981
Table 194.Access port register map and reset values. . . . .988
Table 195.CPU2 CTI inputs. . . . .989
Table 196.CPU2 CTI outputs. . . . .990
Table 197.CPU1 CTI inputs. . . . .990
Table 198.CPU1 CTI outputs. . . . .990
Table 199.CTI register map and reset values . . . . .1006
Table 200.DBGMCU register map and reset values . . . . .1015
Table 201.CPU2 processor ROM table . . . . .1017
Table 202.CPU2 ROM table . . . . .1017
Table 203.CPU2 processor ROM table register map and reset values. . . . .1024
Table 204.CPU2 ROM table register map and reset values . . . . .1030
Table 205.CPU2 DWT register map and reset values. . . . .1042
Table 206.CPU2 BPU register map and reset values . . . . .1051
Table 207.CPU1 ROM table . . . . .1052
Table 208.CPU1 ROM table register map and reset values . . . . .1059
Table 209.CPU1 DWT register map and reset values. . . . .1071
Table 210.CPU1 ITM register map and reset values. . . . .1080
Table 211.CPU1 FPB register map and reset values . . . . .1087
Table 212.CPU1 TPIU register map and reset values. . . . .1098
Table 213.Document revision history . . . . .1105

List of figures

Figure 1. System architecture . . . . . 52

Figure 2. Memory map . . . . . 55

Figure 3. Sequential 16-bit instructions execution . . . . . 67

Figure 4. Changing the Read protection (RDP) level . . . . . 91

Figure 5. Radio system block diagram . . . . . 119

Figure 6. CRC calculation unit block diagram . . . . . 121

Figure 7. Power supply overview . . . . . 128

Figure 8. Brown-out reset waveform . . . . . 131

Figure 9. PVD thresholds . . . . . 132

Figure 10. CPU2 boot options . . . . . 133

Figure 11. Low-power modes possible transitions . . . . . 136

Figure 12. Real-time radio activity flags . . . . . 151

Figure 13. Simplified diagram of the reset circuit . . . . . 174

Figure 14. Clock tree . . . . . 179

Figure 15. HSE clock sources . . . . . 180

Figure 16. LSE clock sources . . . . . 183

Figure 17. Three-volt or Five-volt tolerant GPIO structure (TT or FT) . . . . . 247

Figure 18. Input floating/pull up/pull down configurations . . . . . 252

Figure 19. Output configuration . . . . . 252

Figure 20. Alternate function configuration . . . . . 253

Figure 21. High impedance-analog configuration . . . . . 254

Figure 22. DMA block diagram . . . . . 285

Figure 23. DMAMUX block diagram . . . . . 308

Figure 24. Synchronization mode of the DMAMUX request line multiplexer channel . . . . . 311

Figure 25. Event generation of the DMA request line multiplexer channel . . . . . 311

Figure 26. Interrupt block diagram . . . . . 321

Figure 27. EXTI block diagram . . . . . 330

Figure 28. Configurable event trigger logic CPU wakeup . . . . . 333

Figure 29. Direct event trigger logic CPU wakeup . . . . . 334

Figure 30. ADC block diagram . . . . . 349

Figure 31. ADC calibration . . . . . 352

Figure 32. Calibration factor forcing . . . . . 352

Figure 33. Enabling/disabling the ADC . . . . . 353

Figure 34. ADC clock scheme . . . . . 354

Figure 35. ADC connectivity . . . . . 356

Figure 36. Analog-to-digital conversion time . . . . . 361

Figure 37. ADC conversion timings . . . . . 361

Figure 38. Stopping an ongoing conversion . . . . . 362

Figure 39. Single conversions of a sequence, software trigger . . . . . 365

Figure 40. Continuous conversion of a sequence, software trigger . . . . . 365

Figure 41. Single conversions of a sequence, hardware trigger . . . . . 366

Figure 42. Continuous conversions of a sequence, hardware trigger . . . . . 366

Figure 43. Data alignment and resolution . . . . . 367

Figure 44. Example of overrun (OVR) . . . . . 368

Figure 45. Wait mode conversion (continuous mode, software trigger) . . . . . 371

Figure 46. Behavior with WAIT = 0, AUTOFF = 1 . . . . . 372

Figure 47. Behavior with WAIT = 1, AUTOFF = 1 . . . . . 372

Figure 48. Analog watchdog guarded area . . . . . 373

Figure 49.ADC_AWD1_OUT signal generation . . . . .375
Figure 50.ADC_AWD1_OUT signal generation (AWD flag not cleared by software) . . . . .375
Figure 51.ADC1_AWD_OUT signal generation (on a single channel) . . . . .375
Figure 52.Analog watchdog threshold update . . . . .376
Figure 53.Temperature sensor and VREFINT channel block diagram . . . . .377
Figure 54.VBAT channel block diagram . . . . .379
Figure 55.TSC block diagram . . . . .399
Figure 56.Surface charge transfer analog I/O group structure . . . . .400
Figure 57.Sampling capacitor voltage variation . . . . .401
Figure 58.Charge transfer acquisition sequence . . . . .402
Figure 59.Spread spectrum variation principle . . . . .403
Figure 60.RNG block diagram . . . . .417
Figure 61.Entropy source model . . . . .418
Figure 62.RNG initialization overview . . . . .420
Figure 63.AES block diagram . . . . .429
Figure 64.ECB encryption and decryption principle . . . . .431
Figure 65.CBC encryption and decryption principle . . . . .432
Figure 66.CTR encryption and decryption principle . . . . .433
Figure 67.GCM encryption and authentication principle . . . . .434
Figure 68.GMAC authentication principle . . . . .434
Figure 69.CCM encryption and authentication principle . . . . .435
Figure 70.Encryption key derivation for ECB/CBC decryption (Mode 2). . . . .438
Figure 71.Example of suspend mode management . . . . .439
Figure 72.ECB encryption . . . . .440
Figure 73.ECB decryption . . . . .440
Figure 74.CBC encryption . . . . .441
Figure 75.CBC decryption . . . . .441
Figure 76.ECB/CBC encryption (Mode 1) . . . . .442
Figure 77.ECB/CBC decryption (Mode 3) . . . . .443
Figure 78.Message construction in CTR mode . . . . .445
Figure 79.CTR encryption . . . . .446
Figure 80.CTR decryption . . . . .446
Figure 81.Message construction in GCM . . . . .448
Figure 82.GCM authenticated encryption . . . . .449
Figure 83.Message construction in GMAC mode . . . . .453
Figure 84.GMAC authentication mode . . . . .453
Figure 85.Message construction in CCM mode . . . . .454
Figure 86.CCM mode authenticated encryption . . . . .456
Figure 87.128-bit block construction with respect to data swap . . . . .460
Figure 88.DMA transfer of a 128-bit data block during input phase . . . . .462
Figure 89.DMA transfer of a 128-bit data block during output phase . . . . .463
Figure 90.PKA block diagram . . . . .478
Figure 91.Advanced-control timer block diagram . . . . .505
Figure 92.Counter timing diagram with prescaler division change from 1 to 2 . . . . .507
Figure 93.Counter timing diagram with prescaler division change from 1 to 4 . . . . .507
Figure 94.Counter timing diagram, internal clock divided by 1 . . . . .509
Figure 95.Counter timing diagram, internal clock divided by 2 . . . . .509
Figure 96.Counter timing diagram, internal clock divided by 4 . . . . .510
Figure 97.Counter timing diagram, internal clock divided by N . . . . .510
Figure 98.Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .511
Figure 99.Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .511
Figure 100.Counter timing diagram, internal clock divided by 1 . . . . .513
Figure 101. Counter timing diagram, internal clock divided by 2 . . . . .513
Figure 102. Counter timing diagram, internal clock divided by 4 . . . . .514
Figure 103. Counter timing diagram, internal clock divided by N . . . . .514
Figure 104. Counter timing diagram, update event when repetition counter is not used . . . . .515
Figure 105. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .516
Figure 106. Counter timing diagram, internal clock divided by 2 . . . . .517
Figure 107. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .517
Figure 108. Counter timing diagram, internal clock divided by N . . . . .518
Figure 109. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .518
Figure 110. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .519
Figure 111. Update rate examples depending on mode and TIMx_RCR register settings . . . . .520
Figure 112. External trigger input block . . . . .521
Figure 113. TIM1 ETR input circuitry . . . . .521
Figure 114. Control circuit in normal mode, internal clock divided by 1 . . . . .522
Figure 115. TI2 external clock connection example . . . . .523
Figure 116. Control circuit in external clock mode 1 . . . . .524
Figure 117. External trigger input block . . . . .524
Figure 118. Control circuit in external clock mode 2 . . . . .525
Figure 119. Capture/compare channel (example: channel 1 input stage) . . . . .526
Figure 120. Capture/compare channel 1 main circuit . . . . .526
Figure 121. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .527
Figure 122. Output stage of capture/compare channel (channel 4) . . . . .527
Figure 123. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .528
Figure 124. PWM input mode timing . . . . .530
Figure 125. Output compare mode, toggle on OC1 . . . . .532
Figure 126. Edge-aligned PWM waveforms (ARR=8) . . . . .533
Figure 127. Center-aligned PWM waveforms (ARR=8) . . . . .534
Figure 128. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .536
Figure 129. Combined PWM mode on channel 1 and 3 . . . . .537
Figure 130. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .538
Figure 131. Complementary output with dead-time insertion . . . . .539
Figure 132. Dead-time waveforms with delay greater than the negative pulse . . . . .539
Figure 133. Dead-time waveforms with delay greater than the positive pulse . . . . .540
Figure 134. Break and Break2 circuitry overview . . . . .542
Figure 135. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .544
Figure 136. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .545
Figure 137. PWM output state following BRK assertion (OSSI=0) . . . . .546
Figure 138. Output redirection (BRK2 request not represented) . . . . .547
Figure 139. Clearing TIMx OCxREF . . . . .548
Figure 140. 6-step generation, COM example (OSSR=1) . . . . .549
Figure 141. Example of one pulse mode . . . . .550
Figure 142. Retriggerable one pulse mode . . . . .552
Figure 143. Example of counter operation in encoder interface mode . . . . .553
Figure 144. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .554
Figure 145. Measuring time interval between edges on 3 signals . . . . .555
Figure 146. Example of Hall sensor interface . . . . .557
Figure 147. Control circuit in reset mode . . . . .558
Figure 148. Control circuit in Gated mode . . . . .559
Figure 149. Control circuit in trigger mode . . . . .560
Figure 150. Control circuit in external clock mode 2 + trigger mode . . . . .561
Figure 151. General-purpose timer block diagram . . . . .603
Figure 152. Counter timing diagram with prescaler division change from 1 to 2 . . . . .605
Figure 153. Counter timing diagram with prescaler division change from 1 to 4 . . . . .605
Figure 154. Counter timing diagram, internal clock divided by 1 . . . . .606
Figure 155. Counter timing diagram, internal clock divided by 2 . . . . .607
Figure 156. Counter timing diagram, internal clock divided by 4 . . . . .607
Figure 157. Counter timing diagram, internal clock divided by N . . . . .608
Figure 158. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .608
Figure 159. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .609
Figure 160. Counter timing diagram, internal clock divided by 1 . . . . .610
Figure 161. Counter timing diagram, internal clock divided by 2 . . . . .610
Figure 162. Counter timing diagram, internal clock divided by 4 . . . . .611
Figure 163. Counter timing diagram, internal clock divided by N . . . . .611
Figure 164. Counter timing diagram, Update event . . . . .612
Figure 165. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .613
Figure 166. Counter timing diagram, internal clock divided by 2 . . . . .614
Figure 167. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .614
Figure 168. Counter timing diagram, internal clock divided by N . . . . .615
Figure 169. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .615
Figure 170. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .616
Figure 171. Control circuit in normal mode, internal clock divided by 1 . . . . .617
Figure 172. TI2 external clock connection example. . . . .617
Figure 173. Control circuit in external clock mode 1 . . . . .618
Figure 174. External trigger input block . . . . .619
Figure 175. Control circuit in external clock mode 2 . . . . .620
Figure 176. Capture/Compare channel (example: channel 1 input stage) . . . . .620
Figure 177. Capture/Compare channel 1 main circuit . . . . .621
Figure 178. Output stage of Capture/Compare channel (channel 1). . . . .621
Figure 179. PWM input mode timing . . . . .623
Figure 180. Output compare mode, toggle on OC1 . . . . .625
Figure 181. Edge-aligned PWM waveforms (ARR=8). . . . .626
Figure 182. Center-aligned PWM waveforms (ARR=8). . . . .628
Figure 183. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .629
Figure 184. Combined PWM mode on channels 1 and 3 . . . . .630
Figure 185. Clearing TIMx_OCxREF . . . . .631
Figure 186. Example of one-pulse mode. . . . .632
Figure 187. Retriggerable one-pulse mode . . . . .634
Figure 188. Example of counter operation in encoder interface mode . . . . .635
Figure 189. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .636
Figure 190. Control circuit in reset mode . . . . .637
Figure 191. Control circuit in gated mode . . . . .638
Figure 192. Control circuit in trigger mode. . . . .639
Figure 193. Control circuit in external clock mode 2 + trigger mode . . . . .640
Figure 194. Master/Slave timer example . . . . .641
Figure 195. Master/slave connection example with 1 channel only timers . . . . .641
Figure 196. Gating TIM2 with OC1REF of TIM1 . . . . .642
Figure 197. Gating TIM2 with Enable of TIM1 . . . . .643
Figure 198. Triggering TIM2 with update of TIM1 . . . . .644
Figure 199. Triggering TIM2 with Enable of TIM1 . . . . .644
Figure 200. Low-power timer block diagram . . . . .675
Figure 201. Glitch filter timing diagram . . . . .677
Figure 202. LPTIM output waveform, single counting mode configuration . . . . .679
Figure 203. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set). . . . .		679
Figure 204. LPTIM output waveform, Continuous counting mode configuration . . . . .680
Figure 205. Waveform generation . . . . .681
Figure 206. Encoder mode counting sequence . . . . .685
Figure 207. RTC block diagram . . . . .699
Figure 208. Independent watchdog block diagram . . . . .738
Figure 209. Watchdog block diagram . . . . .748
Figure 210. Window watchdog timing diagram . . . . .749
Figure 211. Block diagram . . . . .755
Figure 212. I 2 C-bus protocol . . . . .757
Figure 213. Setup and hold timings . . . . .759
Figure 214. I2C initialization flow . . . . .761
Figure 215. Data reception . . . . .762
Figure 216. Data transmission . . . . .763
Figure 217. Target initialization flow . . . . .766
Figure 218. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .768
Figure 219. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .769
Figure 220. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .770
Figure 221. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .771
Figure 222. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .772
Figure 223. Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . .		772
Figure 224. Controller clock generation . . . . .774
Figure 225. Controller initialization flow . . . . .776
Figure 226. 10-bit address read access with HEAD10R = 0 . . . . .776
Figure 227. 10-bit address read access with HEAD10R = 1 . . . . .777
Figure 228. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .778
Figure 229. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .779
Figure 230. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		780
Figure 231. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .782
Figure 232. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .783
Figure 233. Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		784
Figure 234. Timeout intervals for t LOW:SEXT , t LOW:MEXT . . . . .788
Figure 235. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .791
Figure 236. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .792
Figure 237. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .793
Figure 238. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .794
Figure 239. Bus transfer diagrams for SMBus controller transmitter . . . . .795
Figure 240. Bus transfer diagrams for SMBus controller receiver . . . . .797
Figure 241. USART block diagram . . . . .819
Figure 242. Word length programming . . . . .822
Figure 243. Configurable stop bits . . . . .824
Figure 244. TC/TXE behavior when transmitting . . . . .827
Figure 245. Start bit detection when oversampling by 16 or 8. . . . .828
Figure 246. usart_ker_ck clock divider block diagram . . . . .831
Figure 247. Data sampling when oversampling by 16. . . . .832
Figure 248. Data sampling when oversampling by 8. . . . .833
Figure 249. Mute mode using Idle line detection . . . . .840
Figure 250. Mute mode using address mark detection . . . . .841
Figure 251. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .844
Figure 252. Break detection in LIN mode vs. Framing error detection. . . . .845
Figure 253.USART example of synchronous master transmission. . . . .846
Figure 254.USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		846
Figure 255.USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		847
Figure 256.USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		848
Figure 257.ISO 7816-3 asynchronous protocol . . . . .850
Figure 258.Parity error detection using the 1.5 stop bits . . . . .852
Figure 259.IrDA SIR ENDEC block diagram. . . . .856
Figure 260.IrDA data modulation (3/16) - normal mode . . . . .856
Figure 261.Transmission using DMA . . . . .858
Figure 262.Reception using DMA . . . . .859
Figure 263.Hardware flow control between 2 USARTs . . . . .859
Figure 264.RS232 RTS flow control . . . . .860
Figure 265.RS232 CTS flow control . . . . .861
Figure 266.Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .864
Figure 267.Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		864
Figure 268.SPI block diagram. . . . .903
Figure 269.Full-duplex single master/ single slave application. . . . .904
Figure 270.Half-duplex single master/ single slave application . . . . .905
Figure 271.Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		906
Figure 272.Master and three independent slaves. . . . .907
Figure 273.Multimaster application. . . . .908
Figure 274.Hardware/software slave select management . . . . .909
Figure 275.Data clock timing diagram . . . . .910
Figure 276.Data alignment when data length is not equal to 8-bit or 16-bit . . . . .911
Figure 277.Packing data in FIFO for transmission and reception. . . . .915
Figure 278.Master full-duplex communication . . . . .918
Figure 279.Slave full-duplex communication . . . . .919
Figure 280.Master full-duplex communication with CRC . . . . .920
Figure 281.Master full-duplex communication in packed mode . . . . .921
Figure 282.NSSP pulse generation in Motorola SPI master mode. . . . .924
Figure 283.TI mode transfer . . . . .925
Figure 284.IPCC block diagram . . . . .938
Figure 285.IPCC Simplex channel mode transfer timing . . . . .939
Figure 286.IPCC Simplex - Send procedure state diagram . . . . .940
Figure 287.IPCC Simplex - Receive procedure state diagram . . . . .941
Figure 288.IPCC Half-duplex channel mode transfer timing. . . . .942
Figure 289.IPCC Half-duplex - Send procedure state diagram . . . . .942
Figure 290.IPCC Half-duplex - Receive procedure state diagram . . . . .943
Figure 291.HSEM block diagram . . . . .952
Figure 292.Procedure state diagram . . . . .953
Figure 293.Interrupt state diagram . . . . .956
Figure 294.Block diagram of debug support infrastructure. . . . .967
Figure 295.JTAG TAP state machine . . . . .970
Figure 296.Debug and access port connections. . . . .982
Figure 297.Embedded cross trigger . . . . .989
Figure 298.Mapping trigger inputs to outputs . . . . .991
Figure 299.Cross trigger configuration example. . . . .992
Figure 300. CPU2 CoreSight™ topology . . . . .1018
Figure 301. CPU1 CoreSight™ topology . . . . .1053
Figure 302. Trace port interface unit (TPIU) . . . . .1088

Chapters