69. Revision history

Table 797. Document revision history

DateRevisionChanges
15-Feb-20231Initial release.
13-Apr-20232Updated:
– Section 2: Memory and bus architecture
– Section 3: RAMECC monitoring (RAMECC)
– Section 5: Embedded flash memory (FLASH)
– Section 6: Power control (PWR)
– Section 7: Reset and clock control (RCC)
– Section 10: General-purpose I/Os (GPIO)
– Section 43: Basic timers (TIM6/TIM7)
21-Jun-20233Updated:
– Section 2: Memory and bus architecture
– Section 4: System security
– Section 5: Embedded flash memory (FLASH)
– Section 7: Reset and clock control (RCC)
– Section 8: System configuration, boot and security (SBS)
– Section 10: General-purpose I/Os (GPIO)
– Section 66: Debug infrastructure
10-Oct-20234Updated:
– Table 10: Availability of security features
– Figure 1: System architecture
– Table 7: Register boundary addresses
– Table 6: Secure boot process
– Iterated register syntax in Section 10.4: GPIO registers
– Table 85: GPIO register map and reset values
09-Jan-20245Updated:
– Figure 3: Memory map
– Response to tampers
– Section 5.9.22: FLASH RoT status register (FLASH_ROTSR)
– Figure 33: V CORE voltage scaling versus system power modes
– Section 6.8.4: PWR control register 2 (PWR_CSR2)
– Section 10.3.16: High-speed low-voltage mode (HSLV)
– Figure 1004: APB-D CoreSight component topology

Table 797. Document revision history

DateRevisionChanges
12-Mar-20246Updated:
– Read latency in Table 29: FLASH recommended read wait states and programming delays and Section 5.9.1: FLASH access control register (FLASH_ACR)
– IROT_SELECT value in Table 5.4.7: Description of security option bytes
– Section 5.9.22: FLASH RoT status register (FLASH_ROTSR)
– Section 67.1: Unique device ID register (96 bits)
– Section 67.2: Package data register
Aligned capitalization:
– (S)VOS LOW -> (S)VOS low
– (S)VOS HIGH -> (S)VOS high
– STiROT -> STiRoT
15-Jul-20247Inserted several missing “-” and “X” characters in Table 2: Bus-master-to-bus-slave interconnect .
Updated Figure 1: System architecture .
Updated Table 31: Read-only public data organization
Corrected reset values in Table 32: Option byte user words organization .
Updated Table 41: PWR input/output signals connected to package pins or balls .
Updated LDO output voltage and removed some constraints in Section 6.4.1: System supply startup .
Corrected register names in description of bitfield PRESCALER[7:0] in the XSPI device configuration register 2 (XSPI_DCR2) .
In Section 24: Extended-SPI interface (XSPI) :
– Corrected FIFO width in FIFO and data management
– Updated Figure 216: XSPI direct 16-bit mode

Table 797. Document revision history

DateRevisionChanges
16-Dec-20248Updated:

Table 797. Document revision history

DateRevisionChanges
05-Dec-20259

Removed old Section 3.3.4 Read access latency.

Added Default tamper configuration after reset on closed/locked product states.

Corrections to:

  • – Figure 3: Memory map
  • – Table 7: Register boundary addresses: GPIOA/AFR0 and lower reserved boundary above SAES: APB3
  • – Table 20: RAMECC register map and reset values - RAMECC_IER register bit 1.
  • – Section 4.10.2: RSS user functions
  • – Section 5.2: FLASH main features
  • – Section 5.9.18: FLASH option byte key control register (FLASH_OBKEYR)
  • – Table 33: STM32H7Rx/7Sx device lifecycle table
  • – Table 19: Power control block diagram
  • – Table 41: PWR input/output signals connected to package pins or balls - DVDD description
  • – Table 44: Supply configuration control - ID0 startup-configuration description
  • – Section 6.5.7: VCORE maximum voltage level detector
  • – Section 6.8.1: PWR control register 1 (PWR_CR1)
  • – Section 6.8.4: PWR control register 2 (PWR_CSR2)
  • – Table 53: Power control register map and reset values
  • – Section 7.8.12: RCC PLL1 dividers configuration register 1 (RCC_PLL1DIVR1) - DIVN[8:0] frequency range in caution text
  • – Section 7.8.31: RCC Backup domain control register (RCC_BDCR) - Access description text
  • – Section 7.8.32: RCC clock control and status register (RCC_CSR) - Access description text
  • – Section 7.8.44: RCC Reset status register (RCC_RSR) - access description text
  • – Section 8.2: SBS main features (System configuration last sub bullet)
  • – Section 8.5.7: SBS product mode and configuration register (SBS_PMCR) - reset value and AXISRAM_WS bit description
  • – Section 8.5.10: SBS I/O compensation cell control and status register (SBS_CCCSR) - all access types 'rw'
  • – Section 10.3.16: High-speed low-voltage mode (HSLV)
  • – Table 87: Peripheral interconnect matrix
  • – Figure 1002: Block diagram of debug infrastructure
  • – Debug port access port select register (DP_SELECT) - APSEL[7:0] description