19. Nested vectored interrupt controller (NVIC)

19.1 NVIC features

The NVIC includes the following features:

• • up to 140 maskable interrupt channels for STM32H7xxx (not including the 10 interrupt lines of Cortex®-M7 with FPU)
• • 16 programmable priority levels (4 bits of interrupt priority are used)
• • low-latency exception and interrupt handling
• • power management control
• • implementation of system control registers

The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late-arriving interrupts.

All interrupts, including the core exceptions, are managed by the NVIC.

For more information on exceptions and NVIC programming, refer to PM0253 programming manual for Cortex®-M7.

19.1.1 SysTick calibration value register

The SysTick calibration value (SYST_CALIB) is fixed to 0x3E8. It provides a reference timebase of 1 ms based when the SysTick clock frequency is 1 MHz. To match the 1 ms timebase whatever the application frequency, the SysTick reload value must be programmed as follows in the SYST_RVR register:

• • If the SysTick clock source is the 100 MHz CPU clock (HCLK):

• • If the SysTick clock source is an external clock:

where \( F_{\text{HCLK}} \) refers to the AHB frequency expressed in MHz.

For example, to achieve a timebase of 1 ms when the SysTick clock source is the 100 MHz HCLK:

19.1.2 Interrupt and exception vectors

The exception vectors connected to the NVIC are the following: reset, NMI, HardFault, MemManage, Bus Fault, UsageFault, SVCall, DebugMonitor, PendSV, SysTick.

Table 142. NVIC ⁽¹⁾

1. When different signals are connected to the same NVIC interrupt line, they are OR-ed.