11. Peripheral interconnect

11.1 Introduction

Several peripherals have direct connections between them. This allows autonomous communication and or synchronization between peripherals, saving CPU resources, thus power supply consumption.

In addition, these hardware connections remove software latency and allow design of predictable system.

Depending on peripherals, these interconnections can operate in various power modes: Run, Sleep or Stop modes.

11.2 Connection summary

Table 87. Peripheral interconnect matrix ^{(1) (2)}

1. Letters in the table correspond to the type of connection described in Section 11.2: Connection summary

2. The “-” symbol in a gray cell means no interconnect.

11.3 Interconnection details

11.3.1 Master to slave interconnection for timers

From timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM9/TIM12/TIM13/TIM14/TIM15/TIM16/TIM17) to timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM9/TIM12/TIM13/TIM14/TIM15/TIM16/TIM17).

Purpose

Some of the TIMx timers are linked together internally for timer synchronization or chaining. When one timer is configured in master mode, it can reset, start, stop or clock the counter of another timer configured in slave mode.

Timer synchronization

The synchronization modes are detailed in:

• • Section 41.3.30: Timer synchronization for advanced-control timers TIM1
• • Section 42.4.23: Timer synchronization for general-purpose timers TIM2/TIM3/TIM4/TIM5
• • Section 44.4.20: Timer synchronization (TIM9/TIM12 only) for the general-purpose timer (Lite no DT) TIM9/TIM12
• • Section 45.4.26: Timer synchronization (TIM15 only) for the general-purpose timer (Lite) TIM15

Triggering signals

The output (from master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1) following a configurable timer event. It can be also from signals tim16_oc1 and tim17_oc1 in case of TIM16/TIM17. The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.

The possible master/slave connections are given in:

• • Table 410: Internal trigger connection for advanced-control timers TIM1
• • Table 433: TIMx internal trigger connection for the general-purpose timers TIM2/TIM3/TIM4/TIM5
• • Table 454: TIMx internal trigger connection for general-purpose timers TIM9/TIM12
• • Table 466: TIMx internal trigger connection for general-purpose timers TIM15

Active power mode

Timers are optionally active in Run and Sleep modes. The effects of low-power modes on TIMx are given in:

• • Table 422: Effect of low-power modes on TIM1
• • Table 447: Effect of low-power modes on TIM6/TIM7
• • Table 440: Effect of low-power modes on TIM2/TIM3/TIM4/TIM5
• • Table 456: Effect of low-power modes on TIM9/TIM12/TIM13/TIM14
• • Table 472: Effect of low-power modes on TIM15/TIM16/TIM17

11.3.2 Triggers to ADCs

From EXTI, timers (TIM1/TIM2/TIM3/TIM4/TIM6/TIM9/TIM12/TIM15) and LP timers (LPTIM1/ LPTIM2/LPTIM3) to ADC1

Purpose

A conversion, or a sequence of conversions, can be triggered either by software or by an external event (such as timer capture or input pins). For ADC1, if the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then external events can trigger a conversion with the selected polarity. More details in:

• • Section 27.4.18: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN)
• • ADC configuration register (ADC_CFGR)
• • ADC injected sequence register (ADC_JSQR)

General-purpose timers (TIM2/TIM3/TIM4), basic timer (TIM6), advanced-control timers (TIM1) and general-purpose timer (TIM9/TIM12/TIM15) can be used to generate the ADC triggering event through the timer outputs tim_oc and tim_trgo.

Low-power timers (LPTIM1/ LPTIM2/LPTIM3) can be used to generate the ADC triggering event through the LPTIM channels (TIMx synchronization described in Section 41.3.30: Timer synchronization for TIM1) in addition to the EXTI on channels 11 and 15.

Triggering signals

For ADC1, the input triggering signals and the description of the interconnection between ADC1, and timers, are given in:

• • Table 229: ADC interconnection
• • Section 27.4.18: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN)
• • Section 27.4.25: Timing diagrams example (single/continuous modes, hardware/software triggers)

Active power mode

This interconnection is active in Run and Sleep modes for all ADCs. The timers are active in Run and Sleep mode only. The effects of low-power modes are given in:

• • Table 422: Effect of low-power modes on TIM1
• • Table 440: Effect of low-power modes on TIM2/TIM3/TIM4/TIM5
• • Table 456: Effect of low-power modes on TIM9/TIM12/TIM13/TIM14
• • Table 478: STM32H7Rx/7Sx LPTIM features

11.3.3 ADC analog watchdogs as triggers to timers

From ADC1/ADC2 to TIM1

Purpose

The internal analog watchdog output signals coming from ADC1, are connected to on-chip timers. ADC1 can provide trigger event through analog watchdog signals to advanced-control timers (TIM1) in order to reset, start, stop or clock the counter.

Settings description of the ADC analog watchdog and timer trigger, are provided in:

• • Section 41.3.6: External trigger input
• • Table 411: Interconnect to the tim_etr input multiplexer for the internal ADC1 sources connected to TIM1 (tim_etr) input multiplexer
• • Table 228: ADC internal input/output signals for the ADC_AWDx

Triggering signals

The output (from ADC) is on signals ADCn_AWDx_OUT, with n being the ADC instance and x = 1, 2, 3 (three watchdogs per ADC). The input (to timer) is on signal TIMx_ETR (external trigger).

Active power mode

ADC1 are active in Run and Sleep modes.

11.3.4 Triggers on ADF1

From EXTI to ADF1

Purpose

EXTI (EXTI15) can be used to generate a triggering event on ADF1 module and start an A/C conversion.

A description is given in:

• • Section 27.4.2: ADC pins and internal signals
• • Section 30.4.9: Start-up sequence examples

Triggering signals

The adf_trgi trigger input is the triggering input signal. The ADF trigger inputs connections are detailed in:

• • Table 257: ADF trigger connections

Active power mode

This interconnection remains active down to Stop (SVOS high) for ADF1, assuming the trigger source remains active.

11.3.5 Internal input and clock sources to timers

From HSE, LSE, HSI CSI and MCO to TIM (TIM9, TIM12), LP timers (LPTIM1/LPTIM2/LPTIM3/LPTIM4/LPTIM5) and RTC

Purpose

A timer input or timer counter can receive different clock sources and can be used to calibrate internal oscillator on a reference clock for example.

Internal clocks (CSI, HSI) and microcontroller output clock (MCO) can be used as input to timers:

• • HSI and CSI are assigned to general purpose timers TIM12 as external inputs signals. This allows the calibration. HSI/CSI can be selected as counter clock provided by an external clock source in mode1 (tim_ti1_in) Inputs assignment and clock selection description are detailed in:
  • – Section 44.4.5: Clock selection for TIM12
  • – External clock mode1: Table 444: TIM internal input/output signals for TIM12, tim_ti1_in2 (HSI) and tim_ti1_in3(CSI)
• • Microcontroller output clock (MCO) is connected as external input to general-purpose timers TIM9. This allows the calibration or clock measurement. When the low-speed external (LSE) oscillator is used, no additional hardware connections are required. This feature is given in Table 452: Interconnect to the tim_ti1 input multiplexer
• • LSI and LSE can be selected as input capture 2 to LPTIM1 as described in Table 487: LPTIM1 input capture 2 connections
• • HSI/1024 CSI/128 can be selected as input capture 2 to LPTIM2 as described in Table 488: LPTIM2 input capture 2 connections .

Triggering signals

lptim_ic2_mux1 LPTIM input capture selection can be set in the LPTIM configuration register 2 (LPTIM_CFGR2). For timers, the internal clock signal can be selected as counter clock provided by an external clock source in mode1 (tim_ti1_in) and mode2 (external trigger input tim_etr_in).

Active power mode

This feature is available under Run and Sleep modes.

11.3.6 Triggers to low-power timers

From EXTI, TAMP and RTC alarm to LP timers (LPTIM1/LPTIM2/LPTIM3/LPTIM4/LPTIM5)

Purpose

LPTIM1/LPTIM2/LPTIM3/LPTIM4/LPTIM5 counters may be started either by software or after the detection of an active edge on one of the eight trigger inputs.

GPIO can also be selected as LPTIM input capture selection or LPTIM input selection, according to the LPTIM configuration register 2 (LPTIM_CFGR2).

Triggering signals

This trigger feature is described in Table 46.4.7: Trigger multiplexer and the following sections. The input selection is described in Table 483: LPTIM1/2/3/4/5 external trigger connections .

Active power mode

This interconnection remains active down to Stop mode.

11.3.7 RTC wake-up as inputs to timers

From RTC to timers (TIM16)

Purpose

RTC wake-up interrupt can be used as input to general-purpose timers (TIM16) channel 1.

Triggering signals

RTC wake-up signal is connected to tim_ti1_in3 signal as described in Table 452: Interconnect to the tim_ti1 input multiplexer for TIM15.

Active power mode

This interconnection is active down to Stop. Timers are not active but the count is performed at wake-up.

11.3.8 USB OTG SOF as trigger to timers

From USB OTG SOF to TIM2

Purpose

USB OTG SOF (start-of-frame) can generate a trigger to the general-purpose timer TIM2/TIM5. The USB connection to TIM2/TIM5 are described in Table 433: TIMx internal trigger connection .

Triggering signals

The tim_itr13 internal signal is generated by OTG HS SOF, the tim_itr14 internal signal is generated by OTG FS SOF.

Active power mode

This interconnection is active in Run and Sleep modes.

11.3.9 System errors as break signals to timers

The following system-level errors can trigger a timer break event: Cortex-M7 lockup, PVD low threshold, CSS, double ECC errors in AXISRAM1, AXISRAM3, ITCM, DTCM, backup RAM and flash memory.

The purpose of the break event is to disable the timer outputs to protect the power transistors they control.

System errors apply in RUN and Sleep modes.

Active power mode

Timers are optionally active in Run and Sleep modes. The effects of low-power modes on TIMx are given in:

• • Table 422: Effect of low-power modes on TIM1
• • Table 472: Effect of low-power modes on TIM15/TIM16/TIM17

11.3.10 Triggers to GPDMA/HPDMA

From EXTI, RTC (wake-up), timers (TIM1/TIM2/TIM3/TIM4/TIM5/TIM6/TIM7/TIM9/TIM12/TIM15), LP timers (LPTIM1/LPTIM3/LPTIM4/LPTIM5), HP/GPDMA1 transfer complete (gpdma1_chx_tcf/hldma1_chx_tcf), SPI6, LPUART.

Purpose

An HP/GPDMA trigger can be assigned to a HP/GPDMA channel x. A programmed HP/GPDMA transfer can be triggered by a rising/falling edge of a selected input trigger event. The trigger mode can also be programmed to condition the LLI link transfer. More details are given in the sections below:

• • Section 12.3.6: GPDMA triggers and Section 13.3.6: HPDMA triggers
• • Section 12.4.12: GPDMA triggered transfer and Section 13.4.12: HPDMA triggered transfer
• • Section 12.8.9: GPDMA channel x transfer register 2 (GPDMA_CxTR2) and Section 13.8.9: HPDMA channel x transfer register 2 (HPDMA_CxTR2) for more details on:
  • – Trigger selection TRIGSEL[5:0] field
  • – Trigger mode (LLI) defined by TRIGM[1:0].
  • – Trigger polarity as defined by TRIGPOL[1:0]

Triggering signals

GPDMA trigger mapping is specified in Table 94: Programmed GPDMA1 trigger , according to GPDMA_CxTR2.TRIGSEL[5:0].

HPDMA trigger mapping is specified in Table 106: Programmed HPDMA1 trigger , according to HPDMA_CxTR2.TRIGSEL[5:0].

Active power mode

Assuming sources are active down to Stop modes, this interconnection remains functional in Stop.

Refer to:

• • Section 12.6: GPDMA in low-power modes
• • Section 13.6: HPDMA in low-power modes

11.3.11 Internal analog signals to analog peripherals

From internal analog source to ADC (ADC1).

Purpose

The internal reference voltage (VREFINT), the internal temperature sensor (V _SENSE ) monitoring channel are connected to ADC (ADC1) input channels. In addition, the internal

digital core voltage (VCORE) and VBAT are connected to input channels. This is according to:

• • Section 27.4.32: Temperature sensor
• • Section 27.4.33: VBAT supply monitoring
• • Section 27.4.34: Monitoring the internal voltage reference
• • Section 27.4.35: Monitoring the supply voltage

Active power mode

These interconnections remain in Stop modes if the selected peripheral is kept active. Refer to Section 27.5: ADC in low-power modes

11.3.12 ADC data filtering by the ADF1

From ADC1 to ADF1.

Purpose

The ADF1 allows the connection of up to two ADCs to the filter path. For each filter, the DATSRC[1:0] field in the ADF digital filter configuration register x (ADF_DFLTxCICR) is used to select either data from the ADCs in:

• • Section 27.4.4: ADC connectivity
• • Table 229: ADC interconnection
  • – mdf_adcif1_dat[15:0] to adc_da
• • Table 268: Effect of low-power modes on ADF

Active power mode

This feature remains available down to Sleep mode.

11.3.13 Internal tamper sources

From internal peripherals, clocks or monitoring to tamper.

Purpose

In order to detect any abnormal activity or tentative to corrupt the device, tampers are introduced and alert the system of such undesired event. Different actions can be taken in consequences.

List of tamper sources can be found in Table 21: Internal tampers in TAMP

Active power mode

This interconnection is active in all power modes if the tamper source is activated.

11.3.14 Output from tamper to RTC

From TAMP to RTC

Purpose

The RTC can timestamp a tamper event in order to retrieve history in time of such detection. The RTC can also control GPIOs and set a signal based on tamp or alarm status outside the MCU.

Refer to Section 49.3.3: GPIOs controlled by the RTC and TAMP for more details.

Active power mode

This interconnection remain active in all power modes.

11.3.15 Encryption keys to AES/SAES

From TAMP backup registers, system Flash memory to and in between SAES and AES

Purpose

The encryption mechanism requires an hardware key that must be stored in a protected non-volatile memory. Different approaches are implemented in order to load them in a non-readable way. Tamper backup registers or system Flash can be used to store respectively BHK or RHUK, and to implement a dedicated bus to pass it to the SAES.

Refer to Section 36.4.14: SAES operation with wrapped keys for more details.

The AES encryption mechanism (faster than the SAES) can benefit from the sharing key of the SAES. Refer to Section 36.4.15: SAES operation with shared keys for more details.

Active power mode

AES and SAES are operating under Run and Sleep modes.