7. Reset and clock control (RCC)

The RCC block manages the clock and reset generation for the whole microcontroller.

The operating modes to which this section refers are defined in Section 6.6.1: Operating modes of the PWR block.

7.1 RCC main features

AHB-Lite bus interface

Reset block:

• – Generation of local and system reset
• – Bidirectional pin reset allowing to reset the microcontroller or external devices
• – WWDG and IWDG reset supported
• – Power-on (POR) and Brownout (BOR) resets initiated by the power control (PWR)

Clock generation block:

• • Generation and dispatching of clocks for the complete device
• • 3 separate PLLs using integer or fractional ratios
• • Possibility of changing the PLL fractional ratios on-the-fly
• • Smart clock gating to reduce power dissipation
• • System clock protection
• • 2 external oscillators:
  • – High-speed external oscillator (HSE) supporting a wide range of crystals from 4 to 50 MHz frequency ^(a)
  • – Low-speed external oscillator (LSE) for the 32 kHz crystals
• • 4 internal oscillators
  • – High-speed internal oscillator (HSI)
  • – 48 MHz RC oscillator (HSI48)
  • – Low-power internal oscillator (CSI)
  • – Low-speed internal oscillator (LSI)
• • Buffered clock outputs for external devices
• • Generation of two types of interrupts lines:
  • – Dedicated interrupt lines for clock security management
  • – One general interrupt line for other events
• • Clock generation handling in Stop and Standby mode

a. Note that when the USBHSPHY is used, the HSE frequency must be 16, 19.2, 20, 24, 26 or 32 MHz.

7.2 RCC block diagram

Figure 37 shows the RCC block diagram.

Figure 37. RCC block diagram

7.3 RCC pins and internal signals

Table 54 lists the RCC inputs and output signals connected to package pins or balls.

Table 54. RCC input/output signals connected to package pins or balls

The RCC exchanges a lot of internal signals with all components of the product, for that reason, Table 55 only shows the most significant internal signals.

Table 55. RCC internal input/output signals

Table 55. RCC internal input/output signals (Continued)

7.4 RCC reset block functional description

The RCC handles the reset generation for the complete product, using events coming from different sources:

• • assertion of the NRST pin from an external device
• • a failure on the supply voltage applied to VDD, VBAT
• • an exit from Standby
• • a watchdog timeout
• • a software command

The reset scope depends on the source that generates the reset.

7.4.1 Reset from PWR block

The PWR block provides several reset signals to the RCC:

• • The power-on/off reset signal ( pwr_por_rst ), which is asserted when the VDD supply is lower than the VPOR threshold.
• • The brown-out reset signal ( pwr_bor_rst ), which is asserted when the VDD supply is lower than the VBOR threshold.
• • The core reset signal ( pwr_vcore_ok ), which is asserted when the VDDCORE supply is not valid or available. Note that the VDDCORE voltage is switched off, when the product is in Standby. So when the system exits from Standby mode, the pwr_vcore_ok signal is asserted as long the VDDCORE voltage provided by the internal regulator is not valid. Note that when VDD supply is not valid, pwr_vcore_ok is asserted as well.
• • The VSW domain reset signal ( pwr_vsw_rst ), which is asserted when the VSW supply is lower than the expected threshold.

Note: The rcc_vcore_rst is generated from the pwr_vcore_ok signal, the main difference between these two signals is that rcc_vcore_rst remains asserted until the option byte loading operation is completed.

Refer to Table 56: Reset coverage summary for details.

Figure 38. Simplified reset circuit

MSV54102V3.

7.4.2 The system and application resets (sys_rst and nreset)

A system reset ( sys_rst ) resets most of the registers to their default values unless otherwise specified in the register description.

A system reset can be generated from one of the following sources:

• • an assertion of the NRST pin (external reset)
• • a reset from the power-on/off reset block ( pwr_por_rst )
• • a reset from the brownout reset block ( pwr_bor_rst )
  Refer to Section 6.5.2: Brownout reset (BOR) for a detailed description of the BOR function.
• • a reset from the independent watchdogs ( iwdg_out_rst )
• • an exit from Standby ( rcc_vcore_rst ).
• • a reset from the window watchdogs depending on WWDG configuration ( wwdg_out_rst )
• • a software reset from the Cortex®-M7 core
  It is generated via the SYSRESETREQ signal issued by the Cortex®-M7 core. This signal is also named SFTRESET in this document.
• • A reset from the low-power mode security reset, depending on option byte configuration ( lpwr_rst ).
• • An option byte reload request from the flash interface ( obl_rst )

The application reset ( nreset ) is similar to the system reset, but is not asserted when the system exits from Standby.

Note: The SYSRESETREQ bit in Cortex®-M7 through the FPU application interrupt and reset control register, must be set to force a software reset on the device. Refer to the Cortex®-M7 with FPU technical reference manual for more details (see http://infocenter.arm.com ).

7.4.3 The NRST reset

The NRST is active low. A pulse stretcher guarantees a minimum reset pulse duration of 20 µs (Refer to datasheet for details). In addition it is possible to extend the NRST assertion thanks to \( C_R \) capacitor. It is not recommended to let the NRST pin unconnected.

When it is not used, connect this pin to ground via a 10 to 100 nF capacitor (CR in Figure 38 ). As shown in Figure 38 , a filter is also present in order to suppress spurs coming from NRST PAD.

7.4.4 Low-power mode security reset (lpwr_rst)

To prevent critical applications from mistakenly enter a low-power mode, two low-power mode security resets are available. When enabled through nRST_STOP and nRST_STANDBY option bytes, a system reset is generated if the following conditions are met:

• • The CPU accidentally enters Stop mode.
  This type of reset is enabled by resetting nRST_STOP user option byte. In this case, whenever the Stop mode entry sequence is successfully executed, a system reset is generated.
• • The system accidentally enter Standby mode.
  This type of reset is enabled by resetting nRST_STANDBY user option byte. In this

case, whenever a Standby mode entry sequence is successfully executed, a system reset is generated.

When the Standby mode is entered, a flag is also set in the power controller.

LPWRRSTF bit in the RCC Reset status register (RCC_RSR) indicates that a low-power mode security reset occurred (see line #7 in Table 57 ).

lpwr_rst is activated when a low-power mode security reset due to CPU occurred.

Refer to Section 5.4: FLASH option bytes for additional information.

Refer to Section 6: Power control (PWR) for additional information and Table 45: Operating mode summary for the overview of the existing power modes.

7.4.5 Backup domain reset

A backup domain reset ( pwr_vsw_rst ) is generated when one of the following events occurs:

• • Software reset, triggered by setting the VSWRST bit in the RCC Backup domain control register (RCC_BDCR) . All RTC registers and the RCC_BDCR register are set to their reset values, with the exception of LSEDRV, which is not changed if LSEON=1. The BKPSRAM is not affected.
• • When the VSW voltage is outside the operating range. All RTC registers and the RCC_BDCR register are set to their reset values. In this case the content of the BKPSRAM is no longer valid.

Refer to Section 6.4.4: Backup domain section of PWR block and to section “ System security ” for additional information.

7.4.6 Coresight debug reset

The coresight debug components can be reset in different ways:

• • Over the DAP by setting to 1 the bit CDBGIRSTREQ of the control/status register of the debug port. This action asserts the debug reset request signal cdbgirstreq connected to the RCC. Then the RCC activates the debug reset ( rcc_dbg_rst ), a handshake signal cdbgirstack is provided to the DAP request. The debug reset remains as long as the cdbgirstreq is to 1, refer to Figure 38 for details.
• • When VDDCORE power-on reset occurs ( rcc_vcore_rst ). This reset is activated after a power-on reset, or when the product exits from Standby.

Refer to Section 1.7.1: CoreSight Debug Reset for details.

7.4.7 Option bytes loading

As shown in Figure 38 , the option bytes loading (OBL) sequence is triggered under the following conditions:

• • After a power-on, or
• • When the system exits from Standby
• • When the flash interface requested a reload of option bytes

The system reset ( sys_rst ) can be released only when the option byte loading (OBL) is completed.

7.4.8 Peripheral resets

The application can individually reset any peripheral whenever requested. This can be done via the RCC_xxxxRSTR registers where “xxxx” is the name of the bus to which the peripheral is connected.

In order to reset a peripheral, the corresponding reset bit must be set to 1, and then set back to 0. There is no need to enable the peripheral clock in order to reset a peripheral.

Note also that the CRYPT, SAES and HASH blocks can be reset in the case of a tamper event.

7.4.9 Reset coverage summary

Table 56: Reset coverage summary gives a detailed view of the reset coverage of the most important reset sources.

Note: When \( V_{DD} \) is not valid, \( V_{DDCORE} \) is also not valid.

1. The 'X' means that the function is reset by the corresponding reset line, the '-' means that the function is not reset by the corresponding reset line.

2. The pwr_por_rst is asserted when the voltage applied to VDD is not valid.
When pwr_por_rst is asserted, the rcc_vcore_rst, NRST, the sys_rst and the nreset, are asserted as well.

1. 3. The rcc_vcore_rst is asserted when the voltage applied to VDD is not valid, or when the system exits from Standby (because VDDCORE was switched off).
   When rcc_vcore_rst is asserted, the sys_rst , and the pwr_dbg_rst are asserted as well.
2. 4. When nreset is asserted, the sys_rst is also asserted.

7.4.10 Reset source identification

The CPU can identify the reset source by checking the reset flags in the RCC_RSR register.

The CPU can reset the flags by setting RMVF bit.

Table 57 shows how the status bits of the RCC_RSR register behave according to the situation that generated the reset. For example, when an IWDG timeout occurs (line #6), if the CPU is reading the RCC_RSR register during the boot phase, both PINRSTF and IWDGRSTF bits are set, indicating that the IWDG also generated a pin reset.

Table 57. Reset source identification (RCC_RSR) ⁽¹⁾

1. 1. Grayed cells highlight the register bits that are set.
2. 2. The SBF bit is located into the PWR_CSR3 register of the PWR block

7.4.11 Power-on and wake-up sequences

For detailed diagrams refer to Section 6.4.1: System supply startup in the PWR section.

The time interval between the event that exits the product from a low-power and the moment where the CPU is able to execute code, depends on the system state and on its configuration. Figure 39 shows the most usual examples.

Power-on wake-up sequence

The power-on wake-up sequence shown in Figure 39 gives the most significant phases of the power-on sequence. It is the longest sequence since the circuit was not powered. Note that this sequence remains unchanged, whatever \( V_{BAT} \) was present or not.

Boot from pin reset

When a pin reset occurs, V _DD is still present. As a result:

• • The regulator settling time is faster since the reference voltage is already stable.
• • The HSI restart delay may be needed if the HSI was not enabled when the NRST occurred, otherwise this restart delay phase is skipped.
• • The Flash memory power recovery delay can also be skipped if the Flash memory was enabled when the NRST occurred.

Note: The boot sequence is similar for pwr_bor_rst, lpwr_rst, STFRESET, iwdg_out_rst and wwdg_out_rst.

Boot from system Standby

When waking up from system Standby, the reference voltage is stable since V _DD has not been removed. As a result, the regulator settling time is fast. Since V _CORE was not present, the restart delay for the HSI, the Flash memory power recovery and the option byte reloading cannot be skipped.

Restart from system Stop

When restarting from Stop, V _DD is still present. As a result, the sequence is mainly composed of two steps:

1. 1. Regulator settling time to reach VOS low (default voltage).
2. 2. HSI/CSI restart delay. This step can be skipped if HSIKERON or CSIKERON bit is set to 1 in the RCC register map .

Figure 39. Boot sequences versus system states

7.5 RCC clock block functional description

The RCC provides a wide choice of clock generators:

• • HSI (high-speed internal oscillator) clock: ~ 8, 16, 32 or 64 MHz
• • HSE (high-speed external oscillator) clock: 4 to 50 MHz
• • LSE (low-speed external oscillator) clock: 32 kHz
• • LSI (low-speed internal oscillator) clock: ~ 32 kHz
• • CSI (low-power internal oscillator) clock: ~4 MHz
• • HSI48 (high-speed internal oscillator) clock: ~48 MHz

The RCC offers a high flexibility for the application to select the appropriate clock for CPU and peripherals, in particular for peripherals that require a specific clock such as SPI/I2S and SAI.

To optimize the power consumption, each clock source can be switched ON or OFF independently.

The RCC provides up to 3 PLLs; each of them can be configured in integer, with or without SSCG, or fractional mode.

As shown in the Figure 40 , the RCC offers two clock outputs (MCO1 and MCO2), with a great flexibility on the clock selection and frequency adjustment.

The SCGU block (system clock generation unit) contains several prescalers used to configure the CPU and bus matrix clock frequencies.

The PKSU block (peripheral kernel clock selection unit) provides several dynamic switches allowing a large choice of kernel clock distribution to peripherals.

The PKEU (peripheral kernel clock enable unit) and SCEU (system clock enable unit) blocks perform the peripheral kernel clock gating, and the bus interface/cores/bus matrix clock gating, respectively.

Figure 40. Top-level clock tree

D The selected input can be changed on-the-fly without spurs on the output signal. x Represents the selected mux input after a system reset.

MSV54104V4

7.5.1 Clock naming convention

The RCC provides clocks to the complete circuit. To avoid misunderstanding, the following terms are used in this document:

• • Peripheral clocks

The peripheral clocks are the clocks provided by the RCC to the peripherals. Two kinds of clock are available:

• – bus interface clocks
• – kernel clocks

A peripheral receives from the RCC a bus interface clock in order to access its registers, and thus control the peripheral operation. This clock is generally the AHB, APB or AXI clock depending on which bus the peripheral is connected to. Some peripherals only need a bus interface clock (such as RNG, TIMx).

Some peripherals also require a dedicated clock to handle the interface function. This clock is named kernel clock. As an example, peripherals such as SAI must generate specific and accurate master clock frequencies, which require dedicated kernel clock frequencies. Another advantage of decoupling the bus interface clock from the specific interface needs, is that the bus clock can be changed without reprogramming the peripheral.

• • CPU clock

The CPU clock is the clock provided to the CPU. It is derived from the system clock ( sys_ck ).

• • Bus matrix clocks

The bus matrix clocks are the clocks provided to the different bridges (APB, AHB or AXI). These clocks are derived from the system clock ( sys_ck ).

7.5.2 Oscillators description

The table hereafter shows the oscillator states versus system modes, when the oscillators are enabled via registers. The term “available” means that the resource can be used if activated via registers.

Table 58. Oscillator states versus system modes

1. If STOPWUCK = 0 or STOPKERWUCK = 0

2. If STOPWUCK = 1 or STOPKERWUCK = 1

3. HSI can remain activated in Stop if HSIKERON = 1, or if a peripheral selecting HSI, generates a kernel clock request.

4. CSI can remain activated in Stop if CSIKERON = 1, or if the peripheral selecting CSI, generates a kernel clock request.

HSE oscillator

The HSE block allows the application to provide a very accurate high-speed clock for the product. The HSE can generate an internal clock from two possible sources:

• • external clock source
• • external crystal/ceramic resonator

Figure 41. HSE/LSE clock source

External clock source (HSE bypass)

In this mode the oscillator is not used, and an external clock source must be provided to OSC_IN pin. The external clock can be low swing (analog) or digital. The OSC_OUT pin must be left HI-Z (see Figure 41).

The external clock signal can be digital or analog (square, sinus or triangle). An analog clock signal with a reduced amplitude, is supported thanks to an internal clock squarer. The input signal must have a duty cycle close to 50%. Refer to the datasheet for additional information.

This mode is selected when HSEBYP = 1, and HSEON = 1. In case of an analog clock input (low swing) the HSEEXT must be set to 0, for a digital clock input, HSEEXT bits must be set to 1.

Figure 42. HSE clock generation

External crystal/ceramic resonator

A crystal/resonator can be connected as shown in Figure 41 : the crystal/resonator and the load capacitors must be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected crystal or ceramic resonator. Refer to the electrical characteristics section of the datasheet for more details.

The oscillator mode is enabled by setting the HSEBYP bit to 0 and HSEON bit to 1.

HSE ready logic

The HSERDY flag indicates when a valid clock is available at HSE output ( hse_ck ). When the HSE is enabled (HSEON set to '1'), the HSERDY flag goes to '1' when 256 valid cycles of HSE have been detected. The hse_ck clock is not released until HSERDY goes to 1.

An interrupt can be generated if enabled in the RCC clock source interrupt enable register (RCC_CIER) .

HSE controls

The HSE can be switched ON and OFF through the HSEON bit.

The hardware does not allow modifying HSEON bit if one of the condition is met:

• • The HSE is used directly (via SW switch) as system clock.
• • The HSE is selected as reference clock for PLL1, with PLL1 enabled and selected to provide the system clock (via SW switch).
• • The bit XSPICKP is set to 1.
• • The bit FMCKP is set to 1.

The hardware does not allow changing the values of HSEBYP, and HSEEXT when HSEON = 1. Bits HSEBYP, HSEEXT and HSEON are located into the RCC register map .

The HSE is automatically disabled by hardware when the system enters Stop or Standby mode (See Table 58: Oscillator states versus system modes ).

In addition, the HSE clock can be driven to the MCO1 and MCO2 outputs and used as clock source for other application components.

Programming sequence

In order initialize the HSE, the application must follow the sequence hereafter:

• • Make sure the HSE is not directly or indirectly used as system clock, if it is the case, use HSI or CSI as clock source for system clock.
• • Make sure that XSPICKP and FMCCKP are set to 0
• • Disable the HSE by writing to 0 the HSEON bit,
• • Check that the HSE is disabled by waiting that the bit HSERDY is set to 0,
• • If the oscillator mode is needed:
  • – Select the oscillator mode by setting HSEBYP to 0,
• • If an external clock is connected to OSC_IN:
  • – Select the bypass mode by setting HSEBYP to 1,
  • – If the input clock is a full-swing digital signal, set HSEEXT to 1
  • – If the input clock is a low-swing signal, set HSEEXT to 0
• • Enable again the HSE by writing the HSEON bit to 1,
• • Wait for HSERDY = 1, then the HSE is ready for use.

LSE oscillator

The LSE block allows the application to provide a very accurate low-frequency clock for the product. The LSE can generate an internal clock from two possible sources:

• • external user clock
• • external crystal/ceramic resonator

External clock source (LSE bypass)

In this mode, the oscillator is not used, and an external clock source must be provided to OSC32_IN pin. The OSC32_OUT pin must be left HI-Z (see Figure 41 ).

The external clock signal can have a frequency up to 1 MHz and be digital or analog (square, sinus or triangle). An analog clock signal with a reduced amplitude, is supported thanks to an internal clock squarer. The input signal must have a duty cycle close to 50%. Refer to the datasheet for additional information.

This mode is selected by setting the LSEBYP and LSEON bits to 1. In case of an analog clock input (low swing) the LSEEXT must be set to 0, for a digital clock input, LSEEXT bits must be set to 1.

Figure 43. LSE clock generation

External crystal/ceramic resonator source (LSE crystal)

The LSE clock is generated from a 32.768 kHz crystal or ceramic resonator. It has the advantage to provide a low-power highly accurate clock source to the real-time clock (RTC) for clock/calendar or other timing functions. A crystal/resonator can be connected as shown in Figure 41 : the crystal/resonator and the load capacitors must be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected crystal or ceramic resonator. Refer to the electrical characteristics section of the datasheet for more details.

The oscillator mode is selected by setting LSEBYP bit to 0 and LSEON bit to 1.

The LSE also offers a programmable driving capability (LSEDRV[1:0]) that can be used to modulate the amplifier driving capability. This driving capability is chosen according to the external crystal/ceramic component requirement to insure a stable oscillation.

The driving capability must be set before enabling the LSE oscillator.

Warning: It is not allowed to change the driving capability when the LSE is enabled. The LSE behavior is not guaranteed in that case.

LSE ready logic

The LSE offers a LSERDY flag which indicates whether the LSE clock is available or not. When the LSE is enabled (LSEON set to 1) the LSERDY flag goes to 1 when certain amount of valid cycles of LSE clock have been detected. The lse_ck clock is not released until LSERDY goes to 1.

When LSEBYP = 0, the RCC waits 4096 clocks cycles before activating the LSERDY flag, when LSEBYP = 1, the RCC waits 8 clocks cycles.

An interrupt, can be generated if enabled in the RCC clock source interrupt enable register (RCC_CIER) .

LSERDY bit is located into the RCC Backup domain control register (RCC_BDCR) .

LSE controls

The LSE control bits LSEBYP, LSEEXT, LSEDRV[1:0] and LSEON are located into the RCC Backup domain control register (RCC_BDCR) . This register is write-protected by DBP bit of PWR_CR1 register. In order to modify the RCC_BDCR register, the bit DBP must be set 1.

The LSE oscillator is switched ON and OFF using the LSEON bit.

The LSE remains enabled when the system enters Stop, Standby or VBAT mode (See Table 58: Oscillator states versus system modes ).

The hardware does not allow changing the values of LSEBYP, and LSEEXT when LSEON = 1.

In addition, the LSE clock can be driven to the MCO1 output and used as clock source for external components.

LSE Programming sequence

In order initialize the LSE, the application must follow the sequence hereafter:

• • Set DBP bit of PWR_CR1 to 1 in order to allow write accesses to RCC_BDCR register.
• • Disable the LSE by writing to 0 the LSEON bit,
• • Check that the LSE is disabled by waiting that the bit LSERDY is set to 0,
• • if the oscillator mode is needed:
  • – Select the oscillator mode by setting LSEBYP to 0,
  • – Configure LSEDRV[1:0],
• • if an external clock is connected to OSC32_IN:
  • – Select the bypass mode by setting LSEBYP to 1,
  • – If the input clock is a full-swing digital signal, set LSEEXT to 1
  • – If the input clock is a low-swing signal, set LSEEXT to 0
• • Enable again the LSE by writing the LSEON bit to 1,
• • Wait for LSERDY = 1, then the LSE is ready for use.
• • If RCC_BDCR register no longer need to be changed, set DBP bit of PWR_CR1 to 0 in order to write-protect accesses.

If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (default value after reset).

HSI oscillator

The HSI block provides the default clock to the product.

The HSI is a high-speed internal RC oscillator that can be used directly as system clock, peripheral clock, or as PLL input. A predivider allows the application to select an HSI output frequency of 8, 16, 32 or 64 MHz. This predivider is controlled by the HSIDIV.

The HSI advantages are the following:

• • low-cost clock source since no external crystal is required
• • faster startup time than HSE (a few microseconds)

The HSI frequency, even with frequency calibration, is less accurate than an external crystal oscillator or ceramic resonator.

HSI controls

The HSI can be switched ON and OFF using the HSION bit.

The hardware does not allow modifying HSION bit if one of the condition is met:

• • The HSI is used directly (via software mux) as system clock.
• • The HSI is selected as reference clock for PLL1, with PLL1 enabled and selected to provide the system clock (via software mux).
• • The bit XSPICKP is set to 1.
• • The bit FMCCPK is set to 1.

Note that the HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case the hardware does not update the HSIDIV with the new value. However it is possible to change the HSIDIV if the HSI is used directly as system clock.

The HSIRDY flag indicates if the HSI is stable or not. At startup, the HSI output clock is not released until this bit is set by hardware.

The HSI clock can also be used as a backup source (auxiliary clock) if the HSE fails (refer to Section : CSS on HSE ).

The HSI can be disabled or not when the system enters Stop mode (See Table 58: Oscillator states versus system modes ).

In addition, the HSI clock can be driven to the MCO1 output and used as clock source for other application components.

Care must be taken when the HSI is used as kernel clock for communication peripherals, the application must take into account the following parameters:

• • the time interval between the moment where the peripheral generates a kernel clock request and the moment where the clock is really available,
• • the frequency accuracy.

HSION, HSIRDY and HSIDIV bits are located in the RCC register map .

HSI calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process variations. That is why each device is factory calibrated by STMicroelectronics to achieve an accuracy of ACC _HSI (refer to the product datasheet for more information).

After a power-on reset, or at the exit of Standby mode, the factory calibration value is loaded in the HSICAL[11:0] bits.

If the application is subject to voltage or temperature variations, this may affect the RC oscillator frequency. The user application can trim the HSI frequency using the HSITRIM[6:0] bits.

Note: HSICAL[11:0] and HSITRIM[6:0] bits are located in the RCC HSI calibration register (RCC_HSICFGR) .

Figure 44. HSI calibration flow

CSI oscillator

The CSI is a low-power RC oscillator that can be used directly as system clock, peripheral clock, or PLL input.

The CSI advantages are the following:

• • low-cost clock source since no external crystal is required
• • faster startup time than HSE (a few microseconds)
• • very low-power consumption.

The CSI provides a clock frequency of about 4 MHz, while the HSI is able to provide a clock up to 64 MHz.

CSI frequency, even with frequency calibration, is less accurate than an external crystal oscillator or ceramic resonator.

CSI controls

The CSI can be switched ON and OFF through the CSION bit. The CSIRDY flag indicates whether the CSI is stable or not. At startup, the CSI output clock is not released until this bit is set by hardware.

The hardware does not allow modifying CSION bit if one of the condition is met:

• • The CSI is used directly (via software mux) as system clock.
• • The CSI is selected as reference clock for PLL1, with PLL1 enabled and selected to provide the system clock (via software mux).
• • The bit XSPICKP is set to 1.
• • The bit FMCCPK is set to 1.

The CSI can be disabled or not when the system enters Stop mode (See Table 58: Oscillator states versus system modes ).

In addition, the CSI clock can be driven to the MCO2 output and used as clock source for other application components.

Even if the CSI settling time is faster than the HSI, care must be taken when the CSI is used as kernel clock for communication peripherals: the application must take into account the following parameters:

• • the time interval between the moment where the peripheral generates a kernel clock request and the moment where the clock is really available,
• • the frequency precision.

Note: CSION and CSIRDY bits are located in the RCC register map .

CSI calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by STMicroelectronics to achieve accuracy of ACC _CSI (refer to the product datasheet for more information).

After a power-on reset, or at the exit of Standby mode, the factory calibration value is loaded in the CSICAL[7:0] bits.

If the application is subject to voltage or temperature variations, this may affect the RC oscillator frequency. The user application can trim the CSI frequency using the CSITRIM[5:0] bits.

Note: Bits CSICAL[7:0] and CSITRIM[5:0] are located into the RCC CSI calibration register (RCC_CSICFGR)

Figure 45. CSI calibration flow

HSI48 oscillator

The HSI48 is an RC oscillator delivering a 48 MHz clock that can be used directly as kernel clock for some peripherals.

The HSI48 oscillator mainly aims at providing an accurate clock to the USB Full-Speed peripherals by means of a special clock recovery system (CRS) circuitry. The CRS can use the USB SOF signal, the LSE or an external signal to automatically adjust the oscillator frequency on-the-fly, with a very small granularity. It is possible to read the calibration value provided to the HSI48 via RCC clock recovery RC register (RCC_CRRRCR) . The HSI48TRIM value can be adjusted through the CRS block, for more details, refer to Section 9: Clock recovery system (CRS) .

Figure 46. HSI48 calibration flow

MSV54108V1

The HSI48 oscillator is disabled as soon as the system enters Stop or Standby mode. When the CRS is not used, this oscillator is free running and thus subject to manufacturing process variations. This is why each device is factory calibrated by STMicroelectronics to achieve an accuracy of ACC _HSI48 (refer to the product datasheet for more information).

The HSI48RDY flag indicates whether the HSI48 oscillator is stable or not. At startup, the HSI48 output clock is not released until this bit is set by hardware.

After a power-on reset, or at the exit of Standby mode, the factory calibration value is loaded into the HSI48.

The HSI48 can be switched ON and OFF using the HSI48ON bit.

The HSI48 clock can also be driven to the MCO1 multiplexer and used as clock source for other application components.

Note: HSI48ON and HSI48RDY bits are located in the RCC register map.

LSI oscillator

The LSI acts as a very-low-power clock source that can be kept running when the system is in Stop or Standby mode for the independent watchdog (IWDG) and auto-wake up unit (AWU). The clock frequency is around 32 kHz. For more details, refer to the electrical characteristics section of the datasheet.

The LSI can be switched ON and OFF using the LSION bit. The LSIRDY flag indicates whether the LSI oscillator is stable or not. If an independent watchdog is started either by hardware or software, the LSI is forced ON and cannot be disabled.

The LSI remains enabled when the system enters Stop or Standby mode (See Table 58: Oscillator states versus system modes ).

At LSI startup, the clock is not provided until the hardware sets the LSIRDY bit. An interrupt can be generated if enabled in the RCC clock source interrupt enable register (RCC_CIER) .

In addition, the LSI clock can be driven to the MCO2 output and used as a clock source for other application components.

Note: Bits LSION and LSIRDY bits are located into the RCC clock control and status register (RCC_CSR).

7.5.3 Clock security system (CSS)

The RCC offers a clock security system for the HSE and LSE oscillators. The clock security systems are capable of detecting a failure on HSE and LSE oscillators. The figure hereafter shows how this function interacts with other blocks.

Figure 47. LSE and HSE CSS function

CSS on HSE

The clock security system can be enabled by software via the HSECSSON bit. The HSECSSON bit can be enabled even when the HSEON is set to 0.

The CSS on HSE is activated when the HSE is enabled and ready, and the software sets the HSECSSON bit to 1. The CSS on HSE is no longer working when the HSE is disabled. For example, this function does not work when the system is in Stop mode.

It is not possible to clear directly the HSECSSON bit by software. The HSECSSON bit is cleared by hardware when a system reset occurs or when the system enters Standby mode (see Section 7.4.2: The system and application resets (sys_rst and nreset) ).

When the CSS on HSE is enabled, the following actions are done by the RCC if a failure is detected:

• • The signal rcc_hsecss_fail is asserted.
• • If the STOPWUCK = 0, the HSI clock is enabled and the SW switch automatically selects HSI as system clock.
• • If the STOPWUCK = 1, the CSI clock is enabled and the SW switch automatically selects CSI as system clock.
• • The HSE is then automatically disabled.
• • If the HSE output was used as clock source for PLLs, the PLLs are also disabled.
• • The XSPI[2:1]SEL switches go to recovery position.
• • The FMCSEL switch goes to recovery position:
  • – if PLL1 has been disabled and FMCSEL is in position 1.
  • – if PLL2 has been disabled and FMCSEL is in position 2.

See details on Section : Clock distribution for SDMMC, FMC, and XSPIs .

• • The clock failure event ( rcc_hsecss_fail ) is also sent to the break inputs of advanced-control timers (TIM1, TIM15, TIM16 and TIM17).
• • A NMI interrupt is generated to inform the software about the failure (CSS interrupt: rcc_hsecss_it ), thus allowing the MCU to perform rescue operations. The CSS interrupt is asserted until the HSECSSF bit is cleared. The HSECSSF flag can be cleared by setting the HSECSSC bit in the RCC clock source interrupt clear register (RCC_CICR) .
• • A tamper event can also be triggered, in order to clear content of the backup registers, and backup RAM.

CSS on LSE

A clock security system on the LSE oscillator can be enabled by software by programming the LSECSSON bit in the RCC Backup domain control register (RCC_BDCR) .

This bit is disabled by hardware if one of the following condition is met:

• • After a \( V_{SW} \) hardware reset ( pwr_vsw_rst ),
• • After a \( V_{SW} \) software reset via VSWRST bit

The software can also disable the clock security system after a LSE failure detection.

The CSS on LSE works in all modes (Run, Stop and Standby) including VBAT.

The LSECSS provides a re-arm feature, offering to the software the possibility to re-arm the LSECSS and re-enable the LSE clock when a failure has been detected. This feature allows the application to decide if the LSE is to be provided again to the RTC even if a failure occurred, or if another action must be performed. For example the application can decide to reset the \( V_{SW} \) domain only if a certain amount of consecutive LSE failures occurred, within a time window.

The LSECSS offers two flag signals:

• • The LSECSSD, capable of retaining an LSE failures even in VBAT mode.
• • The LSECSSF used to generate interrupt in case of LSE failure. This flag is not affected by a failure detected when the product is in VBAT mode

The sequence hereafter describes the LSE enabling sequence with the clock security system enabled.

• • Follow the LSE enable procedure given in the section LSE Programming sequence , except the last step
• • Select the LSE clock via RTCSEL[1:0]
• • Set the LSECSSON bit to 1
• • If RCC_BDCR register no longer needs to be changed, set DBP bit of PWR_CR1 to 0 in order to write-protect accesses.

Note: The LSECSSON bit must be enabled after the LSE is enabled (LSEON bit set by software) and ready (LSERDY set by hardware), and after the RTC clock has been selected through the RTCSEL bit.

If a failure is detected on the LSE, the hardware does the following:

• • The LSE clock is no more delivered to the RTC.
• • The values of RTCSEL, LSECSSON and LSEON bits are not changed by the hardware.
• • A failure event is generated ( rcc_lsecss_fail ). This event allows the system to wake-up from Standby, but also to protect the backup registers and BKPSRAM via TAMP block. This event is also generated in VBAT mode.
• • The interrupt flag LSECSSF is activated (except in VBAT mode) in order to generate an interrupt ( rcc_lsecss_it ).
• • The LSECSSD flag is activated as well, retaining the first LSE failure even in VBAT.

In the software side, different actions can be taken according to the application requirements. Three different cases are described hereafter in order to illustrate the hardware behavior, they can also be combined. The application can also decide to handle LSE failure differently.

Case A:

The application no longer wants to use LSE when a failure is detected:

• • Unlock RCC_BDCR register by setting the DBP bit of PWR_CR1 to 1
• • Disable the CSS function (this step is mandatory)
  • – Clear the LSECSSF bit, if interrupt was enabled for this event
  • – Set the LSECSSON bit to 0
  • – Set the LSEON bit to 0, in order to disable the LSE
• • Change the clock source for the RTC if needed:
  • – Set the RTCEN bit to 0 to disable the RTC clock
  • – Enable the new clock source for the RTC
  • – Select the proper clock source via RTCSEL
  • – Set the RTCEN bit to 1 to enable the RTC clock
• • The application must perform specific actions consecutive to TAMPER events if enabled
• • Lock RCC_BDCR register by setting the DBP bit of PWR_CR1 to 0

Case B:

The application wants to re-initialize the \( V_{SW} \) domain:

• • Unlock RCC_BDCR register by setting the DBP bit of PWR_CR1 to 1
• • Perform a VSW reset by setting VSWRST bit to 1, then back to 0 (it is in reality a pulse of one period of sys_ck)
• • The application must perform specific actions consecutive to TAMPER events if enabled
• • Re-initialize all components of the VSW domain.
• • Lock RCC_BDCR register by setting the DBP bit of PWR_CR1 to 0

Case C:

The application tries to re-use LSE when a failure is detected:

• • If the number of failures in a given time window is higher than a given threshold then go to case A or B. Otherwise continue to next step.
• • Unlock RCC_BDCR register by setting the DBP bit of PWR_CR1 to 1
• • Clear the LSECSSF bit if interrupt was enabled for this event.
• • The application must perform specific actions consecutive to TAMPER events if enabled
• • Set the LSECSSON bit to 0.
• • Re-arm the LSECSS function by writing the LSECSSRA bit to 1, then back to 0.
• • Wait for LSERDY set 1. The LSERDY flag must go to 1 after the oscillator settling time delay plus, 4096 periods of LSE clock. If this is not the case, it probably means that the LSE failure is permanent. It is not possible to set LSECSSON to 1, it is recommended to execute case A or B.
• • Set the LSECSSON bit to 1.
• • When LSECSSON is seen to 1, the LSE is enabled, and protected by LSECSS.
• • Lock RCC_BDCR register by setting the DBP bit of PWR_CR1 to 0

All bits used in this sequences (except DBP) are located into RCC Backup domain control register (RCC_BDCR) .

7.5.4 Clock output generation (MCO1/MCO2)

Two microcontroller clock output pins MCO1 and MCO2, are available. A clock source can be selected for each output. The selected clock can be divided thanks to configurable prescaler (refer to Figure 40 for additional information on signal selection).

MCO1 and MCO2 outputs are controlled via MCO1PRE[3:0], MCO1SEL[2:0], MCO2PRE[3:0] and MCO2SEL[2:0] located in the RCC clock configuration register (RCC_CFGR) .

The GPIO port corresponding to each MCO pin must be programmed in alternate function mode.

The dividers MCO1PRE and MCO2PRE, provide a clock with a duty cycle of 50% for even divisions values. More generally the duty cycle is given by the following formula:

For MCOxPRE = 2 to 15.

Note that the MCO1 and MCO2 outputs are available in Run and Stop modes.

Caution: The clock provided to the MCOs outputs must not exceed the maximum PAD speed, refer to the product datasheet for information about the supported PAD speed.

The table hereafter show the signals available on each MCO output.

Table 59. Oscillator states versus system modes

7.5.5 PLL description

The RCC features three PLLs:

• • PLL1, generally used to provide clocks to the CPU, busses, and some peripherals
• • PLL2, generally used to provide clocks to XSPI and SDMMC, and some peripherals
• • PLL3, dedicated to the kernel clock generation for peripherals

The PLLs integrated into the RCC are completely independent. They offer the following features:

• • A VCO supporting two modes:
  • – a wide-range
  • – a low-range used for instance in audio application cases
• • Input frequency range:
  • – 2 to 16 MHz for the VCO in wide-range mode
  • – 1 to 2 MHz for the VCO in low-range mode
• • VCO frequency range:
  • – 384 to 1672 MHz for the VCO in high-range mode (VCOH), before the divider.
  • – 150 to 420 MHz for the VCO in low-range mode (VCOL)
• • Capability to work either in integer with or without SSGC, or in fractional mode
• • 13-bit sigma-delta modulator, allowing to fine-tune the VCO frequency by steps of 10 to 0.3 ppm
• • The sigma-delta modulator can be updated on-the-fly without generating frequency overshoots on PLLs outputs.
• • PLLs offer up to 5 outputs with post-dividers.

For better flexibility, all PLLs offer two VCOs (VCOH and VCOL), the application can select the wanted VCO via PLLxVCOSEL bit.

The frequency of the reference clock provided to the PLLs ( refx_ck ) must range from 1 to 16 MHz. The DIVMx dividers of the RCC PLLs clock source selection register (RCC_PLLCKSEL) must be properly programmed in order to match this condition. In addition, the PLLxRGE[1:0] field of the RCC PLLs configuration register (RCC_PLLCFG) must be set according to the reference input frequency to guarantee an optimal performance of the PLL.

The user application can then configure the proper VCO. VCOL must be chosen when the reference clock frequency is lower than 2 MHz.

To reduce the power consumption, it is recommended to configure the VCO output to the smaller range.

Figure 48. PLL block diagram

The PLLs can be enabled by setting PLLxON to 1. The PLLxRDY bits indicate that the PLL is ready (means locked).

The DIVN loop divider must be programmed to achieve the expected frequency at VCO output. The VCO output range must be respected.

PLLs have a divider-by-2, at VCOH output, insuring that the clock provided to the post-dividers has a duty-cycle of 50%.

The frequency of the clocks provided by the PLLs can also be adjusted thanks to post-divider DIVP , DIVQ , DIVR , DIVS and DIVT . The post-divider values can be changed without disabling the PLLs, if their respective enable bits are set to 0.

The post-dividers provide clocks with 50% duty-cycle in the following conditions:

• • When the post-dividers are dividing the clock by an even value.
• • When VCOH is used and post-dividers are bypassed.
• • When VCOH is selected and post-dividers DIVS and DIVT are used,

PLL programming recommendations

This section is providing a list of recommendations to follow in order to guarantee a good usage of the PLLs. Note that programming examples are given in Section 1.6.2: PLL programming.

• • Before enabling the PLLs, the user must ensure that the reference frequency ( refx_ck ) provided to the PLL is stable and in the good range.
• • When one or several PLL outputs are not used, the application must set the corresponding enable bit DIV[y]ENx and the divider value DIV[y]x to 0 (with x = 1, 2 or 3, and y = P, Q, R, S or T).
• • In order to ensure the good behavior of the PLL, the bits PLLxPEN , PLLxQEN , PLLxREN , PLLxSEN and PLLxTEN must be set to 0 before disabling the corresponding PLL. In the same way, the bits PLLxPEN , PLLxQEN , PLLxREN ,

PLLxSEN and PLLxTEN can be set to 1 only if the corresponding bit PLLON is already set to 1 and the PLL is ready.

Refer to section Section 7.7.1: PLL programming procedure for additional information.

PLL protections

• • The RCC hardware does not allow changing DIVMx, DIVN, PLLxRGE, PLLxVCOSEL when the corresponding PLLx is ON and it is also not possible to change PLLSRC when one of the PLL is ON.
• • The RCC hardware does not allow changing of the post-dividers' DIVy when the corresponding PLLxyEN bit is set to 1 (with x = 1, 2 or 3, and y = P, Q, R, S or T).
• • The hardware prevents writing PLL1ON or PLL1PEN to 0 if the PLL1 is currently used to deliver the system clock. There are other hardware protections on the clock generators (refer to Section 7.5.7: Clock protection ).

The PLLs are disabled by hardware when the system enters Stop or Standby mode

PLLs using HSE as reference clock are also disabled by hardware if an HSE failure is detected.

Note: The refx_ck clock is provided to the PLLx when the corresponding PLLON bit is set to 1.

The PLLs can work in 3 different modes:

• • In integer mode
• • In fractional mode
• • In spread spectrum mode

Using the PLLs in integer mode

The PLL is working in integer mode when the sigma-delta modulator (SDM) is loaded with a 0, and the bit PLLxSSCGEN = 0.

In order to load 0 into the SDM, the user has to perform the following sequence:

• – Write PLLxFRACLE of RCC PLLs configuration register (RCC_PLLCFGR) to 0
• – Write FRACN[12:0] to 0,
• – Write PLLxFRACLE to 1
• – Wait at least 5 µs

The bits FRACN[12:0] are located in the RCC_PLLxFRACR registers.

The VCO frequency ( \( F_{VCO} \) ) and output frequencies expressions are given by the following table:

Table 60. VCO frequency and output frequency in integer mode

Refer to section Section 7.7.1: PLL programming procedure for additional information.

Using the PLLs in fractional mode

The fractional mode is activated when the value loaded into the SDM is different from 0, and the bit PLLxSSCGEN = 0.

The SDM value can be updated at anytime by the application by executing the following sequence:

• – Write PLLxFRACLE bit to '0'
• – Write into FRACN[12:0] the new fractional value,
• – Write PLLxFRACLE to '1'.
  The new FRACN value is loaded into the SDM when PLLxFRACLE bit goes from 0 to 1.
• – Wait at least 5 µs

The sigma delta modulator is designed in order to minimize the jitter impact while allowing very small frequency steps.

When the PLL is used in fractional mode, the DIVN divider must be initialized before enabling the PLL.

This feature can be used either to generate a specific frequency, with a good accuracy from any crystal value, or to perform a fine tuning of the frequency on-the-fly.

The VCO frequency ( \( F_{VCO} \) ) and output frequencies expressions are given by the following table:

Table 61. VCO frequency and output frequency in fractional mode

Refer to section Section 7.7.1: PLL programming procedure for additional information.

Using the PLLs in spread spectrum mode

The spread spectrum mode is activated when the SDM loaded with 0, and the bit PLLxSSCGEN = 1. This feature is available on all PLLs.

The VCOH must be selected when the spread spectrum mode is activated. VCOH is selected by setting PLLxVCOSEL to 0. PLLxVCOSEL are located into the RCC clock configuration register (RCC_CFGR) .

The spread spectrum technique consist of modulating the VCO frequency with a low-frequency signal (in our case a triangular signal), in order to spread the clock energy into a wider frequency band. As a consequence, the amount of emitted EMI peaks is reduced.

The parameters of the spread spectrum modulation are adjusted via the following fields:

• • MODPER[12:0]: used to adjust the modulation frequency
• • INCSTEP[14:0]: used to adjust the modulation depth (or modulation index)
• • SPREADSEL: used to define if the modulation is centered around the VCO frequency (center-spread) or if it is lowered with respect to VCO frequency (down-spread).

The bits MODPER[12:0], INCSTEP[14:0] and SPREADSEL are located into the RCC_PLLxSSCGR registers with x=1, 2 or 3.

Figure 49 shows the signal modulating the nominal frequency ( \( F_N \) ), when SPREADSEL = 0 (center-spread) and SPREADSEL = 1 (down-spread). The nominal frequency is the frequency output by the PLL in integer mode, when no clock spreading is applied.

Setting the SPREADSEL bit to '1' (down-spread) guarantees that the PLL output frequency does not exceed the programmed frequency value when the SSCG is enabled.

Figure 49. Spread-spectrum modulation

MSV54111V1

The peak modulation depth (in percentage) is given by the following formula:

Note that MODPER x INCSTEP must not exceed \( (2^{15}-1) \) .

The modulation frequency ( \( F_{\text{mod}} \) ) is given by:

Note: Refer to the datasheet of the product for the recommended modulation frequency range

In order to use the spread spectrum feature, the user has to do the following:

• • Program the PLL as explained into Section : Using the PLLs in integer mode in order to adjust the nominal frequency ( \( F_N \) ) according to the targeted by the application.
• • Compute the MODPER value according to the wanted modulation frequency ( \( F_{\text{mod}} \) ):

• • Compute the INCSTEP value according to the wanted modulation depth ( \( M_D \) ):

Check that MODPER x INCSTEP does not exceed \( (2^{15}-1) \) .

• • Then DIVP, Q, R, S or T can be adjusted, and the bit PLLxSSCGEN can be set to 1, and the PLL enabled.

The user can check \( F_{MIN} \) , \( F_{MAX} \) and \( F_C \) as follow:

• • If SSCG_MODE = '0' (centered-spread)
  \( F_C \) is given by the formula of the Section : Using the PLLs in integer mode
  \( F_{MIN} = F_C \times (1 - M_D/100) \)
  \( F_{MAX} = F_C \times (1 + M_D/100) \)
• • If SSCG_MODE = '1' (down-spread)
  \( F_{MAX} \) is given by the formula of the Section : Using the PLLs in integer mode
  \( F_{MIN} = F_{MAX} \times (1 - 2 \times M_D/100) \)
  \( F_C = F_{MAX} \times (1 - M_D/100) \)

Figure 50 shows the digital signal generated by Triangular Waveform Generator (TWG block), and the way of MODPER and INCSTEP are changing the triangular waveform.

Figure 50. Triangular waveform generator

Refer to section Section 7.7.1: PLL programming procedure for additional information.

7.5.6 System clock (sys_ck)

System clock selection

After a system reset, the HSI is selected as system clock and all PLLs are switched OFF. When a clock source is used for the system clock, it is not possible for the software to disable the selected source via the xxxON bits.

Of course, the system clock can be stopped by the hardware when the system enters Stop or Standby mode.

When the system is running, the user application can select the system clock ( sys_ck ) among the 4 following sources:

• • HSE
• • HSI
• • CSI
• • pll1_p_ck

This function is controlled by programming the RCC clock configuration register (RCC_CFGR) . A switch from one clock source to another occurs only if the target clock

source is ready (clock stable after startup delay or PLL locked). If a clock source that is not yet ready is selected, the switch occurs when the clock source is ready.

The SWS status bits in the RCC clock configuration register (RCC_CFGR) indicate which clock is currently used as system clock. The other status bits in the RCC_CR register indicate which clock(s) is (are) ready.

System clock generation

Figure 51 shows a simplified view of the clock distribution for the CPU and busses. All the dividers shown in the block diagram can be changed on-the-fly without generating timing violations. This feature is a very simple solution to adapt the busses frequencies to the application needs, thus optimizing the power consumption.

The CPRE divider can be used to adjust the CPU clock. However this also impacts the clock frequency of all bus matrix. CPRE is controlled via RCC_CDCFGR register.

In the same way, BMPRE divider can be used to adjust the clock for the bus matrix (AHB and AXI), but this also impacts the clock frequency of APB busses. BMPRE is controlled via RCC_BMCFGR register.

Most of the prescalers are controlled via RCC_CDCFGR and RCC_SRDCFGR registers.

Figure 51. Core and bus clock generation

1. Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles.

Note that the application must respect the maximum allowed frequencies: F _CPU Max and F _BUS Max . F _BUS represents the maximum allowed frequency for the AHB and AXI busses. Refer to the product datasheet for maximum values.

Note as well that the trace clock ( trace_ck ) is generated from sys_cpu_ck clock, divided by 3. For additional information refer to Section : Clock distribution for Debug and Trace .

7.5.7 Clock protection

The RCC does not allow to disable the system clock ( sys_ck ). Several protections are implemented in order to prevent actions disabling accidentally the system clock.

In addition, protection bits are available in order to prevent accidental disabling of FMC and XSPI block activities.

The protections consist on ignoring the invalid write operations. It is recommended to read back registers having protection to insure that the clock configuration expected by the software is accepted by the RCC.

The table hereafter shows the protections handled by the RCC.

Table 62. Clock protection summary

There is also clock protection mechanism in case of HSE failure, refer to Section : CSS on HSE .

7.5.8 Clock generation in Stop and Standby modes

When the whole system enters Stop mode, all the clocks (system and kernel clocks) are stopped and the following clock sources are disabled as well:

• • CSI, HSI (depending on HSIKERON, and CSIKERON bits)
• • HSE
• • PLL1, PLL2 and PLL3
• • HSI48

The content of the RCC registers is not altered except for PLL1ON, PLL2ON, PLL3ON, HSEON and HSI48ON that are set to 0.

HSION and CSION bits are also affected depending on STOPWUCK and STOPKERWUCK bits (see Table 63 ).

When the CPU requested to go in Stop mode, the RCC first stop all the requested clocks, and inform the PWR that all clocks have been properly stopped. As shown in Figure 52 , three main signals are used to control power transitions:

• • The rcc_pwrds is used to indicate to the PWR that the RCC has stopped all the clocks, and thus the PWR can go to Stop or Standby.
• • The pwr_wkup is used to indicate to the RCC to re-enable the clocks.
• • The exti_wkup is used to indicate to the PWR that an event requests to exit the system from Stop mode.

Figure 52. Key signals controlling low-power modes

graph LR
    WE[Wake-up events] --> EXTI[EXTI]
    EXTI -- exti_wkup --> PWR[PWR]
    PWR -- pwr_wkup --> RCC[RCC]
    RCC -- rcc_pwrds --> PWR
    SYSCK((sys_ck)) --> PWR
    SYSCK --> RCC
  

Exiting Stop mode

When the microcontroller exits system Stop mode via a wake-up event, the application can select which oscillator (HSI and/or CSI) is used to restart. The STOPWUCK bit selects the oscillator used as system clock. The STOPKERWUCK bit selects the oscillator used as kernel clock for peripherals. The STOPKERWUCK bit is useful if after a system Stop, a peripheral needs a kernel clock generated by an oscillator different from the one used for the system clock.

All these bits belong to the RCC clock configuration register (RCC_CFGR) .

Table 63 gives a detailed description of their behavior.

Table 63. STOPWUCK and STOPKERWUCK description

During Stop mode

There are two specific cases where the HSI or CSI can be enabled during system Stop mode:

• • when a dedicated peripheral requests the kernel clock
  The peripheral receives the HSI or CSI according to the kernel clock source selected for this peripheral (via PERxSRC).
• • when the HSIKERON or CSIKERON bits are set the HSI and CSI are kept running during Stop mode but the outputs are gated. The clock is then available immediately when the system exits Stop mode or when a peripheral requests the kernel clock (see Table 64 for details).

HSIKERON and CSIKERON bits belong to RCC register map . Table 64 gives a detailed description of their behavior.

Table 64. HSIKERON and CSIKERON behavior

1. 1. \( t_{su(HSI)} \) and \( t_{su(CSI)} \) are the startup times of the HSI and CSI oscillators (refer to the product datasheet for values of these parameters).

When the microcontroller exists Standby mode, the HSI is selected as system and kernel clock. The RCC registers are reset to their initial values except for the RCC_RSR and RCC_BDCR registers.

Note that the HSI and CSI outputs provide two clock paths (see Figure 40 ):

• • one path for the system clock ( hsi_ck or csi_ck )
• • one path for the peripheral kernel clock ( hsi_ker_ck or csi_ker_ck ).

When a peripheral requests the kernel clock in system Stop mode, only the path providing the hsi_ker_ck or csi_ker_ck is activated.

Caution: The CPU does not get automatically the same clock frequencies when leaving Stop mode: it is up to the application to restore the previous clock settings if needed.

7.5.9 Peripheral clock distribution

Some peripherals are designed to work with two different clock domains that operate asynchronously:

• • a clock domain synchronous with the register and bus interface ( ckg_bus_perx clock)
• • a clock domain generally synchronous with the peripheral (kernel clock)

The benefit of having peripherals supporting these two clock domains is that the user application has more freedom to choose optimized clock frequency for the CPU, bus matrix and for the kernel part of the peripheral.

As a consequence, the user application can change the bus frequency without reprogramming the peripherals. As an example an on-going transfer with UART is not disturbed if its APB clock is changed on-the-fly.

Table 65 shows the clocks the RCC delivers to the peripherals. Note as well that the clock named per_ck, is the output of a mux which allows the application to select:

• • hsi_ker_ck, or
• • csi_ker_ck, or
• • hse_ker_ck

Table 65. Peripheral clock distribution summary

Table 65. Peripheral clock distribution summary

Table 65. Peripheral clock distribution summary

Table 65. Peripheral clock distribution summary

Table 65. Peripheral clock distribution summary

Table 65. Peripheral clock distribution summary

Table 65. Peripheral clock distribution summary

Table 65. Peripheral clock distribution summary

1. F _MAX value depends on the device reference and can be found on the datasheet of the product.

2. 'A' Means that the kernel clock is asynchronous with respect to bus interface clock.

3. 'S' Means that the kernel clock is synchronous with respect to bus interface clock.

4. Reset value

5. The RTC switch is in the VSW voltage domain

Figure 53 to Figure 68 provide a more detailed description of kernel clock distribution. Refer to Section 7.5.12: Peripheral clock gating control for more details.

To reduce the amount of switches, some peripherals share the same kernel clock source. Nevertheless, all peripherals have their dedicated enable signal.

Clock distribution for ADF, SAIs, and SPDIFRX

The audio peripherals generally need specific accurate frequencies, except for SPDIFRX. As shown in Figure 53 and Figure 56, the kernel clock of the SAIs or SPI(I2S)s can be generated by:

• • PLL1 when the amount of active PLLs must be reduced (for SAIs and SPI/I2S1 to 3)
• • APB2 peripheral clock (for SPI/I2S4 and 5)
• • APB4 peripheral clock (for SPI/I2S6)
• • PLL2 or 3 for optimal flexibility in frequency generation
• • HSE, HSI or CSI for use-cases where the current consumption is critical
• • I2S_CKIN when an external clock reference needs to be used

The SPDIFRX does not require a specific kernel clock frequency but only a frequency high enough to sample properly the incoming stream. Refer to the SPDIFRX description for more details.

The SPDIFRX also provides a symbol clock (spdifrx_symb_ck) which is 64 times faster than the received samples. The symbol clock is proposed as kernel clock for SAI2 in order to ease bridging from SPDIFRX to SAI2.

The audio blocks also have common kernel clocks in order to ease data exchange.

The ADF can work even in Stop mode as long as the bus clock is not requested. Working in Stop mode is possible only if the application selected csi_ker_ck or hsi_ker_ck as kernel clock sources. The ADF asserts the adf_ker_ckreq when the kernel clock is requested.

The kernel clock mechanism works only if the kernel clock source is provided by an RC oscillator ( hsi_ker_ck or csi_ker_ck ).

Figure 53. Clock distribution for SAIs, ADF and SPDIFRX

1. 1. X represents the selected mux input after a system reset.

Clock distribution for SPIs, SPI/I2Ss

SPI peripherals do not need an accurate kernel clock frequency but a clock fast enough for the serial interface. The SPI/I2S peripherals may request accurate kernel clock frequency when using the I2S function. For that purpose the source can be selected among the following ones:

• • The bus clock (for SPIs)
• • PLL1 when the amount of active PLLs must be reduced
• • PLL2 or PLL3 if better flexibility is required. As an example, this solution allows changing the frequency bus via PLL1 without affecting the speed of some serial interfaces.
• • HSI or CSI or per_ck for low-power use-cases.

The SPI/I2S also have common kernel clocks with audio blocks in order to ease data exchange.

Figure 54. Clock distribution for SPIs and SPI/I2S

1. 1. X represents the selected switch input after a system reset.

Clock distribution for I2C[3:2], and I2C1/I3C1

I2Cs and I3C1 peripherals do not need an accurate kernel clock frequency but a clock fast enough to handle properly the serial interface. The following kernel clock sources are proposed:

• • The bus clock
• • PLL3 in the case where the bus clock cannot be used
• • HSI or CSI for low-power use-cases

The I2Cs and I3C1 can work even in Stop mode as long as the bus clock is not requested. Working in Stop mode is possible only if the application selected csi_ker_ck or hsi_ker_ck as kernel clock sources. The I2Cs and I3C1 assert the i2c_ker_ckreq or i3c_ker_ckreq signals, when the kernel clock is requested.

The kernel clock mechanism works only if the kernel clock source is provided by an RC oscillator ( hsi_ker_ck or csi_ker_ck ).

Figure 55. Clock distribution for I2C[3:2] and I2C1/I3C1

1. 1. X represents the selected switch input after a system reset

Clock distribution for UARTs and USARTs

UARTs need kernel clock frequency allowing the adjustment of the baud rate with an acceptable accuracy (generally less than \( \pm 2\% \) ). For that purpose the source can be selected among the following ones:

• • The bus clock
• • PLL3 in the case where the bus clock cannot be used
• • HSI, CSI or LSE for low-power use-cases

The UARTs can work even in Stop mode as long as the bus clock is not requested. Working in Stop mode is possible only if the application selected csi_ker_ck or hsi_ker_ck as kernel clock sources. The UARTs assert the uartx_ker_ckreq signal, when the kernel clock is requested. The kernel clock mechanism works only if the kernel clock source is provided by an RC oscillator ( hsi_ker_ck or csi_ker_ck ).

UARTs can also work in Stop mode using the LSE clock when high baud rates are not required.

Figure 56. Clock distribution for UARTs, LPUART1 and USARTs

MSV54118V1

1. 1. X represents the selected switch input after a system reset.

Clock distribution for FDCAN

Figure 57. Clock distribution for FDCAN

• 1. D represents the selected switch input after a system reset.

Clock distribution for graphic blocks (GPU2D, LTDC, DCMIPP and PSSI)

Figure 58. Clock distribution for GPU2D

• 1. X represents the selected switch input after a system reset.

Figure 59. Clock distribution for LTDC and DCMIPP

• 1. X represents the selected switch input after a system reset.

The PSSI receives an AHB clock and a kernel clock (pxclk).

The pxclk can be provided either by an external device via PSSI_PIXCK pad, or by the RCC. Note that the clock generated by the RCC is provided to pxclk input by the feedback path of the PSSI_PIXCK pad. The drive of the PSSI_PIXCK is controlled by the PSSI block.

Figure 60. Clock distribution for PSSI

1. 1. X represents the selected switch input after a system reset.

Clock distribution for SDMMCs, FMC, and XSPIs

The FMC kernel clock can be chosen between 4 different sources, giving good flexibility.

For each XSPI, a clock switch allows the selection between 3 different sources, giving good flexibility. It is possible to enable independently each XSPI block.

The switches FMCSEL, XSPI[2:1]SEL, also embeds several protections:

• • In case of HSE failure detected by the HSECSS function, the XSPI[2:1]SEL switches and the FMCSEL switch go to recovery position in order to provide a default clock.
• • A protection bit: FMCCKP prevents the application to accidentally change the FMCSEL value. Refer to Section 7.5.7: Clock protection for details.
• • A protection bit: XSPICKP prevents the application to accidentally change the XSPI[2:1]SEL values. Refer to Section 7.5.7: Clock protection for details.
• • Status fields (FMCSWP, XSPI[2:1]SWP) located into RCC clock protection register (RCC_CKPROTR) allows the application to check the effective position of the switches.
• • If one of the switch is selecting an input with an invalid clock, the switch outputs a recovery clock preventing a memory crash and allowing the application to log or correct the issue. The RCC provides hclk5/4 as recovery clock. In order to work fine, the

application must ensure that the recovery clock frequency is supported by the external device.

• • For the XSPI[2:1]SEL switches:
  • – Going to position 1 is allowed if PLL2ON = PLL2SEN = 1. If the application switches to position 1 when these conditions are not met, the switch generates the recovery clock.
  • – Going to position 2 is allowed if PLL2ON = PLL2TEN = 1. If the application switches to position 2 when these conditions are not met, the switch generates the recovery clock.
• • For the FMCSEL switch:
  • – Going to position 1 is allowed if PLL1ON = PLL1QEN = 1. If the application switches to position 1 when these conditions are not met, the switch generates the recovery clock.
  • – Going to position 2 is allowed if PLL2ON = PLL2REN = 1. If the application switches to position 2 when these conditions are not met, the switch generates the recovery clock.
  • – Going to position 3 is allowed if HSION = 1. If the application switches to position 3 when this condition is not met, the switch generates the recovery clock.

How to handle properly XSPI switches:

• • Switch on the wanted clock source,
• • Ensure the clock source is ready, and conditions described above are met,
• • Set XSPI1SEL to the wanted position,
• • Enable the XSPI clock (XSPIxEN = 1),
• • Read XSPISWP field from RCC_CKPROTR register,
• • If the position given by XSPISWP is the same as the wanted, it means that the XSPIx kernel clock is as expected.
• • If the position given by XSPISWP is 000, it means that there is no clock present at the selected input.

The XSPIs must provide a clock to the external memory, with a duty cycle distortion generally lower than 5%. In order to reach this requirement, the kernel clock provided to the XSPIs has a typical duty cycle of 50%. In addition, the XSPIs embed prescaler allowing clock division by even ratios.

Figure 61. Clock distribution for FMC, XSPIs, and MCEs

1. 1. X represents the selected switch input after a system reset.

The SDMMC1 and SDMMC2 share the same kernel clock. A clock switch allows the selection between 2 different sources. It is possible to enable independently each SDMMC block. Note that when one of the SDMMC is enabled via its SDMMC[2:1]EN bit, the associated delay block is enabled as well.

The application must take care about the duty-cycle of the kernel clock provided to the SDMMC blocks.

Table 66. SDMMC interface clock constraints

Table 66. SDMMC interface clock constraints

For example, if the SDMMC works in SDR50, then a kernel clock of 50 MHz, with a duty cycle better than 30-70% is enough. If the SDMMC works in DDR50, then it is recommended to provide a kernel clock of 100 MHz, and divide the frequency of the kernel clock by two, using the SDMMC divider in order to insure a duty-cycle very close to 50% for the SDMMC_CK.

Figure 62. Clock distribution for SDMMC[2:1] and DB_SDMMC[2:1]

1. 1. X represents the selected switch input after a system reset.

Clock distribution for OTGFS, OTGHS and UCPD

Figure 63 shows the clock distribution for the USB blocks.

• • The USB type-C power delivery block (UCPD), uses ucpd_ker_ck as kernel clock. The ucpd_ker_ck is directly generated from the HSI output divided by 4.
• • The USBPHYC, embeds a PLL accepting a reference input frequency of 16, 19.2, 20, 24, 26 or 32 MHz. The reference clock can be selected among:
  • – hse_osc_ck
  • – hse_ker_ck/2 or
  • – pll3_q_ck

The USBPHYC provides a 60 MHz clock to the OTGHS block, and a 48 MHz clock to the OTGFS block. The clock hse_osc_ck is the direct output of the HSE oscillator.

• • The OTGHS receives the 60 MHz clock from the USBPHYC ( phy60m_ck ), when working in HS or FS mode.
• • The OTGFS receives a 48 MHz clock. The application can select:
  • – the clk48mohci (from USBPHYC)
  • – the hsi48_ker_ck for crystal-less applications
  • – hse_ker_ck or
  • – pll3_q_ck

The selection of the reference clock for the USBPHYC is performed by a simple MUX. In order to change the clock source, the application must follow the sequence hereafter:

• • Disable the USBPHYC clock by setting USBPHYCEN to 0
• • Change the clock source selector (USBPHYCSEL) to the wanted value
• • Enable the USBPHYC clock by setting USBPHYCEN to 1.

Figure 63. Clock distribution for USB and UCPD

1. 1. X represents the selected switch input after a system reset.

Clock distribution for ETH1

The Ethernet clocks provided by the RCC are available on ETH_CLK pad. The application can select if the ETH_CLK is generated from the HSE kernel clock or from the pll3_s_ck .

The RCC also provides the bus clock and the reference clock for the PTP function.

Note that the bus and PTP clocks generation are controlled via ETH1MACEN and ETH1MACLPEN bits.

Figure 64. Clock distribution for ETH1

1. 1. X represents the selected switch input after a system reset.

The signal ETH_SEL is provided by the SBS block and defines the interface type used:

In MII mode (orange path):

• • The transmit clock is received from the external PHY via the pad ETH_MII_TX_CLK.
• • The receive clock is received from the external PHY via the pad ETH_MII_RX_CLK.
• • The clock frequency is 2.5 MHz for Ethernet at 10 Mbps or 25 MHz for Ethernet at 100 Mbps.

In RMI mode (blue path):

• • The reference clock (50 MHz) can be selected between several sources:
  • – The ETH_RMII_REF_CLK pad, if the reference clock is provided by the PHY
  • – The hse_ker_ck in case the Ethernet PHY is providing a reference clock connected to OSC_IN
  • – The ETH_CLK feedback clock (eth_clk_fb) if the RCC is providing the reference clock to the PHY. This selection is controlled via ETH1REFCKSEL[1:0].
• • The ETH_SEL must be set to 1,
  • – a clock must be provided to clk_rx_i and clk_tx_i inputs
  • – The clock frequency at clk_rx_i and clk_tx_i inputs is 2.5 MHz (division by 20) for Ethernet at 10 Mbps, and 25 MHz (division by 2) for Ethernet at 100 Mbps.
  • – The transmit and receive clock frequency can be adjusted dynamically to 2.5 or 25 MHz according to the signal mac_speed_o[0] provided by the ETH block.

Note that the ETH1REFCKSEL mux position cannot be changed when a clock is provided to the ETH1 block. In order to select the wanted mux position the following sequence must be respected:

• • Set bits ETH1TXEN, ETH1RXEN and ETH1MACEN to 0,
• • Set ETH1REFCKSEL to the wanted position,
• • Set bits ETH1TXEN, ETH1RXEN and ETH1MACEN to 1

The RCC can generate a reference clock of 25 or 50 MHz to the external PHY, via ETH_CLK pad. The figure hereafter shows the possible clock configurations.

The ETH_CLK is generated only if:

• • ETH1TXEN or ETH1RXEN are enabled, and
• • the system is in Run or Sleep, and
• • the clock source selected by ETH1PHYCKSEL is available.

The bits ETH1REFCKSEL[1:0] and ETH1PHYCKSEL are located into the RCC AHB peripheral kernel clock selection register (RCC_CCIPR1) .

Figure 65. ETH clock configuration

The ETH1 block provides information on the MAC speed (mac_speed_o[1:0]), which may change dynamically:

• • mac_speed_o[1:0] = 0b10: for 10 Mbps
• • mac_speed_o[1:0] = 0b11 or 0b0x: for 100 Mbps

Clock distribution for ADC1-2

Figure 66. Clock distribution For ADCs

1. 1. X represents the selected switch input after a system reset.

Clock distribution for SAES and RNG

Figure 67. Clock distribution for SAES and RNG

1. 1. X represents the selected switch input after a system reset.

The RNG block is using the hsi48_ker_ck as kernel clock. The logic handling controlling the clock of the RNG is different from standard peripherals. When enabled, the RNG has to assert its kernel clock request, in order to get a kernel clock. For example, if the SAES needs the RNG resource, the RNG must also be enabled. Refer to Section 7.5.12: Peripheral clock gating control for details.

Clock distribution for HDMI-CEC

Figure 68. Clock distribution for HDMI-CEC

1. 1. X represents the selected switch input after a system reset

Clock distribution for TIM and LPTIM

The TIMs timers are using kernel clocks (tim_ker_ck) phase aligned with the bus interface clock.

The working frequency of the timers clock depends on:

• • The APB prescaler corresponding to the bus where the timer is connected, and
• • The bit TIMPRE

Figure 69. Clock distribution for TIMs

1. 1. X represents the selected switch input after a system reset
2. 2. Can be changed on the fly

The Table 67 shows how to select the timer clock frequency.

Table 67. Ratio between clock timer and pclk

1. 1. PPRE1 and PPRE2 are the prescaler for the APB1 and APB2 clocks.
2. 2. TIMPRE belongs to RCC clock configuration register (RCC_CFGR) .

The LPTIMs timers have a kernel clocks fully asynchronous with respect to their bus interface clock. The kernel clock can be selected among up to 6 clock sources.

The LPTIMs also use lse_ck and lsi_ck as kernel clock, allowing them to work even when the system is in Stop mode.

Figure 70. Clock distribution for LPTIMs

1. X represents the selected switch input after a system reset

Clock distribution for RTC/AWU clock

The rtc_ck clock source can be one of the following:

• • the hse_rtc_ck ( hse_ker_ck divided by a programmable prescaler)
• • the lse_ck
• • the lsi_ck clock

The source clock is selected by programming the RTCSEL[1:0] bits in the RCC Backup domain control register (RCC_BDCR) and the RTCPRE[5:0] bits in the RCC clock configuration register (RCC_CFGR) .

This selection cannot be modified without resetting the Backup domain.

Figure 71. Clock distribution for RTC

1. 1. X represents the selected switch input after a system reset

If the LSE is selected as RTC clock, the RTC works normally even if the backup or the \( V_{DD} \) supply disappears.

The LSE clock is in the Backup domain, whereas the other oscillators are not. As a consequence:

• • If LSE is selected as RTC clock, the RTC continues working even if the \( V_{DD} \) supply is switched OFF, provided the \( V_{BAT} \) supply is maintained.
• • If LSI is selected as the RTC clock, the AWU state is not guaranteed if the \( V_{DD} \) supply is powered off.
• • If the HSE clock is used as RTC clock, the RTC state is not guaranteed if the \( V_{DD} \) supply is powered off or if the \( V_{CORE} \) supply is powered off. In addition the HSE is not available if the system goes to Stop.

The rtc_ck clock is enabled through RTCEN bit located in the RCC Backup domain control register (RCC_BDCR) .

The RTC bus interface clock (APB clock) is enabled through RTCAPBEN and RTCAPBLPEN bits located in RCC_APB4ENR/LPENR registers.

Note: To read the RTC calendar register when the APB clock frequency is less than seven times the RTC clock frequency ( \( F_{APB} < 7 \times F_{RTCLCK} \) ), the software must read the calendar time and date registers twice. The data are correct if the second read access to RTC_TR gives the same result than the first one. Otherwise a third read access must be performed.

Clock distribution for watchdog

The RCC provides the clock for the two watchdog blocks available on the circuit. The independent watchdog (IWDG) is connected to the LSI. The window watchdog (WWDG) is connected to the APB clock.

If an independent watchdog is started by either hardware option or software access, the LSI is forced ON and cannot be disabled. After the LSI oscillator setup delay, the clock is provided to the IWDG.

The window watchdog clock (pclk1) can be enabled by setting the WWDGEN bit in RCC_APB1ENR register. The software cannot stop WWDG down-counting by setting WWDGEN bit to '0'.

The WWDG block is frozen when the MCU goes to Stop mode.

Figure 72. Clock distribution for WWDG and IWDG

1. 1. X represents the selected switch input after a system reset

Clock distribution for Debug and Trace

The clock generation for the trace and debug is controlled by the DBGMCU block. The DBGCKEN bit allows the application to provide a clock to the debug components. It is also possible to enable this clock via the Debug Access Port.

The trace clock generation is controlled via TRACECKEN bit.

Figure 73. Clock distribution for DBG and trace

1. 1. X represents the selected switch input after a system reset

Clock frequency measurement using TIMx

Most of the clock source generator frequencies can be measured by means of the input capture of TIMx.

• • Calibrating the HSI or CSI with the LSE:

The primary purpose of having the LSE connected to a TIMx input capture is to be able to accurately measure the HSI or CSI. This requires to use the HSI or CSI as system clock source either directly or via PLL1. The number of system clock counts between

consecutive edges of the LSE signal gives a measurement of the internal clock period. Taking advantage of the high precision of LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency with the same resolution, and trim the source to compensate for manufacturing-process and/or temperature- and voltage-related frequency deviations.

The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio). The precision is therefore tightly linked to the ratio between the two clock sources. The greater the ratio is, the more accurate the measurement is.

The HSI and CSI oscillators have dedicated user-accessible calibration bits for this purpose (see RCC CSI calibration register (RCC_CSICFGR) ). When HSI or CSI is used via the PLLx, the system clock can also be fine-tuned by using the fractional divider of the PLLs.

• • Calibrating the LSI with the HSI:

The LSI frequency can also be measured: this is useful for applications that do not have a crystal. The ultra-low-power LSI oscillator has a large manufacturing process deviation. The LSI clock frequency can be measured using the more precise HSI clock source. Using this measurement, a more accurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or an IWDG timeout with an acceptable accuracy can be obtained.

7.5.10 General clock concept overview

The RCC handles the distribution of the CPU, bus interface and peripheral clocks for the system, according to the CPU operating mode (refer to Section 7.5.1: Clock naming convention for details on clock definitions).

For each peripheral, the application can control the activation/deactivation of its kernel and bus interface clock. Prior to use a peripheral, the CPU must enable it (by setting PERxEN to 1), and define if this peripheral remains active in Sleep mode (by setting PERxLPEN to 1). This is called 'allocation' of a peripheral by the CPU (refer to Section 7.5.11: Peripheral allocation for more details).

The peripheral allocation is used:

• • by the RCC to automatically control the clock gating according to the CPU modes, and
• • by the PWR to control the supply voltages of VCORE.

Memory handling

The CPU can access all the memory areas available in the product:

• • AXISRAM1, AXISRAM2, AXISRAM3, AXISRAM4, ITCM, DTCM1, DTCM2 and FLASH
• • AHBSRAM1 and AHBSRAM2
• • BKPRAM

The BKPRAM, AHBSRAM1 and AHBSRAM2 have dedicated enable bits in order to gate the bus interface clock. The CPU needs to enable them prior to use these memories.

Note: The memory interface clocks (Flash memory and RAM interfaces) can be stopped by software during Sleep mode (via SRAMyLPEN bits).

Refer to Section 7.5.12: Peripheral clock gating control and Section 7.5.13: CPU and bus matrix clock gating control sections for details on clock enabling.

7.5.11 Peripheral allocation

The CPU can allocate a peripheral and hence control its kernel and bus interface clock.

The CPU can allocate a peripheral by setting the dedicated PERxEN bit to 1.

The CPU can control the peripheral clocks gating when it is in Sleep mode via the PERxLPEN bits.

Refer to for additional information.

The peripheral allocation bits (PERxEN bits) are used by the hardware to provide the kernel and bus interface clocks to the peripherals. However they are also used to link peripherals to the CPU. In this way, the hardware is able to safely gate the peripheral clocks and bus matrix clocks according to CPU states.

Clock switches and gating

• • Clock switching delays

The input selected by the clock switches can be changed dynamically without generating spurs or timing violation. For example, if PERxSEL (In Figure 74 ) goes from 0 to 1, the switch first disables the clock output using the currently selected clock (in0_ck), and enables again the clock output using the new selected clock (in1_ck). The disable and enable commands are re-synchronized to their respective clocks. If one of the the two clocks are not present, the sequence cannot be completed, and no clock is output. To recover from this situation, the user must either provide a valid clock to in1_ck input or set back PERxSEL to 0.

During the transition from one input to another, the kernel clock provided to the peripheral is gated, in the worst case, during 2 or 3 clock cycles of the new selected clock. As shown in Figure 74 , both input clocks must be present during transition time.

Figure 74. Kernel clock switching

• • Clock enabling delays

In the same way, the clock gating logic synchronizes the enable command (coming generally from a kernel clock request or PERxEN bits) with the selected clock, in order to avoid generation of spurs.

• – A maximum delay of two periods of the enabled clock may occur between the enable command and the first rising edge of the clock. The enable command can

be the rising edge of the PERxEN bits of RCC_xxxxENR registers, or a kernel clock request asserted by a peripheral.

• – A maximum delay of 1.5 periods of the disabled clock may occur between the disable command and the last falling edge of the clock. The disable command can be the falling edge of the PERxEN bits of RCC_xxxxENR registers, or a kernel clock request released by a peripheral.

Note: Both the kernel and bus interface clocks are affected by this re-synchronization delay.

7.5.12 Peripheral clock gating control

As mentioned previously, each peripheral requires one or several bus interface clock, named rcc_perx_bus_ck (for peripheral 'x'). These clocks can be an APB, AHB or AXI clock, according to which bus or busses, the peripheral is connected.

The clocks used as bus interface for peripherals, can be aclk , hclk[5:1] , pclk[5:4] , or pclk[2:1] , depending on the bus connected to each peripheral.

Some peripherals also require dedicated clocks for their communication interface. These clocks are generally asynchronous with respect to the bus interface clock. They are named kernel clocks ( perx_ker_ck ). Both bus interface and kernel clocks can be gated according to several conditions detailed hereafter.

As shown in Figure 75 , enabling the kernel and bus interface clocks of each peripheral depends on several input signals:

• • PERxEN and PERxLPEN bits,
  PERxEN represents the peripheral enable (allocation) bit for the CPU. The CPU can write these bits to 1 via the RCC_xxxxENR registers.
• • CPU state ( cpu_sleep and cpu_deepsleep signals)
• • Kernel clock request ( perx_ker_ckreq ) of the peripheral itself, when the feature is available

Refer to Section 7.5.11: Peripheral allocation for more details.

Figure 75. Peripheral kernel clock enable logic details

Table 68 gives a detailed description of the enabling logic of the peripheral clocks for peripherals located in the CPU domain and allocated by the CPU.

Table 68. Peripheral clock enabling

As a summary, we can state that the kernel clock is provided to the peripherals when the following conditions are met:

1. 1. The CPU is in Run mode, and the peripheral is enabled.
2. 2. The CPU is in Sleep mode and the peripheral is enabled with PERxLPEN = 1.
3. 3. The CPU is in Stop mode, the peripheral is enabled with PERxLPEN = 1, the peripheral generates a kernel clock request and the selected clock is hsi_ker_ck or csi_ker_ck .
4. 4. The CPU is in Stop mode, the peripheral is enabled with PERxLPEN = 1 and the kernel source clock of the peripheral is lse_ck or lsi_ck .

The bus interface clock is provided to the peripherals only when conditions 1 or 2 are met.

The RNG block is not clocked as other peripherals, the table hereafter shows the way RNG is clocked.

Table 69. RNG clock enabling

7.5.13 CPU and bus matrix clock gating control

The clocks of the CPU, AHB and AXI bridges and APB busses are enabled according to the rules hereafter:

• • The CPU clock ( rcc_cpu_ck ) is enabled when the CPU is in Run or Sleep mode.
• • The AXI bridge clock is enabled when the CPU is in Run or Sleep mode.
• • Each AXI master and slave has an independent clock gating activated by default, to further reduce the power consumption. When activated the clock is automatically enabled on bus transaction request. The RCC AXI clocks gating disable register (RCC_CKGDISR) allows the application to control this behavior.
• • The AHB bus matrix clock is enabled if one of the following conditions is met:
  • – The CPU is in Run mode
  • – The CPU is in Sleep mode, and at least one peripheral connected to this bridge have both its PERxEN and PERxLPEN set to 1.
  • – The CPU is in Sleep mode, and AHB1, AHB2, AHB3, AHB4 or AHB5 has its clock enabled
• • The clocks of the bridges AHB1, 2, 3, 4, 5 are enabled when one of the following conditions is met:
  • – The CPU is in Run mode.
  • – The CPU is in Sleep mode with at least one peripheral connected to this bus having both its PERxEN and PERxLPEN set to 1.
  • – The CPU is in Sleep mode and the APB bus connected to the AHB bridge has its clock enabled.
• • The APB1, 2, 4, 5 clock busses are enabled when one of the following conditions is met:
  • – The CPU is in Run mode.
  • – When the CPU is in Sleep mode with at least one peripheral connected to this bus having both its PERxEN and PERxLPEN set to 1.

7.5.14 Low-power emulation modes

In order to ease the debugging of the circuit, the RCC is able to handle an emulation mode for Stop and Standby modes.

Sleep emulation mode

The Sleep emulation mode is controlled by the DBG_SLEEP bit of the DBGMCU_CR register. When the processor goes to Sleep with DBG_SLEEP = 1, then the processor clock, the clocks of all enabled peripherals, debug parts, and interconnect are maintained activated.

Stop emulation mode

The Stop emulation mode is controlled by the DBG_STOP bit of DBGMCU_CR register. When the processor goes to Stop with DBG_STOP = 1, then:

• • The PWR and the RCC remains activated.
• • The VDDCORE voltage is set to the minimum VOS value.
• • The RCC selects HSI or CSI as system clock, depending on STOPWUCK bit.
• • The processor clock is gated (rcc_cpu_ck, see Figure 51 ),
• • The free-running clock is generated (rcc_fclk, see Figure 51 ), and all the debug parts remain clocked.
• • All peripheral clocks are gated. Peripherals can still receive a kernel clock if they request it, and if the kernel clock source is an RC oscillator. They also receive the kernel clock if the kernel clock source is LSI or LSE.
• • The interconnect clocks are gated.

When a wake-up event occurs:

• • The VDDCORE voltage remains to the minimum VOS value.
• • The peripheral waking up the system sends the interrupt to the NVIC via the EXTI.
• • The CPU exits from STOP and the RCC provide the processor clock and interconnect clocks.

Standby emulation mode

The Standby emulation mode is controlled by the DBG_STANDBY bit of the DBGMCU_CR register.

When the system goes to Standby with DBG_STANDBY = '1', then:

• • The VDDCORE voltage is not switched-off, but remains to the minimum VOS value.
• • All the VDDCORE domain is under reset except the debug part.
• • The debug part is clocked.
• • Peripherals on VBat or VDD domains are not reset.

When the system exits from Standby, then:

• • Option bytes are reloaded.
• • The reset of the VDDCORE domain is released.
• • The Standby flag is updated as well.

7.6 RCC interrupts

The RCC provides three interrupt lines:

• • rcc_it : general interrupt line providing events when the PLLs are ready or when the oscillators are ready
• • rcc_hsecss_it : interrupt line dedicated to the failure detection of the HSE CSS (clock security system)
• • rcc_lsecss_it : interrupt line dedicated to the failure detection of the LSE CSS

The interrupt enable is controlled via RCC clock source interrupt enable register (RCC_CIER) , except for the HSE CSS failure. When the HSE CSS feature is enabled, it is not possible to mask the interrupt generation.

The interrupt flags can be checked via RCC clock source interrupt flag register (RCC_CIFR) , and these flags can be cleared via RCC clock source interrupt clear register (RCC_CICR) .

Note: The interrupt flags are not relevant if the corresponding interrupt enable bit is not set.

Table 70 gives a summary of the interrupt sources and the way to control them.

Table 70. Interrupt sources and control

1. The security system feature must also be enabled (LSECSSON = 1), in order to generate interrupts.

2. It is not possible to mask this interrupt when the security system feature is enabled (HSECSSON = 1).

7.7 RCC Programming examples

7.7.1 PLL programming procedure

PLL initialization procedure

The recommended initialization sequence of the PLLs for the integer and fractional mode is given hereafter:

• • The PLL is supposed to be disabled: PLLxPEN, PLLxQEN, PLLxREN, PLLxSEN, PLLxTEN, PLLxON, and PLLxRDY set to '0', if it is not the case, refer to PLL disabling procedure .
• • Enable the wanted clock source (HSE, HSI, or CSI) and wait for the ready flag.
• • Select the clock source via PLLSCR into RCC PLLs clock source selection register (RCC_PLLCKSELR) .
• • Initialize the pre-dividers (DIVMx) in order to provide to the PLL, a valid reference clock. DIVMx are located into RCC PLLs clock source selection register (RCC_PLLCKSELR) .
• • Configure the PLL:
  • – In integer or clock spreading mode the application must ensure that a 0 is loaded into the SDM. This can be done as follows:
    • - Set PLLxFRACLE to 0
    • - Write FRACN to 0
    • - Set PLLxFRACLE to 1
    • - Write FRACN to 0
    • - Wait at least 5 µs
  • – In fractional mode, the application must load the SDM with the wanted value (FracInitValue) by executing a sequence similar to the integer mode, but with FRACN = FracInitValue.
  • – Program the fields PLLxRGE, PLLxVCOSEL, SSCG_CTRL, DIVxN, DIVxP, DIVxQ, DIVxR, DIV2S and DIV2T.
  • – If the clock spreading mode is used, program also the fields MODPER, INCSTEP, SPREADSEL, TPDFNDIS, RPDFNDIS, and set PLLxSSCGEN to 1.
  • – If the clock spreading mode is not used, set PLLxSSCGEN to 0.
• • Enable the PLL:
  • – Set the corresponding PLLxON bit to 1, and wait for PLLxRDY bit set to 1,
  • – If the PLL is in fractional mode, the FRACLE bit must not be set back to 0 as long as PLLxRDY = 0.
• • When the PLLxRDY bit is equal to 1, the application can enable the wanted outputs by setting PLLxPEN, PLLxQEN, PLLxREN, PLLxSEN, PLLxTEN to 1.
• • If the application intends to tune the PLL frequency on-the-fly (only possible in fractional mode), then:
  • – Set PLLxFRACLE to '0',
    When FRACLE = '0', the sigma delta modulator is still operating with the current value,
  • – Write the new value into FRACN[12:0] (FracValue(n)),
  • – Set PLLxFRACLE to 1, in order to latch the content of FRACN[12:0] into the SDM.

• – Wait at least 5 µs.

Note: When the PLLxRDY goes to 1, it means that the PLLx output frequency is within 2% of its target value.

Reprogramming post-dividers

When the PLLs are enabled, it is possible to change the values of a post-dividers (DIVP, DIVQ, DIVR, DIVS or DIVT) without disabling the corresponding PLLx, by performing the following sequence:

• • Disable the wanted output by setting the bit PLLxPEN, PLLxQEN, PLLxREN, PLLxSEN or PLLxTEN to 0,
• • Change the value of the corresponding post-divider (DIVP, DIVQ, DIVR, DIVS or DIVT),
• • Re-enable this output by setting the bit PLLxPEN, PLLxQEN, PLLxREN, PLLxSEN or PLLxTEN to 1.

PLL disabling procedure

The recommended disabling sequence is given hereafter:

• • Disable all the post-dividers by setting PLLxPEN, PLLxQEN, PLLxREN, PLLxSEN and PLLxTEN bits of PLLx to 0,
• • Disable the PLL: set PLLxON bit of PLLx to 0,
• • Wait for PLLxRDY = 0.

Using the SSCG block

For example, if an application needs to generate with the PLL2, a clock signal having the following characteristics:

• • A frequency at DIVS output ( Fpll2_s_ck ) of 200 MHz Max,
• • With a modulation depth of 0.5% peak ( \( M_D \) ),
• • With a frequency modulation of 28 kHz ( \( F_{MOD} \) ).

The assumption is that the crystal oscillator is 8 MHz ( \( F_{hse\_ck} \) ).

DIVM2 is programmed to 0 in order to provide a reference clock of 8 MHz to the PLL2 ( \( F_{ref2\_ck} \) ). The VCOH must be selected when SSCG is used.

From a 8 MHz reference clock, it is possible to generate 200 MHz, by programming the PLL2 as follow: \( (DIVN+1) = 50 \) , \( (F_{vco} = 800 \text{ MHz}) \) , \( (DIVS+1) = 4 \) .

The application has to compute the following parameters:

Computing MODPER:

Computing INCSTEP:

Check that MODPER x INCSTEP is lower than \( (2^{15}-1) \)

In the example, MODPER x INCSTEP = 1633 \( \Rightarrow \) OK

Due to rounding operations, the modulation period and the modulation depth does not completely match the target. The real modulation depth is:

And the modulation frequency (Fmod) is:

The down-spread modulation must be used (SPREADSEL = 1) to keep the maximum frequency to a value lower than 200 MHz.

7.7.2 Frequency configuration examples

This section gives various frequency settings for CPU and XSPI interfaces, combined with audio constraints. The case without audio constraints is not shown as it is obvious that PLL1 and PLL2 can provide the expected frequency. If audio applications are required, several options are offered to the user:

• • Generate the kernel clock with PLL1, PLL2 or PLL3
• • Use the external audio clock input (I2S_CKIN)
• • Use oscillators

In this section, we explore the cases where PLL1 or PLL2 are used for audio.

Note as well that PLL2 is also used for XSPIs, if it is shared for audio application, it is not recommended to activate the SSCG.

The configurations listed in the tables hereafter are not exhaustive, many other setting are available. For example if the clock provided to the SAI must be shared with FDCAN, then the application would like to generate a clock around 100 MHz to insure good working conditions for FDCAN. These considerations are not taken into account in these tables.

Note also that in order to get the best clock quality at PLL output, \( F_{\text{REF}} \) must be as close as possible to 16 MHz. This is not always easy to do for PLLs in integer mode, but can be done easily when the PLLs are in fractional mode (as shown in the tables).

Table 71. Clock configuration examples with PLLs in integer mode

1. F _REF is the reference frequency at PLL1 or PLL2 inputs

2. F _VCO is the clock frequency at VCO output of PLL1 or PLL2

3. F _CPU is the clock frequency provided to the CPU (rcc_cpu_ck)

4. F _XSPI is the kernel clock frequency provided to the XSPI1 or XSPI2 (xspi_ker_ck)

5. F _AUDIO is the kernel clock frequency provided to the audio blocks SAIX, SPI/I2Sx, ...
For a 48 kHz stream, the expected kernel clock is 48 kHz x 256 x k, with k integer
For a 44.1 kHz stream, the expected kernel clock is 44.1 kHz x 256 x k, with k integer

1. Note that for all these configurations, PLLxRGE is always equal to 3.

2. F _REF is the reference frequency at PLL1 or PLL2 inputs.

3. F _VCO is the clock frequency at VCO output of PLL1 or PLL2

4. F _CPU is the clock frequency provided to the CPU (rcc_cpu_ck)

5. F _XSPI is the kernel clock frequency provided to the XSPI1 or XSPI2 (xspi_ker_ck)

6. F _AUDIO is the kernel clock frequency provided to the audio blocks SAIX, SPI/I2Sx,....
For a 48 kHz stream, the expected kernel clock is 48 kHz x 256 x k, with k integer
For a 44.1 kHz stream, the expected kernel clock is 44.1 kHz x 256 x k, with k integer

7.8 RCC registers

7.8.1 RCC source control register (RCC_CR)

Address offset: 0x000

Reset value: 0x0000 0025

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 PLL3RDY : PLL3 clock ready flag

Set by hardware to indicate that the PLL3 is locked.

0: PLL3 unlocked (default after reset)

1: PLL3 locked

Bit 28 PLL3ON : PLL3 enable

Set and cleared by software to enable PLL3.

Cleared by hardware when entering Stop or Standby mode.

0: PLL3 OFF (default after reset)

1: PLL3 ON

Bit 27 PLL2RDY : PLL2 clock ready flag

Set by hardware to indicate that the PLL2 is locked.

0: PLL2 unlocked (default after reset)

1: PLL2 locked

Bit 26 PLL2ON : PLL2 enable

Set and cleared by software to enable PLL2.

Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if FMCCCKP = 1, or XSPICKP = 1.

0: PLL2 OFF (default after reset)

1: PLL2 ON

Bit 25 PLL1RDY : PLL1 clock ready flag

Set by hardware to indicate that the PLL1 is locked.

0: PLL1 unlocked (default after reset)

1: PLL1 locked

Set and cleared by software to enable PLL1.

Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3) or if FMCCCKP = 1, or if XSPICKP = 1.

0: PLL1 OFF (default after reset)

1: PLL1 ON

Bits 23:21 Reserved, must be kept at reset value.

Set by software to enable clock security system on HSE.

This bit is “set only” (disabled by a system reset or when the system enters in Standby mode).

When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected.

0: CSS on HSE OFF (clock detector OFF) (default after reset)

1: CSS on HSE ON (clock detector ON if the HSE oscillator is stable, OFF if not).

Set and reset by software to select the external clock type (analog or digital).

The external clock must be enabled with the HSEON bit to be used by the device.

The HSEEXT bit can be written only if the HSE oscillator is disabled.

0: HSE in analog mode (default after reset)

1: HSE in digital mode

Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device.

The HSEBYP bit can be written only if the HSE oscillator is disabled.

0: HSE oscillator not bypassed (default after reset)

1: HSE oscillator bypassed with an external clock

Set by hardware to indicate that the HSE oscillator is stable.

0: HSE clock is not ready (default after reset)

1: HSE clock is ready

Set and cleared by software.

Cleared by hardware to stop the HSE when entering Stop or Standby mode.

This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCCKP = 1, or if XSPICKP = 1.

0: HSE is OFF (default after reset)

1: HSE is ON

Bits 15:14 Reserved, must be kept at reset value.

Set by hardware to indicate that the HSI48 oscillator is stable.

0: HSI48 clock is not ready (default after reset)

1: HSI48 clock is ready

Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode.

0: HSI48 is OFF (default after reset)

1: HSI48 is ON

Bits 11:10 Reserved, must be kept at reset value.

Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION.

0: no effect on CSI (default after reset)

1: CSI is forced to ON even in Stop mode

Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request).

0: CSI clock is not ready (default after reset)

1: CSI clock is ready

Set and reset by software to enable/disable CSI clock for system and/or peripheral.

Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.

This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCCKP = 1, or if XSPICKP = 1.

0: CSI is OFF (default after reset)

1: CSI is ON

Bit 6 Reserved, must be kept at reset value.

Set and reset by hardware.

As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV.

0: new division ratio not yet propagated to hsi(_ker)_ck (default after reset)

1: hsi(_ker)_ck clock frequency reflects the new HSIDIV value (default register value when the clock setting is completed)

Set and reset by software.

These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored.

00: division by 1, hsi(_ker)_ck = 64 MHz (default after reset)

01: division by 2, hsi(_ker)_ck = 32 MHz

10: division by 4, hsi(_ker)_ck = 16 MHz

11: division by 8, hsi(_ker)_ck = 8 MHz

Set by hardware to indicate that the HSI oscillator is stable.

0: HSI clock is not ready (default after reset)

1: HSI clock is ready

Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION.

0: no effect on HSI (default after reset)

1: HSI is forced to ON even in Stop mode

Set and cleared by software.

Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 0 or STOPKERWUCK = 0.

Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source.

This bit cannot be cleared if the HSI is used directly (via SW switch) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCCKP = 1, or if XSPICKP = 1.

0: HSI is OFF

1: HSI is ON (default after reset)

7.8.2 RCC clock protection register (RCC_CKPROTR)

Address offset: 0x100

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:12 FMCSWP[2:0] : FMC kernel clock switch position

Set by hardware.

This field can be used to verify the real position of FMC kernel switch selector.

000: The switch is in neutral mode and output clock is gated (default after reset)

001: The switch is selecting hclk5

010: The switch is selecting pll1_q_ck

011: The switch is selecting pll2_r_ck

100: The switch is selecting hsi_ker_ck

101: The switch is in recovery position (hclk5/4)

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 XSPI2SWP[2:0] : XSPI2 kernel clock switch position

Set by hardware.

This field can be used to verify the real position of XSPI2 kernel switch selector.

000: The switch is in neutral mode and output clock is gated (default after reset)

001: The switch is selecting hclk5

010: The switch is selecting pll2_s_ck

011: The switch is selecting pll2_t_ck

100: The switch is in recovery position (hclk5/4)

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 XSPI1SWP[2:0] : XSPI1 kernel clock switch position

Set by hardware.

This field can be used to verify the real position of XSPI1 kernel switch selector.

000: The switch is in neutral mode and output clock is gated (default after reset)

001: The switch is selecting hclk5

010: The switch is selecting pll2_s_ck

011: The switch is selecting pll2_t_ck

100: The switch is in recovery position (hclk5/4)

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 FMCCPK : FMC clock protection

Set and cleared by software.

When set to 1, this bit prevents disabling accidentally the FMC. The following fields cannot be modified when this bit is set to 1:

PLL1ON, PLL2ON, PLL1QEN, PLL2REN, HSEON, HSION, CSION, FMCEN, FMCLPEN, FMCRST.

0: Clock protection is disabled (default after reset)

1: Clock protection is enabled

Bit 0 XSPICKP : XSPI clock protection

Set and cleared by software.

When set to 1, this bit prevents disabling accidentally the XSPIs. The following fields cannot be modified when this bit is set to 1:

PLL2ON, PLL2SEN, PLL2TEN, HSEON, HSION, CSION, XSPIxEN, XSPIxLPEN, XSPIxRST.

0: Clock protection is disabled (default after reset)

1: Clock protection is enabled

7.8.3 RCC HSI calibration register (RCC_HSICFGR)

Address offset: 0x004

Reset value: 0x4000 0XXX

Reset value depends on the flash option bytes setting.

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 HSITRIM[6:0] : HSI clock trimming

Set by software to adjust calibration.

HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_opt) in order to form the calibration trimming value.

HSICAL = HSITRIM + FLASH_HSI_opt.

Note: The reset value of the field is 0x40.

Bits 23:12 Reserved, must be kept at reset value.

Bits 11:0 HSICAL[11:0] : HSI clock calibration

Set by hardware by option byte loading.

Adjusted by software through trimming bits HSITRIM.

This field represents the sum of engineering option byte calibration value and HSITRIM bits value.

7.8.4 RCC clock recovery RC register (RCC_CRRCR)

Address offset: 0x008

Reset value: 0x0000 0XXX

Reset value depends on the flash option bytes setting.

Bits 31:10 Reserved, must be kept at reset value.

Bits 9:0 HSI48CAL[9:0] : Internal RC 48 MHz clock calibration

Set by hardware by option byte loading.

Read-only.

7.8.5 RCC CSI calibration register (RCC_CSICFGR)

Address offset: 0x00C

Reset value: 0x2000 0XXX

Reset value depends on the flash option bytes setting.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:24 CSITRIM[5:0] : CSI clock trimming

Set by software to adjust calibration.

CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_opt) in order to form the calibration trimming value.

CSICAL = CSITRIM + FLASH_CSI_opt.

Note: The reset value of the field is 0x20.

Bits 23:8 Reserved, must be kept at reset value.

Bits 7:0 CSICAL[7:0] : CSI clock calibration

Set by hardware by option byte loading.

Adjusted by software through trimming bits CSITRIM.

This field represents the sum of engineering option byte calibration value and CSITRIM bits value.

7.8.6 RCC clock configuration register (RCC_CFGR)

Address offset: 0x010

Reset value: 0x0000 0000

Bits 31:29 MCO2SEL[2:0]: microcontroller clock output 2

Set and cleared by software. Clock source selection may generate glitches on MCO2.

It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.

000: system clock selected ( sys_ck ) (default after reset)

001: PLL2 oscillator clock selected ( pll2_p_ck )

010: HSE clock selected ( hse_ck )

011: PLL1 clock selected ( pll1_p_ck )

100: CSI clock selected ( csi_ck )

101: LSI clock selected ( lsi_ck )

others: reserved

Bits 28:25 MCO2PRE[3:0]: MCO2 prescaler

Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.

0000: prescaler disabled (default after reset)

0001: division by 1 (bypass)

0010: division by 2

0011: division by 3

0100: division by 4

...

1111: division by 15

Bits 24:22 MCO1SEL[2:0]: Microcontroller clock output 1

Set and cleared by software. Clock source selection may generate glitches on MCO1.

It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.

000: HSI clock selected ( hsi_ck ) (default after reset)

001: LSE oscillator clock selected ( lse_ck )

010: HSE clock selected ( hse_ck )

011: PLL1 clock selected ( pll1_q_ck )

100: HSI48 clock selected ( hsi48_ck )

others: reserved

Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.

0000: prescaler disabled (default after reset)

0001: division by 1 (bypass)

0010: division by 2

0011: division by 3

0100: division by 4

...

1111: division by 15

Bits 17:16 Reserved, must be kept at reset value.

This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains.

0: The timers kernel clock is equal to rcc_hclk1 if CDPPREx is corresponding to division by 1 or 2, else it is equal to \( 2 \times F_{\text{rcc\_pclkx\_d2}} \) (default after reset)

1: The timers kernel clock is equal to rcc_hclk1 if CDPPREx is corresponding to division by 1, 2 or 4, else it is equal to \( 4 \times F_{\text{rcc\_pclkx\_d2}} \)

Refer to Table 67: Ratio between clock timer and pclk for more details.

Bit 14 Reserved, must be kept at reset value.

Set and cleared by software to divide the HSE to generate a clock for RTC.

Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source.

000000: no clock (default after reset)

000001: no clock

000010: HSE/2

000011: HSE/3

000100: HSE/4

...

111110: HSE/62

111111: HSE/63

Set and reset by software to select the kernel wake-up clock from system Stop.

0: HSI selected as wake up clock from system Stop (default after reset)

1: CSI selected as wake up clock from system Stop

See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details.

Bit 6 STOPWUCK : system clock selection after a wake up from system Stop

Set and reset by software to select the system wake-up clock from system Stop.

The selected clock is also used as emergency clock for the clock security system (CSS) on HSE.

0: HSI selected as wake up clock from system Stop (default after reset)

1: CSI selected as wake up clock from system Stop

See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details.

Caution: STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10).

Bits 5:3 SWS[2:0] : system clock switch status

Set and reset by hardware to indicate which clock source is used as system clock.

000: HSI used as system clock ( hsi_ck ) (default after reset)

001: CSI used as system clock ( csi_ck )

010: HSE used as system clock ( hse_ck )

011: PLL1 used as system clock ( pll1_p_ck )

others: reserved

Bits 2:0 SW[2:0] : system clock switch

Set and reset by software to select system clock source ( sys_ck ).

Set by hardware in order to force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode or in case of failure of the HSE when used directly or indirectly as system clock.

000: HSI selected as system clock ( hsi_ck ) (default after reset)

001: CSI selected as system clock ( csi_ck )

010: HSE selected as system clock ( hse_ck )

011: PLL1 selected as system clock ( pll1_p_ck )

others: reserved

7.8.7 RCC CPU domain clock configuration register (RCC_CDCFGR)

Address offset: 0x018

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 CPRE[3:0] : CPU domain core prescaler

• Set and reset by software to control the CPU clock division factor.
• Changing this division ratio has an impact on the frequency of the CPU clock and all bus matrix clocks.
• After changing this prescaler value, it takes up to 16 periods of the slowest APB clock before the new division ratio is taken into account. The application can check if the new division factor is taken into account by reading back this register.
• 0xxx: sys_ck not divided (default after reset)
• 1000: sys_ck divided by 2
• 1001: sys_ck divided by 4
• 1010: sys_ck divided by 8
• 1011: sys_ck divided by 16
• 1100: sys_ck divided by 64
• 1101: sys_ck divided by 128
• 1110: sys_ck divided by 256
• 1111: sys_ck divided by 512

Caution: Care must be taken when using the voltage scaling. Due to the propagation delay of the new division factor, after a prescaler factor change and before lowering the \( V_{CORE} \) voltage, this register must be read in order to check that the new prescaler value has been taken into account.

Depending on the clock source frequency and the voltage range, the software application must program a correct value in BMPRE to make sure that the system frequency does not exceed the maximum frequency.

7.8.8 RCC AHB clock configuration register (RCC_BMCFGGR)

Address offset: 0x01C

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 BMPRE[3:0] : Bus matrix clock prescaler

Set and reset by software to control the division factor of rcc_hclk[5:1] and rcc_aclk . This group of clocks is also named sys_bus_ck . Changing this division ratio has an impact on the frequency of all bus matrix clocks.

0xxx: sys_bus_ck = sys_cpu_ck (default after reset)

1000: sys_bus_ck = sys_cpu_ck / 2

1001: sys_bus_ck = sys_cpu_ck / 4

1010: sys_bus_ck = sys_cpu_ck / 8

1011: sys_bus_ck = sys_cpu_ck / 16

1100: sys_bus_ck = sys_cpu_ck / 64

1101: sys_bus_ck = sys_cpu_ck / 128

1110: sys_bus_ck = sys_cpu_ck / 256

1111: sys_bus_ck = sys_cpu_ck / 512

Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update.

Note: Note also that frequency of rcc_hclk[5:1] = rcc_aclk = sys_bus_ck .

7.8.9 RCC APB clocks configuration register (RCC_APBFCGR)

Address offset: 0x020

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:12 PPRE5[2:0] : CPU domain APB5 prescaler

Set and reset by software to control the division factor of rcc_pclk5 .

The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE5 write.

0xx: rcc_pclk5 = sys_bus_ck (default after reset)

100: rcc_pclk5 = sys_bus_ck / 2

101: rcc_pclk5 = sys_bus_ck / 4

110: rcc_pclk5 = sys_bus_ck / 8

111: rcc_pclk5 = sys_bus_ck / 16

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 PPRE4[2:0] : CPU domain APB4 prescaler

Set and reset by software to control the division factor of rcc_pclk4 .

The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE4 write.

0xx: rcc_pclk4 = sys_bus_ck (default after reset)

100: rcc_pclk4 = sys_bus_ck / 2

101: rcc_pclk4 = sys_bus_ck / 4

110: rcc_pclk4 = sys_bus_ck / 8

111: rcc_pclk4 = sys_bus_ck / 16

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 PPRE2[2:0] : CPU domain APB2 prescaler

Set and reset by software to control the division factor of rcc_pclk2 .

The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE2 write.

0xx: rcc_pclk2 = sys_bus_ck (default after reset)

100: rcc_pclk2 = sys_bus_ck / 2

101: rcc_pclk2 = sys_bus_ck / 4

110: rcc_pclk2 = sys_bus_ck / 8

111: rcc_pclk2 = sys_bus_ck / 16

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 PPRE1[2:0] : CPU domain APB1 prescaler

Set and reset by software to control the division factor of rcc_pclk1 .

The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE1 write.

0xx: rcc_pclk1 = sys_bus_ck (default after reset)

100: rcc_pclk1 = sys_bus_ck / 2

101: rcc_pclk1 = sys_bus_ck / 4

110: rcc_pclk1 = sys_bus_ck / 8

111: rcc_pclk1 = sys_bus_ck / 16

7.8.10 RCC PLLs clock source selection register (RCC_PLLCKSELR)

Address offset: 0x028

Reset value: 0x0202 0200

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:20 DIVM3[5:0] : prescaler for PLL3

Set and cleared by software to configure the prescaler of the PLL3.

The hardware does not allow any modification of this prescaler when PLL3 is enabled (PLL3ON = 1).

In order to save power when PLL3 is not used, the value of DIVM3 must be set to 0.

000000: prescaler disabled

000001: division by 1 (bypass)

000010: division by 2

000011: division by 3

...

100000: division by 32 (default after reset)

...

111111: division by 63

Bits 19:18 Reserved, must be kept at reset value.

Bits 17:12 DIVM2[5:0] : prescaler for PLL2

Set and cleared by software to configure the prescaler of the PLL2.

The hardware does not allow any modification of this prescaler when PLL2 is enabled (PLL2ON = 1).

In order to save power when PLL2 is not used, the value of DIVM2 must be set to 0.

000000: prescaler disabled

000001: division by 1 (bypass)

000010: division by 2

000011: division by 3

...

100000: division by 32 (default after reset)

...

111111: division by 63

Bits 11:10 Reserved, must be kept at reset value.

Set and cleared by software to configure the prescaler of the PLL1.
The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1).
In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0.

• 000000: prescaler disabled
• 000001: division by 1 (bypass)
• 000010: division by 2
• 000011: division by 3
• ...
• 100000: division by 32 (default after reset)
• ...
• 111111: division by 63

Bits 3:2 Reserved, must be kept at reset value.

Set and reset by software to select the PLL clock source.
These bits can be written only when all PLLs are disabled.
In order to save power, when no PLL is used, PLLSRC must be set to '11'.

• 00: HSI selected as PLL clock ( hsi_ck ) (default after reset)
• 01: CSI selected as PLL clock ( csi_ck )
• 10: HSE selected as PLL clock ( hse_ck )
• 11: no clock send to DIVMx divider and PLLs

7.8.11 RCC PLLs configuration register (RCC_PLLCFGR)

Address offset: 0x02C

Reset value: 0x0000 0000

Bit 31 Reserved, must be kept at reset value.

Bit 30 PLL3SEN : PLL3 DIVS divider output enable

Set and reset by software to enable the pll3_s_ck output of the PLL3.

To save power, PLL3SEN must be set to 0 when the pll3_s_ck is not used.

0: pll3_s_ck output disabled (default after reset)

1: pll3_s_ck output enabled

Bit 29 PLL3REN : PLL3 DIVR divider output enable

Set and reset by software to enable the pll3_r_ck output of the PLL3.

To save power, PLL3REN and DIVR bits must be set to 0 when the pll3_r_ck is not used.

0: pll3_r_ck output disabled (default after reset)

1: pll3_r_ck output enabled

Bit 28 PLL3QEN : PLL3 DIVQ divider output enable

Set and reset by software to enable the pll3_q_ck output of the PLL3.

To save power, PLL3REN and DIVR bits must be set to 0 when the pll3_r_ck is not used.

0: pll3_q_ck output disabled (default after reset)

1: pll3_q_ck output enabled

Bit 27 PLL3PEN : PLL3 DIVP divider output enable

Set and reset by software to enable the pll3_p_ck output of the PLL3.

To save power, PLL3REN and DIVR bits must be set to 0 when the pll3_r_ck is not used.

0: pll3_p_ck output disabled (default after reset)

1: pll3_p_ck output enabled

Bits 26:25 PLL3RGE[1:0] : PLL3 input frequency range

Set and reset by software to select the proper reference frequency range used for PLL3.

These bits must be written before enabling the PLL3.

00: PLL3 input ( ref3_ck ) clock range frequency between 1 and 2 MHz (default after reset)

01: PLL3 input ( ref3_ck ) clock range frequency between 2 and 4 MHz

10: PLL3 input ( ref3_ck ) clock range frequency between 4 and 8 MHz

11: PLL3 input ( ref3_ck ) clock range frequency between 8 and 16 MHz

Set and reset by software to enable the Spread Spectrum Clock Generator of PLL3, in order to reduce the amount of EMI peaks.

0: SSCG disabled (default after reset)

1: SSCG enabled

Set and reset by software to select the proper VCO frequency range used for PLL3.

This bit must be written before enabling the PLL3. It allows the application to select the VCO range:

• – VCOH: working from 384 to 1672 MHz ( \( F_{ref2\_ck} \) must be between 2 and 16 MHz)

• – VCOL: working from 150 to 420 MHz ( \( F_{ref2\_ck} \) must be between 1 and 2 MHz)

0: VCOH selected (default after reset)

1: VCOL selected

Set and reset by software to latch the content of FRACN into the sigma-delta modulator.

In order to latch the FRACN value into the sigma-delta modulator, PLL3FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator.

Refer to PLL initialization procedure on page 419 for additional information.

PLL3FRACEN must remain at 0 for at least 5 µs

Bit 21 Reserved, must be kept at reset value.

Set and reset by software to enable the pll2_t_ck output of the PLL2.

To save power, PLL2TEN must be set to 0 when the pll2_t_ck is not used.

The hardware prevents writing this bit if XSPICKP = 1.

0: pll2_t_ck output disabled (default after reset)

1: pll2_t_ck output enabled

Set and reset by software to enable the pll2_s_ck output of the PLL2.

To save power, PLL2SEN must be set to 0 when the pll2_s_ck is not used.

The hardware prevents writing this bit if XSPICKP = 1.

0: pll2_s_ck output disabled (default after reset)

1: pll2_s_ck output enabled

Set and reset by software to enable the pll2_r_ck output of the PLL2.

The hardware prevents writing this bit if FMCCCKP = 1.

To save power, PLL3REN and DIVR bits must be set to 0 when the pll3_r_ck is not used.

0: pll2_r_ck output disabled (default after reset)

1: pll2_r_ck output enabled

Set and reset by software to enable the pll2_q_ck output of the PLL2.

To save power, PLL3QEN and DIVQ bits must be set to 0 when the pll2_q_ck is not used.

0: pll2_q_ck output disabled (default after reset)

1: pll2_q_ck output enabled

Set and reset by software to enable the pll2_p_ck output of the PLL2.

To save power, PLL2PEN and DIVP bits must be set to 0 when the pll2_p_ck is not used.

0: pll2_p_ck output disabled (default after reset)

1: pll2_p_ck output enabled

Bits 15:14 PLL2RGE[1:0] : PLL2 input frequency range

Set and reset by software to select the proper reference frequency range used for PLL2.
These bits must be written before enabling the PLL2.

00: PLL3 input ( ref2_ck ) clock range frequency between 1 and 2 MHz (default after reset)
01: PLL3 input ( ref2_ck ) clock range frequency between 2 and 4 MHz
10: PLL3 input ( ref2_ck ) clock range frequency between 4 and 8 MHz
11: PLL3 input ( ref2_ck ) clock range frequency between 8 and 16 MHz

Bit 13 PLL2SSCGEN : PLL2 SSCG enable

Set and reset by software to enable the Spread Spectrum Clock Generator of PLL2, in order to reduce the amount of EMI peaks.

0: SSCG disabled (default after reset)
1: SSCG enabled

Bit 12 PLL2VCOSEL : PLL2 VCO selection

Set and reset by software to select the proper VCO frequency range used for PLL2.
This bit must be written before enabling the PLL2. It allows the application to select the VCO range:

• – VCOH: working from 384 to 1672 MHz ( \( F_{ref2\_ck} \) must be between 2 and 16 MHz)
• – VCOL: working from 150 to 420 MHz ( \( F_{ref2\_ck} \) must be between 1 and 2 MHz)

0: VCOH selected (default after reset)
1: VCOL selected

Bit 11 PLL2FRACLEN : PLL2 fractional latch enable

Set and reset by software to latch the content of FRACN into the sigma-delta modulator.

In order to latch the FRACN value into the sigma-delta modulator, PLL2FRACLEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator.

Refer to PLL initialization procedure on page 419 for additional information.

PLL2FRACLEN must remain at 0 for at least 5 µs.

Bits 10:9 Reserved, must be kept at reset value.

Bit 8 PLL1SEN : PLL1 DIVS divider output enable

Set and reset by software to enable the pll1_s_ck output of the PLL1.

To save power, PLL1SEN must be set to 0 when the pll1_s_ck is not used.

0: pll1_s_ck output disabled (default after reset)
1: pll1_s_ck output enabled

Bit 7 Reserved, must be kept at reset value.

Bit 6 PLL1QEN : PLL1 DIVQ divider output enable

Set and reset by software to enable the pll1_q_ck output of the PLL1.
The hardware prevents writing this bit if FMCCCKP = 1.

In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.

0: pll1_q_ck output disabled (default after reset)
1: pll1_q_ck output enabled

Bit 5 PLL1PEN : PLL1 DIVP divider output enable

Set and reset by software to enable the pll1_p_ck output of the PLL1.
The hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3).

In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled.

0: pll1_p_ck output disabled (default after reset)
1: pll1_p_ck output enabled

Bits 4:3 PLL1RGE[1:0] : PLL1 input frequency range

Set and reset by software to select the proper reference frequency range used for PLL1.
This bit must be written before enabling the PLL1.
00: PLL1 input ( ref1_ck ) clock range frequency between 1 and 2 MHz (default after reset)
01: PLL1 input ( ref1_ck ) clock range frequency between 2 and 4 MHz
10: PLL1 input ( ref1_ck ) clock range frequency between 4 and 8 MHz
11: PLL1 input ( ref1_ck ) clock range frequency between 8 and 16 MHz

Bit 2 PLL1SSCGEN : PLL1 SSCG enable

Set and reset by software to enable the Spread Spectrum Clock Generator of PLL1, in order to reduce the amount of EMI peaks.

0: SSCG disabled (default after reset)

1: SSCG enabled

Bit 1 PLL1VCOSEL : PLL1 VCO selection

Set and reset by software to select the proper VCO frequency range used for PLL1.

This bit must be written before enabling the PLL1. It allows the application to select the VCO range:

• – VCOH: working from 384 to 1672 MHz ( \( f_{ref1\_ck} \) must be between 2 and 16 MHz)
• – VCOL: working from 150 to 420 MHz ( \( f_{ref1\_ck} \) must be between 1 and 2 MHz)

0: VCOH selected (default after reset)

1: VCOL selected

Bit 0 PLL1FRACEN : PLL1 fractional latch enable

Set and reset by software to latch the content of FRACN into the sigma-delta modulator.

In order to latch the FRACN value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator.

Refer to PLL initialization procedure on page 419 for additional information.

PLL1FRACEN must remain at 0 for at least 5 µs.

7.8.12 RCC PLL1 dividers configuration register 1 (RCC_PLL1DIVR1)

Address offset: 0x030

Reset value: 0x0101 0280

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.

Bits 22:16 DIVQ[6:0] : PLL1 DIVQ division factor

Set and reset by software to control the frequency of the pll1_q_ck clock.

These bits can be written only when the PLL1QEN = 0.

0000000: pll1_q_ck = vco1_ck

0000001: pll1_q_ck = vco1_ck / 2 (default after reset)

0000010: pll1_q_ck = vco1_ck / 3

0000011: pll1_q_ck = vco1_ck / 4

...

1111111: pll1_q_ck = vco1_ck / 128

Bits 15:9 DIVP[6:0] : PLL1 DIVP division factor

Set and reset by software to control the frequency of the pll1_p_ck clock.

These bits can be written only when the PLL1PEN = 0.

0000000: pll1_p_ck = vco1_ck

0000001: pll1_p_ck = vco1_ck / 2 (default after reset)

0000010: not allowed

0000011: pll1_p_ck = vco1_ck / 4

...

1111111: pll1_p_ck = vco1_ck / 128

Bits 8:0 DIVN[8:0] : multiplication factor for PLL1 VCO

Set and reset by software to control the multiplication factor of the VCO.

These bits can be written only when the PLL is disabled (PLL1ON = PLL1RDY = 0).

.....: not used

0x006: wrong configuration

0x007: DIVN = 8

...

0x080: DIVN = 129 (default after reset)

...

0x1A3: DIVN = 420

Others: wrong configurations

Caution: The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:

• – 192 to 836 MHz if PLL1VCOSEL = 0
• – 150 to 420 MHz if PLL1VCOSEL = 1

VCO output frequency = \( F_{ref1\_ck} \times \text{DIVN} \) , when fractional value 0 has been loaded into FRACN, with:

• – DIVN between 8 and 420
• – The input frequency \( F_{ref1\_ck} \) must be between 1 and 16 MHz.

7.8.13 RCC PLL1 dividers configuration register 2 (RCC_PLL1DIVR2)

Address offset: 0x0C0

Reset value: 0x0000 0101

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 DIVS[2:0] : PLL1 DIVS division factor

Set and reset by software to control the frequency of the pll1_s_ck clock.
This post-divider performs divisions with 50% duty-cycle.
The duty-cycle of 50% is guaranteed only in the following conditions:

• – With VCOL, if (DIVS+1) is even,
• – With VCOH, for all DIVS values

These bits can be written only when the PLL1SEN = 0.

000: pll1_s_ck = vco1_ck
001: pll1_s_ck = vco1_ck / 2 (default after reset)
010: pll1_s_ck = vco1_ck / 3
011: pll1_s_ck = vco1_ck / 4
100: pll1_s_ck = vco1_ck / 5
101: pll1_s_ck = vco1_ck / 6
110: pll1_s_ck = vco1_ck / 7
111: pll1_s_ck = vco1_ck / 8

7.8.14 RCC PLL1 fractional divider register (RCC_PLL1FRACR)

Address offset: 0x034

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:3 FRACN[12:0] : fractional part of the multiplication factor for PLL1 VCO

Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.

Caution: The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:

• – 192 to 836 MHz if PLL1VCOSEL = 0
• – 150 to 420 MHz if PLL1VCOSEL = 1

VCO output frequency = \( F_{ref1\_ck} \times (DIVN + (FRACN / 2^{13})) \) , with

• – DIVN between 8 and 420
• – FRACN can be between 0 and \( 2^{13} - 1 \)
• – The input frequency \( F_{ref1\_ck} \) must be between 1 and 16 MHz.

To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:

• – Set the bit PLL1FRACEN to 0.
• – Write the new fractional value into FRACN.
• – Set the bit PLL1FRACEN to 1
• – Wait at least 5 µs.

Bits 2:0 Reserved, must be kept at reset value.

7.8.15 RCC PLL1 Spread Spectrum Clock Generator register (RCC_PLL1SSCGR)

Address offset: 0x0CC

Reset value: 0x0000 0000

Bit 31 Reserved, must be kept at reset value.

Bits 30:16 INCSTEP[14:0] : Modulation Depth Adjustment for PLL1

Set and reset by software to adjust the modulation depth of the clock spreading generator.

Bit 15 SPREADSEL : Spread spectrum clock generator mode for PLL1

Set and reset by software to select the clock spreading mode.

• 0: Center-spread modulation selected (default after reset)
• 1: Down-spread modulation selected

Bit 14 RPDFNDIS : Dithering RPDF noise control for PLL1

Set and reset by software.

This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function.

• 0: Dithering noise injection enabled (default after reset)
• 1: Dithering noise injection disabled

Bit 13 TPDFNDIS : Dithering TPDF noise control for PLL1

Set and reset by software.

This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function.

• 0: Dithering noise injection enabled (default after reset)
• 1: Dithering noise injection disabled

Bits 12:0 MODPER[12:0] : Modulation Period Adjustment for PLL1

Set and reset by software to adjust the modulation period of the clock spreading generator.

7.8.16 RCC PLL2 dividers configuration register 1 (RCC_PLL2DIVR1)

Address offset: 0x038

Reset value: 0x0101 0280

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 DIVR[6:0] : PLL2 DIVR division factor

Set and reset by software to control the frequency of the pll2_r_ck clock.

These bits can be written only when the PLL2REN = 0.

0000000: pll2_r_ck = vco2_ck

0000001: pll2_r_ck = vco2_ck / 2 (default after reset)

0000010: pll2_r_ck = vco2_ck / 3

0000011: pll2_r_ck = vco2_ck / 4

...

1111111: pll2_r_ck = vco2_ck / 128

Bit 23 Reserved, must be kept at reset value.

Bits 22:16 DIVQ[6:0] : PLL2 DIVQ division factor

Set and reset by software to control the frequency of the pll2_q_ck clock.

These bits can be written only when the PLL2QEN = 0.

0000000: pll2_q_ck = vco2_ck

0000001: pll2_q_ck = vco2_ck / 2 (default after reset)

0000010: pll2_q_ck = vco2_ck / 3

0000011: pll2_q_ck = vco2_ck / 4

...

1111111: pll2_q_ck = vco2_ck / 128

Bits 15:9 DIVP[6:0] : PLL2 DIVP division factor

Set and reset by software to control the frequency of the pll2_p_ck clock.

These bits can be written only when the PLL2PEN = 0.

0000000: pll2_p_ck = vco2_ck

0000001: pll2_p_ck = vco2_ck / 2 (default after reset)

0000010: pll2_p_ck = vco2_ck / 3

0000011: pll2_p_ck = vco2_ck / 4

...

1111111: pll2_p_ck = vco2_ck / 128

Bits 8:0 DIVN[8:0] : multiplication factor for PLL2 VCO

Set and reset by software to control the multiplication factor of the VCO.

These bits can be written only when the PLL is disabled (PLL2ON = PLL2RDY = 0).

.....: not used

0x006: wrong configuration

0x007: DIVN = 8

...

0x080: DIVN = 129 (default after reset)

...

0x1A3: DIVN = 420

Others: wrong configurations

Caution: The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:

• – 192 to 836 MHz if PLL2VCOSEL = 0
• – 150 to 420 MHz if PLL2VCOSEL = 1

VCO output frequency = \( F_{ref2\_ck} \times DIVN \) , when fractional value 0 has been loaded into FRACN, with

• – DIVN between 8 and 420
• – The input frequency \( F_{ref2\_ck} \) must be between 1 and 16MHz.

7.8.17 RCC PLL2 dividers configuration register 2 (RCC_PLL2DIVR2)

Address offset: 0x0C4

Reset value: 0x0000 0101

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:8 DIVT[2:0] : PLL2 DIVT division factor

Set and reset by software to control the frequency of the pll2_t_ck clock.

This post-divider performs divisions with 50% duty-cycle.

The duty-cycle of 50% is guaranteed only in the following conditions:

• – With VCOL, if (DIVT+1) is even,
• – With VCOH, for all DIVT values

These bits can be written only when the PLL2TEN = 0.

000: pll2_t_ck = vco2_ck

001: pll2_t_ck = vco2_ck / 2 (default after reset)

010: pll2_t_ck = vco2_ck / 3

011: pll2_t_ck = vco2_ck / 4

100: pll2_t_ck = vco2_ck / 5

101: pll2_t_ck = vco2_ck / 6

110: pll2_t_ck = vco2_ck / 7

111: pll2_t_ck = vco2_ck / 8

Bits 7:3 Reserved, must be kept at reset value.

Bits 2:0 DIVS[2:0] : PLL2 DIVS division factor

Set and reset by software to control the frequency of the pll2_s_ck clock.

This post-divider performs divisions with 50% duty-cycle.

The duty-cycle of 50% is guaranteed only in the following conditions:

• – With VCOL, if (DIVS+1) is even,
• – With VCOH, for all DIVS values