6. Power control (PWR)

6.1 Introduction

The power control section (PWR) provides an overview of the supply architecture for the different power domains and of the supply configuration controller.

It also describes the features of the power supply supervisors and explains how the \( V_{\text{CORE}} \) supply domain is configured depending on the operating modes, the selected performance (clock frequency) and the voltage scaling.

6.2 PWR main features

• • Power supplies and supply domains
  • – Core domains ( \( V_{\text{CORE}} = V_{\text{CAP}} \) )
  • – \( V_{\text{DD}} \) domain
  • – Backup domain ( \( V_{\text{SW}}, V_{\text{BKP}} \) )
  • – Analog domain ( \( V_{\text{DDA}} \) )
• • System supply voltage regulation
  • – Switched-mode power supply power-efficient voltage down-converter (SMPS step-down converter)
  • – Voltage regulator (LDO)
• • Peripheral supply regulation
  • – USB regulator
• • Power supply supervision
  • – POR/PDR monitor
  • – BOR monitor
  • – PVD monitor
  • – AVD monitor
  • – \( V_{\text{BAT}} \) thresholds
  • – Temperature thresholds
• • Power management
  • – \( V_{\text{BAT}} \) battery charging
  • – Operating modes
  • – Voltage scaling control
  • – Low-power modes

6.3 PWR block diagram

Figure 19. Power control block diagram

6.3.1 PWR pins and internal signals

Table 41 lists the PWR inputs and output signals connected to package pins or balls, while Table 42 shows the internal PWR signals.

Table 41. PWR input/output signals connected to package pins or balls

Table 42. PWR internal input/output signals

Each of the four wake-up events, WKUPx, can be generated from four pins or internal events

Table 43. table wake-up source selection

6.4 Power supplies

The device requires \( V_{DD} \) and \( V_{DDSMPS} \) power supplies as well as independent supplies for \( V_{DDLDO} \) , \( V_{DDA} \) , \( V_{DDUSB} \) , and \( V_{CAP} \) . It also provides regulated supplies for specific functions (step-down converter, voltage regulator, USB regulator).

• • \( V_{DD} \) : external power supply for I/Os and system analog blocks such as reset, power management and oscillators
• • \( V_{DDxspi1} \) , \( V_{DDxspi2} \) : external power supply for dedicated I/Os (Octo SPI and Hexa Deca SPI memories)
• • \( V_{BAT} \) : optional external power supply for backup domain when \( V_{DD} \) is not present ( \( V_{BAT} \) mode)

This power supply must be connected to \( V_{DD} \) when no battery is used.

• • \( V_{DDSMPS} \) : external power supply for the SMPS step-down converter
  \( V_{DDSMPS} \) must be connected to \( V_{DD} \) or tied to \( V_{SS} \) when the SMPS is not used.

• • \( V_{LXSMPS} \) : step-down converter supply output
• • \( V_{FBSMPS} \) : step-down converter sense feedback
• • \( V_{SSSMPS} \) : separate step-down converter ground
• • \( V_{DDLDO} \) : external power supply for voltage regulator
• • \( V_{CAP} \) : digital core domain supply

This power supply is independent from all the other power supplies:

• – When the voltage regulator is enabled, \( V_{CORE} \) is delivered by the internal voltage regulator.
• – When the voltage regulator is disabled, \( V_{CORE} \) is delivered by an external power supply through \( V_{CAP} \) pin, or by the SMPS step-down converter.
• • \( V_{DDA} \) : external analog power supply for ADCs and voltage reference buffers
  This power supply is independent from all the other power supplies.
• • \( V_{REF+} \) : external reference voltage for ADC.
  • – When the voltage reference buffer is enabled, \( V_{REF+} \) and \( V_{REF-} \) are delivered by the internal voltage reference buffer.
  • – When the voltage reference buffer is disabled, \( V_{REF+} \) is delivered by an independent external reference supply.
• • \( V_{SSA} \) : separate analog and reference voltage ground.
• • \( V_{DD50USB} \) : external power supply for USB regulator.
• • \( V_{DD33USB} \) : USB regulator supply output for USB interface.
  • – When the USB regulator is enabled, \( V_{DD33USB} \) is delivered by the internal USB regulator.
  • – When the USB regulator is disabled, \( V_{DD33USB} \) is delivered by an independent external supply input.
• • \( V_{SS} \) : common ground for all supplies except for step-down converter and analog peripherals.

Note: Depending on the operating power supply range, some peripherals might be used with limited features and performance. For more details, refer to section “General operating conditions” of the device datasheets.

Figure 20. Power supply overview ^(a)

a. Refer to application note AN5935 "Getting started hardware with STM32H7Rx/7Sx MCUs" for the possible power scheme and connected capacitors.

By configuring the SMPS step-down converter and LDO voltage regulator, the supply configurations shown in Figure 21 are supported for the \( V_{CORE} \) core domain and an external supply. For the different configuration available per package refer to the product datasheet.

Note: The SMPS step-down converter is not available on all packages, and the Bypass mode is available only when the SMPS is available.

Figure 21. System supply configurations

MS/V45556V/2

The different supply configurations are controlled through the LDOEN, SDEN, SMPSEXTHP, SDHILEVEL and BYPASS bits in the PWR control register 2 (PWR_CSR2) register according to Table 44 .

In the following table HP refers to High power, LP refers to Low Power and off refers to no supply.

Table 44. Supply configuration control

Table 44. Supply configuration control (continued)

6.4.1 System supply startup

The system startup sequence from power-on in different supply configurations is the following (see Figure 22 and Figure 23 for LDO supply and Direct SMPS supply, respectively):

1. 1. When the system is powered on, the POR monitors \( V_{DD} \) supply. Once \( V_{DD} \) is above the POR threshold level, the SMPS step-down converter and voltage regulator are enabled in the default supply configuration:
   The SMPS step-down converter output level is set at 1.35 V. The voltage regulator LDO output level is set at 1.19 V. Depending on the package and configuration the SMPS provides the voltage to internal power domain and/or LDO or external supply.
2. 2. The system is kept in reset mode as long as \( V_{CORE} \) is not stable.
3. 3. Once \( V_{CORE} \) is stable, the system is taken out of reset and the HSI oscillator is enabled.
4. 4. Once the oscillator is stable, the system is initialized: Flash memory is ready, option bytes are loaded and the CPU starts in limited run mode (Run*).
5. 5. The software must then initialize the system including supply configuration programming in PWR control register 2 (PWR_CSR2) . Once the supply configuration has been configured, the ACTVOSRDY bit in the PWR control status register 1 (PWR_SR1) must be checked to guarantee valid voltage levels:
   1. a) As long as ACTVOSRDY indicates that voltage levels are invalid, the system is in Run* mode and VOS must not be changed.
   2. b) Once ACTVOSRDY indicates that voltage levels are valid, the system is in normal Run mode, and VOS can be changed.

\( V_{CORE} \) directly supplied from the SMPS step-down converter

When \( V_{CORE} \) is directly supplied from the SMPS step-down converter, the \( V_{CORE} \) voltage first settles at \( V_{FBSMPS} \) default level (1.36 V). Due to a too high supply compared to the \( V_{OS} \) level, the ACTVOSRDY bit in the PWR control status register 1 (PWR_SR1) indicates invalid voltage levels. \( V_{CORE} \) settles at \( V_{OS} \) low and ACTVODSRDY indicates valid voltage levels only when the supply configuration has been programmed in PWR control register 2 (PWR_CSR2) (see Figure 22).

Figure 22. Device startup with \( V_{CORE} \) supplied directly from SMPS step-down converter

1. In Run* mode, write operations to RAM are not allowed.

2. \( V_{OS} \) can be changed only when ACTVOSRDY is valid.

When exiting from Standby mode, the supply configuration is known by the system since the content of PWR control register 2 (PWR_CSR2) is retained. However the software must still wait for the ACTVOSRDY bit to be set in PWR control status register 1 (PWR_SR1) to indicate \( V_{CORE} \) voltage levels are valid, before performing changes to VOS.

\( V_{CORE} \) supplied in Bypass mode (LDO and SMPS OFF)

The devices that feature the SMPS can also be used in Bypass mode. When \( V_{CORE} \) is supplied in Bypass mode (LDO and SMPS OFF), the \( V_{CORE} \) voltage must first settle at a default level higher than 1.2 V. Due to the LDO default state after power-up (enabled by default), the external \( V_{CORE} \) voltage must remain higher than 1.2 V until the LDO is disabled by software.

When the LDO is disabled, the external \( V_{CORE} \) voltage can be adjusted according to the user application needs (refer to section General operating conditions of the datasheet for details on \( V_{CORE} \) level versus the maximum operating frequency).

Figure 23. Device startup with \( V_{CORE} \) supplied in Bypass mode from external regulator

6.4.2 Core domain

The \( V_{CORE} \) core domain supply can be provided by the SMPS step-down converter, LDO voltage regulator or by an external supply ( \( V_{CAP} \) ). \( V_{CORE} \) supplies all the digital circuitries except for the backup domain and the Standby circuitry. When a system reset occurs, the voltage regulator is enabled and supplies \( V_{CORE} \) . The SMPS step-down converter is also enabled to deliver 1.36 V. This allows the system to start up in any supply configurations (see Figure 21 ).

After a system reset, the software must configure the used supply configuration in PWR control register 2 (PWR_CSR2) register before changing VOS in the PWR control status register 4 (PWR_CSR4) or the RCC sys_ck frequency. The different system supply configurations are controlled as shown in Table 44 .

Note: The SMPS step-down converter and the LDO are not available on all packages.

LDO voltage regulator

The embedded voltage regulator (LDO) requires external capacitors to be connected to VCAP pins.

The voltage regulator provides three different operating modes: High Power (HP), Low-power (LP) or Off. These modes are used depending on the system operating modes (Run, Stop and Standby).

• • Run modes

The LDO regulator is in Main mode and provides full power to the \( V_{CORE} \) domain (core, memories and digital peripherals). The regulator output voltage can be scaled by software to different voltage levels (VOS low and VOS high) that are configured through the VOS bit in the PWR control status register 4 (PWR_CSR4) . The VOS voltage scaling allows optimizing the power consumption when the system is clocked below the maximum frequency. By default VOS low is selected after system reset. VOS can be changed on-the-fly to adapt to the required system performance.

• • Stop mode

The voltage regulator supplies the \( V_{CORE} \) domain to retain the content of registers and internal memories, and must be set in LP mode.

In LP mode the regulator mode is selected through the SVOS bit in the PWR control register 1 (PWR_CR1) . Due to a lower voltage level for SVOS low scaling, the Stop mode consumption can be further reduced.

• • Standby mode

The voltage regulator is OFF and the \( V_{CORE} \) domains are powered down. The content of the registers and memories is lost except for the Standby circuitry and the backup domain.

For more details, refer to the voltage regulator section in the datasheets.

SMPS step-down converter regulator

The SMPS step-down converter requires an external coil to be connected between the dedicated VLXSMPS pin and, via a capacitor, to VSS.

The SMPS step-down converter can be used in internal supply mode or external supply mode. The internal supply mode is used to directly supply the V _CORE domain, while the external supply mode is used to generate an intermediate supply level (V _{DD_extern} at 1.8 V) which can supply the voltage regulator and optionally an external circuitry.

The SMPS step-down converter works in three different power modes: High Power (HP), Low-power (LP) or Off.

When the SMPS step-down converter is used in internal supply mode, the converter operating modes depend on the system modes (Run, Stop, Standby) and are configured through the VOS and SVOS levels:

• • Run mode

  The SMPS step-down converter operates in HP mode and provides full power to the V _CORE domain (core, memories and digital peripherals). The regulator output voltage can be scaled by software to different voltage levels (VOS low and VOS high) that are configured through the VOS bit in the PWR control status register 4 ( PWR_CSR4 ). The VOS voltage scaling allows optimizing the power consumption when the system is clocked below the maximum frequency. By default VOS low is selected after system reset. VOS can be changed on-the-fly to adapt to the required system performance.

• • Stop mode

  The SMPS step-down converter supplies the V _CORE domain to retain the content of registers and internal memories, and must be set in LP mode. The voltage regulator mode is selected through the SVOS in the PWR control register 1 (PWR_CR1) . In LP mode only SVOS low and SVOS high scaling are allowed. Due to a lower voltage level for these scaling, the Stop mode consumption can be further reduced.

• • Standby mode

  The SMPS step-down converter is OFF and the V _CORE domains are powered down. The content of the registers and memories are lost except for the Standby circuitry and the backup domain.

When the SMPS step-down converter supplies an external circuitry by generating an intermediate voltage level, the converter is forced ON and operates in HP mode. The intermediate voltage level is selected through SDHILEVEL bits in the PWR control register 2 (PWR_CSR2) . V _{DD_extern} is supplied at all times with full power whatever the system modes (Run, Stop, Standby).

Note: The SMPS step-down converter is not available on all packages, the SMPS supplies the voltage regulator and optionally an external circuitry. The LDO may not be used in some configuration,

6.4.3 PWR external supply

When \( V_{CORE} \) is supplied from an external source (Bypass mode), different operating modes can be used depending on the system operating modes (Run, Stop or Standby):

• • In Run modes

The external source supplies full power to the \( V_{CORE} \) domain (core, memories and digital peripherals). The external source output voltage is scalable through different voltage levels (VOS low and VOS high). The externally applied voltage level must be reflected in the VOS bit of PWR_CSR4 register. The RAMs must only be accessed for write operations when the external applied voltage level matches VOS settings.

• • In Stop mode

The external \( V_{CORE} \) supply should be maintain at the VOS level or at least over 0.95 V to ensure proper internal wake up.

• • In Standby mode

The wake mechanism should be monitored externally. Refer to the datasheet for the proper \( V_{CORE} \) ramp time.

6.4.4 Backup domain

To retain the content of the backup domain (RTC, backup registers and backup RAM) when \( V_{DD} \) is turned off, VBAT pin can be connected to an optional voltage which is supplied from a battery or from an another source.

The switching to \( V_{BAT} \) is controlled by the power-down reset embedded in the Reset block that monitors the \( V_{DD} \) supply.

Warning: During \( t_{RSTTEMPO} \) (temporization at \( V_{DD} \) startup) or after a PDR is detected, the power switch between \( V_{BAT} \) and \( V_{DD} \) remains connected to VBAT.

During the startup phase, if \( V_{DD} \) is established in less than \( t_{RSTTEMPO} \) (see the datasheet for the value of \( t_{RSTTEMPO} \) ) and \( V_{DD} > V_{BAT} + 0.6 \) V, a current may be injected into \( V_{BAT} \) through an internal diode connected between \( V_{DD} \) and the power switch ( \( V_{BAT} \) ).

If the power supply/battery connected to the VBAT pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the VBAT pin.

When the \( V_{DD} \) supply is present, the backup domain is supplied from \( V_{DD} \) . This allows saving \( V_{BAT} \) power supply battery life time.

If no external battery is used in the application, it is recommended to connect \( V_{BAT} \) externally to \( V_{DD} \) , and add a 100 nF external ceramic capacitor between \( V_{BAT} \) and \( V_{SS} \) .

When the \( V_{DD} \) supply is present and higher than the PDR threshold, the backup domain is supplied by \( V_{DD} \) and the following functions are available:

• • PC14 and PC15 can be used either as GPIO or as LSE pins.
• • PC13 can be used either as GPIO or as RTC_OUT1, RTC_TS, TAMP_IN1, TAMP_OUT2 pin assuming they have been configured by the RTC or the TAMPER registers (see Section 49.3.3: GPIOs controlled by the RTC and TAMP ).
• • PB9/TAMP_IN2, PE1/TAMP_IN3 when configured by the RTC as tamper pins.

Note: Since the switch only sinks a limited amount of current, the use of PC13 and PC15 GPIOs is restricted: only one I/O can be used as an output at a time. These I/Os must not be used as current sources (for example to drive an LED). Refer to the DS

In \( V_{BAT} \) mode, when the \( V_{DD} \) supply is absent and a supply is present on \( V_{BAT} \) , the backup domain is supplied by \( V_{BAT} \) and the following functions are available:

• • PC14 and PC15 can be used as LSE pins only.
• • PC13 can be used as RTC_OUT1, RTC_TS, TAMP_IN1, TAMP_OUT2 pin assuming they have been configured by the RTC or the TAMPER registers (see Section 49.3.3: GPIOs controlled by the RTC and TAMP ).
• • PB9/TAMP_IN2, PE1/TAMP_IN3 when configured by the RTC as tamper pins.

Accessing the backup domain

After reset, the backup domain (RTC registers and RTC backup registers) is protected against possible unwanted write accesses. To enable access to the backup domain, set the DBP bit in the PWR control register 1 (PWR_CR1) .

For more detail on RTC and backup RAM access, refer to Section 7: Reset and clock control (RCC) .

Backup RAM

The backup domain includes 4 Kbytes of backup RAM accessible in 32-bit, 16-bit or 8-bit data mode. The backup RAM is supplied from the backup regulator in the backup domain. When the backup regulator is enabled through BREN bit in the PWR control status register 1 (PWR_CSR1) , the backup RAM content is retained even in Standby and/or \( V_{BAT} \) mode (it can be considered as an internal EEPROM if \( V_{BAT} \) is always present.)

The backup regulator can be ON or OFF depending whether the application needs the backup RAM function in Standby or \( V_{BAT} \) modes.

After a tamper event, if the RTC flag is set, the backup RAM cannot be used until an erase is explicitly requested. When a tamper event is generated, reading the backup RAM returns 0x0, and any write different from 0 is not effective. The backup RAM can be erased:

• • through the Flash memory interface when a regression from nvstate closed to nvstate open is requested. See also Section 4: System security .
• or
• • by performing a simple dummy write with zero as data to any address of the backup RAM (this action resets the whole backup RAM when it is performed after a tamper event).

Figure 24. Backup domain

6.4.5 V _BAT battery charging

When V _DD is present, the external battery connected to V _BAT can be charged through an internal resistance.

V _BAT charging can be performed either through a 5 kΩ resistor or through a 1.5 kΩ resistor, depending on the VBRS bit value in PWR control register 2 (PWR_CSR2) .

The battery charging is enabled by setting the VBE bit in the PWR control register 2 (PWR_CSR2) . It is automatically disabled in V _BAT mode.

6.4.6 Analog supply

Separate V _DDA analog supply

The analog supply domain is powered by dedicated V _DDA and V _SSA pads that allow the supply to be filtered and shielded from noise on the PCB, thus improving ADC conversion accuracy:

• • The analog supply voltage input is available on a separate V _DDA pin.
• • An isolated supply ground connection is provided on V _SSA pin.

Analog reference voltage \( V_{REF+}/V_{REF-} \)

To achieve better accuracy low-voltage signals, the ADC also has a separate reference voltage, available on \( V_{REF+} \) pin. The user can connect a separate external reference voltage on \( V_{REF+} \) .

The \( V_{REF+} \) controls the highest voltage, represented by the full scale value, the lower voltage reference ( \( V_{REF-} \) ) being connected to \( V_{SSA} \) .

When enabled by ENVR bit in the VREFBUF control and status register (see Section 29: Voltage reference buffer (VREFBUF) ), \( V_{REF+} \) is provided from the internal voltage reference buffer. The internal voltage reference buffer can also deliver a reference voltage to external components through \( V_{REF+}/V_{REF-} \) pins.

When the internal voltage reference buffer is disabled by ENVR, \( V_{REF+} \) is delivered by an independent external reference supply voltage.

Note: \( V_{REF+} \) and \( V_{REF-} \) pins are not available on all packages (in this case they are connected internally respectively to \( V_{DDA} \) and \( V_{SSA} \) ). Do not enable the internal voltage reference buffer when an external power supply is applied to the \( V_{REF+} \) pin.

6.4.7 USB regulator

The USB transceivers are supplied from a dedicated \( V_{DD33USB} \) supply that can be provided either by the integrated USB regulator, or by an external USB supply.

When enabled by USBREGEN bit in the PWR control register 2 (PWR_CSR2) , the \( V_{DD33USB} \) is provided from the USB regulator, which is powered through the \( V_{DD50USB} \) pin generally connected to the USB VBUS line. Before using \( V_{DD33USB} \) , check that it is available by monitoring USB33RDY bit in the PWR control register 2 (PWR_CSR2) . The \( V_{DD33USB} \) supply level detector must be enabled through USB33DEN bit in the PWR_CSR2 register.

When the USB regulator is disabled through USBREGEN bit, \( V_{DD33USB} \) can be provided from an external supply. In this case \( V_{DD33USB} \) and \( V_{DD50USB} \) must be connected together. The \( V_{DD33USB} \) supply level detector must be enabled through USB33DEN bit in the PWR_CSR2 register before using the USB transceivers.

For more information on the USB regulator (see Section 62: USB on-the-go high-speed (OTG_HS) ).

Figure 25. USB supply configurations

6.5 Power supply supervision

Power supply level monitoring is available on the following supplies:

• • V _DD (V _DDSMPS ) can be monitored via POR/PDR (see Section 6.5.1 ), BOR (see Section 6.5.2 ) and PVD monitor (see Section 6.5.3 )
• • V _DDA can be monitored via AVD monitor (see Section 6.5.4 )
• • V _BAT can be monitored via VBAT threshold (see Section 6.5.5 )
• • V _SW can be monitored via rst_vsw, which keeps V _SW domain in Reset mode as long as the level is not OK.
• • V _BKP can be monitored via a BRRDY bit in the PWR control status register 1 (PWR_CSR1) .
• • V _FBSMPS can be monitored via a SDEXTRDY bit in the PWR control register 2 (PWR_CSR2) .
• • V _DD33USB can be monitored via the USB33RDY bit in the PWR control register 2 (PWR_CSR2) .

6.5.1 Power-on reset (POR)/power-down reset (PDR)

The system has an integrated POR/PDR circuitry that ensures proper startup operation.

The system remains in Reset mode when V _DD is below a specified V _POR threshold, without the need for an external reset circuit. Once the V _DD supply level is above the V _POR threshold, the system is taken out of reset (see Figure 26). For more details concerning the power-on/power-down reset threshold, refer to the electrical characteristics section of the datasheets.

By default the PDR is enabled.

Figure 26. Power-on reset/power-down reset waveform

1. 1. For thresholds and hysteresis values, refer to the datasheets.

6.5.2 Brownout reset (BOR)

During power-on, the Brownout reset (BOR) keeps the system under reset until the \( V_{DD} \) supply voltage reaches the specified \( V_{BOR} \) threshold.

The \( V_{BOR} \) threshold is configured through system option bytes. By default, BOR is OFF. The following programmable \( V_{BOR} \) thresholds can be selected:

• • BOR OFF ( \( V_{BOR0} \) )
• • BOR Level 1 ( \( V_{BOR1} \) )
• • BOR Level 2 ( \( V_{BOR2} \) )
• • BOR Level 3 ( \( V_{BOR3} \) )

For more details on the brown-out reset thresholds, refer to the section “Electrical characteristics” of the product datasheets.

A system reset is generated when the BOR is enabled and \( V_{DD} \) supply voltage drops below the selected \( V_{BOR} \) threshold.

BOR can be disabled by programming the system option bytes. To disable the BOR function, \( V_{DD} \) must have been higher than \( V_{BOR0} \) to start the system option byte programming sequence. The power-down is then monitored by the PDR (see Section 6.5.1 ).

Figure 27. BOR thresholds

1. 1. For thresholds and hysteresis values, refer to the datasheets.

6.5.3 Programmable voltage detector (PVD)

The PVD can be used to monitor the \( V_{DD} \) power supply by comparing it to a threshold selected by the PLS[2:0] bits in the PWR control register 1 (PWR_CR1) . The PVD can also be used to monitor a voltage level on the PVD_IN pin. In this case PVD_IN voltage is compared to the internal \( V_{REFINT} \) level.

The PVD is enabled by setting the PVDE bit in the PWR control register 1 (PWR_CR1) .

A PVDO flag is available in the PWR control status register 1 (PWR_SR1) to indicate if \( V_{DD} \) or PVD_IN voltage is higher or lower than the PVD threshold. This event is internally connected to the EXTI and can generate an interrupt, assuming it has been enabled through the EXTI registers. The PVDO output interrupt can be generated when \( V_{DD} \) or PVD_IN voltage drops below the PVD threshold and/or when \( V_{DD} \) or PVD_IN voltage rises above the PVD threshold depending on EXTI rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks.

Figure 28. PVD thresholds

1. 1. For thresholds and hysteresis values, refer to the datasheets.

6.5.4 Analog voltage detector (AVD)

The AVD can be used to monitor the \( V_{DDA} \) supply by comparing it to a threshold selected by the ALS[1:0] bits in the PWR control register 1 (PWR_CR1) .

The AVD is enabled by setting the AVDEN bit in the PWR control register 1 (PWR_CR1) .

An AVDO flag is available in the PWR control status register 1 (PWR_SR1) to indicate whether \( V_{DDA} \) is higher or lower than the AVD threshold. This event is internally connected to the EXTI and can generate an interrupt if enabled through the EXTI registers. The AVDO interrupt can be generated when \( V_{DDA} \) drops below the AVD threshold and/or when \( V_{DDA} \) rises above the AVD threshold depending on EXTI rising/falling edge configuration. As an example the service routine could indicate when the \( V_{DDA} \) supply drops below a minimum level.

Figure 29. AVD thresholds

1. 1. For thresholds and hysteresis values, refer to the datasheets.

6.5.5 Battery voltage thresholds

The battery voltage supply monitors the backup domain \( V_{SW} \) level. \( V_{SW} \) is monitored by comparing it with two threshold levels: \( V_{BAThigh} \) and \( V_{BATlow} \) . VBATH and VBATL flags in the PWR control status register 1 (PWR_CSR1) , indicate if \( V_{SW} \) is higher or lower than the threshold.

The \( V_{BAT} \) supply monitoring can be enabled/disabled via MONEN bit in the PWR control status register 1 (PWR_CSR1) . When it is enabled, the battery voltage thresholds increase power consumption. As an example the \( V_{SW} \) levels monitoring could be used to trigger a tamper event for an over or under voltage of the RTC power supply domain (available in VBAT mode).

VBATH and VBATL are connected to RTC tamper signals (see Section 49: Real-time clock (RTC) ).

Note: Battery voltage monitoring is only available when the backup regulator is enabled (BREN bit set in the PWR control status register 1 (PWR_CSR1)).

When the device does not operate in VBAT mode, the battery voltage monitoring checks \( V_{DD} \) level. When \( V_{DD} \) is available, \( V_{SW} \) is connected to \( V_{DD} \) through the internal power switch (see Section 6.4.4: Backup domain).

Figure 30. VBAT thresholds

1. For thresholds and hysteresis values, refer to the datasheets.

6.5.6 Temperature thresholds

The junction temperature can be monitored by comparing it with two threshold levels, TEMP _high and TEMP _low . TEMPH and TEMPL flags, in the PWR control status register 1 (PWR_CSR1) , indicate whether the device temperature is higher or lower than the threshold. The temperature monitoring can be enabled/disabled via \( MONEN \) bit in the PWR control status register 1 (PWR_CSR1) . When enabled, the temperature thresholds increase power consumption. As an example the levels could be used to trigger a routine to perform temperature control tasks.

The temperature thresholds are available only when the backup regulator is enabled ( \( BREN \) bit set in the PWR_CSR1 register).

TEMPH and TEMPL wake-up interrupts are available on the RTC tamper signals (see Section 49: Real-time clock (RTC) ).

Figure 31. Temperature thresholds

• 1. For thresholds and hysteresis values, refer to the datasheets.

6.5.7 \( V_{CORE} \) maximum voltage level detector

\( V_{CORE} \) is protected against too high voltages in the direct SMPS step-down converter supply configuration. \( V_{CORE} \) overvoltage protection is enabled at startup by hardware once the SMPS step-down converter configuration has been programmed into PWR control register 2 (PWR_CSR2) :

• • \( V_{CORE} \) voltage level stays within range:
  • – The ACTVOSRDY bit in the PWR control status register 1 (PWR_SR1) indicates valid voltage levels.
  • – The system operates normally and \( V_{CORE} \) overvoltage protection is disabled.
• • \( V_{CORE} \) overvoltage (due to a wrongly programmed SMPS step-down converter configuration):
  • – The hardware forces the SMPS step-down converter voltage level to 1.0 V.
  • – The ACTVOSRDY bit stays off, indicating invalid voltage levels. In this case the software must be corrected and re-loaded to program a correct SMPS step-down converter configuration that matches the application supply connections. The system must then be power cycled.

Figure 32. \( V_{CORE} \) overvoltage protection

6.6 Power management

The power management block controls the \( V_{CORE} \) supply in accordance with the system operation modes (see Section 6.6.1 ).

The device power domains can operate in one of the following operating modes:

• • Run (power ON, clock ON)
• • Sleep (power ON, core clock stopped, peripherals keep running)
• • Stop (power ON, clock OFF)
• • Standby (Power OFF, clock OFF).

The \( V_{CORE} \) supply level follows the system operating mode (Run, Stop, Standby).

The following voltage scaling features allow controlling the power with respect to the required system performance (see Section 6.6.2: Voltage scaling ):

• • To obtain a given system performance, the corresponding voltage scaling must be set in accordance with the system clock frequency. To do this, configure the VOS bits to the Run mode voltage scaling.
• • To obtain the best trade-off between power consumption and exit-from-Stop mode latency, configure the SVOS bit to Stop mode voltage scaling.

6.6.1 Operating modes

Several system operating modes are available to tune the system according to the performance required, that is, when the CPU does not need to execute code and are waiting for an external event. It is up to the user to select the operating mode that gives the best compromise between low power consumption, short startup time and available wake-up sources.

The operating modes allow controlling the clock distribution to the different system blocks and powering them.

In Run mode, power consumption can be reduced by one of the following means:

• • Lowering the system performance by slowing down the system clocks and reducing the \( V_{CORE} \) supply level through VOS voltage scaling bit.
• • Gating the clocks to the APBx and AHBx peripherals when they are not used, through PERxEN bits.

Table 45. Operating mode summary

1. The CPU subsystem peripherals that have a PERxLPEN bit operate accordingly.

2. When the CPU is in Stop the last EXTI wake-up source should be cleared by SW.

3. When the system oscillator HSI or CSI is used, the state is controlled by HSIKERON and CSIKERON, otherwise the system oscillator is OFF.

6.6.2 Voltage scaling

The V _CORE domain is supplied from a single voltage regulator supporting voltage scaling with the following features:

• • Run mode voltage scaling
  • – VOS low
  • – VOS high
• • Stop mode voltage scaling
  • – SVOS low
  • – SVOS high

For more details on voltage scaling values, refer to the product datasheets.

After reset, the system starts on the lowest Run mode voltage scaling (VOS low). The voltage scaling can then be changed on-the-fly by software by programming the VOS bit in the PWR control status register 4 (PWR_CSR4) according to the required system performance. When exiting from Stop mode or Standby mode, the Run mode voltage scaling is reset to the default VOS low value.

Before entering Stop mode, the software can preselect the SVOS level in PWR control register 1 (PWR_CR1) . The Stop mode voltage scaling for SVOS low and SVOS high also sets the voltage regulator in Low-power (LP) mode to further reduce power consumption.

In Standby mode the V _CORE supply is switched off.

6.6.3 Power management examples

• • Figure 34 shows \( V_{CORE} \) voltage scaling behavior in Run mode.
• • Figure 35 shows \( V_{CORE} \) voltage scaling behavior in Stop mode.
• • Figure 36 shows \( V_{CORE} \) voltage regulator and voltage scaling behavior in Standby mode.

Example of \( V_{CORE} \) voltage scaling behavior in Run mode

Figure 34 illustrates the following system operation sequence example:

1. 1. After reset, the system starts from HSI with VOS low.
2. 2. The system performance is then increased to a high-speed clock from the PLL with voltage scaling VOS high. To do this:
   1. a) Program the voltage scaling to VOS high.
   2. b) Once the \( V_{CORE} \) supply has reached the required level indicated by VOSRDY, increase the clock frequency by enabling the PLL.
   3. c) Once the PLL is locked, switch the system clock.
3. 3. The next step is to reduce the system performance to HSI clock with voltage scaling VOS low. To do this:
   1. a) Switch the clock to HSI.
   2. b) Disable the PLL.
   3. c) Decrease the voltage scaling to VOS low.

1. 4. The system performance can then be increased to high-speed clock from the PLL. To do this:
   1. a) Program the voltage scaling to VOS high.
   2. b) Once the \( V_{CORE} \) supply has reached the required level indicated by VOSRDY, increase the clock frequency by enabling the PLL.
   3. c) Once the PLL is locked, switch the system clock.

When the system performance (clock frequency) is changed, VOS must be set accordingly, otherwise the system might be unreliable.

Figure 34. Dynamic voltage scaling in Run mode

1. 1. The status of the register bits at each step is shown in blue.

Example of \( V_{CORE} \) voltage scaling behavior in Stop mode

Figure 35 illustrates the following system operation sequence example:

1. 1. The system is running from the PLL in high-performance mode (VOS high voltage scaling).
2. 2. First the CPU subsystem deallocates all the peripheral, in a second step, the CPU subsystem enters Stop mode and the system enters Stop mode. The system clock is stopped and the hardware lowers the voltage scaling to the software preselected SVOS low.

1. 3. The CPU subsystem is then woken up. The system exits from Stop mode and the CPU subsystem exits from Stop mode. The hardware always sets the voltage scaling to VOS low after exiting from Stop mode and waits for the requested supply level to be reached before enabling the HSI clock. Once the HSI clock is stable, the system clock is enabled and switch in run mode under HSI clock.
2. 4. The system performance could then be increased. To do this:
   1. a) The software first sets the voltage scaling to VOS high.
   2. b) Once the \( V_{CORE} \) supply has reached the required level indicated by VOSRDY, the clock frequency can be increased by enabling the PLL.
   3. c) Once the PLL is locked, the system clock can be switched.

Figure 35. Dynamic voltage scaling behavior in Stop mode

1. 1. The status of the register bits at each step is shown in blue.

Example of \( V_{CORE} \) voltage regulator and voltage scaling behavior in Standby mode

Figure 36 illustrates the following system operation sequence example:

1. 1. The system is running from the PLL in high-performance mode (VOS high voltage scaling).
2. 2. The CPU subsystem deallocates all the peripherals and the power is switched off. The system enter in standby mode.
3. 3. The system is then woken up by a wake-up source. The system exits from Standby mode. The hardware sets the voltage scaling to the default VOS low and waits for the requested supply level to be reached before enabling the default HSI oscillator. Once

the HSI clock is stable, the system clock is enabled. The software must then check the ACTVOSRDY is valid before changing the system performance.

1. 4. In a next step, increase the system performance. To do this:
   1. a) The software first increases the voltage scaling to VOS high
   2. b) Before enabling the PLL, it waits for the requested supply level to be reached by monitoring VOSRDY bit.
   3. c) Once the PLL is locked, the system clock can be switched.

Figure 36. Dynamic voltage scaling from Standby mode

1. 1. The status of the register bits at each step is shown in blue.

6.7 Low-power modes

Several low-power modes are available to save power when the CPU does not need to execute code (i.e. when waiting for an external event). It is up to the user application to select the mode that gives the best compromise between low power consumption, short startup time and available wake-up sources:

• • Slowing down system clocks (see Section 7.5.6: System clock (sys_ck) )
• • Controlling individual peripheral clocks (see Section 7.5.12: Peripheral clock gating control )
• • Low-power modes
  • – Sleep (CPU clock stopped and still in RUN mode)
  • – Stop (System clock stopped)
  • – Standby (System powered down)

6.7.1 Slowing down system clocks

In Run mode, the speed of the system clock sys_ck can be reduced. For more details refer to Section 7.5.6: System clock (sys_ck) .

6.7.2 Controlling peripheral clocks

In Run mode, the HCLKx and PCLKx for individual peripherals can be stopped by configuring at any time PERxEN bit in RCC_XXXXENR to reduce power consumption.

To reduce power consumption in CSleep mode, the individual peripheral clocks can be disabled by configuring PERxLPEN bit in RCC_XXXXLPENR. For the peripherals still receiving a clock in Sleep mode, their clock can be slowed down before entering Sleep mode.

Example: for APB2 peripherals: the RCC registers is named: RCC_APB2ENR, this register contains SPI4EN, SAI1EN, and so on.

6.7.3 Entering low-power modes

CPU subsystem Sleep and Stop low-power modes are entered by the MCU when executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex ^® -M System Control register is set on Return from ISR.

The system can enter Stop or Standby low-power mode when all EXTI wake-up sources are cleared.

6.7.4 Exiting from low-power modes

The CPU subsystem exits from Sleep mode through any interrupt or event depending on how the low-power mode was entered:

• • If the WFI instruction or Return from ISR was used to enter to low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the system.
• • If the WFE instruction is used to enter to low-power mode, the CPU exits from low-power mode as soon as an event occurs. The wake-up event can be generated either by:
  • – An NVIC IRQ interrupt.

When SEVONPEND = 0 in the Cortex ^® -M7 System Control register, the interrupt must be enabled in the peripheral control register and in the NVIC.

When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit in the NVIC interrupt clear pending register have to be cleared. Only NVIC interrupts with sufficient priority wakes up and interrupts the MCU.

When SEVONPEND = 1 in the Cortex ^® -M7 System Control register, the interrupt must be enabled in the peripheral control register and optionally in the NVIC.

When the MCU resumes from WFE, the peripheral interrupt pending bit and, when

enabled, the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

All NVIC interrupts wake-up the MCU, even the disabled ones.

Only enabled NVIC interrupts with sufficient priority wake-up and interrupt the MCU.

– An event

An EXTI line must be configured in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It might be necessary to clear the interrupt flag in the peripheral.

The CPU subsystem exits from Stop modes by enabling an EXTI interrupt or event depending on how the low-power mode was entered (see above).

The CPU subsystem exits from Standby mode by enabling an EXTI interrupt or event. Program execution restarts from CPU local reset (such as a reset vector fetched from the system configuration boot and security block (SBS)).

The CPU subsystem exits from Standby mode by enabling an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event. Program execution restarts in the same way as after a system reset (such as boot pin sampling, option bytes loading or reset vector fetched).

6.7.5 Sleep mode

The Sleep mode applies only to the CPU subsystem. In Sleep mode, the CPU clock is stopped. The CPU subsystem peripheral clocks operate according to the values of PERxLPEN bits in RCC_xxxxENR.

Entering Sleep mode

The Sleep mode is entered according to Section 6.7.3: Entering low-power modes , when the SLEEPDEEP bit in the Cortex ^® -M System Control register is cleared.

Refer to Table 46 for details on how to enter to Sleep mode.

Exiting from Sleep mode

The Sleep mode is exited according to Section 6.7.4: Exiting from low-power modes .

Refer to Table 46 for more details on how to exit from Sleep mode.

Table 46. Sleep mode

6.7.6 Stop mode

The Stop mode applies to the MCU. In Stop mode, the CPU clock is stopped. All CPU subsystem peripheral clocks are also stopped.

In Stop mode, CPU subsystem peripherals having a kernel clock request can still request their kernel clock.

The Flash memory can enter low-power Stop mode when it is enabled through FLPS in PWR_CR1 register. This allows a trade-off between domain Stop restart time and low power consumption.

The HSI or CSI can remain enabled in system Stop mode (HSIKERON and CSIKERON set in RCC_CR register). After exiting Stop mode, the clock is quickly available as kernel clock

for peripherals. Other system oscillator sources are stopped in Stop mode and require a starting time after exiting Stop mode.

In Stop mode and SVOS high, peripherals using the LSI or LSE clock and peripherals having a kernel clock request are still able to operate.

In system Stop mode, the following features can be selected to remain active by programming individual control bits:

• • Independent watchdog (IWDG)
  The IWDG is started by writing to its key register or by hardware option. Once started it cannot be stopped except by a reset (see Section 48.3 in Section 48: Independent watchdog (IWDG) ).
• • Real-time clock (RTC)
  This is configured via the RTCEN bit in the RCC Backup domain control register (RCC_BDCR) .
• • Internal RC oscillator (LSI RC)
  This is configured via the LSION bit in the RCC clock control and status register (RCC_CSR) .
• • External 32.768 kHz oscillator (LSE OSC)
  This is configured via the LSEON bit in the RCC Backup domain control register (RCC_BDCR) .
• • Peripherals capable of running on the LSI or LSE clock.
• • Peripherals having a kernel clock request.
• • Internal RC oscillators (HSI and CSI)
  This is configured via the HSIKERON and CSIKERON bits in the RCC source control register (RCC_CR) .
• • The ADC can also consume power during Stop mode, unless they are disabled before entering this mode. To disable them, the ADON bit in the ADC_CR2 register must be written to 0.

The selected SVOS low levels add an additional startup delay when exiting from system Stop mode (see Table 47 ).

Table 47. Stop mode operation

Entering Stop mode

The Stop mode is entered according to Section 6.7.3: Entering low-power modes , when the SLEEPDEEP bit in the Cortex ^® -M System Control register is set.

If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished.

If an access to the domain bus matrix is ongoing, the Stop mode entry is delayed until the domain bus matrix access is complete.

See Table 48 below for details on how to enter to Stop mode.

Table 48. Stop mode

To allow peripherals having a kernel clock request to operate in Stop mode, the system must use SVOS high.

Note: Use a DSB instruction to ensure that outstanding memory transactions complete before entering stop mode.

Exiting from Stop mode

The Stop mode is exited according to Section 6.7.4: Exiting from low-power modes .

Refer to Table 48: Stop mode for more details on how to exit from Stop mode.

When exiting from Stop mode, the system clock, bus matrix clocks and voltage scaling are reset.

STOPF status flag in the PWR CPU control register 3 (PWR_CSR3) indicates that the system has exited from Stop mode.

I/O states in Stop mode

I/O pin configuration remain unchanged in Stop mode.

6.7.7 Standby mode

The Standby mode allows achieving the lowest power consumption. Like Stop mode, it is based on CPU subsystem Stop mode. However the \( V_{CORE} \) supply regulator is powered off.

When the system enters in Standby mode, the voltage regulator is disabled. The complete \( V_{CORE} \) domain is consequently powered off. The PLLs, HSI oscillator, CSI oscillator, HSI48 and the HSE oscillator are also switched off. SRAM and register contents are lost except for backup domain registers (RTC registers, RTC backup register and backup RAM), and Standby circuitry (see Section 6.4.4: Backup domain ).

In system Standby mode, the following features can be selected by programming individual control bits:

• • Independent watchdog (IWDG)
  The IWDG is started by programming its Key register or by hardware option. Once started, it cannot be stopped except by a reset (see Section 48.3 in Section 48: Independent watchdog (IWDG) ).
• • Real-time clock (RTC)
  This is configured via the RTCEN bit in the backup domain control register (RCC_BDCR).
• • Internal RC oscillator (LSI RC)
  This is configured by the LSION bit in the Control/status register (RCC_CSR).
• • External 32.768 kHz oscillator (LSE OSC)
  This is configured by the LSEON bit in the backup domain control register (RCC_BDCR).

Entering Standby mode

The Standby mode is entered according to Section 6.7.3: Entering low-power modes , when the PDDS bits in the PWR CPU control register 3 (PWR_CSR3) is set to one.

If Flash memory programming is ongoing, the Standby mode entry is delayed until the memory access is finished.

Refer to Table 50 for more details on how to enter to Standby mode.

Exiting from Standby mode

The Standby mode is exited according to Section 6.7.4: Exiting from low-power modes .

The system exits from Standby mode when an external Reset (NRST pin), an IWDG Reset, a WKUP pin event, a RTC alarm, a tamper event, or a time stamp event is detected. All registers are reset after waking up from Standby except for power control and status registers ( PWR control register 2 (PWR_CSR2) , PWR CPU control register 3 (PWR_CSR3) ), SBF bit in the PWR CPU control register 3 (PWR_CSR3) , PWR wake-up flag register (PWR_WKUPFR) , and PWR wake-up enable and polarity register (PWR_WKUPEPR) .

After waking up from Standby mode, the program execution restarts in the same way as after a system reset (boot option sampling, boot vector reset fetched, etc.). The SBF status flags in the PWR CPU control register 3 (PWR_CSR3) registers indicate from which mode the system has exited (refer to Table 50 ).

Table 49. Standby and Stop flags

Table 50. Standby mode

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance without pull, except for:

• • Reset pad (still available)
• • RTC_AF1 pin if configured for tamper, time stamp, RTC Alarm out, or RTC clock calibration out
• • WKUP pins (if enabled). The WKUP pin pull configuration can be defined through WKUPPUPD register bits in the PWR wake-up enable and polarity register (PWR_WKUPEPR)
• • I3C pin-pull configuration if enabled through the register PWR_APCR.

6.7.8 Monitoring low-power modes

The devices feature state monitoring pins to monitor the state transition to low-power mode (refer to Table 51 for the list of pins and their description). The GPIO pin corresponding to each monitoring signal has to be programmed in alternate function mode.

This feature is not available in Standby mode since these I/O pins are switched to high impedance.

Table 51. Low-power modes monitoring pin overview

The values of the monitoring pins reflect the state of the CPU and domains. Refer to Table 52 for the GPIO state depending on CPU and domain state.

Table 52. GPIO state according to CPU and domain state

1. 1. The CPU is powered off.

6.8 PWR registers

The PWR registers can be accessed in word, half-word and byte format, unless otherwise specified.

6.8.1 PWR control register 1 (PWR_CR1)

Address offset: 0x000

Reset value: 0x0000 0001

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:14 ALS[1:0] : Analog voltage detector level selection

These bits select the voltage threshold detected by the AVD.

00: AVD level 1

01: AVD level 2

10: AVD level 3

11: AVD level 4

Note: Refer to Section “Electrical characteristics” of the product datasheet for more details.

Bit 13 AVDEN : Peripheral voltage monitor on VDDA enable

0: Peripheral voltage monitor on VDDA disabled

1: Peripheral voltage monitor on VDDA enabled

Bit 12 AVDREADY : analog voltage ready

This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit).

It must be set by software when the expected VDDA analog supply level is available.

The correct analog supply level is indicated by the AVDO bit (PWR_CSR1 register) after setting the AVDEN bit and selecting the supply level to be monitored (ALS bits).

0: peripheral analog voltage VDDA not ready (default)

1: peripheral analog voltage VDDA ready

Bit 11 BOOSTE : analog switch VBoost control

This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range)

The VDD supply voltage can be monitored through the PVD and the PLS bits.

0: booster disabled (default)

1: booster enabled if analog voltage ready (AVD_READY = 1)

Bit 10 Reserved, must be kept at reset value.

This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode.

When it is set, the Flash memory enters low-power mode when device is in Stop mode.

• 0: Flash memory remains in normal mode when device enters Stop (quick restart time).
• 1: Flash memory enters low-power mode when device enters Stop mode (low-power consumption).

In reset state, the RCC_BDCR register, the RTC registers (including the backup registers and backup SRAM).
BREN and MOEN bits in the PWR_CSR1 register, are protected against parasitic write access.

This bit must be set to enable access to these registers.

• 0: Access to RTC, RTC backup registers disabled and backup SRAM write access disabled
• 1: Access to RTC, RTC backup registers and backup SRAM enabled

These bits select the voltage threshold detected by the PVD.

• 000: PVD level 1
• 001: PVD level 2
• 010: PVD level 3
• 011: PVD level 4
• 100: PVD level 5
• 101: PVD level 6
• 110: PVD level 7
• 111: External voltage level on PVD_IN pin
• 111: External voltage level on PVD_IN pin, compared to internal VREFINT level.

Note: Refer to Section “Electrical characteristics” of the product datasheet for more details.

• 0: Programmable voltage detector disabled.
• 1: Programmable voltage detector enabled

• 0: SVOS low
• 1: SVOS high (default)

6.8.2 PWR control status register 1 (PWR_SR1)

Address offset: 0x004

Reset value: 0x0000 0000

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 AVDO : Analog voltage detector output on VDDA

This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit.

0: VDDA is equal or higher than the AVD threshold selected with the ALS[1:0] bits.

1: VDDA is lower than the AVD threshold selected with the ALS[1:0] bits

Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set

Bits 12:5 Reserved, must be kept at reset value.

Bit 4 PVDO : Programmable voltage detect output

This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit.

0: VDD or PVD_IN voltage is equal or higher than the PVD threshold selected through the PLS[2:0] bits.

1: VDD or PVD_IN voltage is lower than the PVD threshold selected through the PLS[2:0] bits.

Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 ACTVOSRDY : Voltage levels ready bit for currently used ACTVOS and SDHILEVEL

This bit is set to 1 by hardware when the voltage regulator and the SMPS step-down converter are both disabled and Bypass mode is selected in PWR control register 2 (PWR_CSR2).

0: Voltage level invalid, above or below current ACTVOS and SDHILEVEL selected levels.

1: Voltage level valid, at current ACTVOS and SDHILEVEL selected levels.

Bit 0 ACTVOS : VOS currently applied for V _CORE voltage scaling selection.

These bit reflect the last VOS value applied to the PMU.

0: VOS low level

1: VOS high level

6.8.3 PWR control status register 1 (PWR_CSR1)

Address offset: 0x008

Reset value: 0x0000 0000

This register is not reset by wake-up from Standby mode, RESET signal and V _DD POR. It is only reset by V _SW POR and VSWRST reset.

This register must not be accessed when VSWRST bit in the RCC_BDCR register resets the V _SW domain.

After reset, the PWR_CSR1 register is write-protected. Prior to modifying its content, the DBP bit in the PWR_CR1 register must be set to disable the write protection.

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 TEMPH : Temperature level monitoring versus high threshold

0: Temperature below high threshold level.

1: Temperature equal or above high threshold level.

Bit 22 TEMPL : Temperature level monitoring versus low threshold

0: Temperature above low threshold level.

1: Temperature equal or below low threshold level.

Bit 21 VBATH : V _BAT level monitoring versus high threshold

0: V _BAT level below high threshold level.

1: V _BAT level equal or above high threshold level.

Bit 20 VBATL : V _BAT level monitoring versus low threshold

0: V _BAT level above low threshold level.

1: V _BAT level equal or below low threshold level.

Bits 19:17 Reserved, must be kept at reset value.

Bit 16 BRRDY : Backup regulator ready

This bit is set by hardware to indicate that the backup regulator is ready.

0: Backup regulator not ready.

1: Backup regulator ready.

Bits 15:5 Reserved, must be kept at reset value.

Bit 4 MONEN : \( V_{BAT} \) and temperature monitoring enable

When set, the \( V_{BAT} \) supply and temperature monitoring is enabled.

0: \( V_{BAT} \) and temperature monitoring disabled.

1: \( V_{BAT} \) and temperature monitoring enabled.

Note: \( V_{BAT} \) and temperature monitoring are only available when the backup regulator is enabled (BREN bit set to 1).

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 BREN : Backup regulator enable

When set, the backup regulator (used to maintain the backup RAM content in Standby and \( V_{BAT} \) modes) is enabled.

If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content is lost in Standby and \( V_{BAT} \) modes.

If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAMs maintained in Standby and \( V_{BAT} \) modes.

0: Backup regulator disabled.

1: Backup regulator enabled.

6.8.4 PWR control register 2 (PWR_CSR2)

Address offset: 0x00C

Reset value: 0x0000 0006

This register is reset only by a power-on reset (POR). It is not reset by a wake-up from Standby mode or RESET signal.

The lower byte of this register is written once after POR and must be written before entering low power mode, changing VOS level.

The lower byte of this register should be written as soon as possible after device start and the regulator state should be verified by reading ACTVOSRDY before entering the low power mode or changing VOS level.

No limitation applies to the upper bytes.

Programming data corresponding to an invalid combination of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS bits (see Table 44: Supply configuration control ) is ignored; data is not written because the written-once mechanism locks the register and any further write access is ignored.

The default supply configuration is kept, and the ACTVOSRDY bit in the PWR control status register 1 (PWR_SR1) continues to indicate invalid voltage levels. The system must be power cycled before writing a new value.

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 USBHHSREGEN : USB HS regulator enable.

0: USB HS PHY regulator disabled (default)

1: USB HS PHY regulator enabled

Note: This bit should only be set if USB HS is used

Bit 26 USB33RDY : USB supply ready.

0: USB33 supply not ready

1: USB33 supply ready.

Bit 25 USBREGEN : USB regulator enable.

0: USB regulator disabled

1: USB regulator enabled.

Bit 24 USB33DEN : VDD33USB voltage level detector enable

0: VDD33USB voltage level detector disabled

1: VDD33USB voltage level detector enabled.

Note: This bit should be set if USB HS, FS, or a GPIO on PMx is used

Bits 23:17 Reserved, must be kept at reset value.

Bit 16 SDEXTRDY : SMPS step-down converter external supply ready

This bit is set by hardware to indicate that the external supply from the SMPS step-down converter is ready.

0: External supply not ready.

1: External supply ready.

Bit 15 EN_XSPIM2 : this bit allows the SW to enable the XSPI interface, when available. The XSPIM_P2 supply must be stable prior to setting this bit. It should also be set when FMC is used.

0: XSPIM2 interface is not enabled

1: XSPIM2 interface is enabled

CAUTION: Not respecting this condition could damage the device.

Bit 14 EN_XSPIM1 : this bit allow the SW to enable the XSPI interface. The XSPIM_P1 supply must be stable prior to setting this bit.

0: XSPIM1 interface is not enabled

1: XSPIM1 interface is enabled

CAUTION not respecting this condition could damage the device

Bits 13:10 Reserved, must be kept at reset value.

Bit 9 VBRS : VBAT charging resistor selection

0: Charge VBAT through a 5 k \( \Omega \) resistor.

1: Charge VBAT through a 1.5 k \( \Omega \) resistor.

Bit 8 VBE : VBAT charging enable

0: VBAT battery charging disabled.

1: VBAT battery charging enabled.

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 SDHILEVEL : SMPS step-down converter voltage output for external supply.

This bit is used when SMPSEXTHP is enabled. In this case SDHILEVEL has to be set to 1 to confirm the regulator settings.

0: Reset value

1: 1.8V

Bit 3 SMPSEXTHP : SMPS external power delivery selection

0: SMPS normal operating mode, no power delivery to external circuits

1: SMPS external operating mode, power delivery to external circuits

Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 44.

Bit 2 SDEN : SMPS step-down converter enable

0: SMPS step-down converter disabled

1: SMPS step-down converter enabled. (Default)

Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 44.

Bit 1 LDOEN : Low drop-out regulator enable

0: Low drop-out regulator disabled.

1: Low drop-out regulator enabled (default)

Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 44.

Bit 0 BYPASS : Power management unit bypass

0: Power management unit normal operation.

1: Power management unit bypassed, voltage monitoring still active.

Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 44.

6.8.5 PWR CPU control register 3 (PWR_CSR3)

This register allows controlling the CPU power.

Address offset: 0x010

Reset value: 0x0000 0000

After Standby Reset value: 0x0000 0200

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 SBF : System Standby flag

This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU CSSF bit"

0: System has not been in Standby mode

1: System has been in Standby mode

Bit 8 STOPF : STOP flag

This bit is set by hardware and cleared only by any reset or by setting the CPU CSSF bit.

0: System has not been in Stop mode

1: System has been in Stop mode

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 CSSF : Clear Standby and Stop flags (always read as 0)

This bit is cleared to 0 by hardware.

0: No effect.

1: flags (STOPF, SBF) are cleared.

Bit 0 PDDS : Power Down Deepsleep.

This bit allows CPU to define the Deepsleep mode

0: Stop mode when device enters Deepsleep.

1: Standby mode when device enters Deepsleep.

6.8.6 PWR control status register 4 (PWR_CSR4)

Address offset: 0x014

Reset value: 0x0000 0002

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 VOSRDY : VOS Ready bit for \( V_{CORE} \) voltage scaling output selection.

When an internal regulator is used, this bit indicates that all the features allowed by the selected VOS can be used."

Note: When Bypass mode is selected in the PWR control register (PWR_CSR2), VOSRDY bit is set to 1 by hardware whatever the \( V_{CORE} \) level.

0: Not ready, voltage level below VOS selected level.

1: Ready, voltage level at or above VOS selected level.

Bit 0 VOS : Voltage scaling selection according to performance

These bits control the \( V_{CORE} \) voltage level and allow to obtains the best trade-off between power consumption and performance:

• – When increasing the performance, the voltage scaling must be changed before increasing the system frequency.
• – When decreasing performance, the system frequency must first be decreased before changing the voltage scaling.

0: VOS low level (default)

1: VOS high level

Note: Refer to Section “Electrical characteristics” of the product datasheet for more details.

6.8.7 PWR wake-up clear register (PWR_WKUPCR)

Address offset: 0x020

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 WKUPC4 :Clear wake-up pin flag for WKUP4

These bits are always read as 0.

0: No effect

1: Writing 1 clears the WKUPF4 wake-up pin flag (bit is cleared to 0 by hardware)

Bit 2 WKUPC3 :Clear wake-up pin flag for WKUP3

These bits are always read as 0.

0: No effect

1: Writing 1 clears the WKUPF3 wake-up pin flag (bit is cleared to 0 by hardware)

Bit 1 WKUPC2 :Clear wake-up pin flag for WKUP2

These bits are always read as 0.

0: No effect

1: Writing 1 clears the WKUPF2 wake-up pin flag (bit is cleared to 0 by hardware)

Bit 0 WKUPC1 :Clear wake-up pin flag for WKUP1

These bits are always read as 0.

0: No effect

1: Writing 1 clears the WKUPF1 wake-up pin flag (bit is cleared to 0 by hardware)

6.8.8 PWR wake-up flag register (PWR_WKUPFR)

Address offset: 0x024

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 WKUPF4 : Wake-up pin WKUP4 flag.

This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC4 bit in the PWR wake-up clear register (PWR_WKUPCR).

0: No wake-up event occurred

1: A wake-up event was received from WKUP4 pin

Bit 2 WKUPF3 : Wake-up pin WKUP3 flag.

This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC3 bit in the PWR wake-up clear register (PWR_WKUPCR).

0: No wake-up event occurred

1: A wake-up event was received from WKUP3 pin

Bit 1 WKUPF2 : Wake-up pin WKUP2 flag.

This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC2 bit in the PWR wake-up clear register (PWR_WKUPCR).

0: No wake-up event occurred

1: A wake-up event was received from WKUP2 pin

Bit 0 WKUPF1 : Wake-up pin WKUP1 flag.

This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC1 bit in the PWR wake-up clear register (PWR_WKUPCR).

0: No wake-up event occurred

1: A wake-up event was received from WKUP1 pin

6.8.9 PWR wake-up enable and polarity register (PWR_WKUPEPR)

Address offset: 0x028

Reset value: 0x0000 0000

(Reset value after Standby: the value of the register is kept in Standby mode.)

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 WKUPPUPDn[1:0] : Wake-up pin pull configuration for WKUPn, (n = 4 to 1)

These bits define the I/O pad pull configuration used when WKUPENn = 1. The associated GPIO port pull configuration must be set to the same value or to 00.

The wake-up pin pull configuration is kept in Standby mode.

00: No pull-up

01: Pull-up

10: Pull-down

11: Reserved

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:8 WKUPP[4:1] : Wake-up pin polarity bit for WKUPn, (n = 4, 3, 2, 1)

These bits define the polarity used for event detection on WKUPn external wake-up pin.

0: Detection on high level (rising edge)

1: Detection on low level (falling edge)

Bits 7:4 Reserved, must be kept at reset value.

Bits 3:0 WKUPEN[4:1] : Enable wake-up Pin WKUPn, (n = 4, 3, 2, 1)

Each bit is set and cleared by software.

0: An event on WKUPn pin does not wake the system up from Standby mode.

1: A rising or falling edge on WKUPn pin wakes the system up from Standby mode.

Note: An additional wake-up event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge.

6.8.10 PWR USB Type-C and Power Delivery register (PWR_UCPDR)

Address offset: 0x02C

Reset value: 0x0000 0002

(Reset value after Standby: the value of the register is kept in Standby mode.)

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 UCPD_STBY : UCPD Standby mode

When set, this bit is used to memorize the UCPD configuration in Standby mode.

This bit must be written to 1 just before entering Standby mode when using UCPD.

It must be written to 0 after exiting the Standby mode and before writing any UCPD registers.

Bit 0 UCPD_DBDIS : UCPD dead battery disable

After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable).

0: UCPD dead battery pull-down behavior enabled on UCPDx_CC1 and UCPDx_CC2 pins

1: UCPD dead battery pull-down behavior disabled on UCPDx_CC1 and UCPDx_CC2 pins

6.8.11 PWR apply pull configuration register (PWR_APCR)

Address offset: 0x030

Reset value: 0x0003 0000

(Reset value after Standby: the value of the register is kept in Standby mode.)

Bit 31 I3CPB9_PU : Port PB9 I3C pull-up bit

When I3C is used on PB9, when set, this bit activates the pull-up on I3C1_SDA (PB9) in standby mode.

Bit 30 I3CPB8_PU : Port PB8 I3C pull-up bit

When I3C is used on PB8, when set, this bit activates the pull-up on I3C1_SCL (PB8) in standby mode.

Bit 29 I3CPB7_PU : Port PB7 I3C pull-up bit

When I3C is used on PB7, when set, this bit activates the pull-up on I3C1_SDA (PB7) in standby mode.

Bit 28 I3CPB6_PU : Port PB6 I3C pull-up bit

When I3C is used on PB6, when set, this bit activates the pull-up on I3C1_SCL (PB6) in standby mode.

Bits 27:18 Reserved, must be kept at reset value.

Bit 17 PO5_PUPD : Port O bit 5 pull-up/down configuration

When this bit is set, a weak pull-up or pull down resistor is applied on PO5 following inverse logic applied on PO4.

If the PUO4 bit in PWR_PUCRO register is set and APC bit is set the weak pull-down is applied on PO5.

If the PDO4 bit in PWR_PDCRO register is set and APC bit is set the weak pull-up is applied on PO5..

Bit 16 PN7_PUPD : Port N bit 7 pull-up/down configuration

When this bit is set, a weak pull-up or pull-down resistor is applied on PN7 following inverse logic applied on PN6.

If the PUN6 bit in PWR_PUCRN register is set and APC bit is set the weak pull-down is applied on PN7.

If the PDN6 bit in PWR_PDCRN register is set and APC bit is set the weak pull-up is applied on PN7.

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 APC : Apply pull-up and pull-down configuration

When this bit is set, the I/O pull-up and pull-down configurations defined in PO5_PUPD, PN7_PUPD bits and PUCRx, PDCRx registers are applied in Standby mode even after wake-up until APC bit is reset to 0.

When this bit is cleared, the I/O pull-up or pull-down configurations defined in PO5_PUPD, PN7_PUPD bits and PUCRx and PDCRx registers are not applied in Standby mode and IO becomes Hi-Z.

6.8.12 PWR port N pull-up control register (PWR_PUCRN)

Address offset: 0x034

Reset value: 0x0000 0000 (POR and System Reset)

(Reset value after Standby: the value of the register is kept in Standby mode.)

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 PUN12 : Port N pull-up bit 12

When set, each bit activates the pull-up on PN12 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD12 bit is also set.

Bits 11:7 Reserved, must be kept at reset value.

Bit 6 PUN6 : Port N pull-up bit 6

When set activates the pull-up on PN6 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PDN6 bit is also set.

Bits 5:2 Reserved, must be kept at reset value.

Bit 1 PUN1 : Port N pull-up bit 1

When set, each bit activates the pull-up on PN1 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD1 bit is also set.

Bit 0 Reserved, must be kept at reset value.

6.8.13 PWR port N pull-down control register (PWR_PDCRN)

Address offset: 0x038

Reset value: 0x0000 0000

(Reset value after Standby: the value of the register is kept in Standby mode.)

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 PDN12 : Port N pull-down bit 12

When set activates the pull-down on PN12 when the APC bit is set in PWR_APCR.

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 PDN8N11 : Port N - PN8 to PN11 pull-down activation

When set, four pull-down resistors are activated on PN8 to PN11 when the APC bit is set in PWR_APCR.

Bit 7 Reserved, must be kept at reset value.

Bit 6 PDN6 : Port N pull-down bit 6

When set activates the pull-down on PN6 when the APC bit is set in PWR_APCR.

Bits 5:3 Reserved, must be kept at reset value.

Bit 2 PDN2N5 : Port N PN2 to PN5 pull-down activation

When set, four pull-down resistors are activated on PN2 to PN5 when the APC bit is set in PWR_APCR.

Bit 1 PDN1 : Port N pull-down bit 1

When set activates the pull-down on PN1 when the APC bit is set in PWR_APCR.

Bit 0 PDN0 : Port N pull-down bit 0

When set activates the pull-down on PN0 when the APC bit is set in PWR_APCR.

6.8.14 PWR port O pull-up control register (PWR_PUCRO)

Address offset: 0x03C

Reset value: 0x0000 0000

(Reset value after Standby: the value of the register is kept in Standby mode.)

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 PUO4 : Port O pull-up bit 4

When set activates the pull-up on PO4 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits PDO4 in PWR_PDCRO is also set.

Bits 3:2 Reserved, must be kept at reset value.

Bits 1:0 PUOn : (n = 1 to 0) Port O pull-up bits

When set, each bit activates the pull-up on POy when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits in PWR_PDCRO is also set.

6.8.15 PWR port O pull-down control register (PWR_PDCRO)

Address offset: 0x040

Reset value: 0x0000 0000

(Reset value after Standby: the value of the register is kept in Standby mode.)

Bits 31:5 Reserved, must be kept at reset value.

Bits 4:0 PDOy : Port O pull-down bit y (y = 4 to 0)

When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR.

6.8.16 PWR port P pull-down control register (PWR_PDCRP)

Address offset: 0x044

Reset value: 0x0000 0000

(Reset value after Standby: the value of the register is kept in Standby mode.)

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 PDP12P15 : Port P12-P15 pull-down activation

When set, four pull-down resistors are activated on P8 to P11 when the APC bit is set in PWR_APCR.

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 PDP8P11 : Port P8-P11 pull-down activation

When set, four pull-down resistors are activated on P8 to P11 when the APC bit is set in PWR_APCR.

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 PDP4P7 : Port P4-P7 pull-down activation

When set, four pull-down resistors are activated on P4 to P7 when the APC bit is set in PWR_APCR.

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 PDP0P3 : Port P0-P3 pull-down activation

When set, four pull-down resistors are activated on P0 to P3 when the APC bit is set in PWR_APCR.

6.8.17 PWR register map

Table 53. Power control register map and reset values

Table 53. Power control register map and reset values (continued)

Refer to Section 2.3 on page 150 for the register boundary addresses.