2. Memory and bus architecture

2.1 System architecture

The STM32H7Rx/7Sx architecture relies on a Arm Cortex-M7 core optimized for execution by means of Cache, TCM, AXI, and an AHB bus matrix. This architecture also features a 64-bit AXI, an 32-bit multilayer AHB bus matrix, and bus bridges allow interconnection of bus masters with bus slaves, as shown in Table 2: Bus-master-to-bus-slave interconnect .

Table 2. Bus-master-to-bus-slave interconnect

1. Bold font type denotes 64-bit bus, plain type denotes 32-bit bus.

2. "X" = access possible, "-" = access not possible.

3. Every transfer can be done in 64 bits

4. Refer to Table 102: Programmed HPDMA1 request for the AHB/APB peripheral request.

5. Refer to Table 94: Programmed GPDMA1 trigger

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. This architecture is shown in the figure below.

Figure 1. System architecture

2.1.1 Bus matrices

AXI bus matrix

The multi AXI bus matrix ensures and arbitrates concurrent accesses from multiple masters to multiple slaves. This allows efficient simultaneous operation of high-speed peripherals.

The arbitration uses a round-robin algorithm with QoS capability.

Refer to Section 2.2: AXI interconnect matrix (AXIM) for more information on AXI interconnect.

AHB bus matrices

The AHB bus matrices ensure and arbitrate concurrent accesses from multiple masters to multiple slaves. This allows efficient simultaneous operation of high-speed peripherals.

The arbitration uses a round-robin algorithm.

2.1.2 Bus-to-bus bridges

To allow peripherals with different types of buses to communicate together, there is a number of bus-to-bus bridges in the system.

The AHB/APB bridges allow connecting peripherals on APB1, APB2, APB4, APB5 to AHB1, AHB2, AHB4 and AHB5, respectively. These AHB/APB bridges provide full synchronous interfacing, which allows the APB peripherals to operate with clocks independent of AHB that they connect to.

The AHB/APB bridges also allow APB1, APB2 and APB4 peripherals to connect to GPDMA1 peripheral buses, without transiting through the AHB BUS.

The AHB/APB bridges convert 8-bit / 16-bit APB data to 32-bit AHB data, by replicating it to the three upper bytes / the upper half-word of the 32-bit word.

The AXI bus matrix incorporates AHB/AXI bus bridge functionality on its slave bus interfaces. The AXI/AHB bus bridges on its master interfaces marked as 32-bit in Figure 1: System architecture are outside the matrix.

The Cortex-M7 CPU provides AHB/TCM-bus (ITCM and DTCM buses) translation from its AHBS slave AHB, allowing the HPDMA controller to access the ITCM and DTCM.

Note: When a 8- or 16-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 8- or 16-bit data to feed the 32-bit vector.

2.1.3 TCM-buses

The DTCM and ITCM (data and instruction tightly coupled RAMs) are connected through dedicated TCM buses directly to the Cortex-M7 core. The HPDMA controller can access the DTCM and ITCM through AHBS, a specific CPU slave AHB. The DTCM and ITCM are accessed by Cortex-M7 at CPU clock speed, with zero wait states.

2.1.4 CPU buses

Cortex-M7 AXIM bus

The Cortex-M7 CPU uses the 64-bit AXIM bus to access all memories (excluding ITCM, and DTCM)

The AXIM bus connects the CPU to the AXI bus matrix in the core domain.

Cortex-M7 ITCM bus

The Cortex-M7 CPU uses the 64-bit ITCM bus for fetching instructions from and accessing data in the ITCM.

Cortex-M7 DTCM bus

The Cortex-M7 CPU uses the 2x32-bit DTCM bus for accessing data in the DTCM. The 2x32-bit DTCM bus allows load/load and load/store instruction pairs to be dual-issued on the DTCM memory. It can also fetch instructions.

Cortex-M7 AHBS bus

The Cortex-M7 CPU uses the 32-bit AHBS slave bus to allow the HPDMA controller to access the ITCM and the DTCM.

Cortex-M7 AHBP bus

The Cortex-M7 CPU uses the 32-bit AHBP bus for accessing AHB1, AHB2, AHB3, AHB4, APB1, APB2 and APB4 peripherals via the AHB bus matrix.

2.1.5 Bus master peripherals

SDMMC1-bus

The SDMMC1 uses a 32-bit bus, connected to the AXI bus matrix, through which it can access internal AXI SRAM and Flash memories, and external memories through the XSPIs controller and the FMC.

SDMMC2-bus

The SDMMC2 uses a 32-bit bus, connected to the AHB bus matrix. Through the system bus matrices, it can access the internal AXI SRAM, SRAM1, SRAM2, SRAM3 SRAM4, backup RAM, Flash memory, and external memories through the XSPIs controller and the FMC.

HPDMA-bus

The HPDMA controller has two bus masters: an AXI 64-bit bus, connected to the AXI bus matrix and an AHB 32-bit bus connected to the Cortex-M7 AHBS slave bus.

The HPDMA is optimized for DMA data transfers between memories since it supports linked list transfers that allow performing a chained list of transfers without the need for CPU intervention. Through the system bus matrices and the Cortex-M7 AHBS slave bus, the HPDMA can access all internal and external memories through the CTOSPIs controller and the FMC.

GPDMA-bus

The GPDMA controller has two 32-bit AHB bus masters connected to the AHB bus matrix.

The memory bus allows the GPDMA data transfers between memories. Through the system bus matrices, the memory bus can access all internal memories except ITCM and DTCM, and external memories through the XSPIs controller and the FMC. It also supports linked list transfers

The peripheral bus allows the GPDMA data transfers between two peripherals, between two memories or between a peripheral and a memory. Through the system bus matrices, the peripheral bus can access all internal memories except ITCM and DTCM, external memories through the XSPIs controller and the FMC, and all AHB and APB peripherals. A direct access to APB1 and APB2 is available, without passing through AHB1.

DMA2D-bus (Chrom-Art Accelerator)

The DMA2D graphics accelerator uses a 64-bit bus, connected to the AXI bus matrix. Through the system bus matrices, internal AXI SRAM, SRAM1, SRAM2, SRAM3, SRAM4 Flash memories and external memories through the XSPIs controller and the FMC.

LTDC-bus (LCD-TFT controller)

The LCD-TFT display controller, LTDC, uses a 64-bit bus, connected to the AXI bus matrix, through which it can access internal AXI SRAM and external memories through the XSPIs controller and the FMC.

Ethernet MAC-bus

The Ethernet MAC uses a 32-bit bus, connected to the AHB bus matrix. Through the system bus matrices, it can access all internal memories except backup RAM, ITCM, DTCM it can also access external memories, through the XSPIs controller and the FMC.

USB OTG-bus

The USBHS1 peripheral uses 32-bit buses, connected to the AHB bus matrix. Through the system bus matrices, it can access all internal memories except backup RAM, ITCM, DTCM and it access the external memories, through the XSPIs controller and the FMC.

2.1.6 GPU2D-bus

These buses connect the GPU2D master interfaces to the bus matrix. These buses are used to load/store data from/to the memory. These buses target the GFXMMU in addition to the data memories: internal Flash memory, internal SRAMs (SRAM1, SRAM2, SRAM3 and SRAM4) and external memories through FMC, XSPIs. A 16-Kbyte data cache (ICACHE) is present on the GPU2D M0 bus in order to improve performances.

2.1.7 GFXMMU-bus

This bus connects the GFXMMU master interface to the bus matrix. This bus is used only by the GFXMMU to load/store data from/to the memory. This bus targets the data memories: internal Flash memory, internal SRAMs (SRAM1, SRAM2, SRAM3 and SRAM4) and external memories through FMC, XSPIs. The GFXMMU has also a slave bus connection to be accessed by graphical peripheral master buses.

2.1.8 Clocks to functional blocks

Upon reset, clocks to blocks such as peripherals and some memories are disabled (except for the SRAM, DTCM, ITCM and Flash memory). To operate a block with no clock upon reset, the software must first enable its clock through RCC_AHBxENR or RCC_APBxENR register, respectively.

2.2 AXI interconnect matrix (AXIM)

2.2.1 AXI introduction

The AXI (advanced extensible interface) interconnect is based on the Arm® CoreLink™ NIC-400 Network Interconnect. The interconnect has eleven initiator ports, or ASIBs (AMBA slave interface blocks), and ten target ports, or AMIBs (AMBA master interface blocks). The ASIBs are connected to the AMIBs via an AXI switch matrix.

Each ASIB is a slave on an AXI bus or AHB (advanced high-performance bus). Similarly, each AMIB is a master on an AXI or AHB bus. Where an ASIB or AMIB is connected to an AHB, it converts between the AHB and the AXI protocol.

The AXI interconnect includes a GPV (global programmer view) which contains registers for configuring certain parameters, such as the QoS (quality of service) level at each ASIB.

Any accesses to unallocated address space are handled by the default slave, which generates the return signals. This ensures that such transactions complete and do not block the issuing master and ASIB.

2.2.2 AXI interconnect main features

• • 64-bit AXI bus switch matrix with eleven ASIBs and ten AMIBs
• • AHB/AXI bridge function built into the ASIBs
• • concurrent connectivity of multiple ASIBs to multiple AMIBs
• • programmable traffic priority management (QoS - quality of service)
• • software-configurable via GPV

2.2.3 AXI interconnect functional description

Block diagram

The AXI interconnect is shown in Figure 2 .

Figure 2. AXI interconnect

ASIB configuration

Table 3 summarizes the characteristics of the ASIBs.

Table 3. ASIB configuration

AMIB configuration

Table 4 summarizes the characteristics of the AMIBs.

Table 4. AMIB configuration

1. 1. Conversion to AHB protocol is done via an AXI/AHB bridge sitting between AXI interconnect and the connected slave.
2. 2. SRAM shared with the ECC ( Table 11: SRAM4 / ECC configurations )
3. 3. SRAM shared with the DTCM ( SRAM3 / DTCM configurations )
4. 4. SRAM shared with the ITCM ( SRAM1 / ITCM configurations )

Quality of service (QoS)

The AXI switch matrix uses a priority-based arbitration when two ASIB simultaneously attempt to access the same AMIB. Each ASIB has programmable read channel and write channel priorities, known as QoS, from 0 to 15, such that the higher the value, the higher the priority. The read channel QoS value is programmed in the AXI interconnect - INI x read QoS register (AXI_INIx_READ_QOS) , and the write channel in the AXI interconnect - INI x write QoS register (AXI_INIx_WRITE_QOS) . The default QoS value for all channels is 0 (lowest priority).

If two coincident transactions arrive at the same AMIB, the higher priority transaction passes before the lower priority. If the two transactions have the same QoS value, then a least-recently-used (LRU) priority scheme is adopted.

The QoS values should be programmed according to the latency requirements for the application. Setting a higher priority for an ASIB ensures a lower latency for transactions initiated by the associated bus master. This can be useful for real-time-constrained tasks, such as graphics processing (LTDC, DMA2D). Assigning a high priority to masters that can make many and frequent accesses to the same slave (such as the Cortex-M7 CPU) can block access to that slave by other lower-priority masters.

Global programmer view (GPV)

The GPV contains configuration registers for the AXI interconnect. These registers are only accessible by the Cortex-M7 CPU.

2.2.4 AXI interconnect registers

AXI interconnect - peripheral ID4 register (AXI_PERIPH_ID_4)

Address offset: 0x1FD0

Reset value: 0x0000 0004

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 COUNT4K[3:0] : Register file size

0x0: N/A

Bits 3:0 JEP106CON[3:0] : JEP106 continuation code

0x4: Arm ^®

AXI interconnect - peripheral ID0 register (AXI_PERIPH_ID_0)

Address offset: 0x1FE0

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PARTNUM[7:0] : Peripheral part number bits 0 to 7

0x00: Part number = 0x400

Address offset: 0x1FE4

Reset value: 0x0000 00B4

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 JEP106ID[3:0] : JEP106 identity bits 0 to 3
0xB: Arm® JEDEC code

Bits 3:0 PARTNUM[11:8] : Peripheral part number bits 8 to 11
0x4: Part number = 0x400

Address offset: 0x1FE8

Reset value: 0x0000 003B

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 REVISION[3:0] : Peripheral revision number
0x3: r0p3

Bit 3 JEDEC : JEP106 code flag
0x1: JEDEC allocated code

Bits 2:0 JEP106ID[6:4] : JEP106 Identity bits 4 to 6
0x3: Arm® JEDEC code

Address offset: 0x1FF0

Reset value: 0x0000 000D

Bits 31:8 Reserved, must be kept at reset value.

0xD: Common ID value

Address offset: 0x1FF4

Reset value: 0x0000 00F0

Bits 31:8 Reserved, must be kept at reset value.

0xF: Generic IP component class

0x0: Common ID value

Address offset: 0x1FF8

Reset value: 0x0000 0005

Bits 31:8 Reserved, must be kept at reset value.

0x05: Common ID value

Address offset: 0x1FFC

Reset value: 0x0000 00B1

Bits 31:8 Reserved, must be kept at reset value.

0xB1: Common ID value

AXI interconnect - TARG x bus matrix issuing functionality register
(AXI_TARGx_FN_MOD_ISS_BM)

Address offset: 0x1008 + 0x1000 * x, (x = 1 to 10)

Reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 WRITE_ISS_OVERRIDE : Switch matrix write issuing override for target

0: Normal issuing capability

1: Set switch matrix write issuing capability to 1

Bit 0 READ_ISS_OVERRIDE : Switch matrix read issuing override for target

0: Normal issuing capability

1: Set switch matrix read issuing capability to 1

AXI interconnect - TARG x issuing functionality modification register
(AXI_TARGx_FN_MOD)

Address offset: 0x1108+ 0x1000 * x, (x = 1 to 10)

Reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 WRITE_ISS_OVERRIDE : Override AMIB write issuing capability

0: Normal issuing capability

1: Force issuing capability to 1

Bit 0 READ_ISS_OVERRIDE : Override AMIB read issuing capability

0: Normal issuing capability

1: Force issuing capability to 1

AXI interconnect - TARG x bus matrix functionality 2 register
(AXI_TARG2_FN_MOD2)

Address offset: 0x3024

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 BYPASS_MERGE : Disable packing of beats to match the output data width. Unaligned transactions are not realigned to the input data word boundary.

0: Normal operation

1: Disable packing

AXI interconnect - TARG x long burst functionality modification register
(AXI_TARG2_FN_MOD_LB)

Address offset: 0x302C

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 FN_MOD_LB : Controls burst breaking of long bursts

0: Long bursts can not be generated at the output of the AMIB

1: Long bursts can be generated at the output of the AMIB

AXI interconnect - INIx issuing functionality modification register (AXI_INIx_FN_MOD)

Address offset: 0x41108+ 0x10000 * x, (x = 1 to 11)

Reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 WRITE_ISS_OVERRIDE : Override ASIB write issuing capability

0: Normal issuing capability

1: Force issuing capability to 1

Bit 0 READ_ISS_OVERRIDE : Override ASIB read issuing capability

0: Normal issuing capability

1: Force issuing capability to 1

AXI interconnect - INI x write QoS register (AXI_INIx_WRITE_QOS)

Address offset: 0x41104 + 0x1000 * x, (x = 1 to 11)

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 AW_QOS[3:0] : Write channel QoS setting

0x0: Lowest priority

0xF: Highest priority

AXI interconnect - INI x issuing functionality modification register (AXI_INIx_FN_MOD2)

Address offset: \( 0x41024 + 0x1000 * x \) , ( \( x = 1 \) to \( 2 \) )

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 BYPASS_MERGE : Disable packing of beats to match the output data width. Unaligned transactions are not realigned to the input data word boundary.

0: Normal operation

1: Disable packing

AXI interconnect - INI x read QoS register (AXI_INIx_READ_QOS)

Address offset: \( 0x41100 + 0x1000 * x \) , ( \( x = 1 \) to \( 11 \) )

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 AR_QOS[3:0] : Read channel QoS setting

0x0: Lowest priority

0xF: Highest priority

2.2.5 AXI interconnect register map

Table 5. AXI interconnect register map and reset values

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

2.3 Memory organization

2.3.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

2.3.2 Memory map and register boundary addresses

Figure 3. Memory map

All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following table.

The following tables gives, the default memory attribute and the boundary addresses of the peripherals available in the devices.

Table 6. Memory map and default device memory area attribute

Table 6. Memory map and default device memory area attribute