RM0477-STM32H7Rx-7Sx

This reference manual targets application developers. It provides complete information on how to use the STM32H7R3, STM32H7S3, STM32H7R7, and STM32H7S7 memory and peripherals.

Microcontrollers of the STM32H7R3/7S3 and STM32H7R7/7S7 lines have different memory sizes, packages, and peripherals. They are referred to as STM32H7Rx/7Sx hereafter.

For ordering information, mechanical, and electrical device characteristics refer to the corresponding datasheets.

For information on the Arm ® Cortex ® -M7 with FPU core, refer to the corresponding Arm technical reference manual available from www.arm.com .

STM32H7Rx/7Sx microcontrollers include ST state-of-the-art patented technology.

Contents

3.2RAMECC main features . . . . .165
3.3RAMECC functional description . . . . .165
3.3.1RAMECC internal signals . . . . .167
3.3.2RAMECC monitor mapping . . . . .168
3.3.3ECC fault injection test on SRAM1, SRAM3, and TCM . . . . .169
3.4RAMECC low-power modes . . . . .169
3.5RAMECC interrupts . . . . .170
3.6RAMECC registers . . . . .171
3.6.1RAMECC interrupt enable register (RAMECC_IER) . . . . .171
3.6.2RAMECC monitor x configuration register
(RAMECC_MxCN) . . . . .		172
3.6.3RAMECC monitor x status register
(RAMECC_MxSR) . . . . .		174
3.6.4RAMECC monitor x failing address register
(RAMECC_MxFAR) . . . . .		174
3.6.5RAMECC monitor x failing data low register
(RAMECC_MxFDRL) . . . . .		175
3.6.6RAMECC monitor x failing data high register
(RAMECC_MxFDRH) . . . . .		175
3.6.7RAMECC monitor x failing ECC error code register
(RAMECC_MxFECR) . . . . .		176
3.6.8RAMECC register map . . . . .177
4System security . . . . .178
4.1Key security features . . . . .178
4.2Secure install . . . . .179
4.3Secure boot . . . . .180
4.3.1Unique boot entry . . . . .180
4.3.2Security services in system flash memory . . . . .181
4.4Secure update . . . . .183
4.5Resource isolation using hide protect levels . . . . .183
4.5.1Temporal isolation using secure hide protection (HDP) . . . . .183
4.6Secure execution . . . . .184
4.6.1Memory protection unit (MPU) . . . . .184
4.6.2Embedded flash memory write protection . . . . .184
4.6.3Tamper detection and response . . . . .184
4.7Secure storage . . . . .187
4.7.1Hardware secret key management . . . . .188
4.7.2Unique ID .....189
4.8Crypto engines .....189
4.8.1Crypto engines features .....189
4.8.2Secure AES co-processor (SAES) .....190
4.8.3Memory cipher engine (MCE) .....190
4.9Product life cycle .....191
4.9.1Product configurations and security services .....192
4.9.2Recommended product settings .....193
4.10System memory .....193
4.10.1Introduction .....193
4.10.2RSS user functions .....193
5Embedded flash memory (FLASH) .....200
5.1Introduction .....200
5.2FLASH main features .....200
5.3FLASH functional description .....201
5.3.1FLASH block diagram .....201
5.3.2FLASH internal signals .....202
5.3.3FLASH architecture and integration in the system .....202
5.3.4Flash memory architecture and usage .....204
5.3.5Flash hide protection schemes .....208
5.3.6Overview of FLASH operations .....209
5.3.7FLASH read operations .....210
5.3.8FLASH program operations .....212
5.3.9FLASH erase operations .....216
5.3.10Flash memory error protections .....218
5.3.11FLASH one-time programmable area .....219
5.3.12FLASH read-only area .....221
5.3.13FLASH reset and clocks .....221
5.4FLASH option bytes .....222
5.4.1About option bytes .....222
5.4.2Option byte loading .....222
5.4.3Option byte words modification .....223
5.4.4Option byte key management .....225
5.4.5Option byte user words overview .....226
5.4.6Description of user option byte word .....228
5.4.7Description of security option bytes . . . . .229
5.5FLASH protection mechanisms . . . . .231
5.5.1FLASH configuration protection . . . . .231
5.5.2Write protection . . . . .232
5.5.3Life cycle management . . . . .233
5.5.4Hide protected system flash area . . . . .234
5.5.5Hide protected user flash area . . . . .234
5.6FLASH low-power modes . . . . .237
5.6.1Introduction . . . . .237
5.6.2Managing the FLASH domain switching to Stop or Standby . . . . .237
5.7FLASH error management . . . . .238
5.7.1Introduction . . . . .238
5.7.2Write protection error (WRPERRF) . . . . .238
5.7.3Programming sequence error (PGSERRF) . . . . .239
5.7.4Strobe error (STRBERRF) . . . . .239
5.7.5Inconsistency error (INCERRF) . . . . .240
5.7.6Error correction code error (SNECCERRF/DBECCERRF) . . . . .240
5.7.7Read secure error (RDSERRF) . . . . .241
5.7.8CRC read error (CRCRDERRF) . . . . .241
5.7.9Option byte change error (OPTERRF) . . . . .241
5.7.10Key valid error (KVEF) . . . . .242
5.7.11Key transfer error (KTEF) . . . . .242
5.7.12Option byte loading error (OBLERRF) . . . . .242
5.7.13Miscellaneous HardFault errors . . . . .243
5.8FLASH interrupts . . . . .243
5.9FLASH registers . . . . .245
5.9.1FLASH access control register (FLASH_ACR) . . . . .245
5.9.2FLASH control key register (FLASH_KEYR) . . . . .246
5.9.3FLASH control register (FLASH_CR) . . . . .246
5.9.4FLASH status register (FLASH_SR) . . . . .249
5.9.5FLASH interrupt enable register (FLASH_IER) . . . . .251
5.9.6FLASH interrupt status register (FLASH_ISR) . . . . .252
5.9.7FLASH interrupt clear register (FLASH_ICR) . . . . .254
5.9.8FLASH CRC control register (FLASH_CRCCR) . . . . .255
5.9.9FLASH CRC start address register (FLASH_CRCSADDR) . . . . .256
5.9.10FLASH CRC end address register (FLASH_CRCEADDR) . . . . .257
5.9.11FLASH CRC data register (FLASH_CRCDATAR) . . . . .257
5.9.12FLASH ECC single error fail address (FLASH_ECCSFADDR) . . . . .258
5.9.13FLASH ECC double error fail address (FLASH_ECCDFADDR) . . . . .258
5.9.14FLASH options key register (FLASH_OPTKEYR) . . . . .259
5.9.15FLASH options control register (FLASH_OPTCR) . . . . .259
5.9.16FLASH options interrupt status register (FLASH_OPTISR) . . . . .260
5.9.17FLASH options interrupt clear register (FLASH_OPTICR) . . . . .261
5.9.18FLASH option byte key control register (FLASH_OBKCR) . . . . .262
5.9.19FLASH option bytes key data register x (FLASH_OBKDRx) . . . . .263
5.9.20FLASH non-volatile status register (FLASH_NVSR) . . . . .263
5.9.21FLASH security status register programming (FLASH_NVS RP) . . . . .264
5.9.22FLASH RoT status register (FLASH_ROTSR) . . . . .265
5.9.23FLASH RoT status register programming (FLASH_ROTSRP) . . . . .266
5.9.24FLASH OTP lock status register (FLASH_OTPLSR) . . . . .266
5.9.25FLASH OTP lock status register programming (FLASH_OTPLSRP) . . . . .267
5.9.26FLASH write protection status register (FLASH_WRPSR) . . . . .267
5.9.27FLASH write protection status register programming
(FLASH_WRPSRP) . . . . .		268
5.9.28FLASH hide protection status register (FLASH_HDPSR) . . . . .268
5.9.29FLASH hide protection status register programming
(FLASH_HDPSRP) . . . . .		269
5.9.30FLASH epoch status register (FLASH_EPOCHSR) . . . . .270
5.9.31FLASH RoT status register programming (FLASH_EPOCHSRP) . . . . .270
5.9.32FLASH option byte word 1 status register (FLASH_OBW1SR) . . . . .271
5.9.33FLASH option byte word 1 status register programming
(FLASH_OBW1SRP) . . . . .		272
5.9.34FLASH option byte word 2 status register (FLASH_OBW2SR) . . . . .273
5.9.35FLASH option byte word 2 status register programming
(FLASH_OBW2SRP) . . . . .		274
5.9.36FLASH register map . . . . .275
6Power control (PWR) . . . . .279
6.1Introduction . . . . .279
6.2PWR main features . . . . .279
6.3PWR block diagram . . . . .280
6.3.1PWR pins and internal signals . . . . .281
6.4Power supplies . . . . .283
6.4.1System supply startup . . . . .287
6.4.2Core domain . . . . .290
6.4.3PWR external supply . . . . .292
6.4.4Backup domain . . . . .292
6.4.5VBAT battery charging . . . . .294
6.4.6Analog supply . . . . .295
6.4.7USB regulator . . . . .296
6.5Power supply supervision . . . . .297
6.5.1Power-on reset (POR)/power-down reset (PDR) . . . . .297
6.5.2Brownout reset (BOR) . . . . .298
6.5.3Programmable voltage detector (PVD) . . . . .299
6.5.4Analog voltage detector (AVD) . . . . .300
6.5.5Battery voltage thresholds . . . . .301
6.5.6Temperature thresholds . . . . .302
6.5.7VCORE maximum voltage level detector . . . . .303
6.6Power management . . . . .304
6.6.1Operating modes . . . . .304
6.6.2Voltage scaling . . . . .305
6.6.3Power management examples . . . . .306
6.7Low-power modes . . . . .309
6.7.1Slowing down system clocks . . . . .310
6.7.2Controlling peripheral clocks . . . . .310
6.7.3Entering low-power modes . . . . .310
6.7.4Exiting from low-power modes . . . . .310
6.7.5Sleep mode . . . . .312
6.7.6Stop mode . . . . .312
6.7.7Standby mode . . . . .315
6.7.8Monitoring low-power modes . . . . .317
6.8PWR registers . . . . .318
6.8.1PWR control register 1 (PWR_CR1) . . . . .318
6.8.2PWR control status register 1 (PWR_SR1) . . . . .320
6.8.3PWR control status register 1 (PWR_CSR1) . . . . .321
6.8.4PWR control register 2 (PWR_CSR2) . . . . .323
6.8.5PWR CPU control register 3 (PWR_CSR3) . . . . .326
6.8.6PWR control status register 4 (PWR_CSR4) . . . . .327
6.8.7PWR wake-up clear register (PWR_WKUPCR) . . . . .328
6.8.8PWR wake-up flag register (PWR_WKUPFR) . . . . .329
6.8.9PWR wake-up enable and polarity register (PWR_WKUPEPR) . . . . .330
6.8.10PWR USB Type-C and Power Delivery register (PWR_UCPDR)331
6.8.11PWR apply pull configuration register (PWR_APCR)332
6.8.12PWR port N pull-up control register (PWR_PUCRN)334
6.8.13PWR port N pull-down control register (PWR_PDCRN)335
6.8.14PWR port O pull-up control register (PWR_PUCRO)336
6.8.15PWR port O pull-down control register (PWR_PDCRO)337
6.8.16PWR port P pull-down control register (PWR_PDCRP)338
6.8.17PWR register map339
7Reset and clock control (RCC)341
7.1RCC main features341
7.2RCC block diagram342
7.3RCC pins and internal signals343
7.4RCC reset block functional description345
7.4.1Reset from PWR block345
7.4.2The system and application resets (sys_rst and nreset)347
7.4.3The NRST reset347
7.4.4Low-power mode security reset (lpwr_rst)347
7.4.5Backup domain reset348
7.4.6Coresight debug reset348
7.4.7Option bytes loading349
7.4.8Peripheral resets349
7.4.9Reset coverage summary349
7.4.10Reset source identification351
7.4.11Power-on and wake-up sequences351
7.5RCC clock block functional description353
7.5.1Clock naming convention355
7.5.2Oscillators description355
7.5.3Clock security system (CSS)365
7.5.4Clock output generation (MCO1/MCO2)368
7.5.5PLL description370
7.5.6System clock ( sys_ck )376
7.5.7Clock protection379
7.5.8Clock generation in Stop and Standby modes380
7.5.9Peripheral clock distribution382
7.5.10General clock concept overview411
7.5.11Peripheral allocation412
7.5.12Peripheral clock gating control . . . . .413
7.5.13CPU and bus matrix clock gating control . . . . .416
7.5.14Low-power emulation modes . . . . .417
7.6RCC interrupts . . . . .418
7.7RCC Programming examples . . . . .419
7.7.1PLL programming procedure . . . . .419
7.7.2Frequency configuration examples . . . . .421
7.8RCC registers . . . . .424
7.8.1RCC source control register (RCC_CR) . . . . .424
7.8.2RCC clock protection register (RCC_CKPROTR) . . . . .428
7.8.3RCC HSI calibration register (RCC_HSICFGR) . . . . .429
7.8.4RCC clock recovery RC register (RCC_CRRRCR) . . . . .430
7.8.5RCC CSI calibration register (RCC_CSICFGR) . . . . .430
7.8.6RCC clock configuration register (RCC_CFGR) . . . . .431
7.8.7RCC CPU domain clock configuration register (RCC_CDCFGR) . . . . .434
7.8.8RCC AHB clock configuration register (RCC_BMCFGR) . . . . .435
7.8.9RCC APB clocks configuration register (RCC_APBCFGR) . . . . .436
7.8.10RCC PLLs clock source selection register (RCC_PLLCKSEL) . . . . .438
7.8.11RCC PLLs configuration register (RCC_PLLCFGR) . . . . .440
7.8.12RCC PLL1 dividers configuration register 1 (RCC_PLL1DIVR1) . . . . .443
7.8.13RCC PLL1 dividers configuration register 2 (RCC_PLL1DIVR2) . . . . .445
7.8.14RCC PLL1 fractional divider register (RCC_PLL1FRACR) . . . . .445
7.8.15RCC PLL1 Spread Spectrum Clock Generator register
(RCC_PLL1SSCG) . . . . .		447
7.8.16RCC PLL2 dividers configuration register 1 (RCC_PLL2DIVR1) . . . . .448
7.8.17RCC PLL2 dividers configuration register 2 (RCC_PLL2DIVR2) . . . . .450
7.8.18RCC PLL2 fractional divider register (RCC_PLL2FRACR) . . . . .451
7.8.19RCC PLL2 Spread Spectrum Clock Generator register
(RCC_PLL2SSCG) . . . . .		452
7.8.20RCC PLL3 dividers configuration register 1 (RCC_PLL3DIVR1) . . . . .453
7.8.21RCC PLL3 dividers configuration register 2 (RCC_PLL3DIVR2) . . . . .455
7.8.22RCC PLL3 fractional divider register (RCC_PLL3FRACR) . . . . .455
7.8.23RCC PLL3 Spread Spectrum Clock Generator register
(RCC_PLL3SSCG) . . . . .		457
7.8.24RCC AHB peripheral kernel clock selection register (RCC_CCIPR1) . . . . .458
7.8.25RCC APB1 peripherals kernel clock selection register
(RCC_CCIPR2) . . . . .		461
7.8.26RCC APB2 peripherals kernel clock selection register (RCC_CCIPR3) . . . . .463
7.8.27RCC APB4,5 peripherals kernel clock selection register (RCC_CCIPR4) . . . . .465
7.8.28RCC clock source interrupt enable register (RCC_CIER) . . . . .467
7.8.29RCC clock source interrupt flag register (RCC_CIFR) . . . . .468
7.8.30RCC clock source interrupt clear register (RCC_CICR) . . . . .470
7.8.31RCC Backup domain control register (RCC_BDCR) . . . . .472
7.8.32RCC clock control and status register (RCC_CSR) . . . . .474
7.8.33RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .475
7.8.34RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .476
7.8.35RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . .477
7.8.36RCC AHB4 peripheral reset register (RCC_AHB4RSTR) . . . . .478
7.8.37RCC AHB5 peripheral reset register (RCC_AHB5RSTR) . . . . .480
7.8.38RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . .482
7.8.39RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . .485
7.8.40RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .486
7.8.41RCC APB4 peripheral reset register (RCC_APB4RSTR) . . . . .488
7.8.42RCC APB5 peripheral reset register (RCC_APB5RSTR) . . . . .490
7.8.43RCC AXI clocks gating disable register (RCC_CKGDISR) . . . . .491
7.8.44RCC Reset status register (RCC_RSR) . . . . .495
7.8.45RCC AHB1 clock enable register (RCC_AHB1ENR) . . . . .497
7.8.46RCC AHB2 clock enable register (RCC_AHB2ENR) . . . . .499
7.8.47RCC AHB3 clock enable register (RCC_AHB3ENR) . . . . .500
7.8.48RCC AHB4 clock enable register (RCC_AHB4ENR) . . . . .501
7.8.49RCC AHB5 clock enable register (RCC_AHB5ENR) . . . . .503
7.8.50RCC APB1 clock enable register 1 (RCC_APB1ENR1) . . . . .505
7.8.51RCC APB1 clock enable register 2 (RCC_APB1ENR2) . . . . .508
7.8.52RCC APB2 clock enable register (RCC_APB2ENR) . . . . .509
7.8.53RCC APB4 clock enable register (RCC_APB4ENR) . . . . .510
7.8.54RCC APB5 clock enable register (RCC_APB5ENR) . . . . .513
7.8.55RCC AHB5 low-power clock enable register (RCC_AHB5LPENR) . . . . .514
7.8.56RCC AHB1 low-power clock enable register (RCC_AHB1LPENR) . . . . .516
7.8.57RCC AHB2 low-power clock enable register (RCC_AHB2LPENR) . . . . .518
7.8.58RCC AHB3 low-power clock enable register (RCC_AHB3LPENR) . . . . .519
7.8.59RCC AHB4 low-power clock enable register (RCC_AHB4LPENR) . . . . .520
7.8.60RCC APB1 low-power clock enable register 1 (RCC_APB1LPENR1) . . . . .522
7.8.61RCC APB1 low-power clock enable register 2 (RCC_APB1LPENR2) . . . . .525
7.8.62RCC APB2 low-power clock enable register (RCC_APB2LPENR) . . .526
7.8.63RCC APB4 low-power clock enable register (RCC_APB4LPENR) . . .528
7.8.64RCC APB5 low-power clock enable register (RCC_APB5LPENR) . . .530
7.9RCC register map . . . . .531
8System configuration, boot and security (SBS) . . . . .540
8.1SBS introduction . . . . .540
8.2SBS main features . . . . .540
8.3SBS functional description . . . . .541
8.3.1SBS block diagram . . . . .541
8.3.2SBS internal signals . . . . .541
8.3.3SBS reset and clocks . . . . .541
8.3.4SBS hide protection management . . . . .542
8.3.5SBS boot control . . . . .542
8.3.6SBS debug management . . . . .543
8.3.7SBS voltage booster for I/O analog switches . . . . .544
8.3.8SBS I/O compensation cell management . . . . .544
8.3.9SBS registers access control . . . . .545
8.3.10SBS error management . . . . .546
8.4SBS interrupts . . . . .546
8.5SBS registers . . . . .546
8.5.1SBS boot status register (SBS_BOOTSR) . . . . .546
8.5.2SBS hide protection control register (SBS_HDPLCR) . . . . .547
8.5.3SBS hide protection status register (SBS_HDPLSR) . . . . .547
8.5.4SBS debug control register (SBS_DBGCR) . . . . .548
8.5.5SBS debug lock register (SBS_DBGLOCKR) . . . . .548
8.5.6SBS RSS command register (SBS_RSSCMDR) . . . . .549
8.5.7SBS product mode and configuration register (SBS_PMCR) . . . . .549
8.5.8SBS FPU interrupt mask register (SBS_FPUIMR) . . . . .550
8.5.9SBS memory erase status register (SBS_MESR) . . . . .551
8.5.10SBS I/O compensation cell control and status register
(SBS_CCCSR) . . . . .		551
8.5.11SBS compensation cell for I/Os value register (SBS_CCVALR) . . . . .554
8.5.12SBS compensation cell for I/Os software value register
(SBS_CCSWVALR) . . . . .		555
8.5.13SBS break lockup register (SBS_BKLOCKR) . . . . .556
8.5.14SBS external interrupt configuration register x (SBS_EXTICRx) . . . . .558
10.3.11Alternate function configuration . . . . .579
10.3.12Analog configuration . . . . .580
10.3.13Using the HSE or LSE oscillator pins as GPIOs . . . . .580
10.3.14Using the GPIO pins in the RTC supply domain . . . . .581
10.3.15Privileged and unprivileged modes . . . . .581
10.3.16High-speed low-voltage mode (HSLV) . . . . .581
10.3.17I/O compensation cell . . . . .582
10.4GPIO registers . . . . .582
10.4.1GPIO port mode register (GPIOx_MODER) (x=A to H, M to P) . . . . .582
10.4.2GPIO port output type register (GPIOx_OTYPER)
(x = A to G, M to P) . . . . .		583
10.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to G, M to P) . . . . .		583
10.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to G, M to P) . . . . .		584
10.4.5GPIO port input data register (GPIOx_IDR)
(x = A to G, M to P) . . . . .		584
10.4.6GPIO port output data register (GPIOx_ODR)
(x = A to G, M to P) . . . . .		585
10.4.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to G, M to P) . . . . .		585
10.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to G, M to P) . . . . .		586
10.4.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to G, M to P) . . . . .		587
10.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to G, M to P) . . . . .		588
10.4.11GPIO port bit reset register (GPIOx_BRR) (x = A to G, M to P) . . . . .589
10.4.12GPIO register map . . . . .590
11Peripheral interconnect . . . . .592
11.1Introduction . . . . .592
11.2Connection summary . . . . .592
11.3Interconnection details . . . . .594
11.3.1Master to slave interconnection for timers . . . . .594
11.3.2Triggers to ADCs . . . . .595
11.3.3ADC analog watchdogs as triggers to timers . . . . .596
11.3.4Triggers on ADF1 . . . . .596
11.3.5Internal input and clock sources to timers . . . . .596
11.3.6Triggers to low-power timers . . . . .597
11.3.7RTC wake-up as inputs to timers . . . . .598
11.3.8USB OTG SOF as trigger to timers . . . . .598
11.3.9System errors as break signals to timers . . . . .598
11.3.10Triggers to GPDMA/HPDMA . . . . .599
11.3.11Internal analog signals to analog peripherals . . . . .599
11.3.12ADC data filtering by the ADF1 . . . . .600
11.3.13Internal tamper sources . . . . .600
11.3.14Output from tamper to RTC . . . . .601
11.3.15Encryption keys to AES/SAES . . . . .601
12General purpose direct memory access controller (GPDMA) . . . . .602
12.1GPDMA introduction . . . . .602
12.2GPDMA main features . . . . .602
12.3GPDMA implementation . . . . .603
12.3.1GPDMA channels . . . . .603
12.3.2GPDMA in low-power modes . . . . .604
12.3.3GPDMA requests . . . . .604
12.3.4GPDMA block requests . . . . .607
12.3.5GPDMA channels with peripheral early termination . . . . .607
12.3.6GPDMA triggers . . . . .608
12.4GPDMA functional description . . . . .610
12.4.1GPDMA block diagram . . . . .610
12.4.2GPDMA channel state and direct programming without
any linked-list . . . . .		610
12.4.3GPDMA channel suspend and resume . . . . .611
12.4.4GPDMA channel abort and restart . . . . .612
12.4.5GPDMA linked-list data structure . . . . .613
12.4.6Linked-list item transfer execution . . . . .616
12.4.7GPDMA channel state and linked-list programming
in run-to-completion mode . . . . .		616
12.4.8GPDMA channel state and linked-list programming in link step mode . . . . .620
12.4.9GPDMA channel state and linked-list programming . . . . .627
12.4.10GPDMA FIFO-based transfers . . . . .629
12.4.11GPDMA transfer request and arbitration . . . . .636
12.4.12GPDMA triggered transfer . . . . .640
12.4.13GPDMA circular buffering with linked-list programming . . . . .641
12.4.14GPDMA transfer in peripheral flow-control mode . . . . .643
12.4.15GPDMA privileged/unprivileged channel . . . . .644
12.4.16GPDMA error management . . . . .644
12.5GPDMA in debug mode . . . . .646
12.6GPDMA in low-power modes . . . . .646
12.7GPDMA interrupts . . . . .647
12.8GPDMA registers . . . . .648
12.8.1GPDMA privileged configuration register (GPDMA_PRIVCFGR) . . . . .648
12.8.2GPDMA configuration lock register (GPDMA_RCFGLOCKR) . . . . .649
12.8.3GPDMA masked interrupt status register (GPDMA_MISR) . . . . .649
12.8.4GPDMA channel x linked-list base address register
(GPDMA_CxLBAR) . . . . .		650
12.8.5GPDMA channel x flag clear register (GPDMA_CxFCR) . . . . .651
12.8.6GPDMA channel x status register (GPDMA_CxSR) . . . . .652
12.8.7GPDMA channel x control register (GPDMA_CxCGR) . . . . .653
12.8.8GPDMA channel x transfer register 1 (GPDMA_CxTR1) . . . . .655
12.8.9GPDMA channel x transfer register 2 (GPDMA_CxTR2) . . . . .658
12.8.10GPDMA channel x block register 1 (GPDMA_CxBR1) . . . . .662
12.8.11GPDMA channel x alternate block register 1 (GPDMA_CxBR1) . . . . .663
12.8.12GPDMA channel x source address register (GPDMA_CxSAR) . . . . .666
12.8.13GPDMA channel x destination address register (GPDMA_CxDAR) . . . . .667
12.8.14GPDMA channel x transfer register 3 (GPDMA_CxTR3) . . . . .668
12.8.15GPDMA channel x block register 2 (GPDMA_CxBR2) . . . . .669
12.8.16GPDMA channel x linked-list address register (GPDMA_CxLLR) . . . . .670
12.8.17GPDMA channel x alternate linked-list address register
(GPDMA_CxLLR) . . . . .		672
12.8.18GPDMA register map . . . . .673
13High-performance direct memory access controller (HPDMA) . . . . .675
13.1HPDMA introduction . . . . .675
13.2HPDMA main features . . . . .675
13.3HPDMA implementation . . . . .676
13.3.1HPDMA channels . . . . .676
13.3.2HPDMA in low-power modes . . . . .677
13.3.3HPDMA requests . . . . .677
13.3.4HPDMA block requests . . . . .678
13.3.5HPDMA channels with peripheral early termination . . . . .678
13.3.6HPDMA triggers . . . . .678
13.4HPDMA functional description . . . . .681
13.4.1HPDMA block diagram . . . . .681
13.4.2HPDMA channel state and direct programming without
any linked-list . . . . .		681
13.4.3HPDMA channel suspend and resume . . . . .682
13.4.4HPDMA channel abort and restart . . . . .683
13.4.5HPDMA linked-list data structure . . . . .684
13.4.6Linked-list item transfer execution . . . . .687
13.4.7HPDMA channel state and linked-list programming
in run-to-completion mode . . . . .		687
13.4.8HPDMA channel state and linked-list programming
in link step mode . . . . .		691
13.4.9HPDMA channel state and linked-list programming . . . . .698
13.4.10HPDMA FIFO-based transfers . . . . .700
13.4.11HPDMA transfer request and arbitration . . . . .716
13.4.12HPDMA triggered transfer . . . . .720
13.4.13HPDMA circular buffering with linked-list programming . . . . .721
13.4.14HPDMA transfer in peripheral flow-control mode . . . . .723
13.4.15HPDMA privileged/unprivileged channel . . . . .724
13.4.16HPDMA error management . . . . .724
13.5HPDMA in debug mode . . . . .726
13.6HPDMA in low-power modes . . . . .726
13.7HPDMA interrupts . . . . .727
13.8HPDMA registers . . . . .728
13.8.1HPDMA privileged configuration register (HPDMA_PRIVCFGR) . . . . .728
13.8.2HPDMA configuration lock register (HPDMA_RCFGLOCKR) . . . . .729
13.8.3HPDMA masked interrupt status register (HPDMA_MISR) . . . . .729
13.8.4HPDMA channel x linked-list base address register
(HPDMA_CxLBAR) . . . . .		730
13.8.5HPDMA channel x flag clear register (HPDMA_CxFCR) . . . . .731
13.8.6HPDMA channel x status register (HPDMA_CxSR) . . . . .732
13.8.7HPDMA channel x control register (HPDMA_CxCR) . . . . .733
13.8.8HPDMA channel x transfer register 1 (HPDMA_CxTR1) . . . . .736
13.8.9HPDMA channel x transfer register 2 (HPDMA_CxTR2) . . . . .739
13.8.10HPDMA channel x block register 1 (HPDMA_CxBR1) . . . . .743
13.8.11HPDMA channel x alternate block register 1 (HPDMA_CxBR1) . . . . .744
13.8.12HPDMA channel x source address register (HPDMA_CxSAR) . . . . .747
13.8.13HPDMA channel x destination address register (HPDMA_CxDAR) . . .748
13.8.14HPDMA channel x transfer register 3 (HPDMA_CxTR3) . . . . .749
13.8.15HPDMA channel x block register 2 (HPDMA_CxBR2) . . . . .750
13.8.16HPDMA channel x linked-list address register (HPDMA_CxLLR) . . . .751
13.8.17HPDMA channel x alternate linked-list address register
(HPDMA_CxLLR) . . . . .		753
13.8.18HPDMA register map . . . . .754
14Chrom-GRC (GFXMMU) . . . . .756
14.1GFXMMU introduction . . . . .756
14.2GFXMMU main features . . . . .756
14.3GFXMMU functional and architectural description . . . . .756
14.3.1GFXMMU block diagram . . . . .756
14.3.2GFXMMU internal signals . . . . .757
14.3.3Virtual memory . . . . .757
14.3.4Packing and unpacking . . . . .759
14.3.5MMU architecture . . . . .760
14.4GTZC TZIC GFXMMU interrupts . . . . .763
14.5GFXMMU registers . . . . .764
14.5.1GFXMMU configuration register (GFXMMU_CR) . . . . .764
14.5.2GFXMMU status register (GFXMMU_SR) . . . . .766
14.5.3GFXMMU flag clear register (GFXMMU_FCR) . . . . .766
14.5.4GFXMMU default value register (GFXMMU_DVR) . . . . .767
14.5.5GFXMMU default alpha register (GFXMMU_DAR) . . . . .767
14.5.6GFXMMU buffer x configuration register (GFXMMU_BxCR) . . . . .768
14.5.7GFXMMU LUT entry x low (GFXMMU_LUTxL) . . . . .768
14.5.8GFXMMU LUT entry x high (GFXMMU_LUTxH) . . . . .769
14.5.9GFXMMU register map . . . . .769
15Chrom-ART Accelerator controller (DMA2D) . . . . .771
15.1DMA2D introduction . . . . .771
15.2DMA2D main features . . . . .771
15.3DMA2D functional description . . . . .772
15.3.1General description . . . . .772
15.3.2DMA2D internal signals . . . . .773
15.3.3DMA2D control . . . . .774
15.3.4DMA2D foreground and background FIFOs . . . . .774
15.3.5DMA2D foreground and background PFC . . . . .774
15.3.6DMA2D foreground and background CLUT interface . . . . .776
15.3.7DMA2D blender . . . . .778
15.3.8DMA2D output PFC . . . . .778
15.3.9DMA2D output FIFO . . . . .778
15.3.10DMA2D output FIFO byte reordering . . . . .779
15.3.11DMA2D AXI master port timer . . . . .781
15.3.12DMA2D transactions . . . . .781
15.3.13DMA2D configuration . . . . .781
15.3.14YCbCr support . . . . .785
15.3.15DMA2D transfer control (start, suspend, abort, and completion) . . . . .785
15.3.16Watermark . . . . .786
15.3.17Error management . . . . .786
15.3.18AXI dead time . . . . .786
15.4DMA2D interrupts . . . . .786
15.5DMA2D registers . . . . .787
15.5.1DMA2D control register (DMA2D_CR) . . . . .787
15.5.2DMA2D interrupt status register (DMA2D_ISR) . . . . .789
15.5.3DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . .789
15.5.4DMA2D foreground memory address register (DMA2D_FGMAR) . . . . .790
15.5.5DMA2D foreground offset register (DMA2D_FGOR) . . . . .790
15.5.6DMA2D background memory address register (DMA2D_BGMAR) . . . . .791
15.5.7DMA2D background offset register (DMA2D_BGOR) . . . . .791
15.5.8DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . .792
15.5.9DMA2D foreground color register (DMA2D_FGCOLR) . . . . .794
15.5.10DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . .794
15.5.11DMA2D background color register (DMA2D_BGCOLR) . . . . .796
15.5.12DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . .		796
15.5.13DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . .		797
15.5.14DMA2D output PFC control register (DMA2D_OPFCCR) . . . . .797
15.5.15DMA2D output color register (DMA2D_OCOLR) . . . . .798
15.5.16DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .799
15.5.17DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .799
15.5.18DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .800
15.5.19DMA2D output memory address register (DMA2D_OMAR) . . . . .800
15.5.20DMA2D output offset register (DMA2D_OOR) . . . . .801
15.5.21DMA2D number of line register (DMA2D_NLR) . . . . .801
15.5.22DMA2D line watermark register (DMA2D_LWR) . . . . .802
15.5.23DMA2D AXI master timer configuration register (DMA2D_AMTCR) . . . . .802
15.5.24DMA2D foreground CLUT (DMA2D_FGCLUTx) . . . . .803
15.5.25DMA2D background CLUT (DMA2D_BGCLUTx) . . . . .803
15.5.26DMA2D register map . . . . .804
16Neo-Chrom graphic processor (GPU2D) . . . . .806
16.1GPU2D introduction . . . . .806
16.2GPU2D main features . . . . .806
16.3GPU2D general description . . . . .807
16.3.1GPU2D block diagram . . . . .807
16.3.2GPU2D pins and internal signals . . . . .807
17Texture cache (ICACHE) . . . . .809
17.1ICACHE introduction . . . . .809
17.2ICACHE main features . . . . .809
17.3ICACHE implementation . . . . .810
17.4ICACHE functional description . . . . .810
17.4.1ICACHE block diagram . . . . .811
17.4.2ICACHE reset and clocks . . . . .811
17.4.3ICACHE TAG memory . . . . .812
17.4.4Direct-mapped ICACHE (1-way cache) . . . . .813
17.4.5ICACHE enable . . . . .814
17.4.6Cacheable and noncacheable traffic . . . . .814
17.4.7Cacheable accesses . . . . .815
17.4.8ICACHE maintenance . . . . .815
17.4.9ICACHE performance monitoring . . . . .816
17.4.10ICACHE boot . . . . .816
17.5ICACHE low-power modes . . . . .816
17.6ICACHE error management and interrupts . . . . .817
17.7ICACHE registers . . . . .817
17.7.1ICACHE control register (ICACHE_CR) . . . . .817
17.7.2ICACHE status register (ICACHE_SR) . . . . .818
17.7.3ICACHE interrupt enable register (ICACHE_IER) . . . . .819
17.7.4ICACHE flag clear register (ICACHE_FCR) . . . . .819
17.7.5ICACHE hit monitor register (ICACHE_HMONR) . . . . .820
17.7.6ICACHE miss monitor register (ICACHE_MMONR) . . . . .820
17.7.7ICACHE register map . . . . .820
18Graphic timer (GFXTIM) . . . . .822
18.1GFXTIM introduction . . . . .822
18.2GFXTIM main features . . . . .822
18.3GFXTIM functional description . . . . .822
18.3.1Block diagram . . . . .822
18.3.2GFXTIM pins and internal signals . . . . .823
18.3.3Clock generator . . . . .824
18.3.4Example of clock generator configuration . . . . .826
18.3.5Absolute timers . . . . .830
18.3.6Relative timers . . . . .831
18.3.7Tearing-effect detection . . . . .832
18.3.8Event generator . . . . .832
18.3.9Watchdog timer . . . . .833
18.4GFXTIM interrupts . . . . .834
18.5GFXTIM registers . . . . .835
18.5.1GFXTIM configuration register (GFXTIM_CR) . . . . .835
18.5.2GFXTIM clock generator configuration register (GFXTIM_CGCR) . . . . .836
18.5.3GFXTIM timers configuration register (GFXTIM_TCR) . . . . .838
18.5.4GFXTIM timers disable register (GFXTIM_TDR) . . . . .839
18.5.5GFXTIM events control register (GFXTIM_EVCR) . . . . .840
18.5.6GFXTIM events selection register (GFXTIM_EVSR) . . . . .840
18.5.7GFXTIM watchdog timer configuration register
(GFXTIM_WDGTCR) . . . . .		842
18.5.8GFXTIM interrupt status register (GFXTIM_ISR) . . . . .844
18.5.9GFXTIM interrupt clear register (GFXTIM_ICR) . . . . .845
18.5.10GFXTIM interrupt enable register (GFXTIM_IER) . . . . .847
18.5.11GFXTIM timers status register (GFXTIM_TSR) . . . . .849
18.5.12GFXTIM line-clock counter reload register (GFXTIM_LCCRR) . . . . .850
18.5.13GFXTIM frame-clock counter reload register (GFXTIM_FCCRR) . . . . .850
18.5.14GFXTIM absolute time register (GFXTIM_ATR) . . . . .850
18.5.15GFXTIM absolute frame counter register (GFXTIM_AFCR) . . . . .851
18.5.16GFXTIM absolute line counter register (GFXTIM_ALCR) . . . . .851
18.5.17GFXTIM absolute frame counter compare 1 register (GFXTIM_AFCC1R) . . . . .852
18.5.18GFXTIM absolute line counter compare 1 register (GFXTIM_ALCC1R) . . . . .852
18.5.19GFXTIM absolute line counter compare 2 register (GFXTIM_ALCC2R) . . . . .852
18.5.20GFXTIM relative frame counter 1 register (GFXTIM_RFC1R) . . . . .853
18.5.21GFXTIM relative frame counter 1 reload register (GFXTIM_RFC1RR) . . . . .853
18.5.22GFXTIM relative frame counter 2 register (GFXTIM_RFC2R) . . . . .854
18.5.23GFXTIM relative frame counter 2 reload register (GFXTIM_RFC2RR) . . . . .854
18.5.24GFXTIM watchdog counter register (GFXTIM_WDGCR) . . . . .854
18.5.25GFXTIM watchdog reload register (GFXTIM_WDGRR) . . . . .855
18.5.26GFXTIM watchdog pre-alarm register (GFXTIM_WDGPAR) . . . . .855
18.5.27GFXTIM register map . . . . .855
19Nested vectored interrupt controller (NVIC) . . . . .858
19.1NVIC features . . . . .858
19.1.1SysTick calibration value register . . . . .858
19.1.2Interrupt and exception vectors . . . . .859
20Extended interrupt and event controller (EXTI) . . . . .866
20.1EXTI main features . . . . .866
20.2EXTI block diagram . . . . .866
20.2.1EXTI connections between peripherals and CPU . . . . .867
20.3EXTI functional description . . . . .868
20.3.1EXTI configurable event input - CPU wake-up . . . . .869
20.3.2EXTI direct event input - CPU wake up . . . . .870
20.4EXTI event input mapping . . . . .871
20.5EXTI functional behavior . . . . .873
20.5.1EXTI CPU interrupt procedure . . . . .874
20.5.2EXTI CPU event procedure . . . . .874
20.5.3EXTI CPU wake-up procedure . . . . .874
20.5.4EXTI software interrupt/event trigger procedure . . . . .874
20.6EXTI registers . . . . .875
20.6.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .875
20.6.2EXTI falling trigger selection register (EXTI_FTSR1) . . . . .875
20.6.3EXTI software interrupt event register (EXTI_SWIER1) . . . . .876
20.6.4EXTI rising trigger selection register (EXTI_RTSR2) . . . . .876
20.6.5EXTI falling trigger selection register (EXTI_FTSR2) . . . . .877
20.6.6EXTI software interrupt event register (EXTI_SWIER2) . . . . .878
20.6.7EXTI interrupt mask register (EXTI_IMR1) . . . . .879
20.6.8EXTI event mask register (EXTI_EMR1) . . . . .880
20.6.9EXTI pending register (EXTI_PR1) . . . . .880
20.6.10EXTI interrupt mask register (EXTI_IMR2) . . . . .881
20.6.11EXTI event mask register (EXTI_EMR2) . . . . .881
20.6.12EXTI pending register (EXTI_PR2) . . . . .882
20.6.13EXTI interrupt mask register (EXTI_IMR3) . . . . .883
20.6.14EXTI event mask register (EXTI_EMR3) . . . . .883
20.6.15EXTI register map . . . . .884
21Cyclic redundancy check calculation unit (CRC) . . . . .886
21.1CRC introduction . . . . .886
21.2CRC main features . . . . .886
21.3CRC functional description . . . . .887
21.3.1CRC block diagram . . . . .887
21.3.2CRC internal signals . . . . .887
21.3.3CRC operation . . . . .887
21.4CRC registers . . . . .889
21.4.1CRC data register (CRC_DR) . . . . .889
21.4.2CRC independent data register (CRC_IDR) . . . . .889
21.4.3CRC control register (CRC_CR) . . . . .890
21.4.4CRC initial value (CRC_INIT) . . . . .891
21.4.5CRC polynomial (CRC_POL) . . . . .891
21.4.6CRC register map . . . . .892
22CORDIC coprocessor (CORDIC) . . . . .893
22.1CORDIC introduction . . . . .893
22.2CORDIC main features . . . . .893
22.3CORDIC functional description . . . . .893
22.3.1General description . . . . .893
22.3.2CORDIC functions . . . . .893
22.3.3Fixed point representation . . . . .900
22.3.4Scaling factor . . . . .900
22.3.5Precision . . . . .901
22.3.6Zero-overhead mode . . . . .904
22.3.7Polling mode . . . . .905
22.3.8Interrupt mode . . . . .906
22.3.9DMA mode . . . . .906
22.4CORDIC registers . . . . .907
22.4.1CORDIC control/status register (CORDIC_CSR) . . . . .907
22.4.2CORDIC argument register (CORDIC_WDATA) . . . . .909
22.4.3CORDIC result register (CORDIC_RDATA) . . . . .910
22.4.4CORDIC register map . . . . .910
23Flexible memory controller (FMC) . . . . .911
23.1FMC main features . . . . .911
23.2FMC block diagram . . . . .912
23.3FMC internal signals . . . . .914
23.4AHB interface . . . . .914
23.5AXI interface . . . . .914
23.5.1Supported memories and transactions . . . . .915
23.6External device address mapping . . . . .916
23.6.1NOR/PSRAM address mapping . . . . .917
23.6.2NAND flash memory address mapping . . . . .917
23.6.3SDRAM address mapping . . . . .918
23.7NOR flash/PSRAM controller . . . . .922
23.7.1External memory interface signals . . . . .923
23.7.2Supported memories and transactions . . . . .925
23.7.3General timing rules . . . . .926
23.7.4NOR flash/PSRAM controller asynchronous transactions . . . . .927
23.7.5Synchronous transactions . . . . .946
23.7.6NOR/PSRAM controller registers . . . . .952
23.8NAND flash controller . . . . .961
23.8.1External memory interface signals . . . . .961
23.8.2NAND flash supported memories and transactions . . . . .962
23.8.3Timing diagrams for NAND flash memories . . . . .963
23.8.4NAND flash operations . . . . .964
23.8.5NAND flash prewait feature . . . . .965
23.8.6Computation of the error correction code (ECC) in NAND flash memory . . . . .966
23.8.7NAND flash controller registers . . . . .967
23.9SDRAM controller . . . . .973
23.9.1SDRAM controller main features . . . . .973
23.9.2SDRAM External memory interface signals . . . . .973
23.9.3SDRAM controller functional description . . . . .974
23.9.4Low-power modes . . . . .981
23.9.5SDRAM controller registers . . . . .983
23.9.6FMC register map . . . . .990
24Extended-SPI interface (XSPI) . . . . .993
24.1XSPI introduction . . . . .993
24.2XSPI main features . . . . .993
24.3XSPI implementation . . . . .994
24.4XSPI functional description . . . . .995
24.4.1XSPI block diagram . . . . .995
24.4.2XSPI pins and internal signals . . . . .999
24.4.3Clock constraints . . . . .1000
24.4.4XSPI interface to memory modes . . . . .1000
24.4.5XSPI regular-command protocol . . . . .1000
24.4.6XSPI regular-command protocol signal interface . . . . .1004
24.4.7HyperBus protocol . . . . .1009
24.4.8Specific features . . . . .1014
24.4.9XSPI operating modes introduction . . . . .1016
24.4.10XSPI indirect mode . . . . .1016
24.4.11XSPI automatic status-polling mode . . . . .1018
24.4.12XSPI memory-mapped mode . . . . .1018
24.4.13XSPI configuration introduction . . . . .1019
24.4.14XSPI system configuration . . . . .1019
24.4.15XSPI device configuration . . . . .1020
24.4.16XSPI regular-command mode configuration . . . . .1022
24.4.17XSPI HyperBus protocol configuration . . . . .1025
24.4.18XSPI error management . . . . .1025
24.4.19XSPI high-speed interface and calibration . . . . .1026
24.4.20XSPI BUSY and ABORT . . . . .1027
24.4.21XSPI reconfiguration or deactivation . . . . .1027
24.4.22NCS behavior .....1028
24.4.23Software control of two external memories .....1029
24.5Address alignment and data number .....1030
24.6XSPI interrupts .....1031
24.7XSPI registers .....1032
24.7.1XSPI control register (XSPI_CR) .....1032
24.7.2XSPI device configuration register 1 (XSPI_DCR1) .....1035
24.7.3XSPI device configuration register 2 (XSPI_DCR2) .....1036
24.7.4XSPI device configuration register 3 (XSPI_DCR3) .....1037
24.7.5XSPI device configuration register 4 (XSPI_DCR4) .....1038
24.7.6XSPI status register (XSPI_SR) .....1038
24.7.7XSPI flag clear register (XSPI_FCR) .....1039
24.7.8XSPI data length register (XSPI_DLR) .....1040
24.7.9XSPI address register (XSPI_AR) .....1040
24.7.10XSPI data register (XSPI_DR) .....1041
24.7.11XSPI polling status mask register (XSPI_PSMKR) .....1042
24.7.12XSPI polling status match register (XSPI_PSMAR) .....1042
24.7.13XSPI polling interval register (XSPI_PIR) .....1043
24.7.14XSPI communication configuration register (XSPI_CCR) .....1043
24.7.15XSPI timing configuration register (XSPI_TCR) .....1045
24.7.16XSPI instruction register (XSPI_IR) .....1046
24.7.17XSPI alternate bytes register (XSPI_ABR) .....1046
24.7.18XSPI low-power timeout register (XSPI_LPTR) .....1046
24.7.19XSPI wrap communication configuration register
(XSPI_WPCCR) .....		1047
24.7.20XSPI wrap timing configuration register (XSPI_WPTCR) .....1049
24.7.21XSPI wrap instruction register (XSPI_WPIR) .....1050
24.7.22XSPI wrap alternate byte register (XSPI_WPABR) .....1050
24.7.23XSPI write communication configuration register
(XSPI_WCCR) .....		1050
24.7.24XSPI write timing configuration register (XSPI_WTCR) .....1052
24.7.25XSPI write instruction register (XSPI_WIR) .....1053
24.7.26XSPI write alternate byte register (XSPI_WABR) .....1053
24.7.27XSPI HyperBus latency configuration register (XSPI_HLCR) .....1054
24.7.28XSPI full-cycle calibration configuration (XSPI_CALFCR) .....1054
24.7.29XSPI DLL master calibration configuration (XSPI_CALMR) .....1055
24.7.30XSPI DLL slave output calibration configuration
(XSPI_CALSOR) .....		1056
26.4.1DLYB control register (DLYB_CR) . . . . .1075
26.4.2DLYB configuration register (DLYB_CFGR) . . . . .1076
26.4.3DLYB register map . . . . .1076
27Analog-to-digital converters (ADC1/2) . . . . .1077
27.1ADC introduction . . . . .1077
27.2ADC main features . . . . .1077
27.3ADC implementation . . . . .1079
27.4ADC functional description . . . . .1080
27.4.1ADC block diagram . . . . .1080
27.4.2ADC pins and internal signals . . . . .1081
27.4.3ADC clocks . . . . .1084
27.4.4ADC connectivity . . . . .1086
27.4.5Slave AHB interface . . . . .1088
27.4.6ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . . . . .1088
27.4.7Single-ended and differential input channels . . . . .1089
27.4.8Calibration (ADCAL, ADCALDIF, ADC_CALFACT) . . . . .1089
27.4.9ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .1092
27.4.10Constraints when writing the ADC control bits . . . . .1093
27.4.11Channel selection (ADC_SQRY, ADC_JSQR) . . . . .1094
27.4.12Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .1095
27.4.13Single conversion mode (CONT = 0) . . . . .1097
27.4.14Continuous conversion mode (CONT = 1) . . . . .1097
27.4.15Starting conversions (ADSTART, JADSTART) . . . . .1098
27.4.16ADC timing . . . . .1099
27.4.17Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .1100
27.4.18Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .1101
27.4.19Injected channel management . . . . .1103
27.4.20Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .1104
27.4.21Queue of context for injected conversions . . . . .1105
27.4.22Programmable resolution (RES) - fast conversion mode . . . . .1113
27.4.23End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . . . .1114
27.4.24End of conversion sequence (EOS, JEOS) . . . . .1114
27.4.25Timing diagrams example (single/continuous modes, hardware/software triggers) . . . . .1115
27.4.26Data management . . . . .1117
27.4.27Managing conversions using the ADF . . . . .1123
27.4.28Dynamic low-power features . . . . .1124
27.4.29Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . .1129
27.4.30Oversampler . . . . .1133
27.4.31Dual ADC modes . . . . .1140
27.4.32Temperature sensor . . . . .1153
27.4.33VBAT supply monitoring . . . . .1155
27.4.34Monitoring the internal voltage reference . . . . .1156
27.4.35Monitoring the supply voltage . . . . .1157
27.5ADC in low-power modes . . . . .1158
27.6ADC interrupts . . . . .1158
27.7ADC registers (for each ADC) . . . . .1160
27.7.1ADC interrupt and status register (ADC_ISR) . . . . .1160
27.7.2ADC interrupt enable register (ADC_IER) . . . . .1162
27.7.3ADC control register (ADC_CR) . . . . .1164
27.7.4ADC configuration register (ADC_CFGR) . . . . .1167
27.7.5ADC configuration register 2 (ADC_CFGR2) . . . . .1172
27.7.6ADC sample time register 1 (ADC_SMPR1) . . . . .1174
27.7.7ADC sample time register 2 (ADC_SMPR2) . . . . .1175
27.7.8ADC watchdog threshold register 1 (ADC_TR1) . . . . .1176
27.7.9ADC watchdog threshold register 2 (ADC_TR2) . . . . .1177
27.7.10ADC watchdog threshold register 3 (ADC_TR3) . . . . .1178
27.7.11ADC regular sequence register 1 (ADC_SQR1) . . . . .1178
27.7.12ADC regular sequence register 2 (ADC_SQR2) . . . . .1179
27.7.13ADC regular sequence register 3 (ADC_SQR3) . . . . .1180
27.7.14ADC regular sequence register 4 (ADC_SQR4) . . . . .1181
27.7.15ADC regular data register (ADC_DR) . . . . .1182
27.7.16ADC injected sequence register (ADC_JSQR) . . . . .1182
27.7.17ADC offset y register (ADC_OFRy) . . . . .1185
27.7.18ADC injected channel y data register (ADC_JDRy) . . . . .1186
27.7.19ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .1187
27.7.20ADC analog watchdog 3 configuration register (ADC_AWD3CR) . . . . .1187
27.7.21ADC Differential mode selection register (ADC_DIFSEL) . . . . .1188
27.7.22ADC calibration factors (ADC_CALFACT) . . . . .1189
27.7.23ADC option register (ADC_OR) . . . . .1189
27.8ADC common registers . . . . .1190
27.8.1ADC common status register (ADC_CSR) . . . . .1190
27.8.2ADC common control register (ADC_CCR) . . . . .1192
27.8.3ADC common regular data register for dual mode (ADC_CDR) . . . . .1195
27.9ADC register map . . . . .1196
28Digital temperature sensor (DTS) . . . . .1200
28.1DTS introduction . . . . .1200
28.2DTS main features . . . . .1200
28.3DTS functional description . . . . .1201
28.3.1DTS block diagram . . . . .1201
28.3.2DTS internal signals . . . . .1201
28.3.3DTS block operation . . . . .1202
28.3.4Operating modes . . . . .1202
28.3.5Calibration . . . . .1202
28.3.6Prescaler . . . . .1202
28.3.7Temperature measurement principles . . . . .1203
28.3.8Sampling time . . . . .1204
28.3.9Quick measurement mode . . . . .1204
28.3.10Trigger input . . . . .1205
28.3.11On-off control and ready flag . . . . .1205
28.3.12Temperature measurement sequence . . . . .1206
28.4DTS low-power modes . . . . .1207
28.5DTS interrupts . . . . .1207
28.5.1Temperature window comparator . . . . .1207
28.5.2Synchronous interrupt . . . . .1207
28.5.3Asynchronous wake-up . . . . .1207
28.6DTS registers . . . . .1208
28.6.1Temperature sensor configuration register 1 (DTS_CFGR1) . . . . .1208
28.6.2Temperature sensor T0 value register 1 (DTS_T0VALR1) . . . . .1210
28.6.3Temperature sensor ramp value register (DTS_RAMPVALR) . . . . .1210
28.6.4Temperature sensor interrupt threshold register 1 (DTS_ITR1) . . . . .1211
28.6.5Temperature sensor data register (DTS_DR) . . . . .1211
28.6.6Temperature sensor status register (DTS_SR) . . . . .1212
28.6.7Temperature sensor interrupt enable register (DTS_ITENR) . . . . .1213
28.6.8Temperature sensor clear interrupt flag register (DTS_ICIFR) . . . . .1214
28.6.9Temperature sensor option register (DTS_OR) . . . . .1215
30.7.4Global frequency response .....1270
30.7.5Total ADF gain .....1271
30.7.6How to compute SAD thresholds .....1274
30.8ADF registers .....1278
30.8.1ADF global control register (ADF_GCR) .....1278
30.8.2ADF clock generator control register (ADF_CKGCR) .....1278
30.8.3ADF serial interface control register 0 (ADF_SITF0CR) .....1280
30.8.4ADF bitstream matrix control register 0 (ADF_BSMX0CR) .....1282
30.8.5ADF digital filter control register 0 (ADF_DFLT0CR) .....1282
30.8.6ADF digital filter configuration register 0 (ADF_DFLT0CICR) .....1284
30.8.7ADF reshape filter configuration register 0 (ADF_DFLT0RSFR) .....1285
30.8.8ADF delay control register 0 (ADF_DLY0CR) .....1286
30.8.9ADF DFLT0 interrupt enable register (ADF_DFLT0IER) .....1287
30.8.10ADF DFLT0 interrupt status register 0 (ADF_DFLT0ISR) .....1288
30.8.11ADF SAD control register (ADF_SADCR) .....1289
30.8.12ADF SAD configuration register (ADF_SADCFGR) .....1291
30.8.13ADF SAD sound level register (ADF_SADSDLVR) .....1292
30.8.14ADF SAD ambient noise level register (ADF_SADANLVR) .....1293
30.8.15ADF digital filter data register 0 (ADF_DFLT0DR) .....1293
30.8.16ADF register map .....1293
31Digital camera interface pixel pipeline (DCMIPP) .....1296
31.1DCMIPP introduction .....1296
31.2DCMIPP main features .....1298
31.3DCMIPP functional description .....1299
31.3.1DCMIPP block diagram .....1299
31.3.2DCMIPP pads and internal signals .....1299
31.3.3DCMIPP reset and clocks .....1300
31.3.4DCMIPP maximum resolution .....1302
31.3.5DCMIPP minimum requirements for frame structure .....1302
31.3.6Description of DCMIPP pixel format support .....1302
31.4DCMIPP input and flow control .....1303
31.4.1DCMIPP common configuration .....1303
31.4.2Parallel input interface .....1304
31.4.3Frame counter .....1307
31.4.4Frame control .....1307
31.4.5Pipe deactivation .....1311
31.10.16DCMIPP common interrupt enable register (DCMIPP_CMIER) . . . .1337
31.10.17DCMIPP common status register 1 (DCMIPP_CMSR1) . . . . .1338
31.10.18DCMIPP common status register 2 (DCMIPP_CMSR2) . . . . .1339
31.10.19DCMIPP common interrupt clear register (DCMIPP_CMFCR) . . . .1340
31.10.20DCMIPP Pipe0 flow selection configuration register
(DCMIPP_P0FSCR) . . . . .		1341
31.10.21DCMIPP Pipe0 flow control configuration register
(DCMIPP_P0FCTCR) . . . . .		1341
31.10.22DCMIPP Pipe0 statistic/crop start register (DCMIPP_P0SCSTR) . . .1342
31.10.23DCMIPP Pipe0 statistic/crop size register (DCMIPP_P0SCSZR) . . .1343
31.10.24DCMIPP Pipe0 dump counter register (DCMIPP_P0DCCNTR) . . . .1343
31.10.25DCMIPP Pipe0 dump limit register (DCMIPP_P0DCLMTR) . . . . .1344
31.10.26DCMIPP Pipe0 pixel packer configuration register
(DCMIPP_P0PPCR) . . . . .		1344
31.10.27DCMIPP Pipe0 pixel packer Memory0 address register 1
(DCMIPP_P0PPM0AR1) . . . . .		1345
31.10.28DCMIPP Pipe0 pixel packer Memory0 address register 2
(DCMIPP_P0PPM0AR2) . . . . .		1346
31.10.29DCMIPP Pipe0 interrupt enable register (DCMIPP_P0IER) . . . . .1346
31.10.30DCMIPP Pipe0 status register (DCMIPP_P0SR) . . . . .1347
31.10.31DCMIPP Pipe0 interrupt clear register (DCMIPP_P0FCR) . . . . .1348
31.10.32DCMIPP Pipe0 current flow control configuration register
(DCMIPP_P0CFCTCR) . . . . .		1349
31.10.33DCMIPP Pipe0 current statistic/crop start register
(DCMIPP_P0CSCSTR) . . . . .		1349
31.10.34DCMIPP Pipe0 current statistic/crop size register
(DCMIPP_P0CSCSZR) . . . . .		1350
31.10.35DCMIPP Pipe0 current pixel packer configuration register
(DCMIPP_P0CPPCR) . . . . .		1351
31.10.36DCMIPP Pipe0 current pixel packer Memory0 address register 1
(DCMIPP_P0CPPM0AR1) . . . . .		1352
31.10.37DCMIPP Pipe0 current pixel packer Memory0 address register 2
(DCMIPP_P0CPPM0AR2) . . . . .		1352
31.11DCMIPP register map . . . . .1354
32Parallel synchronous slave interface (PSSI) . . . . .1357
32.1PSSI introduction . . . . .1357
32.2PSSI main features . . . . .1357
32.3PSSI functional description . . . . .1357
32.3.1PSSI block diagram . . . . .1358
32.3.2PSSI pins and internal signals . . . . .1358
32.3.3PSSI clock . . . . .1359
32.3.4PSSI data management . . . . .1359
32.3.5PSSI optional control signals . . . . .1361
32.4PSSI interrupts . . . . .1364
32.5PSSI registers . . . . .1364
32.5.1PSSI control register (PSSI_CR) . . . . .1364
32.5.2PSSI status register (PSSI_SR) . . . . .1366
32.5.3PSSI raw interrupt status register (PSSI_RIS) . . . . .1367
32.5.4PSSI interrupt enable register (PSSI_IER) . . . . .1368
32.5.5PSSI masked interrupt status register (PSSI_MIS) . . . . .1368
32.5.6PSSI interrupt clear register (PSSI_ICR) . . . . .1369
32.5.7PSSI data register (PSSI_DR) . . . . .1369
32.5.8PSSI register map . . . . .1370
33LCD-TFT display controller (LTDC) . . . . .1371
33.1Introduction . . . . .1371
33.2LTDC main features . . . . .1371
33.3LTDC functional description . . . . .1372
33.3.1LTDC block diagram . . . . .1372
33.3.2LTDC pins and internal signals . . . . .1372
33.3.3LTDC reset and clocks . . . . .1373
33.4LTDC programmable parameters . . . . .1375
33.4.1LTDC global configuration parameters . . . . .1375
33.4.2Layer programmable parameters . . . . .1377
33.5LTDC interrupts . . . . .1381
33.6LTDC programming procedure . . . . .1382
33.7LTDC registers . . . . .1383
33.7.1LTDC synchronization size configuration register (LTDC_SSCR) . . . . .1383
33.7.2LTDC back porch configuration register (LTDC_BPCR) . . . . .1383
33.7.3LTDC active width configuration register (LTDC_AWCR) . . . . .1384
33.7.4LTDC total width configuration register (LTDC_TWCR) . . . . .1385
33.7.5LTDC global control register (LTDC_GCR) . . . . .1385
33.7.6LTDC shadow reload configuration register (LTDC_SRCR) . . . . .1387
33.7.7LTDC background color configuration register (LTDC_BCCR) . . . . .1387
33.7.8LTDC interrupt enable register (LTDC_IER) . . . . .1388
33.7.9LTDC interrupt status register (LTDC_ISR) . . . . .1389
33.7.10LTDC interrupt clear register (LTDC_ICR) . . . . .1389
33.7.11LTDC line interrupt position configuration register (LTDC_LIPCR) . . .1390
33.7.12LTDC current position status register (LTDC_CPSR) . . . . .1390
33.7.13LTDC current display status register (LTDC_CDSR) . . . . .1391
33.7.14LTDC layer x control register (LTDC_LxCR) . . . . .1391
33.7.15LTDC layer x window horizontal position configuration register
(LTDC_LxWHPER) . . . . .		1392
33.7.16LTDC layer x window vertical position configuration register
(LTDC_LxWVPER) . . . . .		1393
33.7.17LTDC layer x color keying configuration register
(LTDC_LxCKCR) . . . . .		1394
33.7.18LTDC layer x pixel format configuration register
(LTDC_LxPFCR) . . . . .		1394
33.7.19LTDC layer x constant alpha configuration register
(LTDC_LxCACR) . . . . .		1395
33.7.20LTDC layer x default color configuration register
(LTDC_LxDCCR) . . . . .		1395
33.7.21LTDC layer x blending factors configuration register
(LTDC_LxBFCR) . . . . .		1396
33.7.22LTDC layer x color frame buffer address register
(LTDC_LxCFBAR) . . . . .		1397
33.7.23LTDC layer x color frame buffer length register
(LTDC_LxCFBLR) . . . . .		1397
33.7.24LTDC layer x color frame buffer line number register
(LTDC_LxCFBLNR) . . . . .		1398
33.7.25LTDC layer x CLUT write register (LTDC_LxCLUTWR) . . . . .1398
33.7.26LTDC register map . . . . .1399
34JPEG codec (JPEG) . . . . .1402
34.1JPEG introduction . . . . .1402
34.2JPEG codec main features . . . . .1402
34.3JPEG codec block functional description . . . . .1403
34.3.1General description . . . . .1403
34.3.2JPEG internal signals . . . . .1403
34.3.3JPEG decoding procedure . . . . .1404
34.3.4JPEG encoding procedure . . . . .1406
34.4JPEG codec interrupts . . . . .1409
34.5JPEG codec registers . . . . .1409
34.5.1JPEG codec control register (JPEG_CONFR0) . . . . .1409
34.5.2JPEG codec configuration register 1 (JPEG_CONFR1) . . . . .1410
34.5.3JPEG codec configuration register 2 (JPEG_CONFR2) . . . . .1411
34.5.4JPEG codec configuration register 3 (JPEG_CONFR3) . . . . .1411
34.5.5JPEG codec configuration register x (JPEG_CONFRx) . . . . .1412
34.5.6JPEG control register (JPEG_CR) . . . . .1413
34.5.7JPEG status register (JPEG_SR) . . . . .1414
34.5.8JPEG clear flag register (JPEG_CFR) . . . . .1415
34.5.9JPEG data input register (JPEG_DIR) . . . . .1416
34.5.10JPEG data output register (JPEG_DOR) . . . . .1416
34.5.11JPEG quantization memory x (JPEG_QMEMx_y) . . . . .1417
34.5.12JPEG Huffman min (JPEG_HUFFMINx_y) . . . . .1417
34.5.13JPEG Huffman min x (JPEG_HUFFMINx_y) . . . . .1418
34.5.14JPEG Huffman base (JPEG_HUFFBASEx) . . . . .1418
34.5.15JPEG Huffman symbol (JPEG_HUFFSYMBx) . . . . .1419
34.5.16JPEG DHT memory (JPEG_DHTMEMx) . . . . .1420
34.5.17JPEG Huffman encoder ACx (JPEG_HUFFENC_ACx_y) . . . . .1420
34.5.18JPEG Huffman encoder DCx (JPEG_HUFFENC_DCx_y) . . . . .1421
34.5.19JPEG codec register map . . . . .1422
35True random number generator (RNG) . . . . .1424
35.1RNG introduction . . . . .1424
35.2RNG main features . . . . .1424
35.3RNG functional description . . . . .1425
35.3.1RNG block diagram . . . . .1425
35.3.2RNG internal signals . . . . .1425
35.3.3Random number generation . . . . .1425
35.3.4RNG initialization . . . . .1428
35.3.5RNG operation . . . . .1429
35.3.6RNG clocking . . . . .1431
35.3.7Error management . . . . .1431
35.3.8RNG low-power use . . . . .1432
35.4RNG interrupts . . . . .1433
35.5RNG processing time . . . . .1433
35.6RNG entropy source validation . . . . .1434
35.6.1Introduction . . . . .1434
35.6.2Validation conditions .....1434
35.7RNG registers .....1435
35.7.1RNG control register (RNG_CR) .....1435
35.7.2RNG status register (RNG_SR) .....1437
35.7.3RNG data register (RNG_DR) .....1438
35.7.4RNG noise source control register (RNG_NSCR) .....1439
35.7.5RNG health test control register (RNG_HTCR) .....1440
35.7.6RNG register map .....1440
36Secure AES coprocessor (SAES) .....1441
36.1SAES introduction .....1441
36.2SAES main features .....1441
36.3SAES implementation .....1442
36.4SAES functional description .....1442
36.4.1SAES block diagram .....1442
36.4.2SAES internal signals .....1443
36.4.3SAES reset and clocks .....1444
36.4.4SAES symmetric cipher implementation .....1444
36.4.5SAES encryption or decryption typical usage .....1445
36.4.6SAES authenticated encryption, decryption, and cipher-based message authentication .....1447
36.4.7SAES ciphertext stealing and data padding .....1447
36.4.8SAES suspend and resume operations .....1448
36.4.9SAES basic chaining modes (ECB, CBC) .....1448
36.4.10SAES counter (CTR) mode .....1453
36.4.11SAES Galois/counter mode (GCM) .....1455
36.4.12SAES Galois message authentication code (GMAC) .....1459
36.4.13SAES counter with CBC-MAC (CCM) .....1461
36.4.14SAES operation with wrapped keys .....1466
36.4.15SAES operation with shared keys .....1470
36.4.16SAES data registers and data swapping .....1471
36.4.17SAES key registers .....1474
36.4.18SAES initialization vector registers .....1475
36.4.19SAES error management .....1475
36.5SAES interrupts .....1477
36.6SAES DMA requests .....1478
37.4.8CRYP suspend and resume operations . . . . .1503
37.4.9CRYP basic chaining modes (ECB, CBC) . . . . .1503
37.4.10CRYP counter mode (CTR) . . . . .1508
37.4.11CRYP AES Galois/counter mode (GCM) . . . . .1510
37.4.12CRYP AES Galois message authentication code (GMAC) . . . . .1516
37.4.13CRYP AES Counter with CBC-MAC (CCM) . . . . .1517
37.4.14AES key sharing with secure AES co-processor . . . . .1522
37.4.15CRYP data registers and data swapping . . . . .1523
37.4.16CRYP key registers . . . . .1526
37.4.17CRYP initialization vector registers . . . . .1526
37.4.18CRYP error management . . . . .1527
37.5CRYP interrupts . . . . .1527
37.6CRYP DMA requests . . . . .1528
37.7CRYP processing time . . . . .1529
37.8CRYP registers . . . . .1530
37.8.1CRYP control register (CRYP_CR) . . . . .1530
37.8.2CRYP status register (CRYP_SR) . . . . .1532
37.8.3CRYP data input register (CRYP_DINR) . . . . .1534
37.8.4CRYP data output register (CRYP_DOUTR) . . . . .1534
37.8.5CRYP DMA control register (CRYP_DMACR) . . . . .1535
37.8.6CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . .1535
37.8.7CRYP raw interrupt status register (CRYP_RISR) . . . . .1536
37.8.8CRYP masked interrupt status register (CRYP_MISR) . . . . .1536
37.8.9CRYP key register 0L (CRYP_K0LR) . . . . .1537
37.8.10CRYP key register 0R (CRYP_K0RR) . . . . .1538
37.8.11CRYP key register 1L (CRYP_K1LR) . . . . .1538
37.8.12CRYP key register 1R (CRYP_K1RR) . . . . .1538
37.8.13CRYP key register 2L (CRYP_K2LR) . . . . .1539
37.8.14CRYP key register 2R (CRYP_K2RR) . . . . .1539
37.8.15CRYP key register 3L (CRYP_K3LR) . . . . .1540
37.8.16CRYP key register 3R (CRYP_K3RR) . . . . .1540
37.8.17CRYP initialization vector register 0L (CRYP_IV0LR) . . . . .1540
37.8.18CRYP initialization vector register 0R (CRYP_IV0RR) . . . . .1541
37.8.19CRYP initialization vector register 1L (CRYP_IV1LR) . . . . .1541
37.8.20CRYP initialization vector register 1R (CRYP_IV1RR) . . . . .1542
37.8.21CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) . . . . .1542
37.8.22CRYP context swap GCM registers (CRYP_CSGCMxR) . . . . .1543

37.8.23 CRYP register map ..... 1543

38 Hash processor (HASH) ..... 1545

38.1 HASH introduction ..... 1545

38.2 HASH main features ..... 1545

38.3 HASH implementation ..... 1546

38.4 HASH functional description ..... 1546

38.4.1 HASH block diagram ..... 1546

38.4.2 HASH internal signals ..... 1546

38.4.3 About secure hash algorithms ..... 1547

38.4.4 Message data feeding ..... 1547

38.4.5 Message digest computing ..... 1548

38.4.6 Message padding ..... 1550

38.4.7 HMAC operation ..... 1552

38.4.8 HASH suspend/resume operations ..... 1553

38.4.9 HASH DMA interface ..... 1555

38.4.10 HASH error management ..... 1556

38.4.11 HASH processing time ..... 1556

38.5 HASH interrupts ..... 1557

38.6 HASH registers ..... 1557

38.6.1 HASH control register (HASH_CR) ..... 1557

38.6.2 HASH data input register (HASH_DIN) ..... 1559

38.6.3 HASH start register (HASH_STR) ..... 1560

38.6.4 HASH digest registers ..... 1561

38.6.5 HASH interrupt enable register (HASH_IMR) ..... 1563

38.6.6 HASH status register (HASH_SR) ..... 1563

38.6.7 HASH context swap registers ..... 1564

38.6.8 HASH register map ..... 1565

39 Memory cipher engine (MCE) ..... 1567

39.1 MCE introduction ..... 1567

39.2 MCE main features ..... 1567

39.3 MCE implementation ..... 1568

39.4 MCE functional description ..... 1569

39.4.1 MCE block diagram ..... 1569

39.4.2 MCE internal signals ..... 1569

39.4.3MCE programming . . . . .1570
39.4.4MCE reset and clocks . . . . .1571
39.4.5MCE block cipher encryption mode . . . . .1571
39.4.6MCE stream cipher encryption mode . . . . .1573
39.4.7MCE AXI traffic management . . . . .1574
39.4.8MCE encryption disable options . . . . .1574
39.4.9MCE error management . . . . .1575
39.5MCE interrupts . . . . .1575
39.6MCE registers . . . . .1576
39.6.1MCE configuration register (MCE_CR) . . . . .1576
39.6.2MCE status register (MCE_SR) . . . . .1576
39.6.3MCE illegal access status register (MCE_IASR) . . . . .1577
39.6.4MCE illegal access clear register (MCE_IACR) . . . . .1578
39.6.5MCE illegal access interrupt enable register (MCE_IAIER) . . . . .1578
39.6.6MCE privileged configuration register (MCE_PRIVCFGR) . . . . .1579
39.6.7MCE illegal access error status register (MCE_IAESR) . . . . .1579
39.6.8MCE illegal address register (MCE_IADDR) . . . . .1580
39.6.9MCE region x configuration register (MCE_REGCRx) . . . . .1580
39.6.10MCE start address for region x register
(MCE_SADDRx) . . . . .		1582
39.6.11MCE end address for region x register
(MCE_EADDRx) . . . . .		1582
39.6.12MCE attribute for region x register (MCE_ATTRx) . . . . .1583
39.6.13MCE master key x (MCE_MKEYRx) . . . . .1583
39.6.14MCE fast master key x (MCE_FMKEYRx) . . . . .1583
39.6.15MCE cipher context z configuration register (MCE_CCzCFGR) . . . . .1584
39.6.16MCE cipher context z nonce register 0 (MCE_CCzNR0) . . . . .1586
39.6.17MCE cipher context z nonce register 1 (MCE_CCzNR1) . . . . .1586
39.6.18MCE cipher context z key register 0 (MCE_CCzKEYR0) . . . . .1587
39.6.19MCE cipher context z key register 1 (MCE_CCzKEYR1) . . . . .1587
39.6.20MCE cipher context z key register 2 (MCE_CCzKEYR2) . . . . .1588
39.6.21MCE cipher context z key register 3 (MCE_CCzKEYR3) . . . . .1588
39.6.22MCE register map . . . . .1589
40Public key accelerator (PKA) . . . . .1591
40.1PKA introduction . . . . .1591
40.2PKA main features . . . . .1591

40.7.3 PKA clear flag register (PKA_CLRFR) . . . . . 1622

40.7.4 PKA RAM . . . . . 1622

40.7.5 PKA register map . . . . . 1623

41 Advanced-control timers (TIM1) . . . . . 1624

41.1 TIM1 introduction . . . . . 1624

41.2 TIM1 main features . . . . . 1625

41.3 TIM1 functional description . . . . . 1626

41.3.1 Block diagram . . . . . 1626

41.3.2 TIM1 pins and internal signals . . . . . 1627

41.3.3 Time-base unit . . . . . 1631

41.3.4 Counter modes . . . . . 1633

41.3.5 Repetition counter . . . . . 1645

41.3.6 External trigger input . . . . . 1646

41.3.7 Clock selection . . . . . 1647

41.3.8 Capture/compare channels . . . . . 1651

41.3.9 Input capture mode . . . . . 1653

41.3.10 PWM input mode . . . . . 1654

41.3.11 Forced output mode . . . . . 1655

41.3.12 Output compare mode . . . . . 1656

41.3.13 PWM mode . . . . . 1657

41.3.14 Asymmetric PWM mode . . . . . 1665

41.3.15 Combined PWM mode . . . . . 1666

41.3.16 Combined 3-phase PWM mode . . . . . 1667

41.3.17 Complementary outputs and dead-time insertion . . . . . 1668

41.3.18 Using the break function . . . . . 1671

41.3.19 Bidirectional break inputs . . . . . 1677

41.3.20 Clearing the tim_ocxref signal on an external event . . . . . 1678

41.3.21 6-step PWM generation . . . . . 1679

41.3.22 One-pulse mode . . . . . 1680

41.3.23 Retriggerable One-pulse mode . . . . . 1682

41.3.24 Pulse on compare mode . . . . . 1683

41.3.25 Encoder interface mode . . . . . 1685

41.3.26 Direction bit output . . . . . 1702

41.3.27 UIF bit remapping . . . . . 1703

41.3.28 Timer input XOR function . . . . . 1703

41.3.29 Interfacing with Hall sensors . . . . . 1703

41.3.30Timer synchronization . . . . .1705
41.3.31ADC triggers . . . . .1710
41.3.32DMA burst mode . . . . .1710
41.3.33TIM1 DMA requests . . . . .1711
41.3.34Debug mode . . . . .1711
41.4TIM1 low-power modes . . . . .1712
41.5TIM1 interrupts . . . . .1712
41.6TIM1 registers . . . . .1713
41.6.1TIM1 control register 1 (TIM1_CR1) . . . . .1713
41.6.2TIM1 control register 2 (TIM1_CR2) . . . . .1714
41.6.3TIM1 slave mode control register (TIM1_SMCR) . . . . .1718
41.6.4TIM1 DMA/interrupt enable register (TIM1_DIER) . . . . .1722
41.6.5TIM1 status register (TIM1_SR) . . . . .1723
41.6.6TIM1 event generation register (TIM1_EGR) . . . . .1726
41.6.7TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . .1727
41.6.8TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . .		1729
41.6.9TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . .1732
41.6.10TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . .		1733
41.6.11TIM1 capture/compare enable register (TIM1_CCER) . . . . .1736
41.6.12TIM1 counter (TIM1_CNT) . . . . .1740
41.6.13TIM1 prescaler (TIM1_PSC) . . . . .1740
41.6.14TIM1 autoreload register (TIM1_ARR) . . . . .1741
41.6.15TIM1 repetition counter register (TIM1_RCR) . . . . .1741
41.6.16TIM1 capture/compare register 1 (TIM1_CCR1) . . . . .1742
41.6.17TIM1 capture/compare register 2 (TIM1_CCR2) . . . . .1742
41.6.18TIM1 capture/compare register 3 (TIM1_CCR3) . . . . .1743
41.6.19TIM1 capture/compare register 4 (TIM1_CCR4) . . . . .1744
41.6.20TIM1 break and dead-time register (TIM1_BDTR) . . . . .1745
41.6.21TIM1 capture/compare register 5 (TIM1_CCR5) . . . . .1749
41.6.22TIM1 capture/compare register 6 (TIM1_CCR6) . . . . .1750
41.6.23TIM1 capture/compare mode register 3 (TIM1_CCMR3) . . . . .1751
41.6.24TIM1 timer deadtime register 2 (TIM1_DTR2) . . . . .1752
41.6.25TIM1 timer encoder control register (TIM1_ECR) . . . . .1753
41.6.26TIM1 timer input selection register (TIM1_TISEL) . . . . .1754
41.6.27TIM1 alternate function option register 1 (TIM1_AF1) . . . . .1755
41.6.28TIM1 alternate function register 2 (TIM1_AF2) .....1758
41.6.29TIM1 DMA control register (TIM1_DCR) .....1760
41.6.30TIM1 DMA address for full transfer (TIM1_DMAR) .....1762
41.6.31TIM1 register map .....1762
42General-purpose timers (TIM2/TIM3/TIM4/TIM5) .....1765
42.1TIM2/TIM3/TIM4/TIM5 introduction .....1765
42.2TIM2/TIM3/TIM4/TIM5 main features .....1765
42.3TIM2/TIM3/TIM4/TIM5 implementation .....1766
42.4TIM2/TIM3/TIM4/TIM5 functional description .....1767
42.4.1Block diagram .....1767
42.4.2TIM2/TIM3/TIM4/TIM5 pins and internal signals .....1768
42.4.3Time-base unit .....1771
42.4.4Counter modes .....1773
42.4.5Clock selection .....1785
42.4.6Capture/compare channels .....1789
42.4.7Input capture mode .....1791
42.4.8PWM input mode .....1792
42.4.9Forced output mode .....1793
42.4.10Output compare mode .....1793
42.4.11PWM mode .....1795
42.4.12Asymmetric PWM mode .....1803
42.4.13Combined PWM mode .....1804
42.4.14Clearing the tim_ocxref signal on an external event .....1805
42.4.15One-pulse mode .....1807
42.4.16Retriggerable one-pulse mode .....1808
42.4.17Pulse on compare mode .....1809
42.4.18Encoder interface mode .....1811
42.4.19Direction bit output .....1829
42.4.20UIF bit remapping .....1830
42.4.21Timer input XOR function .....1830
42.4.22Timers and external trigger synchronization .....1830
42.4.23Timer synchronization .....1834
42.4.24ADC triggers .....1839
42.4.25DMA burst mode .....1840
42.4.26TIM2/TIM3/TIM4/TIM5 DMA requests .....1841
42.4.27Debug mode .....1841
42.4.28TIM2/TIM3/TIM4/TIM5 low-power modes . . . . .1841
42.4.29TIM2/TIM3/TIM4/TIM5 interrupts . . . . .1842
42.5TIM2/TIM3/TIM4/TIM5 registers . . . . .1843
42.5.1TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . .1843
42.5.2TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . .1844
42.5.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . .1846
42.5.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . .1850
42.5.5TIMx status register (TIMx_SR)(x = 2 to 5) . . . . .1851
42.5.6TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . .1853
42.5.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) . . . . .1854
42.5.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 2 to 5) . . . . .		1856
42.5.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) . . . . .1858
42.5.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 2 to 5) . . . . .		1859
42.5.11TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5) . . . . .1862
42.5.12TIMx counter (TIMx_CNT)(x = 2 to 5) . . . . .1864
42.5.13TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . .1864
42.5.14TIMx autoreload register (TIMx_ARR)(x = 2 to 5) . . . . .1865
42.5.15TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) . . . . .1865
42.5.16TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) . . . . .1866
42.5.17TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) . . . . .1867
42.5.18TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) . . . . .1868
42.5.19TIMx timer encoder control register (TIMx_ECR)(x = 2 to 5) . . . . .1869
42.5.20TIMx timer input selection register (TIMx_TISEL)(x = 2 to 5) . . . . .1870
42.5.21TIMx alternate function register 1 (TIMx_AF1)(x = 2 to 5) . . . . .1871
42.5.22TIMx alternate function register 2 (TIMx_AF2)(x = 2 to 5) . . . . .1872
42.5.23TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . .1873
42.5.24TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . .1874
42.5.25TIMx register map . . . . .1875
43Basic timers (TIM6/TIM7) . . . . .1878
43.1TIM6/TIM7 introduction . . . . .1878
43.2TIM6/TIM7 main features . . . . .1878
43.3TIM6/TIM7 functional description . . . . .1878
43.3.1TIM6/TIM7 block diagram . . . . .1878
43.3.2TIM6/TIM7 internal signals . . . . .1879
43.3.3TIM6/TIM7 clocks . . . . .1879
43.3.4Time-base unit . . . . .1880
43.3.5Counting mode . . . . .1882
43.3.6UIF bit remapping . . . . .1888
43.3.7ADC triggers . . . . .1889
43.3.8TIM6/TIM7 DMA requests . . . . .1889
43.3.9Debug mode . . . . .1889
43.3.10TIM6/TIM7 low-power modes . . . . .1889
43.3.11TIM6/TIM7 interrupts . . . . .1889
43.4TIM6/TIM7 registers . . . . .1890
43.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . .1890
43.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . .1892
43.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . .1892
43.4.4TIMx status register (TIMx_SR)(x = 6 to 7) . . . . .1893
43.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . .1893
43.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . .1893
43.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . .1894
43.4.8TIMx autoreload register (TIMx_ARR)(x = 6 to 7) . . . . .1894
43.4.9TIMx register map . . . . .1895
44General-purpose timers (TIM9/TIM12/TIM13/TIM14) . . . . .1896
44.1TIM9/TIM12/TIM13/TIM14 introduction . . . . .1896
44.2TIM9/TIM12 main features . . . . .1896
44.3TIM13/TIM14 main features . . . . .1897
44.4TIM9/TIM12/TIM13/TIM14 functional description . . . . .1898
44.4.1Block diagram . . . . .1898
44.4.2TIM9/TIM12/TIM13/TIM14 pins and internal signals . . . . .1899
44.4.3Time-base unit . . . . .1901
44.4.4Counter modes . . . . .1903
44.4.5Clock selection . . . . .1906
44.4.6Capture/compare channels . . . . .1908
44.4.7Input capture mode . . . . .1910
44.4.8PWM input mode (TIM9/TIM12 only) . . . . .1911
44.4.9Forced output mode . . . . .1912
44.4.10Output compare mode . . . . .1913
44.4.11PWM mode . . . . .1914
44.4.12Combined PWM mode (TIM9/TIM12 only) . . . . .1919
44.4.13One-pulse mode . . . . .1920
44.4.14Retriggerable one pulse mode (TIM9/TIM12 only) . . . . .1922
44.4.15UIF bit remapping . . . . .1923
44.4.16Timer input XOR function . . . . .1923
44.4.17TIM9/TIM12 external trigger synchronization . . . . .1923
44.4.18Slave mode – combined reset + trigger mode . . . . .1926
44.4.19Slave mode – combined reset + gated mode . . . . .1926
44.4.20Timer synchronization (TIM9/TIM12 only) . . . . .1926
44.4.21Using timer output as trigger for other timers
(TIM13/TIM14 only) . . . . .		1926
44.4.22ADC triggers (TIM9/TIM12 only) . . . . .1926
44.4.23Debug mode . . . . .1926
44.5TIM9/TIM12/TIM13/TIM14 low-power modes . . . . .1927
44.6TIM9/TIM12/TIM13/TIM14 interrupts . . . . .1927
44.7TIM9/TIM12 registers . . . . .1927
44.7.1TIMx control register 1 (TIMx_CR1)(x = 9, 12) . . . . .1927
44.7.2TIM12 control register 2 (TIMx_CR2)(x = 9, 12) . . . . .1929
44.7.3TIMx slave mode control register (TIMx_SMCR)(x = 9, 12) . . . . .1929
44.7.4TIMx interrupt enable register (TIMx_DIER)(x = 9, 12) . . . . .1931
44.7.5TIMx status register (TIMx_SR)(x = 9, 12) . . . . .1932
44.7.6TIMx event generation register (TIMx_EGR)(x = 9, 12) . . . . .1933
44.7.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 9, 12) . . . . .1934
44.7.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 9, 12) . . . . .		1935
44.7.9TIMx capture/compare enable register (TIMx_CCER)(x = 9, 12) . . . . .1938
44.7.10TIMx counter (TIMx_CNT)(x = 9, 12) . . . . .1939
44.7.11TIMx prescaler (TIMx_PSC)(x = 9, 12) . . . . .1940
44.7.12TIMx autoreload register (TIMx_ARR)(x = 9, 12) . . . . .1940
44.7.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 9, 12) . . . . .1941
44.7.14TIMx capture/compare register 2 (TIMx_CCR2)(x = 9, 12) . . . . .1941
44.7.15TIMx timer input selection register (TIMx_TISEL)(x = 9, 12) . . . . .1942
44.7.16TIM9/TIM12 register map . . . . .1943
44.8TIM13/TIM14 registers . . . . .1945
44.8.1TIMx control register 1 (TIMx_CR1)(x = 13, 14) . . . . .1945
44.8.2TIMx interrupt enable register (TIMx_DIER)(x = 13, 14) . . . . .1946
44.8.3TIMx status register (TIMx_SR)(x = 13, 14) . . . . .1946
44.8.4TIMx event generation register (TIMx_EGR)(x = 13, 14) . . . . .1947
44.8.5TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 13, 14) . . . . .		1948
44.8.6TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 13, 14) . . . . .		1949
44.8.7TIMx capture/compare enable register
(TIMx_CCER)(x = 13, 14) . . . . .		1951
44.8.8TIMx counter (TIMx_CNT)(x = 13, 14) . . . . .1952
44.8.9TIMx prescaler (TIMx_PSC)(x = 13, 14) . . . . .1953
44.8.10TIMx autoreload register (TIMx_ARR)(x = 13, 14) . . . . .1953
44.8.11TIMx capture/compare register 1 (TIMx_CCR1)(x = 13, 14) . . . . .1954
44.8.12TIMx timer input selection register (TIMx_TISEL)(x = 13, 14) . . . . .1954
44.8.13TIM13/TIM14 register map . . . . .1955
45General purpose timers (TIM15/TIM16/TIM17) . . . . .1957
45.1TIM15/TIM16/TIM17 introduction . . . . .1957
45.2TIM15 main features . . . . .1957
45.3TIM16/TIM17 main features . . . . .1958
45.4TIM15/TIM16/TIM17 functional description . . . . .1959
45.4.1Block diagram . . . . .1959
45.4.2TIM15/TIM16/TIM17 pins and internal signals . . . . .1960
45.4.3Time-base unit . . . . .1963
45.4.4Counter modes . . . . .1965
45.4.5Repetition counter . . . . .1969
45.4.6Clock selection . . . . .1970
45.4.7Capture/compare channels . . . . .1972
45.4.8Input capture mode . . . . .1974
45.4.9PWM input mode (only for TIM15) . . . . .1976
45.4.10Forced output mode . . . . .1977
45.4.11Output compare mode . . . . .1977
45.4.12PWM mode . . . . .1979
45.4.13Combined PWM mode (TIM15 only) . . . . .1984
45.4.14Complementary outputs and dead-time insertion . . . . .1985
45.4.15Using the break function . . . . .1988
45.4.16Bidirectional break input . . . . .1992
45.4.17Clearing the tim_ocxref signal on an external event . . . . .1993
45.4.186-step PWM generation . . . . .1994
45.4.19One-pulse mode . . . . .1996
45.4.20Retriggerable one pulse mode (TIM15 only) . . . . .1997
45.4.21UIF bit remapping . . . . .1998
45.4.22Timer input XOR function (TIM15 only) . . . . .1998
45.4.23External trigger synchronization (TIM15 only) . . . . .1998
45.4.24Slave mode – combined reset + trigger mode (TIM15 only) . . . . .2001
45.4.25Slave mode – combined reset + gated mode (TIM15 only) . . . . .2001
45.4.26Timer synchronization (TIM15 only) . . . . .2002
45.4.27Using timer output as trigger for other timers (TIM16/TIM17 only) . . . . .2002
45.4.28ADC triggers (TIM15 only) . . . . .2002
45.4.29DMA burst mode . . . . .2002
45.4.30TIM15/TIM16/TIM17 DMA requests . . . . .2003
45.4.31Debug mode . . . . .2004
45.5TIM15/TIM16/TIM17 low-power modes . . . . .2004
45.6TIM15/TIM16/TIM17 interrupts . . . . .2004
45.7TIM15 registers . . . . .2004
45.7.1TIM15 control register 1 (TIM15_CR1) . . . . .2005
45.7.2TIM15 control register 2 (TIM15_CR2) . . . . .2006
45.7.3TIM15 slave mode control register (TIM15_SMCR) . . . . .2008
45.7.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .2010
45.7.5TIM15 status register (TIM15_SR) . . . . .2011
45.7.6TIM15 event generation register (TIM15_EGR) . . . . .2013
45.7.7TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .2014
45.7.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		2016
45.7.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .2018
45.7.10TIM15 counter (TIM15_CNT) . . . . .2021
45.7.11TIM15 prescaler (TIM15_PSC) . . . . .2021
45.7.12TIM15 autoreload register (TIM15_ARR) . . . . .2022
45.7.13TIM15 repetition counter register (TIM15_RCR) . . . . .2022
45.7.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .2023
45.7.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .2024
45.7.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .2024
45.7.17TIM15 timer deadtime register 2 (TIM15_DTR2) . . . . .2027
45.7.18TIM15 input selection register (TIM15_TISEL) . . . . .2028
45.7.19TIM15 alternate function register 1 (TIM15_AF1) . . . . .2029
45.7.20TIM15 alternate function register 2 (TIM15_AF2) . . . . .2031
45.7.21TIM15 DMA control register (TIM15_DCR) . . . . .2032
45.7.22TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .2033
45.7.23TIM15 register map .....2033
45.8TIM16/TIM17 registers .....2036
45.8.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) .....2036
45.8.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) .....2037
45.8.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) .....2038
45.8.4TIMx status register (TIMx_SR)(x = 16 to 17) .....2039
45.8.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) .....2040
45.8.6TIMx capture/compare mode register 1 (TIMx_CCMR1)
(x = 16 to 17) .....		2041
45.8.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) .....		2042
45.8.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) .2044
45.8.9TIMx counter (TIMx_CNT)(x = 16 to 17) .....2047
45.8.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) .....2047
45.8.11TIMx auto-reautoreload register (TIMx_ARR)(x = 16 to 17) .....2048
45.8.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) .....2048
45.8.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) .....2049
45.8.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) .....2050
45.8.15TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16 to 17) .....2053
45.8.16TIMx input selection register (TIMx_TISEL)(x = 16 to 17) .....2054
45.8.17TIMx alternate function register 1 (TIMx_AF1)(x = 16 to 17) .....2054
45.8.18TIMx alternate function register 2 (TIMx_AF2)(x = 16 to 17) .....2057
45.8.19TIMx DMA control register (TIMx_DCR)(x = 16 to 17) .....2057
45.8.20TIM16/TIM17 DMA address for full transfer
(TIMx_DMAR)(x = 16 to 17) .....		2058
45.8.21TIM16/TIM17 register map .....2060
46Low-power timer (LPTIM) .....2062
46.1LPTIM introduction .....2062
46.2LPTIM main features .....2062
46.3LPTIM implementation .....2063
46.4LPTIM functional description .....2064
46.4.1LPTIM block diagram .....2064
46.4.2LPTIM pins and internal signals .....2065
46.4.3LPTIM input and trigger mapping .....2067
46.4.4LPTIM reset and clocks .....2068
46.4.5Glitch filter .....2069
46.4.6Prescaler . . . . .2070
46.4.7Trigger multiplexer . . . . .2070
46.4.8Operating mode . . . . .2071
46.4.9Timeout function . . . . .2073
46.4.10Waveform generation . . . . .2073
46.4.11Register update . . . . .2074
46.4.12Counter mode . . . . .2075
46.4.13Timer enable . . . . .2075
46.4.14Timer counter reset . . . . .2076
46.4.15Encoder mode . . . . .2076
46.4.16Repetition counter . . . . .2078
46.4.17Capture/compare channels . . . . .2079
46.4.18Input capture mode . . . . .2080
46.4.19PWM mode . . . . .2082
46.4.20DMA requests . . . . .2084
46.4.21Debug mode . . . . .2085
46.5LPTIM low-power modes . . . . .2085
46.6LPTIM interrupts . . . . .2085
46.7LPTIM registers . . . . .2086
46.7.1LPTIMx interrupt and status register (LPTIMx_ISR)(x = 4 to 5) . . . . .2087
46.7.2LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1 to 3) . . . . .		2088
46.7.3LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1 to 3) . . . . .		2090
46.7.4LPTIMx interrupt clear register (LPTIMx_ICR)(x = 4 to 5) . . . . .2092
46.7.5LPTIMx interrupt clear register [alternate] (LPTIMx_ICR)
(x = 1 to 3) . . . . .		2093
46.7.6LPTIMx interrupt clear register [alternate] (LPTIMx_ICR)
(x = 1 to 3) . . . . .		2094
46.7.7LPTIMx interrupt enable register (LPTIMx_DIER)(x = 4 to 5) . . . . .2095
46.7.8LPTIMx interrupt enable register [alternate] (LPTIMx_DIER)
(x = 1 to 3) . . . . .		2097
46.7.9LPTIMx interrupt enable register [alternate] (LPTIMx_DIER)
(x = 1 to 3) . . . . .		2098
46.7.10LPTIM configuration register (LPTIM_CFGR) . . . . .2100
46.7.11LPTIM control register (LPTIM_CR) . . . . .2103
46.7.12LPTIM compare register 1 (LPTIM_CCR1) . . . . .2104
46.7.13LPTIM autoreload register (LPTIM_ARR) . . . . .2105
46.7.14LPTIM counter register (LPTIM_CNT) . . . . .2105
46.7.15LPTIM configuration register 2 (LPTIM_CFGR2) . . . . .2106
46.7.16LPTIM repetition register (LPTIM_RCR) . . . . .2107
46.7.17LPTIM capture/compare mode register 1 (LPTIM_CCMR1) . . . . .2107
46.7.18LPTIM compare register 2 (LPTIM_CCR2) . . . . .2110
46.7.19LPTIM register map . . . . .2110
47System window watchdog (WWDG) . . . . .2113
47.1WWDG introduction . . . . .2113
47.2WWDG main features . . . . .2113
47.3WWDG implementation . . . . .2113
47.4WWDG functional description . . . . .2114
47.4.1WWDG block diagram . . . . .2114
47.4.2WWDG internal signals . . . . .2114
47.4.3Enabling the watchdog . . . . .2115
47.4.4Controlling the down-counter . . . . .2115
47.4.5How to program the watchdog timeout . . . . .2115
47.4.6Debug mode . . . . .2116
47.5WWDG interrupts . . . . .2117
47.6WWDG registers . . . . .2117
47.6.1WWDG control register (WWDG_CR) . . . . .2117
47.6.2WWDG configuration register (WWDG_CFR) . . . . .2118
47.6.3WWDG status register (WWDG_SR) . . . . .2118
47.6.4WWDG register map . . . . .2119
48Independent watchdog (IWDG) . . . . .2120
48.1IWDG introduction . . . . .2120
48.2IWDG main features . . . . .2120
48.3IWDG implementation . . . . .2120
48.4IWDG functional description . . . . .2121
48.4.1IWDG block diagram . . . . .2121
48.4.2IWDG internal signals . . . . .2122
48.4.3Software and hardware watchdog modes . . . . .2122
48.4.4Window option . . . . .2123
48.4.5Debug . . . . .2126
48.4.6Register access protection . . . . .2126
48.5IWDG low power modes . . . . .2127
48.6IWDG interrupts . . . . .2127
48.7IWDG registers . . . . .2129
48.7.1IWDG key register (IWDG_KR) . . . . .2130
48.7.2IWDG prescaler register (IWDG_PR) . . . . .2130
48.7.3IWDG reload register (IWDG_RLR) . . . . .2131
48.7.4IWDG status register (IWDG_SR) . . . . .2131
48.7.5IWDG window register (IWDG_WINR) . . . . .2133
48.7.6IWDG early wake-up interrupt register (IWDG_EWCR) . . . . .2133
48.7.7IWDG register map . . . . .2135
49Real-time clock (RTC) . . . . .2136
49.1RTC introduction . . . . .2136
49.2RTC main features . . . . .2136
49.3RTC functional description . . . . .2136
49.3.1RTC block diagram . . . . .2136
49.3.2RTC pins and internal signals . . . . .2138
49.3.3GPIOs controlled by the RTC and TAMP . . . . .2139
49.3.4RTC privilege protection modes . . . . .2142
49.3.5Clock and prescalers . . . . .2143
49.3.6Real-time clock and calendar . . . . .2144
49.3.7Calendar ultra-low power mode . . . . .2145
49.3.8Programmable alarms . . . . .2145
49.3.9Periodic auto-wake-up . . . . .2145
49.3.10RTC initialization and configuration . . . . .2146
49.3.11Reading the calendar . . . . .2149
49.3.12Resetting the RTC . . . . .2150
49.3.13RTC synchronization . . . . .2151
49.3.14RTC reference clock detection . . . . .2151
49.3.15RTC smooth digital calibration . . . . .2152
49.3.16Timestamp function . . . . .2154
49.3.17Calibration clock output . . . . .2155
49.3.18Tamper and alarm output . . . . .2155
49.4RTC low-power modes . . . . .2156
49.5RTC interrupts . . . . .2156
49.6RTC registers . . . . .2157
49.6.1RTC time register (RTC_TR) . . . . .2157
49.6.2RTC date register (RTC_DR) . . . . .2158
49.6.3RTC subsecond register (RTC_SSR) . . . . .2159
49.6.4RTC initialization control and status register (RTC_ICSR) . . . . .2160
49.6.5RTC prescaler register (RTC_PRER) . . . . .2162
49.6.6RTC wake-up timer register (RTC_WUTR) . . . . .2162
49.6.7RTC control register (RTC_CR) . . . . .2163
49.6.8RTC privilege mode control register (RTC_PRIVCFGR) . . . . .2167
49.6.9RTC write protection register (RTC_WPR) . . . . .2168
49.6.10RTC calibration register (RTC_CALR) . . . . .2169
49.6.11RTC shift control register (RTC_SHIFTTR) . . . . .2170
49.6.12RTC timestamp time register (RTC_TSTR) . . . . .2171
49.6.13RTC timestamp date register (RTC_TSDR) . . . . .2172
49.6.14RTC timestamp subsecond register (RTC_TSSSR) . . . . .2173
49.6.15RTC alarm A register (RTC_ALRMAR) . . . . .2173
49.6.16RTC alarm A subsecond register (RTC_ALRMASSR) . . . . .2174
49.6.17RTC alarm B register (RTC_ALRMBR) . . . . .2175
49.6.18RTC alarm B subsecond register (RTC_ALRMBSSR) . . . . .2176
49.6.19RTC status register (RTC_SR) . . . . .2177
49.6.20RTC masked interrupt status register (RTC_MISR) . . . . .2179
49.6.21RTC status clear register (RTC_SCR) . . . . .2180
49.6.22RTC alarm A binary mode register (RTC_ALRABINR) . . . . .2181
49.6.23RTC alarm B binary mode register (RTC_ALRBBINR) . . . . .2181
49.6.24RTC register map . . . . .2183
50Tamper and backup registers (TAMP) . . . . .2185
50.1TAMP introduction . . . . .2185
50.2TAMP main features . . . . .2185
50.3TAMP functional description . . . . .2186
50.3.1TAMP block diagram . . . . .2186
50.3.2TAMP pins and internal signals . . . . .2187
50.3.3GPIOs controlled by the RTC and TAMP . . . . .2189
50.3.4TAMP register write protection . . . . .2190
50.3.5Backup registers protection zones . . . . .2190
50.3.6TAMP privilege protection modes . . . . .2190
50.3.7Boot hardware key (BHK) . . . . .2191
50.3.8Tamper detection . . . . .2191
51.4.8I2C target mode . . . . .2239
51.4.9I2C controller mode . . . . .2248
51.4.10I2C_TIMINGR register configuration examples . . . . .2259
51.4.11SMBus specific features . . . . .2261
51.4.12SMBus initialization . . . . .2263
51.4.13SMBus I2C_TIMEOUTR register configuration examples . . . . .2265
51.4.14SMBus target mode . . . . .2266
51.4.15SMBus controller mode . . . . .2269
51.4.16Wake-up from Stop mode on address match . . . . .2272
51.4.17Error conditions . . . . .2273
51.5I2C in low-power modes . . . . .2275
51.6I2C interrupts . . . . .2275
51.7I2C DMA requests . . . . .2276
51.7.1Transmission using DMA . . . . .2276
51.7.2Reception using DMA . . . . .2276
51.8I2C debug modes . . . . .2276
51.9I2C registers . . . . .2277
51.9.1I2C control register 1 (I2C_CR1) . . . . .2277
51.9.2I2C control register 2 (I2C_CR2) . . . . .2280
51.9.3I2C own address 1 register (I2C_OAR1) . . . . .2282
51.9.4I2C own address 2 register (I2C_OAR2) . . . . .2282
51.9.5I2C timing register (I2C_TIMINGR) . . . . .2283
51.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .2284
51.9.7I2C interrupt and status register (I2C_ISR) . . . . .2285
51.9.8I2C interrupt clear register (I2C_ICR) . . . . .2288
51.9.9I2C PEC register (I2C_PECR) . . . . .2289
51.9.10I2C receive data register (I2C_RXDR) . . . . .2289
51.9.11I2C transmit data register (I2C_TXDR) . . . . .2290
51.9.12I2C register map . . . . .2291
52Improved inter-integrated circuit (I3C) . . . . .2292
52.1I3C introduction . . . . .2292
52.2I3C main features . . . . .2292
52.3I3C implementation . . . . .2294
52.3.1I3C instantiation . . . . .2294
52.3.2I3C wake-up from low-power mode(s) . . . . .2294
52.3.3I3C FIFOs . . . . .2294
52.3.4I3C triggers . . . . .2294
52.3.5I3C interrupt(s) . . . . .2294
52.3.6I3C MIPI ® support . . . . .2295
52.4I3C block diagram . . . . .2296
52.5I3C pins and internal signals . . . . .2296
52.6I3C reset and clocks . . . . .2297
52.6.1I3C reset . . . . .2297
52.6.2I3C clocks and requirements . . . . .2297
52.7I3C peripheral state and programming . . . . .2299
52.7.1I3C peripheral state . . . . .2299
52.7.2I3C controller state and programming sequence . . . . .2300
52.7.3I3C target state and programming sequence . . . . .2304
52.8I3C registers and programming . . . . .2308
52.8.1I3C register set, as controller/target . . . . .2308
52.8.2I3C registers and fields use versus peripheral state, as controller . . . . .2309
52.8.3I3C registers and fields usage versus peripheral state, as target . . . . .2312
52.9I3C bus transfers and programming . . . . .2314
52.9.1I3C command set (CCC), as controller/target . . . . .2314
52.9.2I3C broadcast/direct CCC transfer (except ENTDAA, RSTACT),
as controller . . . . .		2318
52.9.3I3C broadcast ENTDAA CCC transfer, as controller . . . . .2320
52.9.4I3C broadcast/direct RSTACT CCC transfer, as controller . . . . .2320
52.9.5I3C broadcast/direct CCC transfer
(except ENTDAA, DEFTGTS, DEFGRPA), as target . . . . .		2322
52.9.6I3C broadcast ENTDAA CCC transfer, as target . . . . .2324
52.9.7I3C broadcast DEFTGTS CCC transfer, as target . . . . .2325
52.9.8I3C broadcast DEFGRPA CCC transfer, as target . . . . .2326
52.9.9I3C direct GETSTATUS CCC response, as target . . . . .2327
52.9.10I3C private read/write transfer, as controller . . . . .2328
52.9.11I3C private read/write transfer, as target . . . . .2329
52.9.12Legacy I2C read/write transfer, as controller . . . . .2330
52.9.13I3C IBI transfer, as controller/target . . . . .2331
52.9.14I3C hot-join request transfer, as controller/target . . . . .2332
52.9.15I3C controller-role request transfer, as controller/target . . . . .2333
52.10I3C FIFOs management, as controller . . . . .2334
52.10.1C-FIFO management, as controller . . . . .2334
52.10.2TX-FIFO management, as controller . . . . .2335
52.10.3RX-FIFO management, as controller . . . . .2338
52.10.4S-FIFO management, as controller . . . . .2340
52.11I3C FIFOs management, as target . . . . .2342
52.11.1RX-FIFO management, as target . . . . .2342
52.11.2TX-FIFO management, as target . . . . .2343
52.12I3C error management . . . . .2346
52.12.1Controller error management . . . . .2346
52.12.2Target error management . . . . .2348
52.13I3C wake-up from low-power mode(s) . . . . .2349
52.13.1Wake-up from Stop . . . . .2349
52.14I3C in low-power modes . . . . .2352
52.15I3C interrupts . . . . .2353
52.16I3C registers . . . . .2354
52.16.1I3C message control register (I3C_CR) . . . . .2354
52.16.2I3C message control register [alternate] (I3C_CR) . . . . .2356
52.16.3I3C configuration register (I3C_CFGGR) . . . . .2358
52.16.4I3C receive data byte register (I3C_RDR) . . . . .2363
52.16.5I3C receive data word register (I3C_RDWR) . . . . .2363
52.16.6I3C transmit data byte register (I3C_TDR) . . . . .2364
52.16.7I3C transmit data word register (I3C_TDWR) . . . . .2365
52.16.8I3C IBI payload data register (I3C_IBIDR) . . . . .2367
52.16.9I3C target transmit configuration register (I3C_TGTTDR) . . . . .2368
52.16.10I3C status register (I3C_SR) . . . . .2369
52.16.11I3C status error register (I3C_SER) . . . . .2370
52.16.12I3C received message register (I3C_RMR) . . . . .2372
52.16.13I3C event register (I3C_EVR) . . . . .2373
52.16.14I3C interrupt enable register (I3C_IER) . . . . .2377
52.16.15I3C clear event register (I3C_CEVR) . . . . .2379
52.16.16I3C own device characteristics register (I3C_DEVR0) . . . . .2381
52.16.17I3C device x characteristics register (I3C_DEVRx) . . . . .2383
52.16.18I3C maximum read length register (I3C_MAXRLR) . . . . .2385
52.16.19I3C maximum write length register (I3C_MAXWLR) . . . . .2386
52.16.20I3C timing register 0 (I3C_TIMINGR0) . . . . .2387
52.16.21I3C timing register 1 (I3C_TIMINGR1) . . . . .2388
52.16.22I3C timing register 2 (I3C_TIMINGR2) . . . . .2390
52.16.23I3C bus characteristics register (I3C_BCR) . . . . .2391
52.16.24I3C device characteristics register (I3C_DCR) . . . . .2392
52.16.25I3C get capability register (I3C_GETCAPR) . . . . .2393
52.16.26I3C controller-role capability register (I3C_CRCAPR) . . . . .2394
52.16.27I3C get max data speed register (I3C_GETMXDSR) . . . . .2395
52.16.28I3C extended provisioned ID register (I3C_EPIDR) . . . . .2397
52.16.29I3C register map . . . . .2398
53Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .2401
53.1USART introduction . . . . .2401
53.2USART main features . . . . .2401
53.3USART extended features . . . . .2402
53.4USART implementation . . . . .2402
53.5USART functional description . . . . .2404
53.5.1USART block diagram . . . . .2404
53.5.2USART pins and internal signals . . . . .2404
53.5.3USART clocks . . . . .2406
53.5.4USART character description . . . . .2406
53.5.5USART FIFOs and thresholds . . . . .2409
53.5.6USART transmitter . . . . .2409
53.5.7USART receiver . . . . .2412
53.5.8USART baud rate generation . . . . .2419
53.5.9Tolerance of the USART receiver to clock deviation . . . . .2421
53.5.10USART auto baud rate detection . . . . .2422
53.5.11USART multiprocessor communication . . . . .2424
53.5.12USART Modbus communication . . . . .2426
53.5.13USART parity control . . . . .2427
53.5.14USART LIN (local interconnection network) mode . . . . .2428
53.5.15USART synchronous mode . . . . .2430
53.5.16USART single-wire half-duplex communication . . . . .2434
53.5.17USART receiver timeout . . . . .2434
53.5.18USART smartcard mode . . . . .2435
53.5.19USART IrDA SIR ENDEC block . . . . .2439
53.5.20Continuous communication using USART and DMA . . . . .2442
53.5.21RS232 hardware flow control and RS485 driver enable . . . . .2444
53.5.22USART low-power management . . . . .2447
53.6USART in low-power modes . . . . .2450
53.7USART interrupts . . . . .2450
53.8USART registers . . . . .2453
53.8.1USART control register 1 (USART_CR1) . . . . .2453
53.8.2USART control register 1 [alternate] (USART_CR1) . . . . .2457
53.8.3USART control register 2 (USART_CR2) . . . . .2460
53.8.4USART control register 3 (USART_CR3) . . . . .2464
53.8.5USART control register 3 [alternate] (USART_CR3) . . . . .2468
53.8.6USART baud rate register (USART_BRR) . . . . .2471
53.8.7USART guard time and prescaler register (USART_GTPR) . . . . .2472
53.8.8USART receiver timeout register (USART_RTOR) . . . . .2473
53.8.9USART request register (USART_RQR) . . . . .2474
53.8.10USART interrupt and status register (USART_ISR) . . . . .2475
53.8.11USART interrupt and status register [alternate] (USART_ISR) . . . . .2481
53.8.12USART interrupt flag clear register (USART_ICR) . . . . .2486
53.8.13USART receive data register (USART_RDR) . . . . .2487
53.8.14USART transmit data register (USART_TDR) . . . . .2488
53.8.15USART prescaler register (USART_PRESC) . . . . .2488
53.8.16USART register map . . . . .2489
54Low-power universal asynchronous receiver transmitter (LPUART) . . . . .2491
54.1LPUART introduction . . . . .2491
54.2LPUART main features . . . . .2491
54.3LPUART implementation . . . . .2492
54.4LPUART functional description . . . . .2494
54.4.1LPUART block diagram . . . . .2494
54.4.2LPUART pins and internal signals . . . . .2495
54.4.3LPUART clocks . . . . .2496
54.4.4LPUART character description . . . . .2496
54.4.5LPUART FIFOs and thresholds . . . . .2498
54.4.6LPUART transmitter . . . . .2498
54.4.7LPUART receiver . . . . .2502
54.4.8LPUART baud rate generation . . . . .2506
54.4.9Tolerance of the LPUART receiver to clock deviation . . . . .2507
54.4.10LPUART multiprocessor communication . . . . .2508
54.4.11LPUART parity control . . . . .2510
54.4.12LPUART single-wire half-duplex communication . . . . .2511
54.4.13Continuous communication using DMA and LPUART . . . . .2511
54.4.14RS232 hardware flow control and RS485 driver enable . . . . .2514
54.4.15LPUART low-power management . . . . .2516
54.5LPUART in low-power modes . . . . .2519
54.6LPUART interrupts . . . . .2520
54.7LPUART registers . . . . .2521
54.7.1LPUART control register 1 (LPUART_CR1) . . . . .2521
54.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .2524
54.7.3LPUART control register 2 (LPUART_CR2) . . . . .2527
54.7.4LPUART control register 3 (LPUART_CR3) . . . . .2529
54.7.5LPUART control register 3 [alternate] (LPUART_CR3) . . . . .2532
54.7.6LPUART baud rate register (LPUART_BRR) . . . . .2534
54.7.7LPUART request register (LPUART_RQR) . . . . .2534
54.7.8LPUART interrupt and status register (LPUART_ISR) . . . . .2535
54.7.9LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .2540
54.7.10LPUART interrupt flag clear register (LPUART_ICR) . . . . .2543
54.7.11LPUART receive data register (LPUART_RDR) . . . . .2544
54.7.12LPUART transmit data register (LPUART_TDR) . . . . .2544
54.7.13LPUART prescaler register (LPUART_PRESC) . . . . .2545
54.7.14LPUART register map . . . . .2546
55Serial peripheral interface (SPI) . . . . .2548
55.1SPI introduction . . . . .2548
55.2SPI main features . . . . .2548
55.3SPI implementation . . . . .2549
55.4SPI functional description . . . . .2550
55.4.1SPI block diagram . . . . .2550
55.4.2SPI pins and internal signals . . . . .2551
55.4.3SPI communication general aspects . . . . .2552
55.4.4Communications between one master and one slave . . . . .2552
55.4.5Standard multislave communication . . . . .2555
55.4.6Multimaster communication . . . . .2558
55.4.7Slave select (NSS pin) management . . . . .2559
55.4.8Ready pin (RDY) management . . . . .2563
55.4.9Communication formats . . . . .2563
55.4.10Configuring the SPI . . . . .2565
55.4.11Enabling the SPI . . . . .2566
55.4.12SPI data transmission and reception procedures . . . . .2567
55.4.13Disabling the SPI . . . . .2571
55.4.14Communication using DMA (direct memory addressing) . . . . .2572
55.5SPI specific modes and control . . . . .2574
55.5.1TI mode . . . . .2574
55.5.2SPI error flags . . . . .2574
55.5.3CRC computation . . . . .2578
55.6SPI in low-power modes . . . . .2579
55.7SPI interrupts . . . . .2579
55.8I2S main features . . . . .2581
55.9I2S functional description . . . . .2581
55.9.1I2S general description . . . . .2581
55.9.2Pin sharing with SPI function . . . . .2582
55.9.3Bitfields usable in I2S/PCM mode . . . . .2582
55.9.4Slave and master modes . . . . .2583
55.9.5Supported audio protocols . . . . .2583
55.9.6Additional serial interface flexibility . . . . .2589
55.9.7Startup sequence . . . . .2591
55.9.8Stop sequence . . . . .2593
55.9.9Clock generator . . . . .2594
55.9.10Internal FIFOs . . . . .2596
55.9.11FIFO status flags . . . . .2597
55.9.12Handling of underrun situation . . . . .2597
55.9.13Handling of overrun situation . . . . .2598
55.9.14Frame error detection . . . . .2599
55.9.15DMA interface . . . . .2601
55.9.16Programing examples . . . . .2601
55.10I2S interrupts . . . . .2604
55.11SPI/I2S registers . . . . .2604
55.11.1SPI/I2S control register 1 (SPI_CR1) . . . . .2604
55.11.2SPI/I2S control register 2 (SPI_CR2) . . . . .2606
55.11.3SPI/I2S configuration register 1 (SPI_CFG1) . . . . .2607
55.11.4SPI/I2S configuration register 2 (SPI_CFG2) . . . . .2610
55.11.5SPI/I2S interrupt enable register (SPI_IER) . . . . .2612

55.11.6 SPI/I2S status register (SPI_SR) . . . . . 2613

55.11.7 SPI/I2S interrupt/status flags clear register (SPI_IFCR) . . . . . 2616

55.11.8 SPI/I2S transmit data register (SPI_TXDR) . . . . . 2617

55.11.9 SPI/I2S receive data register (SPI_RXDR) . . . . . 2617

55.11.10 SPI/I2S polynomial register (SPI_CRCPOLY) . . . . . 2618

55.11.11 SPI/I2S transmitter CRC register (SPI_TXCRC) . . . . . 2618

55.11.12 SPI/I2S receiver CRC register (SPI_RXCRC) . . . . . 2619

55.11.13 SPI/I2S underrun data register (SPI_UDRDR) . . . . . 2620

55.11.14 SPI/I2S configuration register (SPI_I2SCFGR) . . . . . 2620

55.11.15 SPI/I2S register map . . . . . 2622

56 Serial audio interface (SAI) . . . . . 2624

56.1 SAI introduction . . . . . 2624

56.2 SAI main features . . . . . 2624

56.3 SAI implementation . . . . . 2625

56.4 SAI functional description . . . . . 2626

56.4.1 SAI block diagram . . . . . 2626

56.4.2 SAI pins and internal signals . . . . . 2627

56.4.3 Main SAI modes . . . . . 2628

56.4.4 SAI synchronization mode . . . . . 2629

56.4.5 Audio data size . . . . . 2630

56.4.6 Frame synchronization . . . . . 2630

56.4.7 Slot configuration . . . . . 2633

56.4.8 SAI clock generator . . . . . 2635

56.4.9 Internal FIFOs . . . . . 2638

56.4.10 PDM interface . . . . . 2640

56.4.11 AC'97 link controller . . . . . 2648

56.4.12 SPDIF output . . . . . 2650

56.4.13 Specific features . . . . . 2653

56.4.14 Error flags . . . . . 2657

56.4.15 Disabling the SAI . . . . . 2660

56.4.16 SAI DMA interface . . . . . 2660

56.5 SAI interrupts . . . . . 2661

56.6 SAI registers . . . . . 2663

56.6.1 SAI global configuration register (SAI_GCR) . . . . . 2663

56.6.2 SAI configuration register 1 (SAI_ACR1) . . . . . 2663

56.6.3SAI configuration register 2 (SAI_ACR2) . . . . .2666
56.6.4SAI frame configuration register (SAI_AFRCR) . . . . .2668
56.6.5SAI slot register (SAI_ASLOTR) . . . . .2669
56.6.6SAI interrupt mask register (SAI_AIM) . . . . .2670
56.6.7SAI status register (SAI_ASR) . . . . .2672
56.6.8SAI clear flag register (SAI_ACLRFR) . . . . .2674
56.6.9SAI data register (SAI_ADR) . . . . .2675
56.6.10SAI configuration register 1 (SAI_BCR1) . . . . .2675
56.6.11SAI configuration register 2 (SAI_BCR2) . . . . .2678
56.6.12SAI frame configuration register (SAI_BFRCR) . . . . .2680
56.6.13SAI slot register (SAI_BSLOTR) . . . . .2681
56.6.14SAI interrupt mask register (SAI_BIM) . . . . .2682
56.6.15SAI status register (SAI_BSR) . . . . .2683
56.6.16SAI clear flag register (SAI_BCLRFR) . . . . .2685
56.6.17SAI data register (SAI_BDR) . . . . .2686
56.6.18SAI PDM control register (SAI_PDMCR) . . . . .2687
56.6.19SAI PDM delay register (SAI_PDMDLY) . . . . .2688
56.6.20SAI register map . . . . .2690
57SPDIFRX receiver interface (SPDIFRX) . . . . .2692
57.1SPDIFRX interface introduction . . . . .2692
57.2SPDIFRX main features . . . . .2692
57.3SPDIFRX functional description . . . . .2692
57.3.1SPDIFRX pins and internal signals . . . . .2693
57.3.2S/PDIF protocol (IEC-60958) . . . . .2694
57.3.3SPDIFRX decoder (SPDIFRX_DC) . . . . .2696
57.3.4SPDIFRX tolerance to clock deviation . . . . .2700
57.3.5SPDIFRX synchronization . . . . .2700
57.3.6SPDIFRX handling . . . . .2702
57.3.7Data reception management . . . . .2704
57.3.8Dedicated control flow . . . . .2706
57.3.9Reception errors . . . . .2707
57.3.10Clocking strategy . . . . .2709
57.3.11Symbol clock generation . . . . .2709
57.3.12DMA interface . . . . .2711
57.3.13Interrupt generation . . . . .2712
57.3.14Register protection . . . . .2713
57.4Programming procedures . . . . .2713
57.4.1Initialization phase . . . . .2714
57.4.2Handling of interrupts coming from SPDIFRX . . . . .2715
57.4.3Handling of interrupts coming from DMA . . . . .2715
57.5SPDIFRX interface registers . . . . .2716
57.5.1SPDIFRX control register (SPDIFRX_CR) . . . . .2716
57.5.2SPDIFRX interrupt mask register (SPDIFRX_IMR) . . . . .2718
57.5.3SPDIFRX status register (SPDIFRX_SR) . . . . .2719
57.5.4SPDIFRX interrupt flag clear register (SPDIFRX_IFCR) . . . . .2721
57.5.5SPDIFRX data input register (SPDIFRX_FMT0_DR) . . . . .2722
57.5.6SPDIFRX data input register (SPDIFRX_FMT1_DR) . . . . .2722
57.5.7SPDIFRX data input register (SPDIFRX_FMT2_DR) . . . . .2723
57.5.8SPDIFRX channel status register (SPDIFRX_CSR) . . . . .2724
57.5.9SPDIFRX debug information register (SPDIFRX_DIR) . . . . .2724
57.5.10SPDIFRX interface register map . . . . .2725
58Management data input/output (MDIOS) . . . . .2726
58.1MDIOS introduction . . . . .2726
58.2MDIOS main features . . . . .2726
58.3MDIOS functional description . . . . .2727
58.3.1MDIOS block diagram . . . . .2727
58.3.2MDIOS pins and internal signals . . . . .2727
58.3.3MDIOS protocol . . . . .2727
58.3.4MDIOS enabling and disabling . . . . .2728
58.3.5MDIOS data . . . . .2729
58.3.6MDIOS APB frequency . . . . .2730
58.3.7Write/read flags and interrupts . . . . .2730
58.3.8MDIOS error management . . . . .2731
58.3.9MDIOS in Stop mode . . . . .2732
58.3.10MDIOS interrupts . . . . .2732
58.4MDIOS registers . . . . .2732
58.4.1MDIOS configuration register (MDIOS_CR) . . . . .2732
58.4.2MDIOS write flag register (MDIOS_WRFR) . . . . .2733
58.4.3MDIOS clear write flag register (MDIOS_CWRFR) . . . . .2734
58.4.4MDIOS read flag register (MDIOS_RDFR) . . . . .2734
58.4.5MDIOS clear read flag register (MDIOS_CRDFR) . . . . .2735
58.4.6MDIOS status register (MDIOS_SR) .....2735
58.4.7MDIOS clear flag register (MDIOS_CLRFR) .....2736
58.4.8MDIOS input data register x (MDIOS_DINRx) .....2736
58.4.9MDIOS output data register x (MDIOS_DOUTRx) .....2737
58.4.10MDIOS register map .....2737
59Secure digital input/output MultiMediaCard interface (SDMMC) ..2739
59.1SDMMC main features .....2739
59.2SDMMC implementation .....2739
59.3SDMMC bus topology .....2740
59.4SDMMC operation modes .....2742
59.5SDMMC functional description .....2743
59.5.1SDMMC block diagram .....2743
59.5.2SDMMC pins and internal signals .....2743
59.5.3General description .....2744
59.5.4SDMMC adapter .....2746
59.5.5SDMMC AHB slave interface .....2768
59.5.6SDMMC AHB master interface .....2769
59.5.7AHB and SDMMC_CK clock relation .....2772
59.6Card functional description .....2772
59.6.1SD I/O mode .....2772
59.6.2CMD12 send timing .....2780
59.6.3Sleep (CMD5) .....2784
59.6.4Interrupt mode (Wait-IRQ) .....2785
59.6.5Boot operation .....2786
59.6.6Response R1b handling .....2789
59.6.7Reset and card cycle power .....2790
59.7Hardware flow control .....2791
59.8Ultra-high-speed phase I (UHS-I) voltage switch .....2791
59.9SDMMC interrupts .....2795
59.10SDMMC registers .....2796
59.10.1SDMMC power control register (SDMMC_POWER) .....2796
59.10.2SDMMC clock control register (SDMMC_CLKCR) .....2797
59.10.3SDMMC argument register (SDMMC_ARGR) .....2799
59.10.4SDMMC command register (SDMMC_CMDR) .....2799
59.10.5SDMMC command response register (SDMMC_RESPCMDR) .....2801
59.10.6SDMMC response x register (SDMMC_RESPxR) . . . . .2802
59.10.7SDMMC data timer register (SDMMC_DTIMER) . . . . .2802
59.10.8SDMMC data length register (SDMMC_DLENR) . . . . .2803
59.10.9SDMMC data control register (SDMMC_DCTRL) . . . . .2804
59.10.10SDMMC data counter register (SDMMC_DCNTR) . . . . .2805
59.10.11SDMMC status register (SDMMC_STAR) . . . . .2806
59.10.12SDMMC interrupt clear register (SDMMC_ICR) . . . . .2809
59.10.13SDMMC mask register (SDMMC_MASKR) . . . . .2811
59.10.14SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . . . .2814
59.10.15SDMMC DMA control register (SDMMC_IDMACTRLR) . . . . .2814
59.10.16SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . .2815
59.10.17SDMMC IDMA buffer base address register
(SDMMC_IDMABASER) . . . . .		2816
59.10.18SDMMC IDMA linked list address register (SDMMC_IDMALAR) . . . . .2816
59.10.19SDMMC IDMA linked list memory base register
(SDMMC_IDMABAR) . . . . .		2817
59.10.20SDMMC data FIFO registers x (SDMMC_FIFORx) . . . . .2818
59.10.21SDMMC register map . . . . .2818
60FD controller area network (FDCAN) . . . . .2821
60.1FDCAN introduction . . . . .2821
60.2FDCAN main features . . . . .2823
60.3FDCAN functional description . . . . .2824
60.3.1FDCAN block diagram . . . . .2824
60.3.2FDCAN pins and internal signals . . . . .2825
60.3.3Bit timing . . . . .2826
60.3.4Operating modes . . . . .2827
60.3.5Error management . . . . .2836
60.3.6Message RAM . . . . .2837
60.3.7FIFO acknowledge handling . . . . .2846
60.3.8FDCAN Rx FIFO element . . . . .2846
60.3.9FDCAN Tx buffer element . . . . .2848
60.3.10FDCAN Tx event FIFO element . . . . .2850
60.3.11FDCAN standard message ID filter element . . . . .2851
60.3.12FDCAN extended message ID filter element . . . . .2852
60.4FDCAN registers . . . . .2854
60.4.1FDCAN core release register (FDCAN_CREL) . . . . .2854
60.4.2FDCAN endian register (FDCAN_ENDN) . . . . .2854
60.4.3FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . .2854
60.4.4FDCAN test register (FDCAN_TEST) . . . . .2855
60.4.5FDCAN RAM watchdog register (FDCAN_RWD) . . . . .2856
60.4.6FDCAN CC control register (FDCAN_CCCR) . . . . .2857
60.4.7FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . .2858
60.4.8FDCAN timestamp counter configuration register (FDCAN_TSCC) .2860
60.4.9FDCAN timestamp counter value register (FDCAN_TSCV) . . . . .2860
60.4.10FDCAN timeout counter configuration register (FDCAN_TOCC) . . .2861
60.4.11FDCAN timeout counter value register (FDCAN_TOCV) . . . . .2862
60.4.12FDCAN error counter register (FDCAN_ECR) . . . . .2862
60.4.13FDCAN protocol status register (FDCAN_PSR) . . . . .2863
60.4.14FDCAN transmitter delay compensation register (FDCAN_TDCR) . .2865
60.4.15FDCAN interrupt register (FDCAN_IR) . . . . .2865
60.4.16FDCAN interrupt enable register (FDCAN_IE) . . . . .2868
60.4.17FDCAN interrupt line select register (FDCAN_ILS) . . . . .2870
60.4.18FDCAN interrupt line enable register (FDCAN_ILE) . . . . .2871
60.4.19FDCAN global filter configuration register (FDCAN_RXGFC) . . . . .2871
60.4.20FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . .2873
60.4.21FDCAN high-priority message status register (FDCAN_HPMS) . . . .2873
60.4.22FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . .2874
60.4.23CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . .2875
60.4.24FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . .2875
60.4.25FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . .2876
60.4.26FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . .2876
60.4.27FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . .2877
60.4.28FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . .2877
60.4.29FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . .2878
60.4.30FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . .2879
60.4.31FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) .2879
60.4.32FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . .2880
60.4.33FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . .		2880
60.4.34FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_TXBCIE) . . . . .		2881
60.4.35FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . .2881
60.4.36FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . .2882
60.4.37FDCAN CFG clock divider register (FDCAN_CKDIV) . . . . .2882
60.4.38FDCAN register map . . . . .2883
61USB on-the-go full-speed (OTG_FS) . . . . .2887
61.1OTG_FS introduction . . . . .2887
61.2OTG_FS main features . . . . .2888
61.2.1General features . . . . .2888
61.2.2Host-mode features . . . . .2889
61.2.3Peripheral-mode features . . . . .2889
61.3OTG_FS implementation . . . . .2890
61.4OTG_FS functional description . . . . .2891
61.4.1OTG_FS block diagram . . . . .2891
61.4.2OTG_FS pin and internal signals . . . . .2891
61.4.3OTG_FS core . . . . .2892
61.4.4Embedded full-speed OTG PHY connected to OTG_FS . . . . .2892
61.4.5OTG detections . . . . .2893
61.5OTG_FS dual role device (DRD) . . . . .2893
61.5.1ID line detection . . . . .2893
61.6OTG_FS as a USB peripheral . . . . .2894
61.6.1Peripheral states . . . . .2894
61.6.2Peripheral endpoints . . . . .2895
61.7OTG_FS as a USB host . . . . .2897
61.7.1USB host states . . . . .2898
61.7.2Host channels . . . . .2899
61.7.3Host scheduler . . . . .2901
61.8OTG_FS SOF trigger . . . . .2902
61.8.1Host SOFs . . . . .2902
61.8.2Peripheral SOFs . . . . .2902
61.9OTG_FS low-power modes . . . . .2903
61.10OTG_FS Dynamic update of the OTG_HFIR register . . . . .2904
61.11OTG_FS data FIFOs . . . . .2904
61.11.1Peripheral FIFO architecture . . . . .2905
61.11.2Host FIFO architecture . . . . .2906
61.11.3FIFO RAM allocation . . . . .2907
61.12OTG_FS system performance . . . . .2909
61.13OTG_FS interrupts . . . . .2909
61.14OTG_FS control and status registers . . . . .2911
61.14.1CSR memory map . . . . .2911
61.15OTG_FS registers . . . . .2916
61.15.1OTG control and status register (OTG_GOTGCTL) . . . . .2916
61.15.2OTG interrupt register (OTG_GOTGINT) . . . . .2918
61.15.3OTG AHB configuration register (OTG_GAHBCFG) . . . . .2919
61.15.4OTG USB configuration register (OTG_GUSBCFG) . . . . .2920
61.15.5OTG reset register (OTG_GRSTCTL) . . . . .2921
61.15.6OTG core interrupt register [alternate] (OTG_GINTSTS) . . . . .2924
61.15.7OTG core interrupt register [alternate] (OTG_GINTSTS) . . . . .2928
61.15.8OTG interrupt mask register [alternate] (OTG_GINTMSK) . . . . .2932
61.15.9OTG interrupt mask register [alternate] (OTG_GINTMSK) . . . . .2933
61.15.10OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . .2935
61.15.11OTG receive status debug read register [alternate]
(OTG_GRXSTSR) . . . . .		2936
61.15.12OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . . . .2937
61.15.13OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . . . .2938
61.15.14OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .2939
61.15.15OTG host non-periodic transmit FIFO size register [alternate]
(OTG_HNPTXFSIZ) . . . . .		2940
61.15.16Endpoint 0 Transmit FIFO size [alternate] (OTG_DIEPTXF0) . . . . .2940
61.15.17OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . .		2941
61.15.18OTG general core configuration register (OTG_GCCFG) . . . . .2942
61.15.19OTG core ID register (OTG_CID) . . . . .2943
61.15.20OTG core LPM configuration register (OTG_GLPMCFG) . . . . .2943
61.15.21OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . .		2948
61.15.22OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . .		2948
61.15.23Host-mode registers . . . . .2948
61.15.24OTG host configuration register (OTG_HCFG) . . . . .2949
61.15.25OTG host frame interval register (OTG_HFIR) . . . . .2949
61.15.26OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . .		2950
61.15.27OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . .		2951
61.15.28OTG host all channels interrupt register (OTG_HAINT) . . . . .2952
61.15.29 OTG host all channels interrupt mask register
(OTG_HAINTMSK) .....		2952
61.15.30 OTG host port control and status register (OTG_HPRT) .....2953
61.15.31 OTG host channel x characteristics register (OTG_HCCHARx) .....2955
61.15.32 OTG host channel x interrupt register (OTG_HCINTx) .....2956
61.15.33 OTG host channel x interrupt mask register (OTG_HCINTMSKx) ..2957
61.15.34 OTG host channel x transfer size register (OTG_HCTSIZx) .....2958
61.15.35 Device-mode registers .....2959
61.15.36 OTG device configuration register (OTG_DCFG) .....2959
61.15.37 OTG device control register (OTG_DCTL) .....2960
61.15.38 OTG device status register (OTG_DSTS) .....2963
61.15.39 OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) .....		2964
61.15.40 OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) .....		2965
61.15.41 OTG device all endpoints interrupt register (OTG_DAINIT) .....2966
61.15.42 OTG all endpoints interrupt mask register
(OTG_DAINMSK) .....		2967
61.15.43 OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) .....		2967
61.15.44 OTG device each endpoint interrupt register (OTG_DEACHINT) ..2968
61.15.45 OTG device each endpoint interrupt mask register
(OTG_DEACHINTMSK) .....		2968
61.15.46 OTG device each IN endpoint-1 interrupt mask register
(OTG_DIEPEACHM) .....		2969
61.15.47 OTG device each OUT endpoint-1 interrupt mask register
(OTG_DOEPEACHMSK1) .....		2970
61.15.48 OTG device control IN endpoint 0 control register
(OTG_DIEPCTL0) .....		2971
61.15.49 OTG device IN endpoint x control register [alternate]
(OTG_DIEPCTLx) .....		2973
61.15.50 OTG device IN endpoint x control register [alternate]
(OTG_DIEPCTLx) .....		2975
61.15.51 OTG device IN endpoint x interrupt register (OTG_DIEPINTx) .....2977
61.15.52 OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) .....		2978
61.15.53 OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) .....		2979
61.15.54 OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) .2979
61.15.55 OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) .....		2980
61.15.56OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . .2982
61.15.57OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) . . . . .		2983
61.15.58OTG device OUT endpoint x control register [alternate]
(OTG_DOEPCTLx) . . . . .		2984
61.15.59OTG device OUT endpoint x control register [alternate]
(OTG_DOEPCTLx) . . . . .		2986
61.15.60OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) . . . . .		2988
61.15.61OTG power and clock gating control register (OTG_PCGCCTL) . . .2989
61.15.62OTG power and clock gating control register 1 (OTG_PCGCCTL1) . . .2990
61.15.63OTG_FS register map . . . . .2991
61.16OTG_FS programming model . . . . .2999
61.16.1Core initialization . . . . .2999
61.16.2Host initialization . . . . .3000
61.16.3Device initialization . . . . .3000
61.16.4Host programming model . . . . .3001
61.16.5Device programming model . . . . .3022
61.16.6Worst case response time . . . . .3043
61.16.7OTG programming model . . . . .3045
62USB on-the-go high-speed (OTG_HS) . . . . .3046
62.1OTG_HS introduction . . . . .3046
62.2OTG_HS main features . . . . .3047
62.2.1General features . . . . .3047
62.2.2Host-mode features . . . . .3048
62.2.3Peripheral-mode features . . . . .3048
62.3OTG_HS implementation . . . . .3048
62.4OTG_HS functional description . . . . .3049
62.4.1OTG_HS block diagram . . . . .3049
62.4.2OTG_HS pin and internal signals . . . . .3049
62.4.3OTG_HS core . . . . .3050
62.4.4OTG detections . . . . .3050
62.4.5High-speed OTG PHY connected to OTG_HS . . . . .3050
62.4.6Battery charging detection . . . . .3050
62.5OTG_HS dual role device (DRD) . . . . .3051
62.5.1ID line detection . . . . .3051
62.6OTG_HS as a USB peripheral . . . . .3052
62.6.1Peripheral states . . . . .3052
62.6.2Peripheral endpoints . . . . .3053
62.7OTG_HS as a USB host . . . . .3055
62.7.1USB host states . . . . .3056
62.7.2Host channels . . . . .3057
62.7.3Host scheduler . . . . .3059
62.8OTG_HS SOF trigger . . . . .3060
62.8.1Host SOFs . . . . .3060
62.8.2Peripheral SOFs . . . . .3060
62.9OTG_HS low-power modes . . . . .3061
62.10OTG_HS Dynamic update of the OTG_HFIR register . . . . .3062
62.11OTG_HS data FIFOs . . . . .3062
62.11.1Peripheral FIFO architecture . . . . .3063
62.11.2Host FIFO architecture . . . . .3064
62.11.3FIFO RAM allocation . . . . .3065
62.12OTG_HS interrupts . . . . .3067
62.13OTG_HS control and status registers . . . . .3069
62.13.1CSR memory map . . . . .3069
62.14OTG_HS registers . . . . .3074
62.14.1OTG control and status register (OTG_GOTGCTL) . . . . .3074
62.14.2OTG interrupt register (OTG_GOTGINT) . . . . .3076
62.14.3OTG AHB configuration register (OTG_GAHBCFG) . . . . .3077
62.14.4OTG USB configuration register (OTG_GUSBCFG) . . . . .3078
62.14.5OTG reset register (OTG_GRSTCTL) . . . . .3080
62.14.6OTG core interrupt register [alternate] (OTG_GINTSTS) . . . . .3083
62.14.7OTG core interrupt register [alternate] (OTG_GINTSTS) . . . . .3087
62.14.8OTG interrupt mask register [alternate] (OTG_GINTMSK) . . . . .3092
62.14.9OTG interrupt mask register [alternate] (OTG_GINTMSK) . . . . .3093
62.14.10OTG receive status debug read register [alternate]
(OTG_GRXSTSR) . . . . .		3095
62.14.11OTG receive status debug read register [alternate]
(OTG_GRXSTSR) . . . . .		3096
62.14.12OTG status read and pop registers (OTG_GRXSTSP) . . . . .3097
62.14.13OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . . . .3098
62.14.14OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .3099
62.14.15 OTG host non-periodic transmit FIFO size register [alternate]
(OTG_HNPTXFSIZ) . . . . .		3100
62.14.16 Endpoint 0 transmit FIFO size [alternate] (OTG_DIEPTXF0) . . . . .3100
62.14.17 OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . .		3101
62.14.18 OTG general core configuration register (OTG_GCCFG) . . . . .3102
62.14.19 OTG core ID register (OTG_CID) . . . . .3103
62.14.20 OTG core LPM configuration register (OTG_GLPMCFG) . . . . .3104
62.14.21 OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . .		3108
62.14.22 OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . .		3108
62.14.23 Host-mode registers . . . . .3108
62.14.24 OTG host configuration register (OTG_HCFG) . . . . .3109
62.14.25 OTG host frame interval register (OTG_HFIR) . . . . .3109
62.14.26 OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . .		3110
62.14.27 OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . .		3111
62.14.28 OTG host all channels interrupt register (OTG_HAINT) . . . . .3112
62.14.29 OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . .		3112
62.14.30 OTG host port control and status register (OTG_HPRT) . . . . .3113
62.14.31 OTG host channel x characteristics register (OTG_HCCHARx) . . . . .3115
62.14.32 OTG host channel x split control register (OTG_HCSPLTx) . . . . .3116
62.14.33 OTG host channel x interrupt register (OTG_HCINTx) . . . . .3117
62.14.34 OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .3118
62.14.35 OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .3119
62.14.36 OTG host channel x DMA address register(OTG_HCDMAx) . . . . .3120
62.14.37 Device-mode registers . . . . .3120
62.14.38 OTG device configuration register (OTG_DCFG) . . . . .3120
62.14.39 OTG device control register (OTG_DCTL) . . . . .3122
62.14.40 OTG device status register (OTG_DSTS) . . . . .3124
62.14.41 OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . .		3125
62.14.42 OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . .		3126
62.14.43 OTG device all endpoints interrupt register (OTG_DAINT) . . . . .3127
62.14.44 OTG all endpoints interrupt mask register
(OTG_DAINMSK) . . . . .		3128
62.14.45OTG device threshold control register (OTG_DTHRCTL)3128
62.14.46OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK)		3129
62.14.47OTG device IN endpoint x control register [alternate]
(OTG_DIEPCTLx)		3130
62.14.48OTG device IN endpoint x control register [alternate]
(OTG_DIEPCTLx)		3132
62.14.49OTG device IN endpoint x interrupt register (OTG_DIEPINTx)3134
62.14.50OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0)		3135
62.14.51OTG device IN endpoint x DMA address register
(OTG_DIEPDMAx)		3136
62.14.52OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx)		3136
62.14.53OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx)3137
62.14.54OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0)		3137
62.14.55OTG device OUT endpoint x interrupt register (OTG_DOEPINTx)3139
62.14.56OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0)		3141
62.14.57OTG device OUT endpoint x DMA address register
(OTG_DOEPDMAx)		3142
62.14.58OTG device OUT endpoint x control register [alternate]
(OTG_DOEPCTLx)		3142
62.14.59OTG device OUT endpoint x control register [alternate]
(OTG_DOEPCTLx)		3144
62.14.60OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx)		3146
62.14.61OTG power and clock gating control register (OTG_PCGCCTL)3147
62.14.62OTG power and clock gating control register 1 (OTG_PCGCCTL1)3148
62.14.63OTG_HS register map3149
62.15OTG_HS programming model3156
62.15.1Core initialization3156
62.15.2Host initialization3157
62.15.3Device initialization3158
62.15.4DMA mode3158
62.15.5Host programming model3158
62.15.6Device programming model3191
62.15.7Worst case response time3211
62.15.8OTG programming model3213
63USB Type-C ® /USB Power Delivery interface (UCPD) . . . . .3214
63.1UCPD introduction . . . . .3214
63.2UCPD main features . . . . .3214
63.3UCPD implementation . . . . .3215
63.4UCPD functional description . . . . .3215
63.4.1UCPD block diagram . . . . .3216
63.4.2UCPD reset and clocks . . . . .3217
63.4.3Physical layer protocol . . . . .3218
63.4.4UCPD BMC transmitter . . . . .3224
63.4.5UCPD BMC receiver . . . . .3226
63.4.6UCPD Type-C pull-ups (Rp) and pull-downs (Rd) . . . . .3227
63.4.7UCPD Type-C voltage monitoring and de-bouncing . . . . .3228
63.4.8UCPD fast role swap (FRS) . . . . .3228
63.4.9UCPD DMA Interface . . . . .3228
63.4.10Wake-up from Stop mode . . . . .3228
63.5UCPD programming sequences . . . . .3229
63.5.1Initialization phase . . . . .3229
63.5.2Type-C state machine handling . . . . .3229
63.5.3USB PD transmit . . . . .3231
63.5.4USB PD receive . . . . .3232
63.5.5UCPD software trimming . . . . .3233
63.6UCPD low-power modes . . . . .3233
63.7UCPD interrupts . . . . .3234
63.8UCPD registers . . . . .3235
63.8.1UCPD configuration register 1 (UCPD_CFGR1) . . . . .3235
63.8.2UCPD configuration register 2 (UCPD_CFGR2) . . . . .3237
63.8.3UCPD configuration register 3 (UCPD_CFGR3) . . . . .3237
63.8.4UCPD control register (UCPD_CR) . . . . .3238
63.8.5UCPD interrupt mask register (UCPD_IMR) . . . . .3240
63.8.6UCPD status register (UCPD_SR) . . . . .3242
63.8.7UCPD interrupt clear register (UCPD_ICR) . . . . .3245
63.8.8UCPD Tx ordered set type register (UCPD_TX_ORDSETR) . . . . .3246
63.8.9UCPD Tx payload size register (UCPD_TX_PAYSZR) . . . . .3246
63.8.10UCPD Tx data register (UCPD_TXDR) . . . . .3247
63.8.11UCPD Rx ordered set register (UCPD_RX_ORDSETR) . . . . .3247
63.8.12UCPD Rx payload size register (UCPD_RX_PAYSZR) . . . . .3248

63.8.13 UCPD receive data register (UCPD_RXDR) . . . . . 3249
63.8.14 UCPD Rx ordered set extension register 1
(UCPD_RX_ORDEXTR1) . . . . . 3249
63.8.15 UCPD Rx ordered set extension register 2
(UCPD_RX_ORDEXTR2) . . . . . 3250
63.8.16 UCPD register map . . . . . 3250

64 Ethernet (ETH): media access control
(MAC) with DMA controller . . . . . 3253

64.1 Ethernet introduction . . . . . 3253
64.2 Ethernet main features . . . . . 3253
64.2.1 Standard compliance . . . . . 3253
64.2.2 MAC features . . . . . 3253
64.2.3 Transaction layer (MTL) features . . . . . 3255
64.2.4 DMA block features . . . . . 3256
64.2.5 Bus interface features . . . . . 3256
64.3 Ethernet pins and internal signals . . . . . 3257
64.4 Ethernet architecture . . . . . 3258
64.4.1 DMA controller . . . . . 3259
64.4.2 MTL . . . . . 3268
64.4.3 MAC . . . . . 3268
64.5 Ethernet functional description: MAC . . . . . 3273
64.5.1 Double VLAN processing . . . . . 3273
64.5.2 Source address and VLAN insertion, replacement, or deletion . . . . . 3274
64.5.3 Packet filtering . . . . . 3276
64.5.4 IEEE 1588 timestamp support . . . . . 3283
64.5.5 Checksum offload engine . . . . . 3308
64.5.6 TCP segmentation offload . . . . . 3314
64.5.7 IPv4 ARP offload . . . . . 3320
64.5.8 Loopback . . . . . 3321
64.5.9 Flow control . . . . . 3322
64.5.10 MAC management counters . . . . . 3324
64.5.11 Interrupts generated by the MAC . . . . . 3326
64.5.12 MAC and MMC register descriptions . . . . . 3326
64.6 Ethernet functional description: PHY interfaces . . . . . 3327
64.6.1 Station management agent (SMA) . . . . . 3327
64.6.2 Media independent interface (MII) . . . . . 3334

64.6.3Reduced media independent interface (RMII) . . . . .3335
64.7Ethernet low-power modes . . . . .3338
64.7.1Low-power management . . . . .3338
64.7.2Energy-efficient Ethernet (EEE) . . . . .3344
64.8Ethernet interrupts . . . . .3350
64.8.1DMA interrupts . . . . .3350
64.8.2MTL interrupts . . . . .3352
64.8.3MAC interrupts . . . . .3352
64.9Ethernet programming model . . . . .3353
64.9.1DMA initialization . . . . .3353
64.9.2MTL initialization . . . . .3354
64.9.3MAC initialization . . . . .3354
64.9.4Performing normal receive and transmit operation . . . . .3355
64.9.5Stopping and starting transmission . . . . .3356
64.9.6Programming guidelines for switching to new descriptor list
in RxDMA . . . . .		3356
64.9.7Programming guidelines for switching the AHB clock frequency . . . . .3356
64.9.8Programming guidelines for MII link state transitions . . . . .3357
64.9.9Programming guidelines for IEEE 1588 timestamping . . . . .3358
64.9.10Programming guidelines for PTP offload feature . . . . .3359
64.9.11Programming guidelines for Energy Efficient Ethernet (EEE) . . . . .3363
64.9.12Programming guidelines for flexible pulse-per-second (PPS) output . . . . .3365
64.9.13Programming guidelines for IEEE 1588 auxiliary snapshot . . . . .3367
64.9.14Programming guidelines for TSO . . . . .3367
64.9.15Programming guidelines to perform VLAN filtering on the receiver . . . . .3368
64.10Descriptors . . . . .3369
64.10.1Descriptor overview . . . . .3369
64.10.2Descriptor structure . . . . .3369
64.10.3Transmit descriptor . . . . .3373
64.10.4Receive descriptor . . . . .3385
64.11Ethernet registers . . . . .3397
64.11.1Ethernet register maps . . . . .3397
64.11.2Ethernet DMA registers . . . . .3397
64.11.3Ethernet MTL registers . . . . .3418
64.11.4Ethernet MAC and MMC registers . . . . .3428
65HDMI-CEC controller (CEC) . . . . .3522
65.1HDMI-CEC introduction . . . . .3522
65.2HDMI-CEC controller main features . . . . .3522
65.3HDMI-CEC functional description . . . . .3523
65.3.1HDMI-CEC pin and internal signals . . . . .3523
65.3.2HDMI-CEC block diagram . . . . .3524
65.3.3Message description . . . . .3524
65.3.4Bit timing . . . . .3525
65.4Arbitration . . . . .3525
65.4.1SFT option bit . . . . .3527
65.5Error handling . . . . .3527
65.5.1Bit error . . . . .3527
65.5.2Message error . . . . .3528
65.5.3Bit rising error (BRE) . . . . .3528
65.5.4Short bit period error (SBPE) . . . . .3528
65.5.5Long bit period error (LBPE) . . . . .3528
65.5.6Transmission error detection (TXERR) . . . . .3530
65.6HDMI-CEC interrupts . . . . .3531
65.7HDMI-CEC registers . . . . .3532
65.7.1CEC control register (CEC_CR) . . . . .3532
65.7.2CEC configuration register (CEC_CFGR) . . . . .3533
65.7.3CEC Tx data register (CEC_TXDR) . . . . .3535
65.7.4CEC Rx data register (CEC_RXDR) . . . . .3535
65.7.5CEC interrupt and status register (CEC_ISR) . . . . .3535
65.7.6CEC interrupt enable register (CEC_IER) . . . . .3537
65.7.7HDMI-CEC register map . . . . .3539
66Debug infrastructure . . . . .3540
66.1Introduction . . . . .3540
66.2Debug infrastructure features . . . . .3541
66.3Debug infrastructure functional description . . . . .3541
66.3.1Debug infrastructure block diagram . . . . .3541
66.3.2Debug infrastructure powering, clocking and reset . . . . .3542
66.3.3Security . . . . .3543
66.3.4Debug authentication . . . . .3545
66.4Serial-wire and JTAG debug port (SWJ-DP) . . . . .3546
66.4.1Serial wire debug port . . . . .3547
66.4.2JTAG debug port . . . . .3549
66.4.3Debug port registers . . . . .3552
66.4.4Debug port register map . . . . .3561
66.5Access ports . . . . .3562
66.5.1MEM-AP registers . . . . .3563
66.5.2Access port register map . . . . .3571
66.6Trace and debug subsystem functional description . . . . .3572
66.6.1System ROM tables . . . . .3572
66.6.2System ROM registers . . . . .3576
66.6.3System ROM register map and reset values . . . . .3580
66.6.4Cross trigger interfaces (CTI) and matrix (CTM) . . . . .3582
66.6.5CTI registers . . . . .3585
66.6.6CTI register map and reset values . . . . .3599
66.6.7Trace funnel (CSTF) . . . . .3601
66.6.8Trace funnel registers . . . . .3602
66.6.9Trace funnel register map and reset values . . . . .3611
66.6.10Embedded trace FIFO (ETF) . . . . .3613
66.6.11ETF registers . . . . .3615
66.6.12ETF register map and reset values . . . . .3632
66.6.13Trace port interface unit (TPIU) . . . . .3635
66.6.14TPIU registers . . . . .3636
66.6.15TPIU register map and reset values . . . . .3651
66.7Serial wire output (SWO) . . . . .3653
66.7.1SWO registers . . . . .3654
66.7.2SWO register map and reset values . . . . .3663
66.8Microcontroller debug unit (DBGMCU) . . . . .3665
66.8.1DBGMCU registers . . . . .3666
66.8.2DBGMCU register map and reset values . . . . .3680
66.9Cortex-M7 debug functional description . . . . .3683
66.9.1Cortex-M7 ROM tables . . . . .3683
66.9.2Cortex-M7 CPU ROM registers . . . . .3686
66.9.3Cortex-M7 CPU ROM table register map and reset values . . . . .3690
66.9.4Cortex-M7 PPB ROM registers . . . . .3691
66.9.5Cortex-M7 PPB ROM table register map and reset values . . . . .3695
66.9.6Cortex-M7 data watchpoint and trace unit (DWT) . . . . .3696
66.9.7Cortex-M7 DWT registers . . . . .3697

List of tables

Table 1.Availability of security features . . . . .121
Table 2.Bus-master-to-bus-slave interconnect . . . . .123
Table 3.ASIB configuration . . . . .130
Table 4.AMIB configuration . . . . .130
Table 5.AXI interconnect register map and reset values . . . . .140
Table 6.Memory map and default device memory area attribute. . . . .152
Table 7.Register boundary addresses. . . . .154
Table 8.SRAMs structure. . . . .161
Table 9.SRAM1 / ITCM configurations . . . . .161
Table 10.SRAM3 / DTCM configurations. . . . .161
Table 11.SRAM4 / ECC configurations . . . . .162
Table 12.ITCM/AXI configuration. . . . .162
Table 13.DTCM/AXI configuration. . . . .162
Table 14.ECC/AXI configuration . . . . .162
Table 15.Boot modes. . . . .163
Table 16.RAMECC internal input/output signals . . . . .167
Table 17.ECC controller mapping . . . . .168
Table 18.Effect of low-power modes on RAMECC . . . . .169
Table 19.RAMECC interrupt requests . . . . .170
Table 20.RAMECC register map and reset values . . . . .177
Table 21.Internal tampers in TAMP . . . . .185
Table 22.Effect of low-power modes on TAMP . . . . .187
Table 23.Accelerated cryptographic operations . . . . .189
Table 24.Product life-cycle states . . . . .192
Table 25.Macros for RSS services . . . . .193
Table 26.RSS lib interface functions . . . . .194
Table 27.FLASH internal input/output signals . . . . .202
Table 28.Flash memory organization . . . . .205
Table 29.FLASH recommended read wait states and programming delays . . . . .211
Table 30.Flash memory OTP organization . . . . .219
Table 31.Read-only public data organization . . . . .221
Table 32.Option byte user words organization . . . . .226
Table 33.STM32H7Rx/7Sx device lifecycle table . . . . .230
Table 34.Flash interface register protection summary. . . . .232
Table 35.Flash security lifecycle definition . . . . .233
Table 36.Boot level and HDP area protections (non STiRoT case). . . . .235
Table 37.Boot level and HDP area protections (STiRoT case) . . . . .235
Table 38.Effect of low-power modes on the embedded flash memory . . . . .237
Table 39.Flash interrupt request . . . . .244
Table 40.FLASH register map and reset values . . . . .275
Table 41.PWR input/output signals connected to package pins or balls. . . . .281
Table 42.PWR internal input/output signals . . . . .281
Table 43.table wake-up source selection . . . . .282
Table 44.Supply configuration control . . . . .286
Table 45.Operating mode summary . . . . .305
Table 46.Sleep mode. . . . .312
Table 47.Stop mode operation . . . . .313
Table 48.Stop mode . . . . .314
Table 49.Standby and Stop flags. . . . .316
Table 50.Standby mode. . . . .316
Table 51.Low-power modes monitoring pin overview . . . . .317
Table 52.GPIO state according to CPU and domain state . . . . .317
Table 53.Power control register map and reset values . . . . .339
Table 54.RCC input/output signals connected to package pins or balls . . . . .343
Table 55.RCC internal input/output signals . . . . .343
Table 56.Reset coverage summary. . . . .350
Table 57.Reset source identification (RCC_RSR). . . . .351
Table 58.Oscillator states versus system modes . . . . .355
Table 59.Oscillator states versus system modes . . . . .369
Table 60.VCO frequency and output frequency in integer mode. . . . .373
Table 61.VCO frequency and output frequency in fractional mode. . . . .374
Table 62.Clock protection summary . . . . .379
Table 63.STOPWUCK and STOPKERWUCK description. . . . .381
Table 64.HSIKERON and CSIKERON behavior . . . . .381
Table 65.Peripheral clock distribution summary . . . . .382
Table 66.SDMMC interface clock constraints . . . . .399
Table 67.Ratio between clock timer and pclk . . . . .407
Table 68.Peripheral clock enabling . . . . .414
Table 69.RNG clock enabling . . . . .415
Table 70.Interrupt sources and control . . . . .418
Table 71.Clock configuration examples with PLLs in integer mode. . . . .422
Table 72.Clock configuration examples with PLLs in fractional mode. . . . .423
Table 73.RCC register map and reset values . . . . .531
Table 74.SBS input/output pins . . . . .541
Table 75.SBS internal input/output signals . . . . .541
Table 76.SBS boot control. . . . .543
Table 77.Analog switches recommended configuration . . . . .544
Table 78.SBS register map and reset values . . . . .559
Table 79.CRS features . . . . .561
Table 80.CRS internal input/output signals . . . . .562
Table 81.CRS interconnection. . . . .563
Table 82.Effect of low-power modes on CRS . . . . .566
Table 83.Interrupt control bits . . . . .566
Table 84.CRS register map and reset values . . . . .571
Table 85.Port bit configuration. . . . .574
Table 86.GPIO register map and reset values . . . . .590
Table 87.Peripheral interconnect matrix . . . . .592
Table 88.GPDMA1 channel implementation . . . . .603
Table 89.GPDMA1 wake-up in low-power modes. . . . .604
Table 90.Programmed GPDMA1 request . . . . .604
Table 91.Programmed GPDMA1 request as a block request . . . . .607
Table 92.GPDMA1 channel with peripheral early termination. . . . .607
Table 93.Programmed GPDMA1 request with peripheral early termination . . . . .608
Table 94.Programmed GPDMA1 trigger . . . . .608
Table 95.Programmed GPDMA source/destination burst . . . . .629
Table 96.Programmed data handling . . . . .634
Table 97.Effect of low-power modes on GPDMA . . . . .646
Table 98.GPDMA interrupt requests . . . . .647
Table 99.GPDMA register map and reset values . . . . .673
Table 100.Implementation of HPDMA1 channels . . . . .676
Table 101.HPDMA1 in low-power modes . . . . .677
Table 102.Programmed HPDMA1 request . . . . .677
Table 103.Programmed HPDMA1 request as a block request . . . . .678
Table 104.HPDMA1 channel with peripheral early termination . . . . .678
Table 105.Programmed HPDMA request with peripheral early termination . . . . .678
Table 106.Programmed HPDMA1 trigger . . . . .678
Table 107.Programmed HPDMA source/destination burst . . . . .700
Table 108.Programmed data handling . . . . .705
Table 109.Effect of low-power modes on HPDMA . . . . .726
Table 110.HPDMA interrupt requests . . . . .727
Table 111.HPDMA register map and reset values . . . . .754
Table 112.GFXMMU internal input/output signals . . . . .757
Table 113.GFXMMU interrupt requests . . . . .763
Table 114.GFXMMU register map and reset values . . . . .769
Table 115.DMA2D internal signals . . . . .773
Table 116.DMA2D trigger interconnections . . . . .773
Table 117.Supported color mode in input . . . . .774
Table 118.Data order in memory . . . . .775
Table 119.Alpha mode configuration . . . . .776
Table 120.Supported CLUT color mode . . . . .777
Table 121.CLUT data order in memory . . . . .777
Table 122.Supported color mode in output . . . . .778
Table 123.Data order in memory . . . . .779
Table 124.Standard data order in memory . . . . .779
Table 125.Output FIFO byte reordering steps . . . . .780
Table 126.MCU order in memory . . . . .785
Table 127.DMA2D interrupt requests . . . . .786
Table 128.DMA2D register map and reset values . . . . .804
Table 129.GPU2D internal input/output signals . . . . .807
Table 130.GPU2D trigger connections . . . . .808
Table 131.ICACHE features . . . . .810
Table 132.TAG memory dimensioning parameters
for n-way set associative operating mode (default) . . . . .		812
Table 133.TAG memory dimensioning parameters for direct-mapped cache mode . . . . .813
Table 134.ICACHE cacheability for AHB transaction . . . . .814
Table 135.ICACHE interrupts . . . . .817
Table 136.ICACHE register map and reset values . . . . .820
Table 137.GFXTIM input/output pins . . . . .823
Table 138.GFXTIM internal signals . . . . .823
Table 139.GFXTIM trigger interconnections . . . . .824
Table 140.Graphic timer interrupt requests . . . . .834
Table 141.GFXTIM register map and reset values . . . . .855
Table 142.NVIC . . . . .859
Table 143.EXTI event input configurations and register control . . . . .868
Table 144.EXTI event input mapping . . . . .871
Table 145.Masking functionality . . . . .873
Table 146.Extended interrupt and event controller register map and reset values . . . . .884
Table 147.CRC internal input/output signals . . . . .887
Table 148.CRC register map and reset values . . . . .892
Table 149.CORDIC functions . . . . .894
Table 150.Cosine parameters . . . . .894
Table 151.Sine parameters . . . . .895
Table 152.Phase parameters . . . . .895
Table 153.Modulus parameters . . . . .896
Table 154.Arctangent parameters . . . . .897
Table 155.Hyperbolic cosine parameters . . . . .897
Table 156.Hyperbolic sine parameters . . . . .898
Table 157.Hyperbolic arctangent parameters . . . . .898
Table 158.Natural logarithm parameters . . . . .899
Table 159.Natural log scaling factors and corresponding ranges . . . . .899
Table 160.Square root parameters . . . . .900
Table 161.Square root scaling factors and corresponding ranges . . . . .900
Table 162.Precision vs. number of iterations. . . . .903
Table 163.CORDIC register map and reset value . . . . .910
Table 164.FMC pins . . . . .914
Table 165.FMC bank mapping options . . . . .917
Table 166.NOR/PSRAM bank selection . . . . .917
Table 167.NOR/PSRAM External memory address . . . . .917
Table 168.NAND memory mapping and timing registers. . . . .918
Table 169.NAND bank selection . . . . .918
Table 170.SDRAM bank selection. . . . .918
Table 171.SDRAM address mapping . . . . .919
Table 172.SDRAM address mapping with 8-bit data bus width. . . . .919
Table 173.SDRAM address mapping with 16-bit data bus width. . . . .920
Table 174.SDRAM address mapping with 32-bit data bus width. . . . .921
Table 175.Programmable NOR/PSRAM access parameters . . . . .923
Table 176.Non-multiplexed I/O NOR flash memory. . . . .923
Table 177.16-bit multiplexed I/O NOR flash memory . . . . .924
Table 178.Non-multiplexed I/Os PSRAM/SRAM . . . . .924
Table 179.16-Bit multiplexed I/O PSRAM . . . . .924
Table 180.NOR flash/PSRAM: Example of supported memories
and transactions . . . . .		925
Table 181.FMC_BCRx bitfields (mode 1) . . . . .928
Table 182.FMC_BTRx bitfields (mode 1) . . . . .929
Table 183.FMC_BCRx bitfields (mode A) . . . . .931
Table 184.FMC_BTRx bitfields (mode A) . . . . .932
Table 185.FMC_BWTRx bitfields (mode A). . . . .932
Table 186.FMC_BCRx bitfields (mode 2/B). . . . .934
Table 187.FMC_BTRx bitfields (mode 2/B). . . . .935
Table 188.FMC_BWTRx bitfields (mode 2/B) . . . . .935
Table 189.FMC_BCRx bitfields (mode C) . . . . .937
Table 190.FMC_BTRx bitfields (mode C) . . . . .938
Table 191.FMC_BWTRx bitfields (mode C). . . . .938
Table 192.FMC_BCRx bitfields (mode D) . . . . .940
Table 193.FMC_BTRx bitfields (mode D) . . . . .940
Table 194.FMC_BWTRx bitfields (mode D). . . . .941
Table 195.FMC_BCRx bitfields (Muxed mode) . . . . .943
Table 196.FMC_BTRx bitfields (Muxed mode) . . . . .943
Table 197.FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .949
Table 198.FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .949
Table 199.FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .950
Table 200.FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .951
Table 201.Programmable NAND flash access parameters . . . . .961
Table 202.8-bit NAND flash memory . . . . .961
Table 203.16-bit NAND flash memory . . . . .962
Table 204.Supported memories and transactions . . . . .962
Table 205.ECC result relevant bits . . . . .972
Table 206.SDRAM signals . . . . .973
Table 207.FMC register map . . . . .990
Table 208.XSPI implementation . . . . .994
Table 209.XSPI input/output pins . . . . .999
Table 210.XSPI internal signals . . . . .999
Table 211.Command/address phase description . . . . .1010
Table 212.OctaRAM command address bit assignment
(based on 64 Mb OctaRAM) . . . . .		1022
Table 213.Address alignment cases . . . . .1030
Table 214.XSPI interrupt requests . . . . .1031
Table 215.XSPI register map and reset values . . . . .1057
Table 216.XSPIM implementation . . . . .1061
Table 217.XSPIM input/output pins . . . . .1062
Table 218.Use cases . . . . .1063
Table 219.XSPIM register map and reset values . . . . .1071
Table 220.DLYB internal input/output signals . . . . .1073
Table 221.DLYB interconnection . . . . .1073
Table 222.Delay block control . . . . .1073
Table 223.DLYB register map and reset values . . . . .1076
Table 224.ADC features . . . . .1079
Table 225.Memory location of the temperature sensor calibration values . . . . .1079
Table 226.Memory location of the internal reference voltage sensor
calibration value . . . . .		1079
Table 227.ADC input/output pins . . . . .1081
Table 228.ADC internal input/output signals . . . . .1081
Table 229.ADC interconnection . . . . .1081
Table 230.Configuring the trigger polarity for regular external triggers . . . . .1101
Table 231.Configuring the trigger polarity for injected external triggers . . . . .1102
Table 232.TSAR timings depending on resolution . . . . .1114
Table 233.Offset computation versus data resolution . . . . .1117
Table 234.Analog watchdog channel selection . . . . .1129
Table 235.Analog watchdog 1 comparison . . . . .1130
Table 236.Analog watchdog 2 and 3 comparison . . . . .1130
Table 237.Maximum output results versus N and M (gray cells indicate truncation) . . . . .1134
Table 238.Oversampler operating modes summary . . . . .1139
Table 239.Effect of low-power modes on the ADC . . . . .1158
Table 240.ADC interrupts . . . . .1159
Table 241.DELAY bits versus ADC resolution . . . . .1194
Table 242.ADC global register map . . . . .1196
Table 243.ADC register map and reset values for each ADC (offset = 0x000
for master ADC, 0x100 for slave ADC) . . . . .		1196
Table 244.ADC register map and reset values (master and slave ADC
common registers) . . . . .		1198
Table 245.DTS internal input/output signals . . . . .1201
Table 246.Sampling time configuration . . . . .1204
Table 247.Trigger configuration . . . . .1205
Table 248.Temperature sensor behavior in low-power modes . . . . .1207
Table 249.Interrupt control bits . . . . .1208
Table 250.DTS register map and reset values . . . . .1216
Table 251.VREFBUF typical values . . . . .1218
Table 252.VREF buffer modes . . . . .1219
Table 253.VREFBUF register map and reset values. . . . .1221
Table 254.ADF features . . . . .1223
Table 255.ADF external pins . . . . .1224
Table 256.ADF internal signals . . . . .1224
Table 257.ADF trigger connections . . . . .1225
Table 258.Control of the common clock generation . . . . .1231
Table 259.Clock constraints with respect to the incoming stream. . . . .1232
Table 260.Data size according to CIC order and CIC decimation values . . . . .1237
Table 261.Possible gain values . . . . .1238
Table 262.Recommended maximum gain values
versus CIC decimation ratios . . . . .		1240
Table 263.Most common microphone settings . . . . .1241
Table 264.HPF 3 dB cut-off frequency examples . . . . .1243
Table 265.ANSLP values versus FRSIZE and sampling rates . . . . .1256
Table 266.Threshold values according SNTHR . . . . .1257
Table 267.Register protection summary . . . . .1263
Table 268.Effect of low-power modes on ADF . . . . .1264
Table 269.ADF interrupt requests . . . . .1265
Table 270.Examples of ADF settings for microphone capture . . . . .1266
Table 271.Programming sequence (CIC4) . . . . .1267
Table 272.Programming sequence (CIC5) . . . . .1268
Table 273.Output signal levels . . . . .1273
Table 274.ADF register map and reset values . . . . .1293
Table 275.Available pipeline . . . . .1296
Table 276.Glossary . . . . .1297
Table 277.DCMIPP input/output pads . . . . .1299
Table 278.DCMIPP input/output pins . . . . .1300
Table 279.DCMIPP clocks. . . . .1300
Table 280.DCMIPP resets. . . . .1300
Table 281.Parallel interface maximum resolution (80 MHz) . . . . .1301
Table 282.Supported pixel formats . . . . .1302
Table 283.DCMIPP_CMCR bit function. . . . .1303
Table 284.DCMIPP_PRCR bit function . . . . .1306
Table 285.DCMIPP_PRESR and DCMIPP_PRESUR bit function . . . . .1307
Table 286.DCMIPP_PxFCTCR bit function . . . . .1309
Table 287.DCMIPP_P0PPCR bit function . . . . .1313
Table 288.DCMIPP_P0DCCNTR and DCMIPP_P0DCLMTR bit function. . . . .1315
Table 289.DCMIPP_PxPPCR bit function . . . . .1316
Table 290.Parallel interface input pixel formats. . . . .1317
Table 291.Correspondence between index and DCMIPP_PRCR register values. . . . .1318
Table 292.Parallel interface input pixel formats. . . . .1319
Table 293.Dump pipe OUTPUT pixel formats . . . . .1319
Table 294.Shadow and physical registers . . . . .1322
Table 295.DCMIPP low power modes. . . . .1323
Table 296.DCMIPP interrupts . . . . .1326
Table 297.Event connection . . . . .1326
Table 298.DCMIPP registers organization . . . . .1327
Table 299.DCMIPP register map and reset values . . . . .1354
Table 300.PSSI input/output pins . . . . .1358
Table 301.PSSI internal input/output signals. . . . .1359
Table 302.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .1360
Table 303.Positioning of captured data bytes in 32-bit words (16-bit width) . . . . .1361
Table 304.PSSI interrupt requests. . . . .1364
Table 305.PSSI register map and reset values . . . . .1370
Table 306.LTDC external pins . . . . .1372
Table 307.LTDC internal signals . . . . .1373
Table 308.LTDC trigger interconnection . . . . .1373
Table 309.Clock domain for each register . . . . .1373
Table 310.LTDC register access and update durations . . . . .1374
Table 311.Pixel data mapping versus color format . . . . .1378
Table 312.LTDC interrupt requests . . . . .1382
Table 313.LTDC register map and reset values . . . . .1399
Table 314.JPEG internal signals . . . . .1403
Table 315.JPEG trigger connections . . . . .1404
Table 316.JPEG codec interrupt requests . . . . .1409
Table 317.JPEG codec register map and reset values . . . . .1422
Table 318.RNG internal input/output signals . . . . .1425
Table 319.RNG interrupt requests . . . . .1433
Table 320.RNG initialization times. . . . .1434
Table 321.RNG configurations . . . . .1434
Table 322.Configuration selection . . . . .1435
Table 323.RNG register map and reset map. . . . .1440
Table 324.CRYP versus SAES features . . . . .1442
Table 325.SAES internal input/output signals . . . . .1443
Table 326.SAES approved symmetric key functions . . . . .1444
Table 327.Counter mode initialization vector definition . . . . .1454
Table 328.Initialization of IV registers in GCM mode. . . . .1457
Table 329.GCM last block definition . . . . .1457
Table 330.Initialization of IV registers in CCM mode. . . . .1463
Table 331.AES data swapping example . . . . .1472
Table 332.Key endianness in SAES_KEYRx registers (128/256-bit keys) . . . . .1474
Table 333.IVI bitfield spread over SAES_IVRx registers. . . . .1475
Table 334.SAES interrupt requests . . . . .1477
Table 335.Processing latency for ECB, CBC and CTR. . . . .1478
Table 336.Processing latency for GCM and CCM (in SAES kernel clock cycles) . . . . .1479
Table 337.SAES register map and reset values . . . . .1492
Table 338.CRYP versus SAES features. . . . .1496
Table 339.CRYP internal input/output signals . . . . .1498
Table 340.CRYP approved AES symmetric key functions . . . . .1498
Table 341.Counter mode initialization vector definition . . . . .1509
Table 342.GCM mode IVI registers initialization . . . . .1512
Table 343.GCM last block definition . . . . .1512
Table 344.CCM mode IVI registers initialization . . . . .1519
Table 345.AES data swapping example . . . . .1524
Table 346.Key endianness in CRYP_KxR/LR registers (128/192/256-bit keys) . . . . .1526
Table 347.Initialization vector endianness in CRYP_IVxR registers (AES). . . . .1526
Table 348.CRYP interrupt requests. . . . .1528
Table 349.Processing latency for ECB, CBC and CTR. . . . .1529
Table 350.Processing latency for GCM and CCM (in clock cycles). . . . .1530
Table 351.CRYP register map and reset values . . . . .1543
Table 352.HASH internal input/output signals . . . . .1546
Table 353.Information on supported hash algorithms . . . . .1547
Table 354.Hash processor outputs . . . . .1550
Table 355.Processing time (in clock cycle) . . . . .1556
Table 356.HASH interrupt requests . . . . .1557
Table 357.HASH1 register map and reset values . . . . .1565
Table 358.MCE implementation . . . . .1568
Table 359.MCE internal input/output signals . . . . .1569
Table 360.MCE block cipher latencies . . . . .1573
Table 361.MCE stream cipher latencies . . . . .1574
Table 362.MCE interrupt requests . . . . .1575
Table 363.MCE register map and reset values . . . . .1589
Table 364.Internal input/output signals . . . . .1592
Table 365.PKA integer arithmetic functions list . . . . .1593
Table 366.PKA prime field (Fp) elliptic curve functions list . . . . .1594
Table 367.Example of 'a' curve coefficient for ECC Fp scalar . . . . .1600
Table 368.Montgomery parameter computation . . . . .1600
Table 369.Modular addition . . . . .1601
Table 370.Modular subtraction . . . . .1601
Table 371.Montgomery multiplication . . . . .1602
Table 372.Modular exponentiation (normal mode) . . . . .1603
Table 373.Modular exponentiation (fast mode) . . . . .1603
Table 374.Modular exponentiation (protected mode) . . . . .1604
Table 375.Modular inversion . . . . .1604
Table 376.Modular reduction . . . . .1605
Table 377.Arithmetic addition . . . . .1605
Table 378.Arithmetic subtraction . . . . .1605
Table 379.Arithmetic multiplication . . . . .1606
Table 380.Arithmetic comparison . . . . .1606
Table 381.CRT exponentiation . . . . .1607
Table 382.Point on elliptic curve Fp check . . . . .1608
Table 383.ECC Fp scalar multiplication . . . . .1608
Table 384.ECDSA sign - Inputs . . . . .1610
Table 385.ECDSA sign - Outputs . . . . .1610
Table 386.Extended ECDSA sign - additional outputs . . . . .1611
Table 387.ECDSA verification - inputs . . . . .1611
Table 388.ECDSA verification - outputs . . . . .1612
Table 389.ECC complete addition . . . . .1612
Table 390.ECC double base ladder . . . . .1613
Table 391.ECC projective to affine . . . . .1614
Table 392.Family of supported curves for ECC operations . . . . .1615
Table 393.Modular exponentiation . . . . .1616
Table 394.ECC scalar multiplication . . . . .1616
Table 395.ECDSA signature average computation time . . . . .1617
Table 396.ECDSA verification average computation times . . . . .1617
Table 397.ECC double base ladder average computation times . . . . .1617
Table 398.ECC projective to affine average computation times . . . . .1617
Table 399.ECC complete addition average computation times . . . . .1617
Table 400.Point on elliptic curve Fp check average computation times . . . . .1617
Table 401.Montgomery parameters average computation times . . . . .1618
Table 402.PKA interrupt requests . . . . .1618
Table 403.PKA register map and reset values . . . . .1623
Table 404.TIM input/output pins . . . . .1627
Table 405.TIM internal input/output signals . . . . .1627
Table 406.Interconnect to the tim_ti1 input multiplexer . . . . .1628
Table 407.Interconnect to the tim_ti2 input multiplexer . . . . .1628
Table 408.Interconnect to the tim_ti3 input multiplexer . . . . .1629
Table 409.Interconnect to the tim_ti4 input multiplexer . . . . .1629
Table 410.Internal trigger connection . . . . .1629
Table 411.Interconnect to the tim_etr input multiplexer . . . . .1629
Table 412.Timer break interconnect . . . . .1630
Table 413.Timer break2 interconnect . . . . .1630
Table 414.System break interconnect . . . . .1630
Table 415.CCR and ARR register change dithering pattern . . . . .1663
Table 416.CCR register change dithering pattern in center-aligned PWM mode . . . . .1664
Table 417.Behavior of timer outputs versus tim_brk/tim_brk2 inputs . . . . .1676
Table 418.Break protection disarming conditions . . . . .1678
Table 419.Counting direction versus encoder signals (CC1P = CC2P = 0) . . . . .1686
Table 420.Counting direction versus encoder signals and polarity settings . . . . .1690
Table 421.DMA request . . . . .1711
Table 422.Effect of low-power modes on TIM1 . . . . .1712
Table 423.Interrupt requests . . . . .1712
Table 424.Output control bits for complementary tim_ocx and tim_ocxn channels with break feature . . . . .1739
Table 425.TIM1 register map and reset values . . . . .1762
Table 426.STM32H7Rx/7Sx general purpose timers . . . . .1766
Table 427.TIM input/output pins . . . . .1768
Table 428.TIM internal input/output signals . . . . .1768
Table 429.Interconnect to the tim_ti1 input multiplexer . . . . .1769
Table 430.Interconnect to the tim_ti2 input multiplexer . . . . .1769
Table 431.Interconnect to the tim_ti3 input multiplexer . . . . .1769
Table 432.Interconnect to the tim_ti4 input multiplexer . . . . .1770
Table 433.TIMx internal trigger connection . . . . .1770
Table 434.Interconnect to the tim_etr input multiplexer . . . . .1770
Table 435.CCR and ARR register change dithering pattern . . . . .1802
Table 436.CCR register change dithering pattern in center-aligned PWM mode . . . . .1803
Table 437.Counting direction versus encoder signals(CC1P = CC2P = 0) . . . . .1812
Table 438.Counting direction versus encoder signals and polarity settings . . . . .1817
Table 439.DMA request . . . . .1841
Table 440.Effect of low-power modes on TIM2/TIM3/TIM4/TIM5 . . . . .1841
Table 441.Interrupt requests . . . . .1842
Table 442.Output control bit for standard tim_ocx channels . . . . .1863
Table 443.TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . .1875
Table 444.TIM internal input/output signals . . . . .1879
Table 445.TIMx_ARR register change dithering pattern . . . . .1888
Table 446.DMA request . . . . .1889
Table 447.Effect of low-power modes on TIM6/TIM7 . . . . .1889
Table 448.Interrupt request . . . . .1889
Table 449.TIMx register map and reset values . . . . .1895
Table 450.TIM input/output pins . . . . .1899
Table 451.TIM internal input/output signals . . . . .1899
Table 452.Interconnect to the tim_ti1 input multiplexer . . . . .1900
Table 453.Interconnect to the tim_ti2 input multiplexer . . . . .1900
Table 454.TIMx internal trigger connection . . . . .1900
Table 455.CCR and ARR register change dithering pattern . . . . .1918
Table 456.Effect of low-power modes on TIM9/TIM12/TIM13/TIM14 . . . . .1927
Table 457.Interrupt requests . . . . .1927
Table 458.Output control bit for standard tim_ocx channels . . . . .1939
Table 459.TIMx register map and reset values (x = 9, 12) . . . . .1943
Table 460.Output control bit for standard tim_ocx channels . . . . .1952
Table 461.TIM13/TIM14 register map and reset values . . . . .1955
Table 462.TIM input/output pins . . . . .1960
Table 463.TIM internal input/output signals . . . . .1961
Table 464.Interconnect to the tim_ti1 input multiplexer . . . . .1961
Table 465.Interconnect to the tim_ti2 input multiplexer . . . . .1962
Table 466.TIMx internal trigger connection . . . . .1962
Table 467.Timer break interconnect . . . . .1963
Table 468.System break interconnect . . . . .1963
Table 469.CCR and ARR register change dithering pattern . . . . .1983
Table 470.Break protection disarming conditions . . . . .1992
Table 471.DMA request . . . . .2003
Table 472.Effect of low-power modes on TIM15/TIM16/TIM17 . . . . .2004
Table 473.Interrupt requests . . . . .2004
Table 474.Output control bits for complementary tim_ocx and tim_ocxn channels with break feature (TIM15). . . . .2020
Table 475.TIM15 register map and reset values . . . . .2033
Table 476.Output control bits for complementary tim_oc1 and tim_oc1n channels with break feature (TIM16/TIM17) . . . . .2046
Table 477.TIM16/TIM17 register map and reset values . . . . .2060
Table 478.STM32H7Rx/7Sx LPTIM features . . . . .2063
Table 479.LPTIM1/2/3 input/output pins . . . . .2065
Table 480.LPTIM4/5 input/output pins . . . . .2065
Table 481.LPTIM1/2/3 internal signals . . . . .2066
Table 482.LPTIM4/5 internal signals . . . . .2066
Table 483.LPTIM1/2/3/4/5 external trigger connections . . . . .2067
Table 484.LPTIM1/2/3 input 1 connections . . . . .2067
Table 485.LPTIM1/2/3 input 2 connections . . . . .2067
Table 486.LPTIM1/2/3 input capture 1 connections . . . . .2067
Table 487.LPTIM1 input capture 2 connections . . . . .2068
Table 488.LPTIM2 input capture 2 connections . . . . .2068
Table 489.LPTIM3 input capture 2 connections . . . . .2068
Table 490.Prescaler division ratios . . . . .2070
Table 491.Encoder counting scenarios . . . . .2077
Table 492.Input capture Glitch filter latency (in counter step unit). . . . .2081
Table 493.Interrupt events . . . . .2086
Table 494.LPTIM register map and reset values . . . . .2110
Table 495.WWDG features . . . . .2113
Table 496.WWDG internal input/output signals . . . . .2114
Table 497.WWDG register map and reset values . . . . .2119
Table 498.IWDG features . . . . .2120
Table 499.IWDG delays versus actions . . . . .2121
Table 500.IWDG internal input/output signals . . . . .2122
Table 501.Effect of low power modes on IWDG . . . . .2127
Table 502.IWDG interrupt request . . . . .2129
Table 503.IWDG register map and reset values . . . . .2135
Table 504.RTC input/output pins . . . . .2138
Table 505.RTC internal input/output signals . . . . .2138
Table 506.RTC interconnection . . . . .2139
Table 507.RTC pin PC13 configuration . . . . .2139
Table 508.RTC_OUT mapping . . . . .2142
Table 509.Effect of low-power modes on RTC . . . . .2156
Table 510.RTC pins functionality over modes . . . . .2156
Table 511.Interrupt requests . . . . .2157
Table 512.RTC register map and reset values . . . . .2183
Table 513.TAMP input/output pins . . . . .2187
Table 514.TAMP internal input/output signals . . . . .2187
Table 515.TAMP interconnection . . . . .2188
Table 516.Device resource x tamper protection . . . . .2193
Table 517.Active tamper output change period . . . . .2196
Table 518.Minimum ATPER value . . . . .2197
Table 519.Active tamper filtered pulse duration . . . . .2198
Table 520.Effect of low-power modes on TAMP . . . . .2199
Table 521.TAMP pins functionality over modes . . . . .2200
Table 522.Interrupt requests . . . . .2200
Table 523.TAMP register map and reset values . . . . .2226
Table 524.I 2 C implementation . . . . .2229
Table 525.I 2 C input/output pins . . . . .2230
Table 526.I 2 C internal input/output signals . . . . .2231
Table 527.Comparison of analog and digital filters . . . . .2233
Table 528.I 2 C-bus and SMBus specification data setup and hold times . . . . .2235
Table 529.I 2 C configuration . . . . .2239
Table 530.I 2 C-bus and SMBus specification clock timings . . . . .2250
Table 531.Timing settings for f I2CCLK of 8 MHz . . . . .2260
Table 532.Timing settings for f I2CCLK of 16 MHz . . . . .2260
Table 533.SMBus timeout specifications . . . . .2262
Table 534.SMBus with PEC configuration . . . . .2264
Table 535.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms . . . . .2265
Table 536.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .2265
Table 537.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .2265
Table 538.Effect of low-power modes to I 2 C . . . . .2275
Table 539.I 2 C interrupt requests . . . . .2275
Table 540.I 2 C register map and reset values . . . . .2291
Table 541.I 3 C instantiation . . . . .2294
Table 542.I 3 C wake-up . . . . .2294
Table 543.I 3 C FIFOs implementation . . . . .2294
Table 544.I 3 C interrupt(s) . . . . .2294
Table 545.I 3 C peripheral controller/target features versus MIPI v1.1 . . . . .2295
Table 546.I 3 C input/output pins . . . . .2296
Table 547.I 3 C internal input/output signals . . . . .2296
Table 548.I 3 C register usage . . . . .2308
Table 549.I 3 C registers/fields usage versus controller state . . . . .2309
Table 550.I 3 C registers/fields usage versus target state . . . . .2312
Table 551.List of supported I 3 C CCCs, as controller/target . . . . .2315
Table 552.I 3 C controller error management . . . . .2346
Table 553.I 3 C target error management . . . . .2348
Table 554.Effect of low-power modes . . . . .2352
Table 555.I 3 C interrupt requests . . . . .2353
Table 556.I 3 C register map and reset values . . . . .2398
Table 557.Instance implementation on STM32H7Rx/7Sx . . . . .2402
Table 558.USART/LPUART features . . . . .2402
Table 559.USART/UART input/output pins . . . . .2405
Table 560.USART internal input/output signals . . . . .2406
Table 561.Noise detection from sampled data . . . . .2418
Table 562.Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .2422
Table 563.Tolerance of the USART receiver when BRR[3:0] is different from 0000. . . . .2422
Table 564.USART frame formats . . . . .2427
Table 565.Effect of low-power modes on the USART . . . . .2450
Table 566.USART interrupt requests. . . . .2451
Table 567.USART register map and reset values . . . . .2489
Table 568.Instance implementation on STM32H7Rx/7Sx . . . . .2492
Table 569.USART/LPUART features . . . . .2492
Table 570.LPUART input/output pins . . . . .2495
Table 571.LPUART internal input/output signals. . . . .2495
Table 572.Error calculation for programmed baud rates at lpuart_ker_ck_pres= 32.768 kHz . . . . .2506
Table 573.Tolerance of the LPUART receiver. . . . .2507
Table 575.Effect of low-power modes on the LPUART . . . . .2519
Table 576.LPUART interrupt requests. . . . .2520
Table 577.LPUART register map and reset values . . . . .2546
Table 578.SPI features . . . . .2549
Table 579.SPI/I2S input/output pins . . . . .2552
Table 580.SPI internal input/output signals . . . . .2552
Table 581.Effect of low-power modes on the SPI . . . . .2579
Table 582.SPI wake-up and interrupt requests . . . . .2580
Table 583.Bitfields usable in PCM/I2S mode . . . . .2582
Table 584.WS and CK level before SPI/I2S is enabled when AFCNTR = 1 . . . . .2591
Table 585.Serial data line swapping . . . . .2591
Table 586.CLKGEN programming examples for usual I2S frequencies . . . . .2595
Table 587.I2S interrupt requests . . . . .2604
Table 588.SPI register map and reset values . . . . .2622
Table 589.STM32H7Rx/7Sx SAI features . . . . .2625
Table 590.SAI internal input/output signals . . . . .2627
Table 591.SAI input/output pins. . . . .2627
Table 592.External synchronization selection . . . . .2630
Table 593.MCLK_x activation conditions. . . . .2635
Table 594.Clock generator programming examples . . . . .2638
Table 595.SAI_A configuration for TDM mode . . . . .2645
Table 596.TDM frame configuration examples . . . . .2647
Table 597.SOPD pattern . . . . .2651
Table 598.Parity bit calculation . . . . .2651
Table 599.Audio sampling frequency versus symbol rates . . . . .2652
Table 600.SAI interrupt sources . . . . .2661
Table 601.SAI register map and reset values . . . . .2690
Table 602.SPDIFRX internal input/output signals . . . . .2693
Table 603.SPDIFRX pins. . . . .2693
Table 604.Transition sequence for preamble . . . . .2699
Table 605.Minimum spdifrx_ker_ck frequency versus audio sampling rate . . . . .2709
Table 606.Conditions of spdifrx_symb_ck generation. . . . .2710
Table 607.Bit field property versus SPDIFRX state. . . . .2713
Table 608.SPDIFRX interface register map and reset values . . . . .2725
Table 609.MDIOS input/output signals connected to package pins or balls . . . . .2727
Table 610.MDIOS internal input/output signals . . . . .2727
Table 611.Interrupt control bits . . . . .2732
Table 612.MDIOS register map and reset values . . . . .2737
Table 613.SDMMC features . . . . .2739
Table 614.SDMMC operation modes SD and SDIO . . . . .2742
Table 615.SDMMC operation modes e•MMC . . . . .2742
Table 616.SDMMC internal input/output signals . . . . .2743
Table 617.SDMMC pins . . . . .2744
Table 618.SDMMC Command and data phase selection . . . . .2745
Table 619.Command token format . . . . .2751
Table 620.Short response with CRC token format . . . . .2752
Table 621.Short response without CRC token format . . . . .2752
Table 622.Long response with CRC token format . . . . .2752
Table 623.Specific Commands overview . . . . .2753
Table 624.Command path status flags . . . . .2754
Table 625.Command path error handling . . . . .2754
Table 626.Data token format . . . . .2762
Table 627.Data path status flags and clear bits . . . . .2762
Table 628.Data path error handling . . . . .2764
Table 629.Data FIFO access . . . . .2765
Table 630.Transmit FIFO status flags . . . . .2766
Table 631.Receive FIFO status flags . . . . .2767
Table 632.AHB and SDMMC_CK clock frequency relation . . . . .2772
Table 633.SDIO special operation control . . . . .2772
Table 634.4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . .2776
Table 635.CMD12 use cases . . . . .2781
Table 636.SDMMC interrupts . . . . .2795
Table 637.Response type and SDMMC_RESPxR registers . . . . .2802
Table 638.SDMMC register map . . . . .2818
Table 639.CAN subsystem I/O signals . . . . .2825
Table 640.CAN subsystem I/O pins . . . . .2825
Table 641.DLC coding in FDCAN . . . . .2829
Table 642.Possible configurations for frame transmission . . . . .2843
Table 643.Rx FIFO element . . . . .2846
Table 644.Rx FIFO element description . . . . .2846
Table 645.Tx buffer and FIFO element . . . . .2848
Table 646.Tx buffer element description . . . . .2848
Table 647.Tx event FIFO element . . . . .2850
Table 648.Tx event FIFO element description . . . . .2850
Table 649.Standard message ID filter element . . . . .2851
Table 650.Standard message ID filter element field description . . . . .2852
Table 651.Extended message ID filter element . . . . .2852
Table 652.Extended message ID filter element field description . . . . .2853
Table 653.FDCAN register map and reset values . . . . .2883
Table 654.OTG_FS speeds supported . . . . .2887
Table 655.OTG_FS implementation . . . . .2890
Table 656.OTG_FS input/output pins . . . . .2891
Table 657.OTG_FS input/output signals . . . . .2892
Table 658.Compatibility of STM32 low power modes with the OTG . . . . .2903
Table 659.Core global control and status registers (CSRs) . . . . .2911
Table 660.Host-mode control and status registers (CSRs) . . . . .2912
Table 661.Device-mode control and status registers . . . . .2913
Table 662.Data FIFO (DFIFO) access register map . . . . .2915
Table 663.Power and clock gating control and status registers . . . . .2915
Table 664.TRDT values . . . . .2921
Table 665.Minimum duration for soft disconnect . . . . .2962
Table 666.OTG_FS register map and reset values . . . . .2991
Table 667.OTG_HS speeds supported . . . . .3046
Table 668.OTG_HS implementation . . . . .3048
Table 669.OTG_HS input/output pins . . . . .3049
Table 670.OTG_HS input/output signals . . . . .3050
Table 671.Compatibility of STM32 low power modes with the OTG . . . . .3061
Table 672.Core global control and status registers (CSRs). . . . .3069
Table 673.Host-mode control and status registers (CSRs) . . . . .3070
Table 674.Device-mode control and status registers . . . . .3071
Table 675.Data FIFO (DFIFO) access register map . . . . .3073
Table 676.Power and clock gating control and status registers . . . . .3074
Table 677.TRDT values . . . . .3080
Table 678.Minimum duration for soft disconnect . . . . .3123
Table 679.OTG_HS register map and reset values . . . . .3149
Table 680.UCPD implementation . . . . .3215
Table 681.UCPD software trim data . . . . .3215
Table 682.UCPD signals on pins . . . . .3216
Table 683.UCPD internal signals . . . . .3217
Table 684.4b5b symbol encoding table . . . . .3219
Table 685.Ordered sets . . . . .3220
Table 686.Validation of ordered sets . . . . .3220
Table 687.Data size . . . . .3221
Table 688.Coding for ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx . . . . .3229
Table 689.Type-C sequence (source: 3A); cable/sink connected (Rd on CC1; Ra on CC2) . . . . .3231
Table 690.Effect of low power modes on the UCPD . . . . .3233
Table 691.UCPD interrupt requests . . . . .3234
Table 692.UCPD register map and reset values . . . . .3250
Table 693.Ethernet peripheral pins . . . . .3257
Table 694.Ethernet internal input/output signals . . . . .3258
Table 695.Priority scheme for Tx DMA and Rx DMA . . . . .3267
Table 696.Double VLAN processing features in Tx path . . . . .3273
Table 697.Double VLAN processing in Rx path . . . . .3274
Table 698.VLAN insertion or replacement based on VLTi bit . . . . .3275
Table 699.Destination address filtering . . . . .3278
Table 700.Source address filtering . . . . .3279
Table 701.VLAN match status . . . . .3280
Table 702.Ordinary clock: PTP messages for snapshot . . . . .3284
Table 703.End-to-end transparent clock: PTP messages for snapshot . . . . .3285
Table 704.Peer-to-peer transparent clock: PTP messages for snapshot . . . . .3285
Table 705.Egress and ingress latency for PHY interfaces . . . . .3289
Table 706.Minimum PTP clock frequency example . . . . .3290
Table 707.Message format defined in IEEE 1588-2008 . . . . .3290
Table 708.Message format defined in IEEE 1588-2008 . . . . .3291
Table 709.IPv6-UDP PTP packet fields required for control and status . . . . .3292
Table 710.Ethernet PTP packet fields required for control and status . . . . .3293
Table 711.Timestamp Snapshot Dependency on ETH_MACTSCR bits . . . . .3295
Table 712.PTP message generation criteria . . . . .3301
Table 713.Common PTP message header fields . . . . .3303
Table 714.MAC Transmit PTP mode and one-step timestamping operation . . . . .3306
Table 715.Transmit checksum offload engine functions for different packet types . . . . .3310
Table 716.Receive checksum offload engine functions for different packet types . . . . .3313
Table 717.TSO: TCP and IP header fields . . . . .3317
Table 718.Pause packet fields. . . . .3322
Table 719.Tx MAC flow control . . . . .3323
Table 720.Rx MAC flow control . . . . .3323
Table 721.Size of the maximum receive packet . . . . .3326
Table 722.MCD clock selection . . . . .3328
Table 723.MDIO Clause 45 frame structure . . . . .3329
Table 724.MDIO Clause 22 frame structure . . . . .3330
Table 725.Remote wake-up packet filter register . . . . .3341
Table 726.Description of the remote wake-up filter fields . . . . .3341
Table 727.Remote wake-up packet and PMT interrupt generation . . . . .3343
Table 728.Transfer complete interrupt behavior . . . . .3351
Table 729.TDES0 normal descriptor (read format) . . . . .3373
Table 730.TDES1 normal descriptor (read format) . . . . .3374
Table 731.TDES2 normal descriptor (read format) . . . . .3374
Table 732.TDES3 normal descriptor (read format) . . . . .3375
Table 733.TDES0 normal descriptor (write-back format). . . . .3378
Table 734.TDES1 normal descriptor (write-back format). . . . .3378
Table 735.TDES2 normal descriptor (write-back format). . . . .3379
Table 736.TDES3 normal descriptor (write-back format). . . . .3379
Table 737.TDES0 context descriptor. . . . .3382
Table 738.TDES1 context descriptor. . . . .3382
Table 739.TDES2 context descriptor. . . . .3383
Table 740.TDES3 context descriptor. . . . .3383
Table 741.RDES0 normal descriptor (read format) . . . . .3386
Table 742.RDES1 normal descriptor (read format) . . . . .3386
Table 743.RDES2 normal descriptor (read format) . . . . .3386
Table 744.RDES3 normal descriptor (read format) . . . . .3386
Table 745.RDES0 normal descriptor (write-back format) . . . . .3388
Table 746.RDES1 normal descriptor (write-back format) . . . . .3388
Table 747.RDES2 normal descriptor (write-back format) . . . . .3390
Table 748.RDES3 normal descriptor (write-back format) . . . . .3392
Table 749.RDES0 context descriptor . . . . .3395
Table 750.RDES1 context descriptor . . . . .3396
Table 751.RDES2 context descriptor . . . . .3396
Table 752.RDES3 context descriptor . . . . .3396
Table 753.ETH_DMA common register map and reset values . . . . .3416
Table 754.ETH_DMA_CH register map and reset values . . . . .3417
Table 755.ETH_MTL register map and reset values . . . . .3427
Table 756.Giant Packet Status based on S2KP and JE Bits . . . . .3433
Table 757.Packet Length based on the CST and ACS bits . . . . .3433
Table 758.Ethernet MAC register map and reset values . . . . .3512
Table 759.HDMI pin . . . . .3523
Table 760.HDMI-CEC internal input/output signals . . . . .3523
Table 761.Error handling timing parameters . . . . .3529
Table 762.TXERR timing parameters . . . . .3530
Table 763.HDMI-CEC interrupts . . . . .3531
Table 764.HDMI-CEC register map and reset values . . . . .3539
Table 765.Authentication signal states . . . . .3544
Table 766.Authentication signal states . . . . .3544
Table 767.Packet request . . . . .3547

Table 768. ACK response. . . . . 3547
Table 769. Data transfer. . . . . 3548
Table 770. JTAG-DP data registers . . . . . 3550
Table 771. Debug port registers . . . . . 3552
Table 772. Debug port register map and reset values . . . . . 3561
Table 773. MEM-AP registers. . . . . 3563
Table 774. Access port register map and reset values. . . . . 3571
Table 775. System ROM table 1. . . . . 3573
Table 776. System ROM table 2. . . . . 3573
Table 777. System ROM table 1 register map and reset values . . . . . 3580
Table 778. System ROM table 2 register map and reset values . . . . . 3581
Table 779. System CTI inputs . . . . . 3583
Table 780. System CTI outputs . . . . . 3583
Table 781. Cortex-M7 CTI inputs . . . . . 3583
Table 782. Cortex-M7 CTI outputs . . . . . 3584
Table 783. CTI register map and reset values . . . . . 3599
Table 784. CSTF register map and reset values . . . . . 3611
Table 785. ETF register map and reset values. . . . . 3632
Table 786. TPIU register map and reset values . . . . . 3651
Table 787. SWO register map and reset values. . . . . 3663
Table 788. DBGMCU register map and reset values . . . . . 3680
Table 789. Cortex-M7 CPU ROM table . . . . . 3683
Table 790. Cortex-M7 PPB ROM table. . . . . 3684
Table 791. Cortex-M7 CPU ROM table register map and reset values . . . . . 3690
Table 792. Cortex-M7 PPB ROM table register map and reset values . . . . . 3695
Table 793. Cortex-M7 DWT register map and reset values . . . . . 3706
Table 794. Cortex-M7 ITM register map and reset values . . . . . 3715
Table 795. Cortex-M7 FPB register map and reset values. . . . . 3722
Table 796. Cortex-M7 ETM register map and reset values . . . . . 3750
Table 797. Document revision history . . . . . 3760

List of figures

Figure 1.System architecture . . . . .124
Figure 2.AXI interconnect . . . . .129
Figure 3.Memory map . . . . .151
Figure 4.RAM ECC controller implementation schematic. . . . .166
Figure 5.Connection between RAM ECC controller and RAMECC monitoring unit . . . . .167
Figure 6.Secure boot process. . . . .182
Figure 7.Key management principle . . . . .188
Figure 8.Product life-cycle security . . . . .191
Figure 9.FLASH block diagram . . . . .201
Figure 10.Detailed FLASH architecture . . . . .203
Figure 11.Embedded flash memory organization . . . . .204
Figure 12.Embedded flash memory usage (STM32H7R). . . . .206
Figure 13.Embedded flash memory usage (STM32H7S). . . . .207
Figure 14.Flash decommissioning options . . . . .208
Figure 15.FLASH read pipeline architecture . . . . .210
Figure 16.FLASH write pipeline architecture . . . . .214
Figure 17.FLASH stateful initialization . . . . .221
Figure 18.Life cycle management scheme . . . . .233
Figure 19.Power control block diagram . . . . .280
Figure 20.Power supply overview . . . . .284
Figure 21.System supply configurations . . . . .285
Figure 22.Device startup with VCORE supplied directly from SMPS step-down converter . . . . .288
Figure 23.Device startup with VCORE supplied in Bypass mode from external regulator . . . . .289
Figure 24.Backup domain . . . . .294
Figure 25.USB supply configurations . . . . .296
Figure 26.Power-on reset/power-down reset waveform . . . . .297
Figure 27.BOR thresholds . . . . .298
Figure 28.PVD thresholds . . . . .299
Figure 29.AVD thresholds . . . . .300
Figure 30.VBAT thresholds . . . . .301
Figure 31.Temperature thresholds . . . . .302
Figure 32.VCORE overvoltage protection. . . . .303
Figure 33.VCORE voltage scaling versus system power modes . . . . .306
Figure 34.Dynamic voltage scaling in Run mode . . . . .307
Figure 35.Dynamic voltage scaling behavior in Stop mode . . . . .308
Figure 36.Dynamic voltage scaling from Standby mode. . . . .309
Figure 37.RCC block diagram. . . . .342
Figure 38.Simplified reset circuit. . . . .346
Figure 39.Boot sequences versus system states . . . . .352
Figure 40.Top-level clock tree. . . . .354
Figure 41.HSE/LSE clock source . . . . .356
Figure 42.HSE clock generation . . . . .356
Figure 43.LSE clock generation . . . . .358
Figure 44.HSI calibration flow . . . . .362
Figure 45.CSI calibration flow . . . . .363
Figure 46.HSI48 calibration flow . . . . .364
Figure 47.LSE and HSE CSS function . . . . .365
Figure 48.PLL block diagram . . . . .371
Figure 49.Spread-spectrum modulation . . . . .375
Figure 50.Triangular waveform generator . . . . .376
Figure 51.Core and bus clock generation . . . . .378
Figure 52.Key signals controlling low-power modes . . . . .380
Figure 53.Clock distribution for SAIs, ADF and SPDIFRX . . . . .391
Figure 54.Clock distribution for SPIs and SPI/I2S . . . . .392
Figure 55.Clock distribution for I2C[3:2] and I2C1/I3C1 . . . . .393
Figure 56.Clock distribution for UARTs, LPUART1 and USARTs . . . . .394
Figure 57.Clock distribution for FDCAN . . . . .395
Figure 58.Clock distribution for GPU2D . . . . .396
Figure 59.Clock distribution for LTDC and DCMIPP . . . . .396
Figure 60.Clock distribution for PSSI . . . . .397
Figure 61.Clock distribution for FMC, XSPIs, and MCEs . . . . .399
Figure 62.Clock distribution for SDMMC[2:1] and DB_SDMMC[2:1] . . . . .400
Figure 63.Clock distribution for USB and UCPD . . . . .402
Figure 64.Clock distribution for ETH1 . . . . .403
Figure 65.ETH clock configuration . . . . .404
Figure 66.Clock distribution For ADCs . . . . .405
Figure 67.Clock distribution for SAES and RNG . . . . .405
Figure 68.Clock distribution for HDMI-CEC . . . . .406
Figure 69.Clock distribution for TIMs . . . . .406
Figure 70.Clock distribution for LPTIMs . . . . .408
Figure 71.Clock distribution for RTC . . . . .409
Figure 72.Clock distribution for WWDG and IWDG . . . . .410
Figure 73.Clock distribution for DBG and trace . . . . .410
Figure 74.Kernel clock switching . . . . .412
Figure 75.Peripheral kernel clock enable logic details . . . . .413
Figure 76.SBS block diagram . . . . .541
Figure 77.SBS boot control . . . . .542
Figure 78.Compensation cell management . . . . .545
Figure 79.Compensation cell use . . . . .545
Figure 80.CRS block diagram . . . . .562
Figure 81.CRS counter behavior . . . . .564
Figure 82.Structure of three-volt or five-volt tolerant GPIO (TT or FT) . . . . .574
Figure 83.Input floating/pull-up/pull-down configurations . . . . .578
Figure 84.Output configuration . . . . .579
Figure 85.Alternate function configuration . . . . .580
Figure 86.High-impedance analog configuration . . . . .580
Figure 87.GPDMA block diagram . . . . .610
Figure 88.GPDMA channel direct programming without linked-list (GPDMA_CxLLR = 0) . . . . .611
Figure 89.GPDMA channel suspend and resume sequence . . . . .612
Figure 90.GPDMA channel abort and restart sequence . . . . .613
Figure 91.Static linked-list data structure (all Uxx = 1)
of a linear addressing channel x . . . . .		614
Figure 92.Static linked-list data structure (all Uxx = 1)
of a 2D addressing channel x . . . . .		615
Figure 93.GPDMA dynamic linked-list data structure
of a linear addressing channel x . . . . .		616
Figure 94.GPDMA dynamic linked-list data structure
of a 2D addressing channel x . . . . .		616
Figure 95.GPDMA channel execution and linked-list programming in run-to-completion mode (GPDMA_CxCR.LSM = 0) . . . . .618
Figure 96.Inserting a LLI n with an auxiliary GPDMA channel y . . . . .620
Figure 97.GPDMA channel execution and linked-list programming in link step mode (GPDMA_CxCR.LSM = 1) . . . . .622
Figure 98.Building LLI n+1 : GPDMA dynamic linked-lists in link step mode . . . . .623
Figure 99.Replace with a new LLI n ' in register file in link step mode . . . . .624
Figure 100.Replace with a new LLI n ' and LLI n+1 ' in memory in link step mode (option 1) . . . . .625
Figure 101.Replace with a new LLI n ' and LLI n+1 ' in memory in link step mode (option 2) . . . . .626
Figure 102.GPDMA channel execution and linked-list programming . . . . .628
Figure 103.Programmed 2D addressing . . . . .631
Figure 104.GPDMA arbitration policy . . . . .638
Figure 105.Trigger hit, memorization, and overrun waveform . . . . .641
Figure 106.GPDMA circular buffer programming: update of the memory start address with a linear addressing channel . . . . .642
Figure 107.Shared GPDMA channel with circular buffering: update of the memory start address with a linear addressing channel. . . . .643
Figure 108.HPDMA block diagram . . . . .681
Figure 109.HPDMA channel direct programming without linked-list (HPDMA_CxLLR = 0) . . . . .682
Figure 110.HPDMA channel suspend and resume sequence . . . . .683
Figure 111.HPDMA channel abort and restart sequence . . . . .684
Figure 112.Static linked-list data structure (all Uxx = 1) of a linear addressing channel x . . . . .685
Figure 113.Static linked-list data structure (all Uxx = 1) of a 2D addressing channel x . . . . .686
Figure 114.HPDMA dynamic linked-list data structure of linear addressing channel x. . . . .687
Figure 115.HPDMA dynamic linked-list data structure of a 2D addressing channel x . . . . .687
Figure 116.HPDMA channel execution and linked-list programming in run-to-completion mode (HPDMA_CxCR.LSM = 0) . . . . .689
Figure 117.Inserting a LLI n with an auxiliary HPDMA channel y . . . . .691
Figure 118.HPDMA channel execution and linked-list programming in link step mode (HPDMA_CxCR.LSM = 1) . . . . .693
Figure 119.Building LLI n+1 : HPDMA dynamic linked-lists in link step mode . . . . .694
Figure 120.Replace with a new LLI n ' in register file in link step mode . . . . .695
Figure 121.Replace with a new LLI n ' and LLI n+1 ' in memory in link step mode (option 1) . . . . .696
Figure 122.Replace with a new LLI n ' and LLI n+1 ' in memory in link step mode (option 2) . . . . .697
Figure 123.HPDMA channel execution and linked-list programming . . . . .699
Figure 124.Programmed 2D addressing . . . . .702
Figure 125.HPDMA arbitration policy . . . . .717
Figure 126.Trigger hit, memorization and overrun waveform . . . . .721
Figure 127.HPDMA circular buffer programming: update of the memory start address with a linear addressing channel . . . . .722
Figure 128.Shared HPDMA channel with circular buffering: update of the memory start address with a linear addressing channel. . . . .723
Figure 129.GFXMMU block diagram . . . . .756
Figure 130.Virtual buffer . . . . .758
Figure 131.Virtual buffer and physical buffer memory map . . . . .759
Figure 132.MMU block diagram . . . . .760
Figure 133.Block validation/comparator implementation . . . . .762
Figure 134.DMA2D block diagram . . . . .773
Figure 135.Intel 8080 16-bit mode (RGB565) . . . . .780
Figure 136.Intel 8080 18/24-bit mode (RGB888) . . . . .780
Figure 137.GPU2D block diagram . . . . .807
Figure 138.ICACHE block diagram . . . . .811
Figure 139. ICACHE TAG and data memories functional view . . . . .813
Figure 140. GFXTIM block diagram. . . . .823
Figure 141. Clock generator . . . . .825
Figure 142. Waveforms in standalone . . . . .827
Figure 143. Active counters and signals in standalone . . . . .827
Figure 144. Waveforms with external HSYNC and VSYNC. . . . .827
Figure 145. Waveforms with external HSYNC only . . . . .828
Figure 146. Active counters and signals with external HSYNC only . . . . .828
Figure 147. Waveforms with external VSYNC only . . . . .828
Figure 148. Active counters with external VSYNC only . . . . .829
Figure 149. Prescaling when external VSYNC only. . . . .829
Figure 150. Waveforms with external CSYNC only . . . . .829
Figure 151. Active counters and signals with external CSYNC only . . . . .830
Figure 152. Prescaling when external CSYNC only . . . . .830
Figure 153. Tearing-effect configurations . . . . .832
Figure 154. Watchdog timer. . . . .833
Figure 155. EXTI block diagram . . . . .867
Figure 156. Configurable event triggering logic CPU wake-up . . . . .869
Figure 157. Direct event triggering logic CPU wake up . . . . .870
Figure 158. CRC calculation unit block diagram . . . . .887
Figure 159. CORDIC convergence for trigonometric functions . . . . .901
Figure 160. CORDIC convergence for hyperbolic functions . . . . .902
Figure 161. CORDIC convergence for square root . . . . .903
Figure 162. FMC block diagram. . . . .913
Figure 163. FMC memory banks (default mapping) . . . . .916
Figure 164. Mode 1 read access waveforms . . . . .927
Figure 165. Mode 1 write access waveforms. . . . .928
Figure 166. Mode A read access waveforms. . . . .930
Figure 167. Mode A write access waveforms . . . . .931
Figure 168. Mode 2 and mode B read access waveforms. . . . .933
Figure 169. Mode 2 write access waveforms. . . . .933
Figure 170. Mode B write access waveforms . . . . .934
Figure 171. Mode C read access waveforms . . . . .936
Figure 172. Mode C write access waveforms . . . . .936
Figure 173. Mode D read access waveforms . . . . .939
Figure 174. Mode D write access waveforms . . . . .939
Figure 175. Muxed read access waveforms . . . . .942
Figure 176. Muxed write access waveforms . . . . .942
Figure 177. Asynchronous wait during a read access waveforms. . . . .945
Figure 178. Asynchronous wait during a write access waveforms. . . . .945
Figure 179. Wait configuration waveforms. . . . .948
Figure 180. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM). . . . .948
Figure 181. Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . .950
Figure 182. NAND flash controller waveforms for common memory access. . . . .964
Figure 183. Access to non 'CE don't care' NAND-flash. . . . .965
Figure 184. Burst write SDRAM access waveforms . . . . .975
Figure 185. Burst read SDRAM access . . . . .976
Figure 186. Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0) . . . . .977
Figure 187. Read access crossing row boundary . . . . .979
Figure 188. Write access crossing row boundary . . . . .979
Figure 189. Self-refresh mode . . . . .982
Figure 190. Power-down mode . . . . .983
Figure 191. XSPI block diagram for 16-bit configuration (1) .....995
Figure 192. XSPI block diagram for dual-octal configuration (1) .....996
Figure 193. XSPI block diagram for octal configuration .....997
Figure 194. XSPI block diagram in quad configuration .....998
Figure 195. XSPI block diagram for dual-quad configuration .....999
Figure 196. SDR read command in 16-bit configuration .....1001
Figure 197. DTR read in octal-SPI mode with DQS (Macronix mode) example .....1004
Figure 198. SDR write command in octal-SPI mode example .....1006
Figure 199. DTR write in octal-SPI mode (Macronix mode) example .....1007
Figure 200. Example of HyperBus read operation (8-bit data mode) .....1010
Figure 201. HyperBus write operation with initial latency (8-bit data mode) .....1011
Figure 202. HyperBus read operation with additional latency (8-bit data mode) .....1012
Figure 203. HyperBus write operation with additional latency (8-bit data mode) .....1012
Figure 204. HyperBus write operation with no latency (register write) .....1013
Figure 205. HyperBus read operation page crossing with latency (8-bit data mode) .....1013
Figure 206. HyperBus write operation with initial latency (16-bit mode) .....1014
Figure 207. D0/D1 data ordering in octal-SPI DTR mode (Micron) - Read access .....1021
Figure 208. OctaRAM read operation with reverse data ordering D1/D0 .....1021
Figure 209. NCS when CKMODE = 0 (T = CLK period) .....1028
Figure 210. NCS when CKMODE = 1 in SDR mode (T = CLK period) .....1028
Figure 211. NCS when CKMODE = 1 in DTR mode (T = CLK period) .....1028
Figure 212. NCS when CKMODE = 1 with an abort (T = CLK period) .....1029
Figure 213. Example of software control of two external memories .....1029
Figure 214. XSPIM block diagram .....1062
Figure 215. XSPI direct octal mode .....1064
Figure 216. XSPI direct 16-bit mode .....1065
Figure 217. XSPI dual-octal mode .....1065
Figure 218. XSPI swapped (octal) mode .....1066
Figure 219. XSPI multiplexed mode to Port1 .....1067
Figure 220. XSPI multiplexed (octal and dual-octal) mode to Port 2 .....1067
Figure 221. XSPI1 and XSPI2 drive a single external memory (octal mode) .....1068
Figure 222. Single XSPI driving two external memories .....1069
Figure 223. DLYB block diagram .....1072
Figure 224. ADC block diagram .....1080
Figure 225. ADC clock scheme .....1085
Figure 226. ADC1 connectivity .....1086
Figure 227. ADC2 connectivity .....1087
Figure 228. ADC calibration .....1090
Figure 229. Updating the ADC calibration factor .....1091
Figure 230. Mixing single-ended and differential channels .....1092
Figure 231. Enabling / disabling the ADC .....1093
Figure 232. Bulb mode timing diagram .....1096
Figure 233. Analog-to-digital conversion time .....1099
Figure 234. Stopping ongoing regular conversions .....1100
Figure 235. Stopping ongoing regular and injected conversions .....1101
Figure 236. Triggers shared between ADC master and slave .....1102
Figure 237. Injected conversion latency .....1104
Figure 238. Example of ADC_JSQR queue of context (sequence change) .....1107
Figure 239. Example of ADC_JSQR queue of context (trigger change) .....1107
Figure 240. Example of ADC_JSQR queue of context with overflow before conversion. ....1108
Figure 241. Example of ADC_JSQR queue of context with overflow during conversion .....1108
Figure 242. Example of ADC_JSQR queue of context with empty queue (case JQM = 0) .....1109
Figure 243.Example of ADC_JSQR queue of context with empty queue (JQM = 1) . . . . .1110
Figure 244.Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0) -
JADSTP occurs during an ongoing conversion. . . . .		1110
Figure 245.Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0) -
JADSTP occurs during an ongoing conversion and a new
trigger occurs . . . . .		1111
Figure 246.Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0) -
JADSTP occurs outside an ongoing conversion. . . . .		1111
Figure 247.Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 1) . . . . .1112
Figure 248.Flushing ADC_JSQR queue of context by setting ADDIS = 1 (JQM = 0). . . . .1112
Figure 249.Flushing ADC_JSQR queue of context by setting ADDIS = 1 (JQM = 1). . . . .1113
Figure 250.Single conversions of a sequence, software trigger . . . . .1115
Figure 251.Continuous conversion of a sequence, software trigger. . . . .1115
Figure 252.Single conversions of a sequence, hardware trigger . . . . .1116
Figure 253.Continuous conversions of a sequence, hardware trigger . . . . .1116
Figure 254.Right alignment (offset disabled, unsigned value) . . . . .1118
Figure 255.Right alignment (offset enabled, signed value). . . . .1119
Figure 256.Left alignment (offset disabled, unsigned value) . . . . .1119
Figure 257.Left alignment (offset enabled, signed value). . . . .1120
Figure 258.Example of overrun (OVRMOD = 0). . . . .1121
Figure 259.Example of overrun (OVRMOD = 1). . . . .1122
Figure 260.AUTODLY = 1, regular conversion in continuous mode, software trigger . . . . .1125
Figure 261.AUTODLY = 1, regular HW conversions interrupted by injected conversions
(DISCEN = 0; JDISCEN = 0) . . . . .		1126
Figure 262.AUTODLY = 1, regular HW conversions interrupted by injected conversions . . . . .
(DISCEN = 1, JDISCEN = 1) . . . . .		1127
Figure 263.AUTODLY = 1, regular continuous conversions interrupted by injected conversions . . . . .1128
Figure 264.AUTODLY = 1 in auto- injected mode (JAUTO = 1). . . . .1128
Figure 265.Analog watchdog guarded area . . . . .1129
Figure 266.ADC y _AWD x _OUT signal generation (on all regular channels). . . . .1131
Figure 267.ADC y _AWD x _OUT signal generation (AWD x flag not cleared by software) . . . . .1132
Figure 268.ADC y _AWD x _OUT signal generation (on a single regular channel) . . . . .1132
Figure 269.ADC y _AWD x _OUT signal generation (on all injected channels) . . . . .1132
Figure 270.20-bit to 16-bit result truncation . . . . .1134
Figure 271.Numerical example with 5-bit shift and rounding . . . . .1134
Figure 272.Triggered regular oversampling mode (TROVS bit = 1). . . . .1136
Figure 273.Regular oversampling modes (4x ratio) . . . . .1137
Figure 274.Regular and injected oversampling modes used simultaneously . . . . .1138
Figure 275.Triggered regular oversampling with injection . . . . .1138
Figure 276.Oversampling in auto-injected mode . . . . .1139
Figure 277.Dual ADC block diagram (1) . . . . .1141
Figure 278.Injected simultaneous mode on 4 channels: dual ADC mode . . . . .1142
Figure 279.Regular simultaneous mode on 16 channels: dual ADC mode . . . . .1144
Figure 280.Interleaved mode on one channel in continuous conversion mode: dual ADC mode. . . . .1145
Figure 281.Interleaved mode on 1 channel in single conversion mode: dual ADC mode. . . . .1146
Figure 282.Interleaved conversion with injection . . . . .1146
Figure 283.Alternate trigger: injected group of each ADC . . . . .1147
Figure 284.Alternate trigger: 4 injected channels (each ADC) in discontinuous mode. . . . .1148
Figure 285.Alternate + regular simultaneous . . . . .1149
Figure 286.Case of trigger occurring during injected conversion . . . . .1149
Figure 287.Interleaved single channel CH0 with injected sequence CH11, CH12. . . . .1150
Figure 288.Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . .1150
Figure 289. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . .		1150
Figure 290. DMA Requests in regular simultaneous mode when MDMA = 0b00 . . . . .1151
Figure 291. DMA requests in regular simultaneous mode when MDMA = 0b10 . . . . .1152
Figure 292. DMA requests in interleaved mode when MDMA = 0b10 . . . . .1152
Figure 293. Temperature sensor channel block diagram . . . . .1154
Figure 294. VBAT channel block diagram . . . . .1156
Figure 295. VREFINT channel block diagram . . . . .1156
Figure 296. Temperature sensor functional block diagram . . . . .1201
Figure 297. Method for low REF_CLK frequencies . . . . .1203
Figure 298. Method for high REF_CLK frequencies . . . . .1203
Figure 299. Temperature sensor sequence . . . . .1206
Figure 300. VREFBUF block diagram . . . . .1218
Figure 301. ADF block diagram . . . . .1224
Figure 302. SITF overview . . . . .1226
Figure 303. SPI timing example . . . . .1227
Figure 304. Manchester timing example (SITFMOD = 11) . . . . .1228
Figure 305. CKGEN overview . . . . .1231
Figure 306. BSMX overview . . . . .1233
Figure 307. DFLT overview . . . . .1234
Figure 308. Programmable delay . . . . .1235
Figure 309. CIC4 and CIC5 frequency response with decimation ratio = 32 or 16 . . . . .1236
Figure 310. Reshape filter frequency response normalized (FRS / 2 = 1). . . . .1242
Figure 311. Trigger logic for DFLT and CKGEN . . . . .1244
Figure 312. Asynchronous continuous mode (ACQMOD[2:0] = 0) . . . . .1245
Figure 313. Asynchronous single-shot mode (ACQMOD[2:0] = 001) . . . . .1246
Figure 314. Synchronous continuous mode (ACQMOD[2:0] = 010) . . . . .1247
Figure 315. Synchronous single-shot mode (ACQMOD[2:0] = 011) . . . . .1248
Figure 316. Window continuous mode (ACQMOD[2:0] = 100) . . . . .1249
Figure 317. Discard function example . . . . .1251
Figure 318. Start sequence with DFLTEN, in continuous mode, audio configuration . . . . .1251
Figure 319. SAD block diagram . . . . .1252
Figure 320. SAD flow diagram . . . . .1254
Figure 321. SAD timing diagram example . . . . .1260
Figure 322. ADF_DFLTxDATA data format . . . . .1260
Figure 323. Data resynchronization . . . . .1261
Figure 324. Example of overflow and transfer to memory . . . . .1262
Figure 325. ADF interrupt interface . . . . .1265
Figure 326. Sensor connection examples . . . . .1270
Figure 327. Global frequency response . . . . .1270
Figure 328. Detailed frequency response . . . . .1271
Figure 329. Simplified DFLT view with gain information . . . . .1273
Figure 330. SAD example working with SADMOD = 01 . . . . .1276
Figure 331. SAD example working with SADMOD = 1x . . . . .1277
Figure 332. DCMIPP overview . . . . .1296
Figure 333. DCMIPP block diagram . . . . .1299
Figure 334. Snapshot (CPTMODE = 1) and Continuous (CPTMODE = 0) capture modes. . . . .1309
Figure 335. Pipe0 (dump) architecture overview . . . . .1312
Figure 336. PSSI block diagram . . . . .1358
Figure 337. Top-level block diagram . . . . .1358
Figure 338. Data enable in receive mode waveform diagram (CKPOL=0) . . . . .1362
Figure 339. Data enable waveform diagram in transmit mode (CKPOL=1).1362
Figure 340. Ready in receive mode waveform diagram (CKPOL=0).1363
Figure 341. Bidirectional PSSI_DE/PSSI_RDY waveform1364
Figure 342. Bidirectional PSSI_DE/PSSI_RDY connection diagram1364
Figure 343. LTDC block diagram1372
Figure 344. LTDC synchronous timings.1375
Figure 345. Layer window programmable parameters1378
Figure 346. Blending two layers with background1380
Figure 347. Interrupt events.1382
Figure 348. JPEG codec block diagram1403
Figure 349. RNG block diagram1425
Figure 350. NIST SP800-90B entropy source model.1426
Figure 351. RNG initialization overview.1429
Figure 352. SAES block diagram.1443
Figure 353. Encryption/ decryption typical usage1445
Figure 354. Typical operation with authentication1447
Figure 355. Example of suspend mode management.1448
Figure 356. ECB encryption.1449
Figure 357. ECB decryption.1449
Figure 358. CBC encryption.1450
Figure 359. CBC decryption.1450
Figure 360. Message construction in CTR mode.1453
Figure 361. CTR encryption.1454
Figure 362. Message construction in GCM1455
Figure 363. GCM authenticated encryption1457
Figure 364. Message construction in GMAC mode1460
Figure 365. GMAC authentication mode1460
Figure 366. Message construction in CCM mode1461
Figure 367. CCM mode authenticated encryption1463
Figure 368. Operation with wrapped keys for SAES in ECB and CBC modes1467
Figure 369. Operation with wrapped keys for SAES in CTR mode1469
Figure 370. Usage of Shared-key mode1470
Figure 371. 128-bit block construction according to the data type.1473
Figure 372. CRYP block diagram1497
Figure 373. Encryption/ decryption typical usage1499
Figure 374. Typical operation with authentication1502
Figure 375. Example of suspend mode management.1503
Figure 376. ECB encryption.1504
Figure 377. ECB decryption.1504
Figure 378. CBC encryption.1505
Figure 379. CBC decryption.1505
Figure 380. Message construction in CTR mode.1508
Figure 381. CTR encryption.1509
Figure 382. Message construction in GCM1511
Figure 383. GCM authenticated encryption1512
Figure 384. Message construction in GMAC mode1516
Figure 385. GMAC authentication mode1516
Figure 386. Message construction in CCM mode1517
Figure 387. CCM mode authenticated encryption1519
Figure 388. 128-bit block construction according to the data type.1525
Figure 389. HASH block diagram1546
Figure 390. Message data swapping feature.1548
Figure 391. HASH suspend/resume mechanism . . . . .1554
Figure 392. MCE block diagram . . . . .1569
Figure 393. MCE region programming . . . . .1570
Figure 394. MCE implementation of block ciphers . . . . .1572
Figure 395. MCE implementation of stream cipher . . . . .1573
Figure 396. PKA block diagram . . . . .1592
Figure 397. Advanced-control timer block diagram . . . . .1626
Figure 398. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1632
Figure 399. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1632
Figure 400. Counter timing diagram, internal clock divided by 1 . . . . .1634
Figure 401. Counter timing diagram, internal clock divided by 2 . . . . .1634
Figure 402. Counter timing diagram, internal clock divided by 4 . . . . .1635
Figure 403. Counter timing diagram, internal clock divided by N . . . . .1635
Figure 404. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded) . . . . .		1636
Figure 405. Counter timing diagram, update event when ARPE = 1
(TIMx_ARR preloaded) . . . . .		1637
Figure 406. Counter timing diagram, internal clock divided by 1 . . . . .1638
Figure 407. Counter timing diagram, internal clock divided by 2 . . . . .1639
Figure 408. Counter timing diagram, internal clock divided by 4 . . . . .1639
Figure 409. Counter timing diagram, internal clock divided by N . . . . .1640
Figure 410. Counter timing diagram, update event when repetition counter is not used . . . . .1640
Figure 411. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1642
Figure 412. Counter timing diagram, internal clock divided by 2 . . . . .1642
Figure 413. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .1643
Figure 414. Counter timing diagram, internal clock divided by N . . . . .1643
Figure 415. Counter timing diagram, update event with ARPE = 1 (counter underflow) . . . . .1644
Figure 416. Counter timing diagram, Update event with ARPE = 1 (counter overflow) . . . . .1645
Figure 417. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1646
Figure 419. Control circuit in normal mode, internal clock divided by 1 . . . . .1648
Figure 420. tim_ti2 external clock connection example . . . . .1648
Figure 421. Control circuit in external clock mode 1 . . . . .1649
Figure 422. External trigger input block . . . . .1650
Figure 423. Control circuit in external clock mode 2 . . . . .1651
Figure 424. Capture/compare channel (example: channel 1 input stage) . . . . .1651
Figure 425. Capture/compare channel 1 main circuit . . . . .1652
Figure 426. Output stage of capture/compare channel (channel 1, idem ch. 2, 3 and 4) . . . . .1652
Figure 427. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .1653
Figure 428. PWM input mode timing . . . . .1655
Figure 429. Output compare mode, toggle on tim_oc1 . . . . .1657
Figure 430. Edge-aligned PWM waveforms (ARR = 8) . . . . .1658
Figure 431. Center-aligned PWM waveforms (ARR = 8) . . . . .1659
Figure 432. Dithering principle . . . . .1660
Figure 433. Data format and register coding in dithering mode . . . . .1661
Figure 434. PWM resolution vs frequency . . . . .1662
Figure 435. PWM dithering pattern . . . . .1663
Figure 436. Dithering effect on duty cycle in center-aligned PWM mode . . . . .1664
Figure 437. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1666
Figure 438. Combined PWM mode on channel 1 and 3 . . . . .1667
Figure 439. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .1668
Figure 440. Complementary output with symmetrical dead-time insertion . . . . .1669
Figure 441. Asymmetrical deadtime . . . . .1670
Figure 442.Dead-time waveforms with delay greater than the negative pulse . . . . .1670
Figure 443.Dead-time waveforms with delay greater than the positive pulse. . . . .1670
Figure 444.Break and Break2 circuitry overview . . . . .1673
Figure 445.Various output behavior in response to a break event on tim_brk (OSSI = 1) . . . . .1675
Figure 446.PWM output state following tim_brk and tim_brk2 assertion (OSSI = 1) . . . . .1676
Figure 447.PWM output state following tim_brk assertion (OSSI = 0) . . . . .1677
Figure 448.Output redirection (tim_brk2 request not represented). . . . .1678
Figure 449.Clearing TIMx tim_ocxref . . . . .1679
Figure 450.6-step generation, COM example (OSSR = 1) . . . . .1680
Figure 451.Example of one pulse mode. . . . .1681
Figure 452.Retriggerable one-pulse mode . . . . .1683
Figure 453.Pulse generator circuitry . . . . .1683
Figure 454.Pulse generation on compare event, for edge-aligned and encoder modes . . . . .1684
Figure 455.Extended pulsewidth in case of concurrent triggers . . . . .1685
Figure 456.Example of counter operation in encoder interface mode. . . . .1687
Figure 457.Example of encoder interface mode with tim_ti1fp1 polarity inverted. . . . .1687
Figure 458.Quadrature encoder counting modes . . . . .1688
Figure 459.Direction plus clock encoder mode. . . . .1689
Figure 460.Directional clock encoder mode (CC1P = CC2P = 0). . . . .1689
Figure 461.Directional clock encoder mode (CC1P = CC2P = 1). . . . .1690
Figure 462.Index gating options . . . . .1691
Figure 463.Jittered Index signals . . . . .1691
Figure 464.Index generation for IPOS[1:0] = 11 . . . . .1692
Figure 465.Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .1692
Figure 466.Counter reading with index ungated (IPOS[1:0] = 00) . . . . .1693
Figure 467.Counter reading with index gated on channel A and B. . . . .1693
Figure 468.Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11). . . . .1694
Figure 469.Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .1695
Figure 470.Index behavior in x1 and x2 mode (IPOS[1:0] = 01). . . . .1696
Figure 471.Directional index sensitivity. . . . .1696
Figure 472.Counter reset as function of FIDX bit setting . . . . .1697
Figure 473.Index blanking. . . . .1697
Figure 474.Index behavior in clock + direction mode, IPOS[0] = 1. . . . .1698
Figure 475.Index behavior in directional clock mode, IPOS[0] = 1 . . . . .1698
Figure 476.State diagram for quadrature encoded signals. . . . .1699
Figure 477.Up-counting encoder error detection . . . . .1700
Figure 478.Down-counting encode error detection. . . . .1701
Figure 479.Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .1702
Figure 480.Measuring time interval between edges on three signals. . . . .1703
Figure 481.Example of Hall sensor interface . . . . .1705
Figure 482.Control circuit in reset mode . . . . .1706
Figure 483.Control circuit in Gated mode . . . . .1707
Figure 484.Control circuit in trigger mode. . . . .1708
Figure 485.Control circuit in external clock mode 2 + trigger mode . . . . .1709
Figure 486.General-purpose timer block diagram . . . . .1767
Figure 487.Counter timing diagram with prescaler division change from 1 to 2 . . . . .1772
Figure 488.Counter timing diagram with prescaler division change from 1 to 4 . . . . .1773
Figure 489.Counter timing diagram, internal clock divided by 1 . . . . .1774
Figure 490.Counter timing diagram, internal clock divided by 2 . . . . .1774
Figure 491.Counter timing diagram, internal clock divided by 4 . . . . .1775
Figure 492.Counter timing diagram, internal clock divided by N. . . . .1775
Figure 493.Counter timing diagram, Update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .1776
Figure 494. Counter timing diagram, Update event when ARPE = 1 (TIMx_ARR preloaded). . . . .1777
Figure 495. Counter timing diagram, internal clock divided by 1 . . . . .1778
Figure 496. Counter timing diagram, internal clock divided by 2 . . . . .1779
Figure 497. Counter timing diagram, internal clock divided by 4 . . . . .1779
Figure 498. Counter timing diagram, internal clock divided by N . . . . .1780
Figure 499. Counter timing diagram, Update event . . . . .1780
Figure 500. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1782
Figure 501. Counter timing diagram, internal clock divided by 2 . . . . .1782
Figure 502. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .1783
Figure 503. Counter timing diagram, internal clock divided by N . . . . .1783
Figure 504. Counter timing diagram, Update event with ARPE = 1 (counter underflow). . . . .1784
Figure 505. Counter timing diagram, Update event with ARPE = 1 (counter overflow). . . . .1785
Figure 506. Control circuit in normal mode, internal clock divided by 1 . . . . .1786
Figure 507. tim_ti2 external clock connection example . . . . .1786
Figure 508. Control circuit in external clock mode 1 . . . . .1787
Figure 509. External trigger input block . . . . .1788
Figure 510. Control circuit in external clock mode 2 . . . . .1789
Figure 511. Capture/compare channel (example: channel 1 input stage). . . . .1789
Figure 512. Capture/compare channel 1 main circuit . . . . .1790
Figure 513. Output stage of capture/compare channel (channel 1, idem ch.2, 3 and 4). . . . .1790
Figure 514. PWM input mode timing . . . . .1793
Figure 515. Output compare mode, toggle on tim_oc1 . . . . .1795
Figure 516. Edge-aligned PWM waveforms (ARR = 8). . . . .1796
Figure 517. Center-aligned PWM waveforms (ARR = 8). . . . .1797
Figure 518. Dithering principle . . . . .1798
Figure 519. Data format and register coding in dithering mode. . . . .1799
Figure 520. PWM resolution vs frequency (16-bit mode). . . . .1800
Figure 521. PWM resolution vs frequency (32-bit mode). . . . .1800
Figure 522. PWM dithering pattern . . . . .1801
Figure 523. Dithering effect on duty cycle in center-aligned PWM mode . . . . .1802
Figure 524. Generation of two phase-shifted PWM signals with 50% duty cycle . . . . .1804
Figure 525. Combined PWM mode on channels 1 and 3 . . . . .1805
Figure 526. OCREF_CLR input selection multiplexer . . . . .1806
Figure 527. Clearing TIMx tim_ocxref . . . . .1806
Figure 528. Example of One-pulse mode . . . . .1807
Figure 529. Retriggerable one-pulse mode . . . . .1809
Figure 530. Pulse generator circuitry . . . . .1810
Figure 531. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .1810
Figure 532. Extended pulse width in case of concurrent triggers . . . . .1811
Figure 533. Example of counter operation in encoder interface mode . . . . .1813
Figure 534. Example of encoder interface mode with tim_ti1fp1 polarity inverted . . . . .1813
Figure 535. Quadrature encoder counting modes . . . . .1814
Figure 536. Direction plus clock encoder mode. . . . .1815
Figure 537. Directional clock encoder mode (CC1P = CC2P = 0). . . . .1816
Figure 538. Directional clock encoder mode (CC1P = CC2P = 1). . . . .1816
Figure 539. Index gating options . . . . .1818
Figure 540. Jittered Index signals . . . . .1818
Figure 541. Index generation for IPOS[1:0] = 11 . . . . .1819
Figure 542. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .1819
Figure 543. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .1820
Figure 544. Counter reading with index gated on channel A and B. . . . .1820
Figure 545. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11). . . . .1821
Figure 546. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .1822
Figure 547. Index behavior in x1 and x2 mode (IPOS[1:0] = 01) . . . . .1823
Figure 548. Directional index sensitivity . . . . .1823
Figure 549. Counter reset as function of FIDX bit setting . . . . .1824
Figure 550. Index blanking . . . . .1824
Figure 551. Index behavior in clock + direction mode, IPOS[0] = 1 . . . . .1825
Figure 552. Index behavior in directional clock mode, IPOS[0] = 1 . . . . .1825
Figure 553. State diagram for quadrature encoded signals . . . . .1826
Figure 554. Up-counting encoder error detection . . . . .1827
Figure 555. Down-counting encode error detection . . . . .1828
Figure 556. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .1829
Figure 557. Control circuit in reset mode . . . . .1831
Figure 558. Control circuit in gated mode . . . . .1832
Figure 559. Control circuit in trigger mode . . . . .1832
Figure 560. Control circuit in external clock mode 2 + trigger mode . . . . .1834
Figure 561. Master/Slave timer example . . . . .1834
Figure 562. Master/slave connection example with 1 channel only timers . . . . .1835
Figure 563. Gating TIM_slv with tim_oc1ref of TIM_mstr . . . . .1836
Figure 564. Gating TIM_slv with Enable of TIM_mstr . . . . .1837
Figure 565. Triggering TIM_slv with update of TIM_mstr . . . . .1838
Figure 566. Triggering TIM_slv with Enable of TIM_mstr . . . . .1838
Figure 567. Triggering TIM_mstr and TIM_slv with TIM_mstr tim_ti1 input . . . . .1839
Figure 568. Basic timer block diagram . . . . .1878
Figure 569. Control circuit in normal mode, internal clock divided by 1 . . . . .1879
Figure 570. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1881
Figure 571. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1881
Figure 572. Counter timing diagram, internal clock divided by 1 . . . . .1882
Figure 573. Counter timing diagram, internal clock divided by 2 . . . . .1883
Figure 574. Counter timing diagram, internal clock divided by 4 . . . . .1883
Figure 575. Counter timing diagram, internal clock divided by N . . . . .1884
Figure 576. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded) . . . . .		1884
Figure 577. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR
preloaded) . . . . .		1885
Figure 578. Dithering principle . . . . .1886
Figure 579. Data format and register coding in dithering mode . . . . .1886
Figure 580. FCnt resolution vs frequency . . . . .1887
Figure 581. PWM dithering pattern . . . . .1887
Figure 582. General-purpose timer block diagram (TIM9/TIM12) . . . . .1898
Figure 583. General-purpose timer block diagram (TIM13/TIM14) . . . . .1899
Figure 584. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1902
Figure 585. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1902
Figure 586. Counter timing diagram, internal clock divided by 1 . . . . .1903
Figure 587. Counter timing diagram, internal clock divided by 2 . . . . .1904
Figure 588. Counter timing diagram, internal clock divided by 4 . . . . .1904
Figure 589. Counter timing diagram, internal clock divided by N . . . . .1905
Figure 590. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded) . . . . .		1905
Figure 591. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR
preloaded) . . . . .		1906
Figure 592. Control circuit in normal mode, internal clock divided by 1 . . . . .1907
Figure 593. tim_ti2 external clock connection example . . . . .1907
Figure 594.Control circuit in external clock mode 1 . . . . .1908
Figure 595.Capture/compare channel 1 input stage (TIM13/TIM14) . . . . .1909
Figure 596.Capture/compare channel 1 input stage (TIM9/TIM12) . . . . .1909
Figure 597.Capture/compare channel 1 main circuit . . . . .1910
Figure 598.Output stage of capture/compare channel 1 . . . . .1910
Figure 599.PWM input mode timing . . . . .1912
Figure 600.Output compare mode, toggle on tim_oc1. . . . .1914
Figure 601.Edge-aligned PWM waveforms (ARR = 8) . . . . .1915
Figure 602.Dithering principle . . . . .1916
Figure 603.Data format and register coding in dithering mode . . . . .1916
Figure 604.PWM resolution vs frequency . . . . .1917
Figure 605.PWM dithering pattern . . . . .1918
Figure 606.Combined PWM mode on channel 1 and 2 . . . . .1920
Figure 607.Example of one pulse mode . . . . .1921
Figure 608.Retriggerable one pulse mode . . . . .1922
Figure 609.Measuring time interval between edges on 2 signals . . . . .1923
Figure 610.Control circuit in reset mode . . . . .1924
Figure 611.Control circuit in gated mode . . . . .1925
Figure 612.Control circuit in trigger mode . . . . .1925
Figure 613.TIM15 block diagram . . . . .1959
Figure 614.TIM16/TIM17 block diagram . . . . .1960
Figure 615.Counter timing diagram with prescaler division change from 1 to 2 . . . . .1964
Figure 616.Counter timing diagram with prescaler division change from 1 to 4 . . . . .1965
Figure 617.Counter timing diagram, internal clock divided by 1 . . . . .1966
Figure 618.Counter timing diagram, internal clock divided by 2 . . . . .1967
Figure 619.Counter timing diagram, internal clock divided by 4 . . . . .1967
Figure 620.Counter timing diagram, internal clock divided by N . . . . .1968
Figure 621.Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded). . . . .		1968
Figure 622.Counter timing diagram, update event when ARPE = 1
(TIMx_ARR preloaded). . . . .		1969
Figure 623.Update rate examples depending on mode and TIMx_RCR register settings . . . . .1970
Figure 624.Control circuit in normal mode, internal clock divided by 1 . . . . .1971
Figure 625.tim_ti2 external clock connection example . . . . .1971
Figure 626.Control circuit in external clock mode 1 . . . . .1972
Figure 627.Capture/compare channel (example: channel 1 input stage) . . . . .1973
Figure 628.Capture/compare channel 1 main circuit . . . . .1973
Figure 629.Output stage of capture/compare channel (channel 1). . . . .1974
Figure 630.Output stage of capture/compare channel (channel 2 for TIM15) . . . . .1974
Figure 631.PWM input mode timing . . . . .1977
Figure 632.Output compare mode, toggle on tim_oc1 . . . . .1979
Figure 633.Edge-aligned PWM waveforms (ARR = 8) . . . . .1980
Figure 634.Dithering principle . . . . .1981
Figure 635.Data format and register coding in dithering mode . . . . .1981
Figure 636.PWM resolution vs frequency . . . . .1982
Figure 637.PWM dithering pattern . . . . .1983
Figure 638.Combined PWM mode on channel 1 and 2 . . . . .1985
Figure 639.Complementary output with symmetrical dead-time insertion. . . . .1986
Figure 640.Asymmetrical deadtime . . . . .1987
Figure 641.Dead-time waveforms with delay greater than the negative pulse. . . . .1987
Figure 642.Dead-time waveforms with delay greater than the positive pulse. . . . .1987
Figure 643.Break circuitry overview . . . . .1989
Figure 644.Output behavior in response to a break event on tim_brk . . . . .1991
Figure 645.Output redirection . . . . .1993
Figure 646.tim_ocref_clr input selection multiplexer . . . . .1994
Figure 647.6-step generation, COM example (OSSR = 1) . . . . .1995
Figure 648.Example of one pulse mode . . . . .1996
Figure 649.Retriggerable one pulse mode . . . . .1998
Figure 650.Measuring time interval between edges on 2 signals . . . . .1998
Figure 651.Control circuit in reset mode . . . . .1999
Figure 652.Control circuit in gated mode . . . . .2000
Figure 653.Control circuit in trigger mode . . . . .2001
Figure 654.LPTIM1/2/3 block diagram (1) . . . . .2064
Figure 655.LPTIM4/5 block diagram (1) . . . . .2065
Figure 656.Glitch filter timing diagram . . . . .2069
Figure 657.LPTIM output waveform, single-counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . .		2071
Figure 658.LPTIM output waveform, single-counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . .		2072
Figure 659.LPTIM output waveform, Continuous counting mode configuration . . . . .2072
Figure 660.Waveform generation . . . . .2074
Figure 661.Encoder mode counting sequence . . . . .2078
Figure 662.Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1) . . . . .		2079
Figure 663.Capture/compare input stage (channel 1) . . . . .2080
Figure 664.Capture/compare output stage (channel 1) . . . . .2080
Figure 665.Edge-aligned PWM mode (PRELOAD = 1) . . . . .2082
Figure 666.Edge-aligned PWM waveforms (ARR=8 and CCxP = 0) . . . . .2083
Figure 667.PWM mode with immediate update versus preloaded update . . . . .2084
Figure 668.Watchdog block diagram . . . . .2114
Figure 669.Window watchdog timing diagram . . . . .2116
Figure 670.Independent watchdog block diagram . . . . .2121
Figure 671.Reset timing due to timeout . . . . .2123
Figure 672.Reset timing due to refresh in the not allowed area . . . . .2124
Figure 673.Changing PR, RL, and performing a refresh (1) . . . . .2125
Figure 674.Window comparator update (1) . . . . .2126
Figure 675.Independent watchdog interrupt timing diagram . . . . .2128
Figure 676.Early wake-up comparator update (1) . . . . .2129
Figure 677.RTC block diagram . . . . .2137
Figure 678.TAMP block diagram . . . . .2186
Figure 679.Backup registers protection zones . . . . .2190
Figure 680.Tamper sampling with precharge pulse . . . . .2195
Figure 681.Low level detection with precharge and filtering . . . . .2195
Figure 682.Active tamper filtering . . . . .2197
Figure 683.Block diagram . . . . .2230
Figure 684.I 2 C-bus protocol . . . . .2232
Figure 685.Setup and hold timings . . . . .2234
Figure 686.I2C initialization flow . . . . .2236
Figure 687.Data reception . . . . .2237
Figure 688.Data transmission . . . . .2238
Figure 689.Target initialization flow . . . . .2241
Figure 690.Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .2243
Figure 691.Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .2244
Figure 692.Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .2245
Figure 693.Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .2246
Figure 694.Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .2247
Figure 695.Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . .		2247
Figure 696.Controller clock generation . . . . .2249
Figure 697.Controller initialization flow . . . . .2251
Figure 698.10-bit address read access with HEAD10R = 0 . . . . .2251
Figure 699.10-bit address read access with HEAD10R = 1 . . . . .2252
Figure 700.Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .2253
Figure 701.Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .2254
Figure 702.Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		2255
Figure 703.Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .2257
Figure 704.Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .2258
Figure 705.Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		2259
Figure 706.Timeout intervals for t LOW:SEXT , t LOW:MEXT . . . . .2263
Figure 707.Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .2266
Figure 708.Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .2267
Figure 709.Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .2268
Figure 710.Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .2269
Figure 711.Bus transfer diagrams for SMBus controller transmitter . . . . .2270
Figure 712.Bus transfer diagrams for SMBus controller receiver . . . . .2272
Figure 713.I3C block diagram . . . . .2296
Figure 714.I3C (primary) controller state and programming sequence diagram. . . . .2300
Figure 715.I3C target state and programming sequence diagram . . . . .2305
Figure 716.I3C CCC messages, as controller . . . . .2319
Figure 717.I3C broadcast ENTDAA CCC, as controller . . . . .2320
Figure 718.I3C broadcast, direct read and direct write RSTACT CCC, as controller . . . . .2321
Figure 719.I3C CCC messages, as target . . . . .2323
Figure 720.I3C broadcast ENTDAA CCC, as target. . . . .2324
Figure 721.I3C broadcast DEFTGTS CCC, as target. . . . .2325
Figure 722.I3C broadcast DEFGRPA CCC, as target . . . . .2326
Figure 723.I3C private read/write messages, as controller. . . . .2328
Figure 724.I3C private read/write messages, as target . . . . .2329
Figure 725.Legacy I2C read/write messages, as controller . . . . .2330
Figure 726.IBI transfer, as controller/target . . . . .2331
Figure 727.Hot-join request transfer, as controller/target . . . . .2332
Figure 728.Controller-role request transfer, as controller/target . . . . .2333
Figure 729.C-FIFO management, as controller . . . . .2334
Figure 730.TX-FIFO management, as controller . . . . .2336
Figure 731.RX-FIFO management, as controller . . . . .2338
Figure 732.S-FIFO management, as controller . . . . .2341
Figure 733.RX-FIFO management, as target on the I3C bus . . . . .2342
Figure 734.TX-FIFO management with I3C_TGTTDR, as target on the I3C bus. . . . .2344
Figure 735.TX-FIFO management by software without I3C_TGTTDR
if reading less bytes than TX-FIFO size, as target. . . . .		2346
Figure 736.USART block diagram . . . . .2404
Figure 737.Word length programming . . . . .2408
Figure 738.Configurable stop bits . . . . .2410
Figure 739.TC/TXE behavior when transmitting . . . . .2412
Figure 740.Start bit detection when oversampling by 16 or 8. . . . .2413
Figure 741.usart_ker_ck clock divider block diagram . . . . .2416
Figure 742.Data sampling when oversampling by 16 . . . . .2417
Figure 743.Data sampling when oversampling by 8 . . . . .2418
Figure 744.Mute mode using Idle line detection . . . . .2425
Figure 745.Mute mode using address mark detection . . . . .2426
Figure 746.Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .2429
Figure 747.Break detection in LIN mode vs. Framing error detection. . . . .2430
Figure 748.USART example of synchronous master transmission. . . . .2431
Figure 749.USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		2431
Figure 750.USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		2432
Figure 751.USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		2433
Figure 752.ISO 7816-3 asynchronous protocol . . . . .2435
Figure 753.Parity error detection using the 1.5 stop bits . . . . .2437
Figure 754.IrDA SIR ENDEC block diagram. . . . .2441
Figure 755.IrDA data modulation (3/16) - normal mode . . . . .2441
Figure 756.Transmission using DMA . . . . .2443
Figure 757.Reception using DMA . . . . .2444
Figure 758.Hardware flow control between two USARTs. . . . .2444
Figure 759.RS232 RTS flow control . . . . .2445
Figure 760.RS232 CTS flow control . . . . .2446
Figure 761.Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .2449
Figure 762.Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		2449
Figure 763.LPUART block diagram . . . . .2494
Figure 764.LPUART word length programming . . . . .2497
Figure 765.Configurable stop bits . . . . .2499
Figure 766.TC/TXE behavior when transmitting . . . . .2501
Figure 767.lpuart_ker_ck clock divider block diagram . . . . .2505
Figure 768.Mute mode using Idle line detection . . . . .2509
Figure 769.Mute mode using address mark detection . . . . .2510
Figure 770.Transmission using DMA . . . . .2512
Figure 771.Reception using DMA . . . . .2513
Figure 772.Hardware flow control between two LPUARTs. . . . .2514
Figure 773.RS232 RTS flow control . . . . .2514
Figure 774.RS232 CTS flow control . . . . .2515
Figure 775.Wake-up event verified (wake-up event = address match,
FIFO disabled) . . . . .		2518
Figure 776.Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		2518
Figure 777.SPI/I2S block diagram . . . . .2550
Figure 778.Full-duplex single master/ single slave application. . . . .2553
Figure 779.Half-duplex single master/ single slave application . . . . .2554
Figure 780.Simplex single master / single slave application
(master in transmit-only / slave in receive-only mode) . . . . .		2555
Figure 781.Master and three independent slaves connected in star topology . . . . .2556
Figure 782.Master and three slaves connected in circular (daisy chain) topology . . . . .2558
Figure 783.Multimaster application . . . . .2559
Figure 784.Scheme of NSS control logic . . . . .2561
Figure 785.Data flow timing control (SSOE = 1, SSOM = 0, SSM = 0) . . . . .2561
Figure 786. NSS interleaving pulses between data (SSOE = 1, SSOM = 1, SSM = 0) . . . . .2562
Figure 787. Data clock timing diagram . . . . .2564
Figure 788. Data alignment when data size is not equal to 8, 16 or 32 bits . . . . .2565
Figure 789. TI mode transfer . . . . .2574
Figure 790. Optional configurations of the slave behavior when an underrun condition is detected . . . . .2576
Figure 791. Waveform examples . . . . .2584
Figure 792. Master I2S Philips protocol waveforms (16/32-bit full accuracy) . . . . .2585
Figure 793. I2S Philips standard waveforms . . . . .2585
Figure 794. Master MSB-justified 16- or 32-bit full-accuracy length . . . . .2586
Figure 795. Master MSB-justified 16- or 24-bit data length . . . . .2586
Figure 796. Slave MSB-justified 16-, 24- or 32-bit data length . . . . .2587
Figure 797. LSB-justified 16 or 24-bit data length . . . . .2587
Figure 798. Master PCM when the frame length is equal the data length . . . . .2588
Figure 799. Master PCM standard waveforms (16 or 24-bit data length) . . . . .2588
Figure 800. Slave PCM waveforms . . . . .2589
Figure 801. Startup sequence, I2S Philips standard, master . . . . .2592
Figure 802. Startup sequence, I2S Philips standard, slave . . . . .2593
Figure 803. Stop sequence, I2S Philips standard, master . . . . .2593
Figure 804. I 2 S clock generator architecture . . . . .2594
Figure 805. Data Format . . . . .2596
Figure 806. Handling of underrun situation . . . . .2598
Figure 807. Handling of overrun situation . . . . .2599
Figure 808. Frame error detection, with FIXCH = 0 . . . . .2600
Figure 809. Frame error detection, with FIXCH = 1 . . . . .2600
Figure 810. SAI functional block diagram . . . . .2626
Figure 811. Audio frame . . . . .2630
Figure 812. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .2632
Figure 813. FS role is start of frame (FSDEF = 0) . . . . .2633
Figure 814. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .2634
Figure 815. First bit offset . . . . .2634
Figure 816. Audio block clock generator overview . . . . .2636
Figure 817. PDM typical connection and timing . . . . .2640
Figure 818. Detailed PDM interface block diagram . . . . .2641
Figure 819. Start-up sequence . . . . .2642
Figure 820. SAI_ADR format in TDM mode, 32-bit slot width . . . . .2643
Figure 821. SAI_ADR format in TDM mode, 16-bit slot width . . . . .2644
Figure 822. SAI_ADR format in TDM mode, 8-bit slot width . . . . .2645
Figure 823. AC'97 audio frame . . . . .2648
Figure 824. Example of typical AC'97 configuration on devices featuring at least two embedded SAIs (three external AC'97 decoders) . . . . .2649
Figure 825. SPDIF format . . . . .2650
Figure 826. SAI_xDR register ordering . . . . .2651
Figure 827. Data companding hardware in an audio block in the SAI . . . . .2654
Figure 828. Tristate strategy on SD output line on an inactive slot . . . . .2656
Figure 829. Tristate on output data line in a protocol like I2S . . . . .2657
Figure 830. Overrun detection error . . . . .2658
Figure 831. FIFO underrun event . . . . .2658
Figure 832. SPDIFRX block diagram . . . . .2693
Figure 833. S/PDIF sub-frame format . . . . .2694
Figure 834. S/PDIF block format . . . . .2695
Figure 835. S/PDIF preambles . . . . .2695
Figure 836. Channel coding example . . . . .2696
Figure 837. SPDIFRX decoder . . . . .2697
Figure 838. Noise filtering and edge detection . . . . .2697
Figure 839. Thresholds . . . . .2699
Figure 840. Synchronization flowchart. . . . .2701
Figure 841. Synchronization process scheduling . . . . .2702
Figure 842. SPDIFRX states . . . . .2703
Figure 843. SPDIFRX_FMTx_DR register format . . . . .2705
Figure 844. Channel/user data format . . . . .2706
Figure 845. S/PDIF overrun error when RXSTEO = 0 . . . . .2708
Figure 846. S/PDIF overrun error when RXSTEO = 1 . . . . .2709
Figure 847. SPDIFRX interface interrupt mapping diagram . . . . .2712
Figure 848. MDIOS block diagram . . . . .2727
Figure 849. MDIO protocol write frame waveform . . . . .2728
Figure 850. MDIO protocol read frame waveform . . . . .2728
Figure 851. SDMMC “no response” and “no data” operations. . . . .2740
Figure 852. SDMMC (multiple) block read operation . . . . .2740
Figure 853. SDMMC (multiple) block write operation. . . . .2741
Figure 854. SDMMC (sequential) stream read operation . . . . .2741
Figure 855. SDMMC (sequential) stream write operation . . . . .2741
Figure 856. SDMMC block diagram. . . . .2743
Figure 857. SDMMC Command and data phase relation . . . . .2745
Figure 858. Control unit . . . . .2747
Figure 859. Command/response path . . . . .2748
Figure 860. Command path state machine (CPSM) . . . . .2749
Figure 861. Data path . . . . .2755
Figure 862. DDR mode data packet clocking . . . . .2756
Figure 863. DDR mode CRC status / boot acknowledgment clocking. . . . .2756
Figure 864. Data path state machine (DPSM) . . . . .2757
Figure 865. CLKMUX unit . . . . .2768
Figure 866. Linked list structures . . . . .2770
Figure 867. Asynchronous interrupt generation. . . . .2773
Figure 868. Synchronous interrupt period data read . . . . .2774
Figure 869. Synchronous interrupt period data write . . . . .2774
Figure 870. Asynchronous interrupt period data read . . . . .2775
Figure 871. Asynchronous interrupt period data write . . . . .2776
Figure 872. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25. . . . .2779
Figure 873. Clock stop with SDMMC_CK for DDR50, SDR50, SDR104. . . . .2779
Figure 874. Read Wait with SDMMC_CK < 50 MHz . . . . .2780
Figure 875. Read Wait with SDMMC_CK > 50 MHz . . . . .2780
Figure 876. CMD12 stream timing . . . . .2783
Figure 877. CMD5 Sleep Awake procedure . . . . .2785
Figure 878. Normal boot mode operation . . . . .2787
Figure 879. Alternative boot mode operation. . . . .2788
Figure 880. Command response R1b busy signaling . . . . .2789
Figure 881. SDMMC state control . . . . .2790
Figure 882. Card cycle power / power up diagram . . . . .2791
Figure 883. CMD11 signal voltage switch sequence . . . . .2792
Figure 884. Voltage switch transceiver typical application. . . . .2794
Figure 885. CAN subsystem. . . . .2822
Figure 886. FDCAN block diagram . . . . .2824
Figure 887. Bit timing . . . . .2826
Figure 888. Transceiver delay measurement . . . . .2831
Figure 889. Pin control in bus monitoring mode . . . . .2832
Figure 890. Pin control in loop-back mode . . . . .2835
Figure 891. CAN error state diagram. . . . .2836
Figure 892. Message RAM configuration. . . . .2837
Figure 893. Standard message ID filter path . . . . .2840
Figure 894. Extended message ID filter path. . . . .2841
Figure 895. OTG_FS full-speed block diagram . . . . .2891
Figure 896. OTG_FS A-B device connection. . . . .2893
Figure 897. OTG_FS peripheral-only connection . . . . .2894
Figure 898. OTG_FS host-only connection . . . . .2898
Figure 899. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .2902
Figure 900. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .2904
Figure 901. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .2905
Figure 902. Host-mode FIFO address mapping and AHB FIFO access mapping. . . . .2906
Figure 903. Interrupt hierarchy. . . . .2910
Figure 904. Transmit FIFO write task . . . . .3002
Figure 905. Receive FIFO read task . . . . .3003
Figure 906. Normal bulk/control OUT/SETUP . . . . .3004
Figure 907. Bulk/control IN transactions . . . . .3008
Figure 908. Normal interrupt OUT . . . . .3011
Figure 909. Normal interrupt IN . . . . .3016
Figure 910. Isochronous OUT transactions . . . . .3018
Figure 911. Isochronous IN transactions . . . . .3021
Figure 912. Receive FIFO packet read . . . . .3025
Figure 913. Processing a SETUP packet . . . . .3027
Figure 914. Bulk OUT transaction . . . . .3034
Figure 915. TRDT max timing case . . . . .3044
Figure 916. OTG_HS high-speed block diagram. . . . .3049
Figure 917. OTG_HS A-B device connection . . . . .3051
Figure 918. OTG_HS peripheral-only connection . . . . .3052
Figure 919. OTG_HS host-only connection . . . . .3056
Figure 920. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .3060
Figure 921. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .3062
Figure 922. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .3063
Figure 923. Host-mode FIFO address mapping and AHB FIFO access mapping. . . . .3064
Figure 924. Interrupt hierarchy. . . . .3068
Figure 925. Transmit FIFO write task . . . . .3161
Figure 926. Receive FIFO read task . . . . .3162
Figure 927. Normal bulk/control OUT/SETUP . . . . .3163
Figure 928. Bulk/control IN transactions . . . . .3167
Figure 929. Normal interrupt OUT . . . . .3170
Figure 930. Normal interrupt IN . . . . .3175
Figure 931. Isochronous OUT transactions . . . . .3177
Figure 932. Isochronous IN transactions . . . . .3180
Figure 933. Normal bulk/control OUT/SETUP transactions - DMA . . . . .3182
Figure 934. Normal bulk/control IN transaction - DMA. . . . .3184
Figure 935. Normal interrupt OUT transactions - DMA mode . . . . .3185
Figure 936. Normal interrupt IN transactions - DMA mode . . . . .3186
Figure 937. Normal isochronous OUT transaction - DMA mode . . . . .3187
Figure 938. Normal isochronous IN transactions - DMA mode . . . . .3188
Figure 939. Receive FIFO packet read . . . . .3194
Figure 940. Processing a SETUP packet . . . . .3196
Figure 941. Bulk OUT transaction . . . . .3203
Figure 942. TRDT max timing case . . . . .3212
Figure 943. UCPD block diagram . . . . .3216
Figure 944. Clock division and timing elements. . . . .3218
Figure 945. K-code transmission . . . . .3220
Figure 946. Transmit order for various sizes of data . . . . .3221
Figure 947. Packet format . . . . .3222
Figure 948. Line format of Hard Reset. . . . .3222
Figure 949. Line format of Cable Reset. . . . .3223
Figure 950. BIST test data frame. . . . .3224
Figure 951. BIST Carrier Mode 2 frame. . . . .3224
Figure 952. UCPD BMC transmitter architecture. . . . .3225
Figure 953. UCPD BMC receiver architecture . . . . .3226
Figure 954. Ethernet high-level block diagram . . . . .3259
Figure 955. DMA transmission flow (standard mode) . . . . .3262
Figure 956. DMA transmission flow (OSP mode) . . . . .3264
Figure 957. Receive DMA flow . . . . .3266
Figure 958. Overview of MAC transmission flow . . . . .3270
Figure 959. MAC reception flow . . . . .3272
Figure 960. Packet filtering sequence . . . . .3276
Figure 961. Networked time synchronization. . . . .3286
Figure 962. Propagation delay calculation in clocks supporting
peer-to-peer path correction . . . . .		3287
Figure 963. System time update using fine correction method . . . . .3297
Figure 964. TCP segmentation offload overview. . . . .3314
Figure 965. TCP segmentation offload flow. . . . .3315
Figure 966. Header and payload fields of segmented packets . . . . .3318
Figure 967. Supported PHY interfaces . . . . .3327
Figure 968. SMA Interface block . . . . .3327
Figure 969. MDIO packet structure (Clause 45) . . . . .3328
Figure 970. MDIO packet structure (Clause 22) . . . . .3329
Figure 971. SMA write operation flow . . . . .3331
Figure 972. Write data packet . . . . .3332
Figure 973. Read data packet . . . . .3332
Figure 974. Media independent interface (MII) signals . . . . .3334
Figure 975. RMII block diagram. . . . .3336
Figure 976. Transmission bit order . . . . .3337
Figure 977. Receive bit order. . . . .3338
Figure 978. LPI transitions (Transmit, 100 Mbds) . . . . .3346
Figure 979. LPI Tx clock gating (when LPITCSE = 1) . . . . .3347
Figure 980. LPI transitions (receive, 100 Mbit/s) . . . . .3348
Figure 981. Descriptor ring structure . . . . .3369
Figure 982. DMA descriptor ring . . . . .3371
Figure 983. Descriptor tail pointer example 1 . . . . .3371
Figure 984. Descriptor tail pointer example 2 . . . . .3372
Figure 985. Transmit descriptor (read format) . . . . .3373
Figure 986. Transmit descriptor write-back format. . . . .3378
Figure 987. Transmit context descriptor format. . . . .3382
Figure 988. Receive normal descriptor (read format) . . . . .3385
Figure 989. Receive normal descriptor (write-back format). . . . .3387
Figure 990. Receive context descriptor . . . . .3395
Figure 991. Generation of ETH_DMAISR flags . . . . .3410
Figure 992. HDMI-CEC block diagram . . . . .3524
Figure 993. Message structure . . . . .3524
Figure 994. Blocks . . . . .3525
Figure 995. Bit timings . . . . .3525
Figure 996. Signal free time . . . . .3526
Figure 997. Arbitration phase . . . . .3526
Figure 998. SFT of three nominal bit periods . . . . .3526
Figure 999. Error bit timing . . . . .3527
Figure 1000. Error handling . . . . .3529
Figure 1001. TXERR detection . . . . .3530
Figure 1002. Block diagram of debug infrastructure . . . . .3541
Figure 1003. Clock domains of debug infrastructure . . . . .3542
Figure 1004. Product life cycle states and debug authentication . . . . .3545
Figure 1005. SWD successful data transfer . . . . .3548
Figure 1006. JTAG TAP state machine . . . . .3549
Figure 1007. Debug and access port connections . . . . .3562
Figure 1008. APB-D CoreSight component topology . . . . .3575
Figure 1009. Embedded cross trigger . . . . .3582
Figure 1010. Mapping of trigger inputs to outputs . . . . .3584
Figure 1011. ETF state transition diagram . . . . .3614
Figure 1012. Cortex-M7 CoreSight Topology . . . . .3684

Chapters