36. Revision history

Updated Section 1.1: General information , sections 2.1.1: S0: CPU1 (CPU1 Cortex®-M4) I-bus to 2.1.3: S2: CPU1 (CPU1 Cortex®-M4) S-bus, User and read protection option bytes , Section 3.10.7: Flash memory option register (FLASH_OPTR) , Section 5.4.10: Standby mode , Section 6.1.2: System reset , Section 6.2.15: ADC clock , Section 6.4.3: RCC clock configuration register (RCC_CFGR) , Section 6.4.4: RCC PLL configuration register (RCC_PLLCFGR) , Section 6.4.11: RCC AHB2 peripheral reset register (RCC_AHB2RSTR) , Section 6.4.15: RCC APB2 peripheral reset register (RCC_APB2RSTR) , Section 6.4.18: RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) , Section 6.4.22: RCC APB2 peripheral clock enable register (RCC_APB2ENR) , Section 6.4.24: RCC AHB2 peripheral clocks enable in Sleep modes register (RCC_AHB2SMENR) , Section 6.4.28: RCC APB2 peripheral clocks enable in Sleep mode register (RCC_APB2SMENR) , Section 6.4.36: RCC CPU2 AHB2 peripheral clock enable register (RCC_C2AHB2ENR) , Section 6.4.40: RCC CPU2 APB2 peripheral clock enable register (RCC_C2APB2ENR) , Section 6.4.43: RCC CPU2 AHB2 peripheral clocks enable in Sleep modes register (RCC_C2AHB2SMENR) , Section 6.4.47: RCC CPU2 APB2 peripheral clocks enable in Sleep mode register (RCC_C2APB2SMENR) , Section 10.4.2: I/O pin alternate function multiplexer and mapping , sections 10.5.1: GPIO port mode register (GPIOx_MODER) (x =A to E and H) to 10.5.11: GPIO port bit reset register (GPIOx_BRR) (x = A to E and H) , Section 11.2.11: SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2) , Section 11.2.12: SYSCFG CPU1 interrupt mask register 1 (SYSCFG_IMR1) , Section 23.3.4: Charge transfer acquisition sequence , Section 14.1: Introduction , Section 14.2: ADC main features , Section 14.4.11: Configuring the ADC , Calculating the actual V _DDA voltage using the internal reference voltage , Converting a supply-relative ADC measurement to an absolute voltage value , Section 14.14: ADC interrupts , Section 14.15.1: ADC interrupt and status register (ADC_ISR) , Section 14.15.4: ADC configuration register 1 (ADC_CFGR1) , Section 14.15.5: ADC configuration register 2 (ADC_CFGR2) , Section 21.6.1: Comparator 1 control and status register (COMP1_CSR) , Section 26.3.3: PKA reset and clocks , Montgomery space and fast mode operations , Enabling/disabling PKA , Using precomputed Montgomery parameters (PKA fast mode) , sections 26.7.2: PKA status register (PKA_SR) to 26.7.4: PKA RAM , Section 28.4.2: TIM2 control register 2 (TIM2_CR2) , Section 28.4.8: TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) , Section 30.7.1: LPTIM interrupt and status register (LPTIM_ISR) , Section 30.7.2: LPTIM interrupt clear register (LPTIM_ICR) , Section 34.7.19: RTC option register (RTC_OR) , Section 41.8.2: DBGMCU configuration register (DBGMCU_CR) , Section 41.8.4: DBGMCU CPU2 APB1 peripheral freeze register 1 (DBGMCU_C2APB1FZR1) , Section 41.8.6: DBGMCU CPU2 APB1 peripheral freeze register 2 (DBGMCU_C2APB1FZR2) , and Section 41.8.8: DBGMCU CPU2 APB2 peripheral freeze register (DBGMCU_C2APB2FZR) .

Removed former Section 15.7.2: Description of analog watchdog 2 and 3 , Section 15.8: Oversampler , Section 15.12.8: ADC watchdog threshold register (ADC_AWD2T) , Section 15.12.13: ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR) , and Section 15.12.14: ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR) .

Updated Figure 2: Memory map , Figure 5: Radio system block diagram , Figure 13: Simplified diagram of the reset circuit , footnote 3 of Figure 14: Clock tree , Figure 123: Charge transfer acquisition sequence , and Figure 31: ADC block diagram .

Updated Table 1: Memory map and peripheral register boundary addresses , Table 3: Flash memory - Single bank organization , Table 9: Option bytes organization , Table 18: Flash interface register map and reset values , Table 25: Functionalities depending on system operating mode , Table 38: RCC register map and reset values , Table 53: GPIO register map and reset values , Table 54: SYSCFG register map and reset values , Table 72: CPU1 vector table , Table 74: Wake-up interrupt table , Table 91: ADC interrupts , Table 74: ADC register map and reset values , Table 165: Modular exponentiation computation times , Table 170: Montgomery parameters average computation times , Table 181: Output control bit for standard OCx channels , and Table 200: RTC register map and reset values .

Added Table 169: Point on elliptic curve Fp check average computation times .

Minor text edits across the whole document.

Updated document title, Introduction , Section 3.10.6: Flash memory ECC register (FLASH_ECCR) , Section 4.1: Introduction , Section 4.2: Main features , Section 5.6.11: PWR Port B pull-up control register (PWR_PUCRB) , Section 5.6.12: PWR Port B pull-down control register (PWR_PDCRB) , Section 12.4.3: From ADC (ADC1) to timer (TIM1) , Section 6.2: Clocks , Section 6.4.1: RCC clock control register (RCC_CR) , Section 6.4.3: RCC clock configuration register (RCC_CFGR) , sections 10.5.1: GPIO port mode register (GPIOx_MODER) (x = A to E and H) to 10.5.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and H) , Section 10.5.10: GPIO alternate function high register (GPIOx_AFRH) (x = A to E and H) , Section 10.5.11: GPIO port bit reset register (GPIOx_BRR) (x = A to E and H) , Section 14.4.4: DMAMUX request line multiplexer , Section 16.6.9: EXTI CPU wakeup with interrupt mask register (EXTI_IMR1) , Section 16.6.9: EXTI CPU wakeup with interrupt mask register (EXTI_IMR1) , Section 16.6.13: EXTI CPU wakeup with interrupt mask register (EXTI_IMR2) , Section 16.6.15: EXTI CPU wakeup with event mask register (EXTI_EMR2) , Section 16.6.16: EXTI CPU2 wakeup with event mask register (EXTI_C2EMR2) , Section 26.3.4: PKA public key acceleration , Section 26.4.5: Modular and Montgomery multiplication , Section 26.5.1: Supported elliptic curves , Section 27.4.23: TIM1 option register 1 (TIM1_OR1) , Section 36.2: USART main features , Section 8.4.1: HSEM register semaphore x (HSEM_Rx) , and Section 8.4.2: HSEM read lock register semaphore x (HSEM_RLRx) .

Added Note: in Section 30.4.6: Trigger multiplexer and footnote to Table 146: Montgomery multiplication .

Added Section 36.6: USART in low-power modes and Section 37.5: LPUART in low-power modes .

Updated Figure 2: Memory map and Figure 178: TIM1 ETR input circuitry .
Updated Table 1: Memory map and peripheral register boundary addresses , Table 33: PWR register map and reset values , Table 53: GPIO register map and reset values , Table 81: EXTI register map and reset values , Table 131: CTR mode initialization vector definition , Table 133: Initialization of AES_IVRx registers in GCM mode , Table 171: PKA interrupt requests , Table 226: USART interrupt requests , and Table 236: LPUART interrupt requests .
Minor text edits across the whole document.

Updated User and read protection option bytes , reset values in sections 3.10.7: Flash memory option register (FLASH_OPTR) to 3.10.14: Flash memory IPCC mailbox data buffer address register (FLASH_IPCCBR) , Section 17.2: CRC main features , Polynomial programmability , Section 17.4: CRC registers , Section 5.4: Low-power modes , Section 5.4.4: Exiting Low-power mode , Section 6.2: Clocks , Section 6.2.7: LSI1 clock , Section 6.2.8: LSI2 clock , Section 6.4.1: RCC clock control register (RCC_CR) , Section 6.4.31: RCC control/status register (RCC_CSR) , Section 14.4.3: ADC voltage regulator (ADVREGEN) , Section 14.4.16: Starting conversions (ADSTART) , Section 30.7.4: LPTIM configuration register (LPTIM_CFGGR) , Section 36.8.3: USART control register 2 (USART_CR2) , Section 37.4.14: LPUART low-power management , Section 37.7.3: LPUART control register 2 (LPUART_CR2) , Section 8.4: HSEM registers , and Section 41.8.1: DBGMCU identity code register (DBGMCU_IDCODE) .
Updated Table 21: Sub-system low power wake-up sources , Table 25: Functionalities depending on system operating mode , Table 72: ADC input/output pins , Table 120: Acquisition sequence summary , and Table 279: DBGMCU register map and reset values .
Updated Figure 44: CRC calculation unit block diagram , Figure 11: Low-power modes possible transitions and added footnote to it, Figure 14: Clock tree , Figure 31: ADC block diagram , Figure 121: Surface charge transfer analog I/O group structure , and Figure 156: Advanced-control timer block diagram .
Minor text edits across the whole document.

Updated Section 17.4.2: CRC independent data register (CRC_IDR) , Section 5.6.2: PWR control register 2 (PWR_CR2) , Section 6.2.12: Clock security system on LSE (LSECSS) , Section 10.4.2: I/O pin alternate function multiplexer and mapping , Section 14.4.6: Calibration (ADCAL) , DMA operation in different operating modes , Section 27.3.16: Using the break function , Section 27.4.8: TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) , Section 34.4.14: Calibration clock output , Section 36.5.20: RS232 hardware flow control and RS485 Driver Enable , Section 36.8.4: USART control register 3 (USART_CR3) , Communication using DMA (direct memory addressing) , Section 37.4.13: RS232 hardware flow control and RS485 Driver Enable , Section 37.7.4: LPUART control register 3 (LPUART_CR3) , Communication using DMA (direct memory addressing) , and Section 41.8.1: DBGMCU identity code register (DBGMCU_IDCODE) .

Updated Table 20: CRC register map and reset values .

Added footnote 2 to Table 19: Supply configuration control .

Updated Figure 147: GCM authenticated encryption and Figure 179: Control circuit in normal mode, internal clock divided by 1 .

Added Section 42.4: Part number codification register .

Updated Introduction , Section 5.4: Low-power modes , Section 5.4.4: Exiting Low-power mode , Section 6.2: Clocks , Section 6.2.7: LSI1 clock , Section 14.4.6: Calibration (ADCAL) , Section 14.4.11: Configuring the ADC , Section 14.11: Temperature sensor and internal reference voltage , Section 14.15.3: ADC control register (ADC_CR) , Section 14.15.4: ADC configuration register 1 (ADC_CFGR1) , Section 14.15.5: ADC configuration register 2 (ADC_CFGR2) , Section 14.15.18: ADC calibration factor (ADC_CALFACT) , Section 24.2: RNG main features , and Section 41.7.15: CTI lock access register (CTI_LAR) .

Renamed \( t_{ADCVREG\_SETUP} \) into \( t_{ADCVREG\_STUP} \) throughout Section 14: Analog-to-digital converter (ADC) .

Updated Table 21: Sub-system low power wake-up sources and Table 25: Functionalities depending on system operating mode .

Updated Figure 11: Low-power modes possible transitions .

Minor text edits across the whole document.

Updated document title, Introduction , Section 3.3.1: Flash memory organization , CPU2 secure SRAM2 areas , Section 4.1: Introduction , Section 4.2: Main features , Section 6.4.30: RCC backup domain control register (RCC_BDCR) , Section 6.4.31: RCC control/status register (RCC_CSR) , Section 41.7.3: CTI application trigger set register (CTI_APPSETR) , and Section 41.8.2: DBGMCU configuration register (DBGMCU_CR) .

Updated Figure 14: Clock tree , Figure 147: GCM authenticated encryption , Figure 311: Transfer bus diagrams for I2C target transmitter (mandatory events only) , Figure 314: Transfer bus diagrams for I2C target receiver (mandatory events only) , and Figure 321: Transfer bus diagrams for I2C controller transmitter (mandatory events only) .

Added Section 43: Important security notice .

Updated Table 240: SPI register map and reset values .

Minor text edits across the whole document.

Added Empty check and Caution in Section 3.3.6: Flash memory program and erase operations .

Updated Section 3.3.7: Flash main memory erase sequences , Section 3.3.8: Flash main memory programming sequences , note in Section 3.6.1: Read protection (RDP) , Section 3.10.4: Flash memory status register (FLASH_SR) , Section 3.10.5: Flash memory control register (FLASH_CR) , Section 3.10.19: Flash memory secure SRAM2 start address and CPU2 reset vector register (FLASH_SRRVR) , Section 5.1: Power supplies , Force SMPS step-down converter Bypass mode , Section 5.2.2: Programmable voltage detector (PVD) , Section 6.1.2: System reset , Section 6.2.14: SMPS step-down converter clock , Converting a supply-relative ADC measurement to an absolute voltage value , Section 14.15.4: ADC configuration register 1 (ADC_CFGR1) , Section 27.4.7: TIM1 capture/compare mode register 1 (TIM1_CCMR1) , Section 28.4.7: TIM2 capture/compare mode register 1 (TIM2_CCMR1) , Section 58.5: WWDG interrupts , Section 58.6.2: WWDG configuration register (WWDG_CFR) , and Section 41.4.11: DP access port select register (DP_SELECTR) .

Updated Figure 121: Surface charge transfer analog I/O group structure , Figure 122: Sampling capacitor voltage variation , and Figure 879: Watchdog block diagram .

Updated Table 272: Debug port register map and reset values .

Minor text edits across the whole document.

Updated document title, Section 3.5: FLASH_UID64 , Section 3.10.16: Flash memory CPU2 status register (FLASH_C2SR) , Section 4.1: Introduction , Section 4.2: Main features , Section 5.1.2: Independent USB transceivers supply , Entering Stop0 mode , Section 5.4.8: Stop1 mode , Section 6.2.20: Clock-out capability , Section 23.3.4: Charge transfer acquisition sequence , Section 27.3.22: Encoder interface mode , and Section 28.3.15: Encoder interface mode .

Updated Figure 2: Memory map , Figure 298: Independent watchdog block diagram , Figure 305: I2C initialization flow , and Figure 308: Target initialization flow .

Minor text edits across the whole document.

Updated Figure 2: Memory map and Figure 301: RTC block diagram .

Updated Section 6.2.3: MSI clock , Temperature sensor , DAC output , V _REFINT and V _DDA and V _SSA LCD_VLCD1 V _BAT internal channels , Section 28.3.18: Timers and external trigger synchronization , Section 34.7.4: RTC initialization and status register (RTC_ISR) , and Section 35.9.1: I2C control register 1 (I2C_CR1) .

Added Section 35.4.15: SMBus controller mode .

Added Table 128: RNG configurations , Table 219: USART/UART input/output pins , Table 220: USART internal input/output signals , Table 229: LPUART input/output pins , and Table 230: LPUART internal input/output signals .

Minor text edits across the whole document.

Added Section 1.3: Register reset value .

Updated CPU2 secure SRAM2 areas , Exiting Standby mode , Section 14.4.6: Calibration (ADCAL) , and Section 14.4.9: ADC clock (CKMODE, PRESC[3:0], LFMEN) .

Replaced master/slave with controller/target in Section 35: Inter-integrated circuit interface (I2C) .

Updated Figure 35: ADC calibration , Figure 36: Calibration factor forcing , Figure 44: Stopping an ongoing conversion , Figure 57: ADC1_AWD_OUT signal generation (on a single channel) , Figure 336: Start bit detection when oversampling by 16 or 8 , Figure 352: Transmission using DMA , and Figure 353: Reception using DMA .

Updated Table 166: USART features and Table 219: USART/UART input/output pins .

Minor text edits across the whole document.

Table 1: Memory map and peripheral register boundary addresses updated.