RM0473-STM32WB15CC

Introduction

This document is addressed to application developers. It provides complete information on how to use the STM32WB15CC microcontroller memory and peripherals.

The STM32WB15CC multiprotocol wireless and ultra-low-power devices embed a powerful and ultra-low-power radio compliant with the Bluetooth ® Low Energy SIG specification v5.4. They contain a dedicated Arm ® Cortex ® -M0+ for performing the real-time low layer operation.

The STM32WB15CC microcontrollers feature 320 Kbytes flash memory and 48 Kbytes SRAM, and include state of the art patented technology.

Available from STMicroelectronics web site www.st.com :

For information on the Arm ® Cortex ® -M4 and Cortex ® -M0+ cores refer to the corresponding Technical Reference Manuals, available from the www.arm.com website.

For information on Bluetooth ® refer to www.bluetooth.com .

Contents

3.3.6Flash memory program and erase operations . . . . .71
3.3.7Flash main memory erase sequences . . . . .72
3.3.8Flash main memory programming sequences . . . . .74
3.4FLASH option bytes . . . . .79
3.4.1Option bytes description . . . . .79
3.4.2Option bytes programming . . . . .86
3.5FLASH UID64 . . . . .89
3.6Flash memory protection . . . . .90
3.6.1Read protection (RDP) . . . . .90
3.6.2Proprietary code readout protection (PCROP) . . . . .94
3.6.3Write protection (WRP) . . . . .95
3.6.4CPU2 security (ESE) . . . . .96
3.7FLASH program/erase suspension . . . . .97
3.8FLASH interrupts . . . . .98
3.9Register access protection . . . . .98
3.10FLASH registers . . . . .99
3.10.1Flash memory access control register (FLASH_ACR) . . . . .99
3.10.2Flash memory key register (FLASH_KEYR) . . . . .100
3.10.3Flash memory option key register (FLASH_OPTKEYR) . . . . .100
3.10.4Flash memory status register (FLASH_SR) . . . . .101
3.10.5Flash memory control register (FLASH_CR) . . . . .102
3.10.6Flash memory ECC register (FLASH_ECCR) . . . . .104
3.10.7Flash memory option register (FLASH_OPTR) . . . . .105
3.10.8Flash memory PCROP zone A start address register
(FLASH_PCROP1ASR) . . . . .		108
3.10.9Flash memory PCROP zone A end address register
(FLASH_PCROP1AER) . . . . .		108
3.10.10Flash memory WRP area A address register (FLASH_WRP1AR) . . . . .109
3.10.11Flash memory WRP area B address register (FLASH_WRP1BR) . . . . .109
3.10.12Flash memory PCROP zone B start address register
(FLASH_PCROP1BSR) . . . . .		110
3.10.13Flash memory PCROP zone B end address register
(FLASH_PCROP1BER) . . . . .		110
3.10.14Flash memory IPCC mailbox data buffer address register
(FLASH_IPCCBR) . . . . .		111
3.10.15Flash memory CPU2 access control register (FLASH_C2ACR) . . . . .111
3.10.16Flash memory CPU2 status register (FLASH_C2SR) . . . . .112
3.10.17Flash memory CPU2 control register (FLASH_C2CR) . . . . .114
6.4Low-power modes . . . . .139
6.4.1Run mode . . . . .145
6.4.2Low-power run mode (LP run) . . . . .145
6.4.3Entering Low-power mode . . . . .146
6.4.4Exiting Low-power mode . . . . .146
6.4.5Sleep mode . . . . .148
6.4.6Low-power sleep mode (LP sleep) . . . . .149
6.4.7Stop0 mode . . . . .150
6.4.8Stop1 mode . . . . .151
6.4.9Standby mode . . . . .152
6.4.10Shutdown mode . . . . .154
6.4.11Auto wake-up from Low-power mode . . . . .155
6.5Real-time radio information . . . . .156
6.6PWR registers . . . . .157
6.6.1PWR control register 1 (PWR_CR1) . . . . .157
6.6.2PWR control register 2 (PWR_CR2) . . . . .158
6.6.3PWR control register 3 (PWR_CR3) . . . . .159
6.6.4PWR control register 4 (PWR_CR4) . . . . .160
6.6.5PWR status register 1 (PWR_SR1) . . . . .161
6.6.6PWR status register 2 (PWR_SR2) . . . . .162
6.6.7PWR status clear register (PWR_SCR) . . . . .163
6.6.8PWR control register 5 (PWR_CR5) . . . . .164
6.6.9PWR Port A pull-up control register (PWR_PUCRA) . . . . .165
6.6.10PWR Port A pull-down control register (PWR_PDCRA) . . . . .165
6.6.11PWR Port B pull-up control register (PWR_PUCRB) . . . . .165
6.6.12PWR Port B pull-down control register (PWR_PDCRB) . . . . .166
6.6.13PWR Port C pull-up control register (PWR_PUCRC) . . . . .166
6.6.14PWR Port C pull-down control register (PWR_PDCRC) . . . . .167
6.6.15PWR Port E pull-up control register (PWR_PUCRE) . . . . .167
6.6.16PWR Port E pull-down control register (PWR_PDCRE) . . . . .168
6.6.17PWR Port H pull-up control register (PWR_PUCRH) . . . . .168
6.6.18PWR Port H pull-down control register (PWR_PDCRH) . . . . .169
6.6.19PWR CPU2 control register 1 (PWR_C2CR1) . . . . .169
6.6.20PWR CPU2 control register 3 (PWR_C2CR3) . . . . .170
6.6.21PWR extended status and status clear register (PWR_EXTSCR) . . . . .171
6.6.22PWR register map and reset value table . . . . .173
8.2.17Watchdog clock .....194
8.2.18True RNG clock .....195
8.2.19Clock-out capability .....195
8.2.20Peripheral clocks enable .....195
8.3Low-power modes .....197
8.4RCC registers .....199
8.4.1RCC clock control register (RCC_CR) .....199
8.4.2RCC internal clock sources calibration register (RCC_ICSCR) .....202
8.4.3RCC clock configuration register (RCC_CFGR) .....203
8.4.4RCC PLL configuration register (RCC_PLLCFGR) .....205
8.4.5RCC clock interrupt enable register (RCC_CIER) .....208
8.4.6RCC clock interrupt flag register (RCC_CIFR) .....209
8.4.7RCC clock interrupt clear register (RCC_CICR) .....211
8.4.8RCC SMPS step-down converter control register (RCC_SMPSSCR) ..212
8.4.9RCC AHB1 peripheral reset register (RCC_AHB1RSTR) .....213
8.4.10RCC AHB2 peripheral reset register (RCC_AHB2RSTR) .....214
8.4.11RCC AHB4 peripheral reset register (RCC_AHB4RSTR) .....215
8.4.12RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) .....216
8.4.13RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) .....216
8.4.14RCC APB2 peripheral reset register (RCC_APB2RSTR) .....217
8.4.15RCC APB3 peripheral reset register (RCC_APB3RSTR) .....218
8.4.16RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) .....218
8.4.17RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) .....219
8.4.18RCC AHB4 peripheral clock enable register (RCC_AHB4ENR) .....220
8.4.19RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) ..221
8.4.20RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) ..222
8.4.21RCC APB2 peripheral clock enable register (RCC_APB2ENR) .....222
8.4.22RCC AHB1 peripheral clocks enable in Sleep modes register
(RCC_AHB1SMENR) .....		223
8.4.23RCC AHB2 peripheral clocks enable in Sleep modes register
(RCC_AHB2SMENR) .....		224
8.4.24RCC AHB4 peripheral clocks enable in Sleep and Stop
modes register (RCC_AHB4SMENR) .....		225
8.4.25RCC APB1 peripheral clocks enable in Sleep mode register 1
(RCC_APB1SMENR1) .....		226
8.4.26RCC APB1 peripheral clocks enable in Sleep mode register 2
(RCC_APB1SMENR2) .....		227
8.4.27RCC APB2 peripheral clocks enable in Sleep mode register
(RCC_APB2SMENR) .....		228

8.4.28 RCC peripherals independent clock configuration register (RCC_CCIPR) . . . . . 229

8.4.29 RCC backup domain control register (RCC_BDCR) . . . . . 230

8.4.30 RCC control/status register (RCC_CSR) . . . . . 232

8.4.31 RCC clock HSE register (RCC_HSECR) . . . . . 234

8.4.32 RCC extended clock recovery register (RCC_EXTCFGR) . . . . . 235

8.4.33 RCC CPU2 AHB1 peripheral clock enable register (RCC_C2AHB1ENR) . . . . . 237

8.4.34 RCC CPU2 AHB2 peripheral clock enable register (RCC_C2AHB2ENR) . . . . . 238

8.4.35 RCC CPU2 AHB4 peripheral clock enable register (RCC_C2AHB4ENR) . . . . . 239

8.4.36 RCC CPU2 APB1 peripheral clock enable register 1 (RCC_C2APB1ENR1) . . . . . 240

8.4.37 RCC CPU2 APB1 peripheral clock enable register 2 (RCC_C2APB1ENR2) . . . . . 241

8.4.38 RCC CPU2 APB2 peripheral clock enable register (RCC_C2APB2ENR) . . . . . 241

8.4.39 RCC CPU2 APB3 peripheral clock enable register (RCC_C2APB3ENR) . . . . . 242

8.4.40 RCC CPU2 AHB1 peripheral clocks enable in Sleep modes register (RCC_C2AHB1SMENR) . . . . . 243

8.4.41 RCC CPU2 AHB2 peripheral clocks enable in Sleep modes register (RCC_C2AHB2SMENR) . . . . . 244

8.4.42 RCC CPU2 AHB4 peripheral clocks enable in Sleep mode register (RCC_C2AHB4SMENR) . . . . . 245

8.4.43 RCC CPU2 APB1 peripheral clocks enable in Sleep mode register 1 (RCC_C2APB1SMENR1) . . . . . 246

8.4.44 RCC CPU2 APB1 peripheral clocks enable in Sleep mode register 2 (RCC_C2APB1SMENR2) . . . . . 247

8.4.45 RCC CPU2 APB2 peripheral clocks enable in Sleep mode register (RCC_C2APB2SMENR) . . . . . 247

8.4.46 RCC CPU2 APB3 peripheral clock enable in Sleep mode register (RCC_C2APB3SMENR) . . . . . 248

8.4.47 RCC register map . . . . . 249

9 General-purpose I/Os (GPIO) . . . . . 255

9.1 Introduction . . . . . 255

9.2 GPIO main features . . . . . 255

9.3 GPIO functional description . . . . . 255

9.3.1 General-purpose I/O (GPIO) . . . . . 258

9.3.2I/O pin alternate function multiplexer and mapping . . . . .258
9.3.3I/O port control registers . . . . .259
9.3.4I/O port data registers . . . . .259
9.3.5I/O data bitwise handling . . . . .259
9.3.6GPIO locking mechanism . . . . .260
9.3.7I/O alternate function input/output . . . . .260
9.3.8External interrupt/wakeup lines . . . . .260
9.3.9Input configuration . . . . .260
9.3.10Output configuration . . . . .261
9.3.11Alternate function configuration . . . . .262
9.3.12Analog configuration . . . . .262
9.3.13Using the LSE oscillator pins as GPIOs . . . . .263
9.3.14Using the GPIO pins in the RTC supply domain . . . . .263
9.3.15Using PH3 as GPIO . . . . .263
9.4GPIO registers . . . . .264
9.4.1GPIO port mode register (GPIOx_MODER)
(x =A to C and E, H) . . . . .		264
9.4.2GPIO port output type register (GPIOx_OTYPER)
(x = A to C and E, H) . . . . .		264
9.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to C and E, H) . . . . .		265
9.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to C and E, H) . . . . .		266
9.4.5GPIO port input data register (GPIOx_IDR)
(x = A to C and E, H) . . . . .		266
9.4.6GPIO port output data register (GPIOx_ODR)
(x = A to C and E, H) . . . . .		267
9.4.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to C and E, H) . . . . .		267
9.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to C and E, H) . . . . .		268
9.4.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to C and E, H) . . . . .		269
9.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to C and E, H) . . . . .		270
9.4.11GPIO port bit reset register (GPIOx_BRR) (x = A to C and E, H) . . . . .271
9.4.12GPIO register map . . . . .272
10System configuration controller (SYSCFG) . . . . .276
10.1SYSCFG main features . . . . .276
10.2SYSCFG registers . . . . .276
10.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .276
10.2.2SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .277
10.2.3SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		278
10.2.4SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . .		279
10.2.5SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . .		280
10.2.6SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . .		282
10.2.7SYSCFG SRAM2 control and status register (SYSCFG_SCSR) . . . . .283
10.2.8SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .284
10.2.9SYSCFG SRAM2 write protection register (SYSCFG_SWPR1) . . . . .285
10.2.10SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . .285
10.2.11SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2) . . . . .285
10.2.12SYSCFG CPU1 interrupt mask register 1 (SYSCFG_IMR1) . . . . .286
10.2.13SYSCFG CPU1 interrupt mask register 2 (SYSCFG_IMR2) . . . . .286
10.2.14SYSCFG CPU2 interrupt mask register 1 (SYSCFG_C2IMR1) . . . . .287
10.2.15SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2) . . . . .288
10.2.16SYSCFG secure IP control register (SYSCFG_SIPCR) . . . . .288
10.2.17SYSCFG register map . . . . .290
11Direct memory access controller (DMA) . . . . .292
11.1Introduction . . . . .292
11.2DMA main features . . . . .292
11.3DMA implementation . . . . .293
11.3.1DMA1 . . . . .293
11.3.2DMA request mapping . . . . .293
11.4DMA functional description . . . . .293
11.4.1DMA block diagram . . . . .293
11.4.2DMA pins and internal signals . . . . .294
11.4.3DMA transfers . . . . .294
11.4.4DMA arbitration . . . . .295
11.4.5DMA channels . . . . .295
11.4.6DMA data width, alignment, and endianness . . . . .299
11.4.7DMA error management . . . . .300
11.5DMA interrupts . . . . .301
11.6DMA registers . . . . .301
11.6.1DMA interrupt status register (DMA_ISR) . . . . .301
11.6.2DMA interrupt flag clear register (DMA_IFCR) . . . . .303
11.6.3DMA channel x configuration register (DMA_CCRx) . . . . .305
11.6.4DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .307
11.6.5DMA channel x peripheral address register (DMA_CPARx) . . . . .308
11.6.6DMA channel x memory address register (DMA_CMARx) . . . . .309
11.6.7DMA register map . . . . .309
12DMA request multiplexer (DMAMUX) . . . . .312
12.1Introduction . . . . .312
12.2DMAMUX main features . . . . .313
12.3DMAMUX implementation . . . . .313
12.3.1DMAMUX instantiation . . . . .313
12.3.2DMAMUX mapping . . . . .313
12.4DMAMUX functional description . . . . .316
12.4.1DMAMUX block diagram . . . . .316
12.4.2DMAMUX signals . . . . .317
12.4.3DMAMUX channels . . . . .317
12.4.4DMAMUX request line multiplexer . . . . .317
12.4.5DMAMUX request generator . . . . .320
12.5DMAMUX interrupts . . . . .321
12.6DMAMUX registers . . . . .322
12.6.1DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR) . . . . .		322
12.6.2DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) . . . . .		323
12.6.3DMAMUX request line multiplexer interrupt clear flag register
(DMAMUX_CFR) . . . . .		323
12.6.4DMAMUX request generator channel x configuration register
(DMAMUX_RGxCR) . . . . .		324
12.6.5DMAMUX request generator interrupt status register
(DMAMUX_RGS) . . . . .		325
12.6.6DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR) . . . . .		325
12.6.7DMAMUX register map . . . . .326
13Nested vectored interrupt controller (NVIC) . . . . .329
13.1NVIC main features . . . . .329
13.2Interrupt block diagram . . . . .329
13.3Interrupt and exception vectors . . . . .330
13.4Interrupt list . . . . .335
14Extended interrupt and event controller (EXTI) . . . . .338
14.1EXTI main features . . . . .338
14.2EXTI block diagram . . . . .338
14.2.1EXTI connections between peripherals and CPU . . . . .340
14.3EXTI functional description . . . . .341
14.3.1EXTI configurable event input wakeup . . . . .341
14.3.2EXTI direct event input wakeup . . . . .343
14.4EXTI functional behavior . . . . .343
14.5EXTI registers . . . . .345
14.5.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .345
14.5.2EXTI falling trigger selection register (EXTI_FTSR1) . . . . .346
14.5.3EXTI software interrupt event register (EXTI_SWIER1) . . . . .346
14.5.4EXTI pending register (EXTI_PR1) . . . . .347
14.5.5EXTI rising trigger selection register (EXTI_RTSR2) . . . . .347
14.5.6EXTI falling trigger selection register (EXTI_FTSR2) . . . . .348
14.5.7EXTI software interrupt event register (EXTI_SWIER2) . . . . .348
14.5.8EXTI pending register (EXTI_PR2) . . . . .349
14.5.9EXTI CPU wakeup with interrupt mask register (EXTI_IMR1) . . . . .350
14.5.10EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR1) . . . . .350
14.5.11EXTI CPU wakeup with event mask register (EXTI_EMR1) . . . . .351
14.5.12EXTI CPU2 wakeup with event mask register (EXTI_C2EMR1) . . . . .351
14.5.13EXTI CPU wakeup with interrupt mask register (EXTI_IMR2) . . . . .352
14.5.14EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR2) . . . . .352
14.5.15EXTI CPU wakeup with event mask register (EXTI_EMR2) . . . . .353
14.5.16EXTI CPU2 wakeup with event mask register (EXTI_C2EMR2) . . . . .353
14.5.17EXTI register map . . . . .354
15Analog-to-digital converter (ADC) . . . . .356
15.1Introduction . . . . .356
15.2ADC main features . . . . .357
15.3ADC functional description . . . . .358
15.3.1ADC pins and internal signals . . . . .358
15.3.2ADC voltage regulator (ADVREGEN) . . . . .359
15.3.3Calibration (ADCAL) . . . . .360
15.3.4ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .362
15.3.5ADC clock (CKMODE, PRESC[3:0]) . . . . .363
15.3.6ADC connectivity . . . . .365
15.3.7Configuring the ADC . . . . .366
15.3.8Channel selection (CHSEL, SCANDIR, CHSELRMOD) . . . . .366
15.3.9Programmable sampling time (SMPx[2:0]) . . . . .367
15.3.10Single conversion mode (CONT = 0) . . . . .368
15.3.11Continuous conversion mode (CONT = 1) . . . . .368
15.3.12Starting conversions (ADSTART) . . . . .369
15.3.13Timings . . . . .370
15.3.14Stopping an ongoing conversion (ADSTP) . . . . .371
15.4Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . . . . .371
15.4.1Discontinuous mode (DISCEN) . . . . .372
15.4.2Programmable resolution (RES) - Fast conversion mode . . . . .372
15.4.3End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . .373
15.4.4End of conversion sequence (EOS flag) . . . . .373
15.4.5Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . .		374
15.4.6Low frequency trigger mode . . . . .376
15.5Data management . . . . .376
15.5.1Data register and data alignment (ADC_DR, ALIGN) . . . . .376
15.5.2ADC overrun (OVR, OVRMOD) . . . . .376
15.5.3Managing a sequence of data converted without using the DMA . . . . .378
15.5.4Managing converted data without using the DMA without overrun . . . . .378
15.5.5Managing converted data using the DMA . . . . .378
15.6Low-power features . . . . .379
15.6.1Wait mode conversion . . . . .379
15.6.2Auto-off mode (AUTOFF) . . . . .380
15.7Analog window watchdog . . . . .382
15.7.1Description of the analog watchdog . . . . .382
15.7.2ADC_AWD1_OUT output signal generation . . . . .383
15.7.3Analog watchdog threshold control . . . . .385
15.8Temperature sensor and internal reference voltage . . . . .385
15.9Battery voltage monitoring . . . . .388
15.10ADC interrupts . . . . .389
15.11ADC registers . . . . .390
15.11.1ADC interrupt and status register (ADC_ISR) . . . . .390
15.11.2ADC interrupt enable register (ADC_IER) . . . . .391
15.11.3ADC control register (ADC_CR) . . . . .392
15.11.4ADC configuration register 1 (ADC_CFGR1) . . . . .394
15.11.5ADC configuration register 2 (ADC_CFGR2) . . . . .397
15.11.6ADC sampling time register (ADC_SMPR) . . . . .398
15.11.7ADC watchdog threshold register (ADC_TR) . . . . .399
15.11.8ADC channel selection register (ADC_CHSELR) . . . . .400
15.11.9ADC channel selection register [alternate] (ADC_CHSELR) . . . . .400
15.11.10ADC data register (ADC_DR) . . . . .402
15.11.11ADC calibration factor (ADC_CALFACT) . . . . .403
15.11.12ADC common configuration register (ADC_CCR) . . . . .403
15.12ADC register map . . . . .404
16Comparator (COMP) . . . . .407
16.1COMP introduction . . . . .407
16.2COMP main features . . . . .407
16.3COMP functional description . . . . .408
16.3.1COMP block diagram . . . . .408
16.3.2COMP pins and internal signals . . . . .408
16.3.3COMP reset and clocks . . . . .409
16.3.4Comparator LOCK mechanism . . . . .409
16.3.5Window comparator . . . . .409
16.3.6Hysteresis . . . . .410
16.3.7Comparator output blanking function . . . . .411
16.3.8COMP power and speed modes . . . . .411
16.4COMP low-power modes . . . . .412
16.5COMP interrupts . . . . .412
16.6COMP registers . . . . .413
16.6.1Comparator 1 control and status register (COMP1_CSR) . . . . .413
16.6.2COMP register map . . . . .416
17Touch sensing controller (TSC) . . . . .417
17.1TSC introduction . . . . .417
17.2TSC main features . . . . .417
17.3TSC functional description . . . . .417
17.3.1TSC block diagram . . . . .417
17.3.2Surface charge transfer acquisition overview . . . . .418
17.3.3Reset and clocks . . . . .421
17.3.4Charge transfer acquisition sequence . . . . .421
17.3.5Spread spectrum feature . . . . .422
17.3.6Max count error . . . . .423
17.3.7Sampling capacitor I/O and channel I/O mode selection . . . . .423
17.3.8Acquisition mode . . . . .424
17.3.9I/O hysteresis and analog switch control . . . . .424
17.4TSC low-power modes . . . . .425
17.5TSC interrupts . . . . .425
17.6TSC registers . . . . .425
17.6.1TSC control register (TSC_CR) . . . . .425
17.6.2TSC interrupt enable register (TSC_IER) . . . . .428
17.6.3TSC interrupt clear register (TSC_ICR) . . . . .428
17.6.4TSC interrupt status register (TSC_ISR) . . . . .429
17.6.5TSC I/O hysteresis control register (TSC_IOHCR) . . . . .429
17.6.6TSC I/O analog switch control register
(TSC_IOASCR) . . . . .		430
17.6.7TSC I/O sampling control register (TSC_IOSCR) . . . . .430
17.6.8TSC I/O channel control register (TSC_IOCCR) . . . . .431
17.6.9TSC I/O group control status register (TSC_IOGCSR) . . . . .431
17.6.10TSC I/O group x counter register (TSC_IOGxCR) . . . . .432
17.6.11TSC register map . . . . .432
18True random number generator (RNG) . . . . .435
18.1RNG introduction . . . . .435
18.2RNG main features . . . . .435
18.3RNG functional description . . . . .436
18.3.1RNG block diagram . . . . .436
18.3.2RNG internal signals . . . . .436
18.3.3Random number generation . . . . .437
18.3.4RNG initialization . . . . .439
18.3.5RNG operation . . . . .440
18.3.6RNG clocking . . . . .441
19.6AES processing latency . . . . .483
19.7AES registers . . . . .484
19.7.1AES control register (AES_CR) . . . . .484
19.7.2AES status register (AES_SR) . . . . .487
19.7.3AES data input register (AES_DINR) . . . . .488
19.7.4AES data output register (AES_DOUTR) . . . . .488
19.7.5AES key register 0 (AES_KEYR0) . . . . .489
19.7.6AES key register 1 (AES_KEYR1) . . . . .490
19.7.7AES key register 2 (AES_KEYR2) . . . . .490
19.7.8AES key register 3 (AES_KEYR3) . . . . .490
19.7.9AES initialization vector register 0 (AES_IVR0) . . . . .491
19.7.10AES initialization vector register 1 (AES_IVR1) . . . . .491
19.7.11AES initialization vector register 2 (AES_IVR2) . . . . .491
19.7.12AES initialization vector register 3 (AES_IVR3) . . . . .492
19.7.13AES key register 4 (AES_KEYR4) . . . . .492
19.7.14AES key register 5 (AES_KEYR5) . . . . .492
19.7.15AES key register 6 (AES_KEYR6) . . . . .493
19.7.16AES key register 7 (AES_KEYR7) . . . . .493
19.7.17AES suspend registers (AES_SUSPxR) . . . . .493
19.7.18AES register map . . . . .494
20Public key accelerator (PKA) . . . . .496
20.1Introduction . . . . .496
20.2PKA main features . . . . .496
20.3PKA functional description . . . . .496
20.3.1PKA block diagram . . . . .496
20.3.2PKA internal signals . . . . .497
20.3.3PKA reset and clocks . . . . .497
20.3.4PKA public key acceleration . . . . .497
20.3.5Typical applications for PKA . . . . .499
20.3.6PKA procedure to perform an operation . . . . .501
20.3.7PKA error management . . . . .502
20.4PKA operating modes . . . . .502
20.4.1Introduction . . . . .502
20.4.2Montgomery parameter computation . . . . .503
20.4.3Modular addition . . . . .504
20.4.4Modular subtraction . . . . .504
20.4.5Modular and Montgomery multiplication . . . . .504
20.4.6Modular exponentiation . . . . .505
20.4.7Modular inversion . . . . .506
20.4.8Modular reduction . . . . .507
20.4.9Arithmetic addition . . . . .507
20.4.10Arithmetic subtraction . . . . .507
20.4.11Arithmetic multiplication . . . . .508
20.4.12Arithmetic comparison . . . . .508
20.4.13RSA CRT exponentiation . . . . .508
20.4.14Point on elliptic curve Fp check . . . . .509
20.4.15ECC Fp scalar multiplication . . . . .510
20.4.16ECDSA sign . . . . .511
20.4.17ECDSA verification . . . . .513
20.5Example of configurations and processing times . . . . .514
20.5.1Supported elliptic curves . . . . .514
20.5.2Computation times . . . . .516
20.6PKA interrupts . . . . .517
20.7PKA registers . . . . .518
20.7.1PKA control register (PKA_CR) . . . . .518
20.7.2PKA status register (PKA_SR) . . . . .519
20.7.3PKA clear flag register (PKA_CLRFR) . . . . .520
20.7.4PKA RAM . . . . .520
20.7.5PKA register map . . . . .521
21Advanced-control timer (TIM1) . . . . .522
21.1TIM1 introduction . . . . .522
21.2TIM1 main features . . . . .523
21.3TIM1 functional description . . . . .525
21.3.1Time-base unit . . . . .525
21.3.2Counter modes . . . . .527
21.3.3Repetition counter . . . . .538
21.3.4External trigger input . . . . .540
21.3.5Clock selection . . . . .541
21.3.6Capture/compare channels . . . . .545
21.3.7Input capture mode . . . . .547
21.3.8PWM input mode . . . . .548
21.3.9Forced output mode . . . . .549
21.3.10Output compare mode . . . . .550
21.3.11PWM mode . . . . .551
21.3.12Asymmetric PWM mode . . . . .554
21.3.13Combined PWM mode . . . . .555
21.3.14Combined 3-phase PWM mode . . . . .556
21.3.15Complementary outputs and dead-time insertion . . . . .557
21.3.16Using the break function . . . . .559
21.3.17Bidirectional break inputs . . . . .565
21.3.18Clearing the OCxREF signal on an external event . . . . .567
21.3.196-step PWM generation . . . . .568
21.3.20One-pulse mode . . . . .569
21.3.21Retriggerable one pulse mode . . . . .570
21.3.22Encoder interface mode . . . . .571
21.3.23UIF bit remapping . . . . .573
21.3.24Timer input XOR function . . . . .574
21.3.25Interfacing with Hall sensors . . . . .574
21.3.26Timer synchronization . . . . .577
21.3.27ADC synchronization . . . . .581
21.3.28DMA burst mode . . . . .581
21.3.29Debug mode . . . . .582
21.4TIM1 registers . . . . .583
21.4.1TIM1 control register 1 (TIM1_CR1) . . . . .583
21.4.2TIM1 control register 2 (TIM1_CR2) . . . . .584
21.4.3TIM1 slave mode control register
(TIM1_SMCR) . . . . .		587
21.4.4TIM1 DMA/interrupt enable register
(TIM1_DIER) . . . . .		589
21.4.5TIM1 status register (TIM1_SR) . . . . .591
21.4.6TIM1 event generation register (TIM1_EGR) . . . . .593
21.4.7TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . .594
21.4.8TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . .		595
21.4.9TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . .598
21.4.10TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . .		599

21.4.11 TIM1 capture/compare enable register (TIM1_CCER) . . . . . 600

21.4.12 TIM1 counter (TIM1_CNT) . . . . . 604

21.4.13 TIM1 prescaler (TIM1_PSC) . . . . . 604

21.4.14 TIM1 auto-reload register (TIM1_ARR) . . . . . 604

21.4.15 TIM1 repetition counter register (TIM1_RCR) . . . . . 605

21.4.16 TIM1 capture/compare register 1 (TIM1_CCR1) . . . . . 605

21.4.17 TIM1 capture/compare register 2 (TIM1_CCR2) . . . . . 606

21.4.18 TIM1 capture/compare register 3 (TIM1_CCR3) . . . . . 606

21.4.19 TIM1 capture/compare register 4 (TIM1_CCR4) . . . . . 607

21.4.20 TIM1 break and dead-time register (TIM1_BDTR) . . . . . 607

21.4.21 TIM1 DMA control register (TIM1_DCR) . . . . . 611

21.4.22 TIM1 DMA address for full transfer (TIM1_DMAR) . . . . . 612

21.4.23 TIM1 option register 1 (TIM1_OR1) . . . . . 613

21.4.24 TIM1 capture/compare mode register 3 (TIM1_CCMR3) . . . . . 613

21.4.25 TIM1 capture/compare register 5 (TIM1_CCR5) . . . . . 614

21.4.26 TIM1 capture/compare register 6 (TIM1_CCR6) . . . . . 615

21.4.27 TIM1 alternate function option register 1 (TIM1_AF1) . . . . . 616

21.4.28 TIM1 Alternate function register 2 (TIM1_AF2) . . . . . 617

21.4.29 TIM1 timer input selection register (TIM1_TISEL) . . . . . 618

21.4.30 TIM1 register map . . . . . 619

22 General-purpose timer (TIM2) . . . . . 622

22.1 TIM2 introduction . . . . . 622

22.2 TIM2 main features . . . . . 622

22.3 TIM2 functional description . . . . . 624

22.3.1 Time-base unit . . . . . 624

22.3.2 Counter modes . . . . . 626

22.3.3 Clock selection . . . . . 636

22.3.4 Capture/Compare channels . . . . . 640

22.3.5Input capture mode . . . . .642
22.3.6PWM input mode . . . . .643
22.3.7Forced output mode . . . . .644
22.3.8Output compare mode . . . . .644
22.3.9PWM mode . . . . .645
22.3.10Asymmetric PWM mode . . . . .649
22.3.11Combined PWM mode . . . . .649
22.3.12Clearing the OCxREF signal on an external event . . . . .650
22.3.13One-pulse mode . . . . .652
22.3.14Retriggerable one pulse mode . . . . .653
22.3.15Encoder interface mode . . . . .654
22.3.16UIF bit remapping . . . . .656
22.3.17Timer input XOR function . . . . .656
22.3.18Timers and external trigger synchronization . . . . .657
22.3.19Timer synchronization . . . . .660
22.3.20DMA burst mode . . . . .665
22.3.21Debug mode . . . . .666
22.4TIM2 registers . . . . .667
22.4.1TIM2 control register 1 (TIM2_CR1) . . . . .667
22.4.2TIM2 control register 2 (TIM2_CR2) . . . . .668
22.4.3TIM2 slave mode control register (TIM2_SMCR) . . . . .670
22.4.4TIM2 DMA/Interrupt enable register (TIM2_DIER) . . . . .673
22.4.5TIM2 status register (TIM2_SR) . . . . .674
22.4.6TIM2 event generation register (TIM2_EGR) . . . . .676
22.4.7TIM2 capture/compare mode register 1 (TIM2_CCMR1) . . . . .677
22.4.8TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) . . . . .678
22.4.9TIM2 capture/compare mode register 2 (TIM2_CCMR2) . . . . .681
22.4.10TIM2 capture/compare mode register 2 [alternate] (TIM2_CCMR2) . . . . .682
22.4.11TIM2 capture/compare enable register
(TIM2_CCER) . . . . .		683
22.4.12TIM2 counter (TIM2_CNT) . . . . .684
22.4.13TIM2 counter [alternate] (TIM2_CNT) . . . . .685
22.4.14TIM2 prescaler (TIM2_PSC) . . . . .685
22.4.15TIM2 auto-reload register (TIM2_ARR) . . . . .685
22.4.16TIM2 capture/compare register 1 (TIM2_CCR1) . . . . .686
22.4.17TIM2 capture/compare register 2 (TIM2_CCR2) . . . . .686
22.4.18TIM2 capture/compare register 3 (TIM2_CCR3) . . . . .687

23 Low-power timer (LPTIM) . . . . . 694

23.7.6LPTIM compare register (LPTIM_CMP) . . . . .714
23.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .714
23.7.8LPTIM counter register (LPTIM_CNT) . . . . .715
23.7.9LPTIM1 option register (LPTIM1_OR) . . . . .715
23.7.10LPTIM2 option register (LPTIM2_OR) . . . . .716
23.7.11LPTIM register map . . . . .717
24Real-time clock (RTC) . . . . .718
24.1Introduction . . . . .718
24.2RTC main features . . . . .719
24.3RTC functional description . . . . .720
24.3.1RTC block diagram . . . . .720
24.3.2Clock and prescalers . . . . .721
24.3.3Real-time clock and calendar . . . . .721
24.3.4Programmable alarms . . . . .722
24.3.5Periodic auto-wake-up . . . . .722
24.3.6RTC initialization and configuration . . . . .723
24.3.7Reading the calendar . . . . .724
24.3.8Resetting the RTC . . . . .725
24.3.9RTC synchronization . . . . .726
24.3.10RTC reference clock detection . . . . .726
24.3.11RTC smooth digital calibration . . . . .727
24.3.12Time-stamp function . . . . .729
24.3.13Tamper detection . . . . .730
24.3.14Calibration clock output . . . . .732
24.3.15Alarm output . . . . .732
24.4RTC low-power modes . . . . .733
24.5RTC interrupts . . . . .733
24.6RTC registers . . . . .734
24.6.1RTC time register (RTC_TR) . . . . .734
24.6.2RTC date register (RTC_DR) . . . . .735
24.6.3RTC control register (RTC_CR) . . . . .736
24.6.4RTC initialization and status register (RTC_ISR) . . . . .739
24.6.5RTC prescaler register (RTC_PRER) . . . . .742
24.6.6RTC wake-up timer register (RTC_WUTR) . . . . .743
24.6.7RTC alarm A register (RTC_ALRMAR) . . . . .744
24.6.8RTC alarm B register (RTC_ALRMBR) . . . . .745
24.6.9RTC write protection register (RTC_WPR) . . . . .746
24.6.10RTC sub second register (RTC_SSR) . . . . .746
24.6.11RTC shift control register (RTC_SHIFTR) . . . . .747
24.6.12RTC timestamp time register (RTC_TSTR) . . . . .748
24.6.13RTC timestamp date register (RTC_TSDR) . . . . .749
24.6.14RTC time-stamp sub second register (RTC_TSSSR) . . . . .750
24.6.15RTC calibration register (RTC_CALR) . . . . .751
24.6.16RTC tamper configuration register (RTC_TAMPCR) . . . . .752
24.6.17RTC alarm A sub second register (RTC_ALRMASSR) . . . . .754
24.6.18RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .755
24.6.19RTC option register (RTC_OR) . . . . .756
24.6.20RTC backup registers (RTC_BKPxR) . . . . .756
24.6.21RTC register map . . . . .757
25Independent watchdog (IWDG) . . . . .759
25.1Introduction . . . . .759
25.2IWDG main features . . . . .759
25.3IWDG functional description . . . . .759
25.3.1IWDG block diagram . . . . .759
25.3.2Window option . . . . .760
25.3.3Hardware watchdog . . . . .761
25.3.4Low-power freeze . . . . .761
25.3.5Register access protection . . . . .761
25.3.6Debug mode . . . . .761
25.4IWDG registers . . . . .762
25.4.1IWDG key register (IWDG_KR) . . . . .762
25.4.2IWDG prescaler register (IWDG_PR) . . . . .763
25.4.3IWDG reload register (IWDG_RLR) . . . . .764
25.4.4IWDG status register (IWDG_SR) . . . . .765
25.4.5IWDG window register (IWDG_WINR) . . . . .766
25.4.6IWDG register map . . . . .767
26System window watchdog (WWDG) . . . . .768
26.1WWDG introduction . . . . .768
26.2WWDG main features . . . . .768
26.3WWDG functional description . . . . .768
26.3.1WWDG block diagram . . . . .769
26.3.2WWDG internal signals . . . . .769
26.3.3Enabling the watchdog . . . . .769
26.3.4Controlling the down-counter . . . . .769
26.3.5How to program the watchdog timeout . . . . .770
26.3.6Debug mode . . . . .771
26.4WWDG interrupts . . . . .771
26.5WWDG registers . . . . .771
26.5.1WWDG control register (WWDG_CR) . . . . .772
26.5.2WWDG configuration register (WWDG_CFR) . . . . .772
26.5.3WWDG status register (WWDG_SR) . . . . .773
26.5.4WWDG register map . . . . .773
27Inter-integrated circuit interface (I2C) . . . . .774
27.1I2C introduction . . . . .774
27.2I2C main features . . . . .774
27.3I2C implementation . . . . .775
27.4I2C functional description . . . . .775
27.4.1I2C block diagram . . . . .776
27.4.2I2C pins and internal signals . . . . .776
27.4.3I2C clock requirements . . . . .777
27.4.4I2C mode selection . . . . .777
27.4.5I2C initialization . . . . .778
27.4.6I2C reset . . . . .782
27.4.7I2C data transfer . . . . .783
27.4.8I2C target mode . . . . .785
27.4.9I2C controller mode . . . . .794
27.4.10I2C_TIMINGR register configuration examples . . . . .805
27.4.11SMBus specific features . . . . .807
27.4.12SMBus initialization . . . . .809
27.4.13SMBus I2C_TIMEOUTR register configuration examples . . . . .811
27.4.14SMBus target mode . . . . .812
27.4.15SMBus controller mode . . . . .815
27.4.16Wake-up from Stop mode on address match . . . . .818
27.4.17Error conditions . . . . .819

27.5 I2C in low-power modes . . . . . 821

27.6 I2C interrupts . . . . . 821

27.7 I2C DMA requests . . . . . 822

27.7.1 Transmission using DMA . . . . . 822

27.7.2 Reception using DMA . . . . . 822

27.8 I2C debug modes . . . . . 822

27.9 I2C registers . . . . . 823

27.9.1 I2C control register 1 (I2C_CR1) . . . . . 823

27.9.2 I2C control register 2 (I2C_CR2) . . . . . 825

27.9.3 I2C own address 1 register (I2C_OAR1) . . . . . 827

27.9.4 I2C own address 2 register (I2C_OAR2) . . . . . 828

27.9.5 I2C timing register (I2C_TIMINGR) . . . . . 829

27.9.6 I2C timeout register (I2C_TIMEOUTR) . . . . . 830

27.9.7 I2C interrupt and status register (I2C_ISR) . . . . . 831

27.9.8 I2C interrupt clear register (I2C_ICR) . . . . . 833

27.9.9 I2C PEC register (I2C_PECR) . . . . . 834

27.9.10 I2C receive data register (I2C_RXDR) . . . . . 834

27.9.11 I2C transmit data register (I2C_TXDR) . . . . . 835

27.9.12 I2C register map . . . . . 836

28 Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . . 837

28.1 USART introduction . . . . . 837

28.2 USART main features . . . . . 838

28.3 USART extended features . . . . . 839

28.4 USART implementation . . . . . 839

28.5 USART functional description . . . . . 840

28.5.1 USART block diagram . . . . . 840

28.5.2 USART signals . . . . . 841

28.5.3 USART character description . . . . . 842

28.5.4 USART FIFOs and thresholds . . . . . 844

28.5.5 USART transmitter . . . . . 844

28.5.6 USART receiver . . . . . 848

28.5.7 USART baud rate generation . . . . . 855

28.5.8 Tolerance of the USART receiver to clock deviation . . . . . 856

28.5.9 USART auto baud rate detection . . . . . 858

28.5.10USART multiprocessor communication . . . . .860
28.5.11USART Modbus communication . . . . .862
28.5.12USART parity control . . . . .863
28.5.13USART LIN (local interconnection network) mode . . . . .864
28.5.14USART synchronous mode . . . . .866
28.5.15USART single-wire half-duplex communication . . . . .870
28.5.16USART receiver timeout . . . . .870
28.5.17USART smartcard mode . . . . .871
28.5.18USART IrDA SIR ENDEC block . . . . .875
28.5.19Continuous communication using USART and DMA . . . . .878
28.5.20RS232 hardware flow control and RS485 Driver Enable . . . . .880
28.5.21USART low-power management . . . . .883
28.6USART in low-power modes . . . . .886
28.7USART interrupts . . . . .887
28.8USART registers . . . . .888
28.8.1USART control register 1 (USART_CR1) . . . . .888
28.8.2USART control register 1 [alternate] (USART_CR1) . . . . .891
28.8.3USART control register 2 (USART_CR2) . . . . .895
28.8.4USART control register 3 (USART_CR3) . . . . .899
28.8.5USART baud rate register (USART_BRR) . . . . .903
28.8.6USART guard time and prescaler register (USART_GTPR) . . . . .903
28.8.7USART receiver timeout register (USART_RTOR) . . . . .904
28.8.8USART request register (USART_RQR) . . . . .905
28.8.9USART interrupt and status register (USART_ISR) . . . . .906
28.8.10USART interrupt and status register [alternate] (USART_ISR) . . . . .912
28.8.11USART interrupt flag clear register (USART_ICR) . . . . .917
28.8.12USART receive data register (USART_RDR) . . . . .919
28.8.13USART transmit data register (USART_TDR) . . . . .919
28.8.14USART prescaler register (USART_PRESC) . . . . .920
28.8.15USART register map . . . . .921
29Low-power universal asynchronous receiver transmitter (LPUART) . . . . .923
29.1LPUART introduction . . . . .923
29.2LPUART main features . . . . .924
29.3LPUART implementation . . . . .925
29.4LPUART functional description . . . . .926
29.4.1LPUART block diagram . . . . .926
29.4.2LPUART signals . . . . .927
29.4.3LPUART character description . . . . .928
29.4.4LPUART FIFOs and thresholds . . . . .929
29.4.5LPUART transmitter . . . . .930
29.4.6LPUART receiver . . . . .933
29.4.7LPUART baud rate generation . . . . .937
29.4.8Tolerance of the LPUART receiver to clock deviation . . . . .938
29.4.9LPUART multiprocessor communication . . . . .939
29.4.10LPUART parity control . . . . .941
29.4.11LPUART single-wire half-duplex communication . . . . .942
29.4.12Continuous communication using DMA and LPUART . . . . .942
29.4.13RS232 hardware flow control and RS485 Driver Enable . . . . .945
29.4.14LPUART low-power management . . . . .947
29.5LPUART in low-power modes . . . . .950
29.6LPUART interrupts . . . . .951
29.7LPUART registers . . . . .952
29.7.1LPUART control register 1 (LPUART_CR1) . . . . .952
29.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .955
29.7.3LPUART control register 2 (LPUART_CR2) . . . . .958
29.7.4LPUART control register 3 (LPUART_CR3) . . . . .960
29.7.5LPUART baud rate register (LPUART_BRR) . . . . .963
29.7.6LPUART request register (LPUART_RQR) . . . . .963
29.7.7LPUART interrupt and status register (LPUART_ISR) . . . . .964
29.7.8LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .968
29.7.9LPUART interrupt flag clear register (LPUART_ICR) . . . . .971
29.7.10LPUART receive data register (LPUART_RDR) . . . . .972
29.7.11LPUART transmit data register (LPUART_TDR) . . . . .972
29.7.12LPUART prescaler register (LPUART_PRESC) . . . . .973
29.7.13LPUART register map . . . . .974
30Serial peripheral interface (SPI) . . . . .976
30.1Introduction . . . . .976
30.2SPI main features . . . . .976
30.3SPI implementation . . . . .977
30.4SPI functional description . . . . .977
30.4.1General description . . . . .977
30.4.2Communications between one master and one slave . . . . .978
30.4.3Standard multislave communication . . . . .980
30.4.4Multimaster communication . . . . .981
30.4.5Slave select (NSS) pin management . . . . .982
30.4.6Communication formats . . . . .983
30.4.7Configuration of SPI . . . . .985
30.4.8Procedure for enabling SPI . . . . .986
30.4.9Data transmission and reception procedures . . . . .986
30.4.10SPI status flags . . . . .996
30.4.11SPI error flags . . . . .997
30.4.12NSS pulse mode . . . . .998
30.4.13TI mode . . . . .998
30.4.14CRC calculation . . . . .999
30.5SPI interrupts . . . . .1001
30.6SPI registers . . . . .1002
30.6.1SPI control register 1 (SPIx_CR1) . . . . .1002
30.6.2SPI control register 2 (SPIx_CR2) . . . . .1004
30.6.3SPI status register (SPIx_SR) . . . . .1006
30.6.4SPI data register (SPIx_DR) . . . . .1007
30.6.5SPI CRC polynomial register (SPIx_CRCPR) . . . . .1008
30.6.6SPI Rx CRC register (SPIx_RXCRCR) . . . . .1008
30.6.7SPI Tx CRC register (SPIx_TXCRCR) . . . . .1008
30.6.8SPI register map . . . . .1010
31Inter-processor communication controller (IPCC) . . . . .1011
31.1Introduction . . . . .1011
31.2IPCC main features . . . . .1011
31.3IPCC functional description . . . . .1011
31.3.1IPCC block diagram . . . . .1012
31.3.2IPCC Simplex channel mode . . . . .1012
31.3.3IPCC Half-duplex channel mode . . . . .1015
31.3.4IPCC interrupts . . . . .1018
31.4IPCC registers . . . . .1019
31.4.1IPCC processor 1 control register (IPCC_C1CR) . . . . .1019
31.4.2IPCC processor 1 mask register (IPCC_C1MR) . . . . .1019
31.4.3IPCC processor 1 status set clear register (IPCC_C1SCR) . . . . .1020
31.4.4IPCC processor 1 to processor 2 status register
(IPCC_C1TOC2SR) . . . . .		1020
31.4.5IPCC processor 2 control register (IPCC_C2CR) . . . . .1021
31.4.6IPCC processor 2 mask register (IPCC_C2MR) . . . . .1021
31.4.7IPCC processor 2 status set clear register (IPCC_C2SCR) . . . . .1022
31.4.8IPCC processor 2 to processor 1 status register
(IPCC_C2TOC1SR) . . . . .		1023
31.4.9IPCC register map . . . . .1024
32Hardware semaphore (HSEM) . . . . .1025
32.1HSEM introduction . . . . .1025
32.2HSEM main features . . . . .1025
32.3Functional description . . . . .1026
32.3.1HSEM block diagram . . . . .1026
32.3.2HSEM internal signals . . . . .1026
32.3.3HSEM lock procedures . . . . .1026
32.3.4HSEM write/read/read lock register address . . . . .1028
32.3.5HSEM unlock procedures . . . . .1028
32.3.6HSEM COREID semaphore clear . . . . .1029
32.3.7HSEM interrupts . . . . .1029
32.3.8AHB bus master ID verification . . . . .1031
32.4HSEM registers . . . . .1032
32.4.1HSEM register semaphore x (HSEM_Rx) . . . . .1032
32.4.2HSEM read lock register semaphore x (HSEM_RLRx) . . . . .1033
32.4.3HSEM interrupt enable register (HSEM_CnIER) . . . . .1034
32.4.4HSEM interrupt clear register (HSEM_CnICR) . . . . .1034
32.4.5HSEM interrupt status register (HSEM_CnISR) . . . . .1034
32.4.6HSEM interrupt status register (HSEM_CnMISR) . . . . .1035
32.4.7HSEM clear register (HSEM_CR) . . . . .1035
32.4.8HSEM clear semaphore key register (HSEM_KEYR) . . . . .1036
32.4.9HSEM register map . . . . .1037
33Debug support (DBG) . . . . .1039
33.1Introduction . . . . .1039
33.2Debug use cases . . . . .1039
33.3DBG functional description . . . . .1041
33.3.1DBG block diagram . . . . .1041
33.3.2DBG pins and internal signals . . . . .1041
33.3.3DBG power domains . . . . .1042
33.3.4DBG clocks . . . . .1042
33.3.5Debug and low power modes . . . . .1043
33.3.6DBG reset . . . . .1043
33.4Serial wire and JTAG debug port (SWJ-DP) . . . . .1043
33.4.1JTAG debug port . . . . .1043
33.4.2SW debug port . . . . .1046
33.4.3Debug port registers . . . . .1047
33.4.4DP debug port identification register (DP_PIDR) . . . . .1048
33.4.5DP abort register (DP_ABORTR) . . . . .1048
33.4.6DP control and status register (DP_CTRL/STATR) . . . . .1049
33.4.7DP data link control register (DP_DLCR) . . . . .1051
33.4.8DP target identification register (DP_TARGETIDR) . . . . .1051
33.4.9DP data link protocol identification register (DP_DLPIDR) . . . . .1052
33.4.10DP resend register (DP_RESENR) . . . . .1052
33.4.11DP access port select register (DP_SELECTR) . . . . .1053
33.4.12DP read buffer register (DP_BUFFR) . . . . .1053
33.4.13DP target selection register (DP_TARGETSELR) . . . . .1054
33.4.14Debug port register map and reset values . . . . .1055
33.5Access ports . . . . .1056
33.5.1AP control/status word register (AP_CSWR) . . . . .1058
33.5.2AP transfer address register (AP_TAR) . . . . .1059
33.5.3AP data read/write register (AP_DRWR) . . . . .1059
33.5.4AP banked data registers (AP_BD0-3R) . . . . .1059
33.5.5AP base address register (AP_BASER) . . . . .1060
33.5.6AP identification register (AP_IDR) . . . . .1060
33.5.7Access port register map and reset values . . . . .1062
33.6Cross trigger interface (CTI) and matrix (CTM) . . . . .1063
33.7Cross trigger interface registers . . . . .1067
33.7.1CTI control register (CTI_CONTROLR) . . . . .1067
33.7.2CTI trigger acknowledge register (CTI_INTACKR) . . . . .1067
33.7.3CTI application trigger set register (CTI_APPSETR) . . . . .1067
33.7.4CTI application trigger clear register (CTI_APPCLEAR) . . . . .1068
33.7.5CTI application pulse register (CTI_APPPULSER) . . . . .1069
33.7.6CTI trigger In x enable register (CTI_INENRx) . . . . .1069
33.7.7CTI trigger out x enable register (CTI_OUTENRx) . . . . .1070
33.7.8CTI trigger in status register (CTI_TRGISTSR) . . . . .1070
33.7.9CTI trigger out status register (CTI_TRGOSTSR) . . . . .1071
33.7.10CTI channel in status register (CTI_CHINSTSR) . . . . .1071
33.7.11CTI channel out status register (CTI_CHOUTSTSR) . . . . .1071
33.7.12CTI channel gate register (CTI_GATER) . . . . .1072
33.7.13CTI claim tag set register (CTI_CLAIMSETR) . . . . .1072
33.7.14CTI claim tag clear register (CTI_CLAIMCLR) . . . . .1073
33.7.15CTI lock access register (CTI_LAR) . . . . .1073
33.7.16CTI lock status register (CTI_LSR) . . . . .1074
33.7.17CTI authentication status register (CTI_AUTHSTATR) . . . . .1074
33.7.18CTI device configuration register (CTI_DEVIDR) . . . . .1075
33.7.19CTI device type identifier register (CTI_DEVTYPE) . . . . .1075
33.7.20CTI CoreSight peripheral identity register 4 (CTI_PIDR4) . . . . .1076
33.7.21CTI CoreSight peripheral identity register 0 (CTI_PIDR0) . . . . .1076
33.7.22CTI CoreSight peripheral identity register 1 (CTI_PIDR1) . . . . .1076
33.7.23CTI CoreSight peripheral identity register 2 (CTI_PIDR2) . . . . .1077
33.7.24CTI CoreSight peripheral identity register 3 (CTI_PIDR3) . . . . .1077
33.7.25CTI CoreSight component identity register 0 (CTI_CIDR0) . . . . .1078
33.7.26CTI CoreSight peripheral identity register 1 (CTI_CIDR1) . . . . .1078
33.7.27CTI CoreSight component identity register 2 (CTI_CIDR2) . . . . .1079
33.7.28CTI CoreSight component identity register 3 (CTI_CIDR3) . . . . .1079
33.7.29CTI register map and reset values . . . . .1080
33.8Microcontroller debug unit (DBGMCU) . . . . .1083
33.8.1DBGMCU identity code register (DBGMCU_IDCODE) . . . . .1083
33.8.2DBGMCU configuration register (DBGMCU_CR) . . . . .1083
33.8.3DBGMCU CPU1 APB1 peripheral freeze register 1
(DBGMCU_APB1FZR1) . . . . .		1084
33.8.4DBGMCU CPU2 APB1 peripheral freeze register 1
(DBGMCU_C2APB1FZR1) . . . . .		1085
33.8.5DBGMCU CPU1 APB1 peripheral freeze register 2
(DBGMCU_APB1FZR2) . . . . .		1086
33.8.6DBGMCU CPU2 APB1 peripheral freeze register 2
(DBGMCU_C2APB1FZR2) . . . . .		1087
33.8.7DBGMCU CPU1 APB2 peripheral freeze register
(DBGMCU_APB2FZR) . . . . .		1087
33.8.8DBGMCU CPU2 APB2 peripheral freeze register (DBGMCU_C2APB2FZR) .....1088
33.8.9DBGMCU register map and reset values .....1089
33.9CPU2 ROM tables .....1091
33.9.1CPU2 ROM1 memory type register (C2ROM1_MEMTYPER) .....1093
33.9.2CPU2 ROM1 CoreSight peripheral identity register 4 (C2ROM1_PIDR4) .....1093
33.9.3CPU2 ROM1 CoreSight peripheral identity register 0 (C2ROM1_PIDR0) .....1093
33.9.4CPU2 ROM1 CoreSight peripheral identity register 1 (C2ROM1_PIDR1) .....1094
33.9.5CPU2 ROM1 CoreSight peripheral identity register 2 (C2ROM1_PIDR2) .....1094
33.9.6CPU2 ROM1 CoreSight peripheral identity register 3 (C2ROM1_PIDR3) .....1095
33.9.7CPU2 ROM1 CoreSight component identity register 0 (C2ROM1_CIDR0) .....1095
33.9.8CPU2 ROM1 CoreSight peripheral identity register 1 (C2ROM1_CIDR1) .....1096
33.9.9CPU2 ROM1 CoreSight component identity register 2 (C2ROM1_CIDR2) .....1096
33.9.10CPU2 ROM1 CoreSight component identity register 3 (C2ROM1_CIDR3) .....1096
33.9.11CPU2 processor ROM table registers and reset values .....1098
33.9.12CPU2 ROM2 memory type register (C2ROM2_MEMTYPER) .....1099
33.9.13CPU2 ROM2 CoreSight peripheral identity register 4 (C2ROM2_PIDR4) .....1099
33.9.14CPU2 ROM2 CoreSight peripheral identity register 0 (C2ROM2_PIDR0) .....1099
33.9.15CPU2 ROM2 CoreSight peripheral identity register 1 (C2ROM2_PIDR1) .....1100
33.9.16CPU2 ROM2 CoreSight peripheral identity register 2 (C2ROM2_PIDR2) .....1100
33.9.17CPU2 ROM2 CoreSight peripheral identity register 3 (C2ROM2_PIDR3) .....1101
33.9.18CPU2 ROM2 CoreSight component identity register 0 (C2ROM2_CIDR0) .....1101
33.9.19CPU2 ROM2 CoreSight peripheral identity register 1 (C2ROM2_CIDR1) .....1102
33.9.20CPU2 ROM2 CoreSight component identity register 2 (C2ROM2_CIDR2) .....1102
33.9.21CPU2 ROM2 CoreSight component identity register 3 (C2ROM2_CIDR3) . . . . .1102
33.9.22CPU2 ROM table register map and reset values . . . . .1104
33.10CPU2 data watchpoint and trace unit (DWT) . . . . .1105
33.10.1DWT control register (DWT_CTRLR) . . . . .1105
33.10.2DWT cycle count register (DWT_CYCCNTR) . . . . .1107
33.10.3DWT CPI count register (DWT_CPICNTR) . . . . .1107
33.10.4DWT exception count register (DWT_EXCCNTR) . . . . .1108
33.10.5DWT sleep count register (DWT_SLP CNTR) . . . . .1108
33.10.6DWT LSU count register (DWT_LSUCNTR) . . . . .1109
33.10.7DWT fold count register (DWT_FOLDCNTR) . . . . .1109
33.10.8DWT program counter sample register (DWT_PCSR) . . . . .1109
33.10.9DWT comparator register x (DWT_COMPxR) . . . . .1110
33.10.10DWT mask register x (DWT_MASKxR) . . . . .1110
33.10.11DWT function register x (DWT_FUNCTxR) . . . . .1110
33.10.12DWT CoreSight peripheral identity register 4 (DWT_PIDR4) . . . . .1111
33.10.13DWT CoreSight peripheral identity register 0 (DWT_PIDR0) . . . . .1112
33.10.14DWT CoreSight peripheral identity register 1 (DWT_PIDR1) . . . . .1112
33.10.15DWT CoreSight peripheral identity register 2 (DWT_PIDR2) . . . . .1113
33.10.16DWT CoreSight peripheral identity register 3 (DWT_PIDR3) . . . . .1113
33.10.17DWT CoreSight component identity register 0 (DWT_CIDR0) . . . . .1114
33.10.18DWT CoreSight peripheral identity register 1 (DWT_CIDR1) . . . . .1114
33.10.19DWT CoreSight component identity register 2 (DWT_CIDR2) . . . . .1114
33.10.20DWT CoreSight component identity register 3 (DWT_CIDR3) . . . . .1115
33.10.21CPU2 DWT registers . . . . .1116
33.11CPU2 breakpoint unit (PBU) . . . . .1119
33.11.1BPU control register (BPU_CTRLR) . . . . .1119
33.11.2BPU remap register (BPU_REMAPR) . . . . .1119
33.11.3BPU comparator registers (BPU_COMPxR) . . . . .1120
33.11.4BPU CoreSight peripheral identity register 4 (BPU_PIDR4) . . . . .1120
33.11.5BPU CoreSight peripheral identity register 0 (BPU_PIDR0) . . . . .1121
33.11.6BPU CoreSight peripheral identity register 1 (BPU_PIDR1) . . . . .1121
33.11.7BPU CoreSight peripheral identity register 2 (BPU_PIDR2) . . . . .1121
33.11.8BPU CoreSight peripheral identity register 3 (BPU_PIDR3) . . . . .1122
33.11.9BPU CoreSight component identity register 0 (BPU_CIDR0) . . . . .1122
33.11.10BPU CoreSight peripheral identity register 1 (BPU_CIDR1) . . . . .1123
33.11.11BPU CoreSight component identity register 2 (BPU_CIDR2) . . . . .1123
33.11.12BPU CoreSight component identity register 3 (BPU_CIDR3) . . . . .1124
33.11.13CPU2 BPU register map and reset values . . . . .1125
33.12CPU2 cross trigger interface (CTI) . . . . .1126
33.13CPU1 ROM table . . . . .1126
33.13.1CPU1 ROM memory type register (C1ROM_MEMTYPE) . . . . .1127
33.13.2CPU1 ROM CoreSight peripheral identity register 4
(C1ROM_PIDR4) . . . . .		1128
33.13.3CPU1 ROM CoreSight peripheral identity register 0
(C1ROM_PIDR0) . . . . .		1128
33.13.4CPU1 ROM CoreSight peripheral identity register 1
(C1ROM_PIDR1) . . . . .		1129
33.13.5CPU1 ROM CoreSight peripheral identity register 2
(C1ROM_PIDR2) . . . . .		1129
33.13.6CPU1 ROM CoreSight peripheral identity register 3
(C1ROM_PIDR3) . . . . .		1130
33.13.7CPU1 ROM CoreSight component identity register 0
(C1ROM_CIDR0) . . . . .		1130
33.13.8CPU1 ROM CoreSight peripheral identity register 1
(C1ROM_CIDR1) . . . . .		1130
33.13.9CPU1 ROM CoreSight component identity register 2
(C1ROM_CIDR2) . . . . .		1131
33.13.10CPU1 ROM CoreSight component identity register 3
(C1ROM_CIDR3) . . . . .		1131
33.13.11CPU1 ROM table register map and reset values . . . . .1133
33.14CPU1 data watchpoint and trace unit (DWT) . . . . .1134
33.14.1DWT control register (DWT_CTRLR) . . . . .1134
33.14.2DWT cycle count register (DWT_CYCCNTR) . . . . .1136
33.14.3DWT CPI count register (DWT_CPICNTR) . . . . .1136
33.14.4DWT exception count register (DWT_EXCCNTR) . . . . .1137
33.14.5DWT sleep count register (DWT_SLPNCNTR) . . . . .1137
33.14.6DWT LSU count register (DWT_LSUCNTR) . . . . .1138
33.14.7DWT fold count register (DWT_FOLDCNTR) . . . . .1138
33.14.8DWT program counter sample register (DWT_PCSR) . . . . .1138
33.14.9DWT comparator register x (DWT_COMPxR) . . . . .1139
33.14.10DWT mask register x (DWT_MASKxR) . . . . .1139
33.14.11DWT function register x (DWT_FUNCTxR) . . . . .1139
33.14.12DWT CoreSight peripheral identity register 4 (DWT_PIDR4) . . . . .1140
33.14.13DWT CoreSight peripheral identity register 0 (DWT_PIDR0) . . . . .1141
33.14.14DWT CoreSight peripheral identity register 1 (DWT_PIDR1) . . . . .1141
33.14.15 DWT CoreSight peripheral identity register 2 (DWT_PIDR2) . . . . .1142
33.14.16 DWT CoreSight peripheral identity register 3 (DWT_PIDR3) . . . . .1142
33.14.17 DWT CoreSight component identity register 0 (DWT_CIDR0) . . . . .1143
33.14.18 DWT CoreSight peripheral identity register 1 (DWT_CIDR1) . . . . .1143
33.14.19 DWT CoreSight component identity register 2 (DWT_CIDR2) . . . . .1143
33.14.20 DWT CoreSight component identity register 3 (DWT_CIDR3) . . . . .1144
33.14.21 CPU1 DWT register map and reset values . . . . .1145
33.15 CPU1 instrumentation trace macrocell (ITM) . . . . .1147
33.15.1 ITM stimulus register x (ITM_STIMRx) . . . . .1147
33.15.2 ITM trace enable register (ITM_TER) . . . . .1147
33.15.3 ITM trace privilege register (ITM_TPR) . . . . .1148
33.15.4 ITM trace control register (ITM_TCR) . . . . .1148
33.15.5 ITM CoreSight peripheral identity register 4 (ITM_PIDR4) . . . . .1149
33.15.6 ITM CoreSight peripheral identity register 0 (ITM_PIDR0) . . . . .1150
33.15.7 ITM CoreSight peripheral identity register 1 (ITM_PIDR1) . . . . .1150
33.15.8 ITM CoreSight peripheral identity register 2 (ITM_PIDR2) . . . . .1151
33.15.9 ITM CoreSight peripheral identity register 3 (ITM_PIDR3) . . . . .1151
33.15.10 ITM CoreSight component identity register 0 (ITM_CIDR0) . . . . .1152
33.15.11 ITM CoreSight peripheral identity register 1 (ITM_CIDR1) . . . . .1152
33.15.12 ITM CoreSight component identity register 2 (ITM_CIDR2) . . . . .1152
33.15.13 ITM CoreSight component identity register 3 (ITM_CIDR3) . . . . .1153
33.15.14 ITM register map and reset values . . . . .1154
33.16 CPU1 breakpoint unit (FPB) . . . . .1155
33.16.1 FPB control register (FPB_CTRLR) . . . . .1155
33.16.2 FPB remap register (FPB_REMAPR) . . . . .1155
33.16.3 FPB comparator registers (FPB_COMPxR) . . . . .1156
33.16.4 FPB CoreSight peripheral identity register 4 (FPB_PIDR4) . . . . .1156
33.16.5 FPB CoreSight peripheral identity register 0 (FPB_PIDR0) . . . . .1157
33.16.6 FPB CoreSight peripheral identity register 1 (FPB_PIDR1) . . . . .1157
33.16.7 FPB CoreSight peripheral identity register 2 (FPB_PIDR2) . . . . .1158
33.16.8 FPB CoreSight peripheral identity register 3 (FPB_PIDR3) . . . . .1158
33.16.9 FPB CoreSight component identity register 0 (FPB_CIDR0) . . . . .1159
33.16.10 FPB CoreSight peripheral identity register 1 (FPB_CIDR1) . . . . .1159
33.16.11 FPB CoreSight component identity register 2 (FPB_CIDR2) . . . . .1159
33.16.12 FPB CoreSight component identity register 3 (FPB_CIDR3) . . . . .1160
33.16.13 FPB register map and reset values . . . . .1161
33.17 CPU1 trace port interface unit (TPIU) . . . . .1162
33.17.1TPIU supported port size register (TPIU_SSPSR) . . . . .1162
33.17.2TPIU current port size register (TPIU_CSPSR) . . . . .1162
33.17.3TPIU asynchronous clock prescaler register (TPIU_ACPR) . . . . .1163
33.17.4TPIU selected pin protocol register (TPIU_SPPR) . . . . .1163
33.17.5TPIU formatter and flush status register (TPIU_FFSR) . . . . .1164
33.17.6TPIU formatter and flush control register (TPIU_FFCR) . . . . .1164
33.17.7TPIU formatter synchronization counter register (TPIU_FSCR) . . . . .1165
33.17.8TPIU claim tag set register (TPIU_CLAIMSETR) . . . . .1165
33.17.9TPIU claim tag clear register (TPIU_CLAIMCLR) . . . . .1166
33.17.10TPIU device configuration register (TPIU_DEVIDR) . . . . .1166
33.17.11TPIU device type identifier register (TPIU_DEVTYPE) . . . . .1167
33.17.12TPIU CoreSight peripheral identity register 4 (TPIU_PIDR4) . . . . .1167
33.17.13TPIU CoreSight peripheral identity register 0 (TPIU_PIDR0) . . . . .1168
33.17.14TPIU CoreSight peripheral identity register 1 (TPIU_PIDR1) . . . . .1168
33.17.15TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) . . . . .1168
33.17.16TPIU CoreSight peripheral identity register 3 (TPIU_PIDR3) . . . . .1169
33.17.17TPIU CoreSight component identity register 0 (TPIU_CIDR0) . . . . .1169
33.17.18TPIU CoreSight peripheral identity register 1 (TPIU_CIDR1) . . . . .1170
33.17.19TPIU CoreSight component identity register 2 (TPIU_CIDR2) . . . . .1170
33.17.20TPIU CoreSight component identity register 3 (TPIU_CIDR3) . . . . .1171
33.17.21CPU1 TPIU register map and reset values . . . . .1172
33.18CPU1 cross trigger interface (CTI) . . . . .1174
33.19References . . . . .1174
34Device electronic signature . . . . .1175
34.1Unique device ID register (96 bits) . . . . .1175
34.2Memory size data register . . . . .1176
34.2.1Flash size data register . . . . .1176
34.3Package data register . . . . .1176
34.4Part number codification register . . . . .1177
35Important security notice . . . . .1178
36Revision history . . . . .1179

List of tables

Table 1.Memory map and peripheral register boundary addresses . . . . .57
Table 2.Boot modes. . . . .61
Table 3.Flash memory - Single bank organization . . . . .65
Table 4.Number of wait states vs, flash memory clock (HCLK4) frequency . . . . .67
Table 5.Page erase overview . . . . .72
Table 6.Mass erase overview . . . . .73
Table 7.Errors in page-based row programming . . . . .78
Table 8.Option bytes format . . . . .79
Table 9.Option bytes organization. . . . .79
Table 10.Option loading control. . . . .88
Table 11.UID64 organization. . . . .89
Table 12.Flash memory read protection status . . . . .90
Table 13.RDP regression from Level 1 to Level 0 and memory erase . . . . .92
Table 14.Access status vs. protection level and execution modes . . . . .93
Table 17.Flash memory interrupt requests . . . . .98
Table 18.Flash interface register map and reset values . . . . .118
Table 19.CRC internal input/output signals . . . . .123
Table 20.CRC register map and reset values . . . . .128
Table 21.Supply configuration control . . . . .131
Table 22.PVM features . . . . .136
Table 23.Sub-system low power wake-up sources . . . . .140
Table 24.Low-power mode summary . . . . .142
Table 25.Functionalities depending on system operating mode . . . . .143
Table 26.Low-power run . . . . .146
Table 27.CPU CSTOP wake-up vs. system operating mode . . . . .147
Table 28.Sleep mode. . . . .148
Table 29.Low-power sleep. . . . .149
Table 30.Stop0 mode . . . . .151
Table 31.Stop1 mode . . . . .152
Table 32.Standby mode. . . . .154
Table 33.Shutdown mode . . . . .155
Table 34.PWR register map and reset values. . . . .173
Table 35.STM32WB15CC peripherals interconnect matrix . . . . .175
Table 36.Maximum clock source frequency . . . . .192
Table 37.SMPS step-down converter clock source selection and division . . . . .193
Table 38.Peripheral clock enable . . . . .196
Table 39.Single core Low power debug configurations. . . . .197
Table 40.RCC register map and reset values . . . . .249
Table 41.Port bit configuration table . . . . .257
Table 42.GPIO register map and reset values . . . . .272
Table 43.SYSCFG register map and reset values. . . . .290
Table 44.DMA implementation . . . . .293
Table 45.DMA internal input/output signals . . . . .294
Table 46.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .299
Table 47.DMA interrupt requests. . . . .301
Table 48.DMA register map and reset values . . . . .309
Table 49.DMAMUX instantiation . . . . .313
Table 50.DMAMUX: assignment of multiplexer inputs to resources . . . . .314
Table 51.DMAMUX: assignment of trigger inputs to resources . . . . .314
Table 52.DMAMUX: assignment of synchronization inputs to resources . . . . .315
Table 53.DMAMUX signals . . . . .317
Table 54.DMAMUX interrupts . . . . .321
Table 55.DMAMUX register map and reset values . . . . .326
Table 56.DMAMUX register map and reset values . . . . .327
Table 57.CPU1 vector table. . . . .331
Table 58.CPU2 vector table. . . . .334
Table 59.Wake-up interrupt table . . . . .336
Table 60.EXTI pin overview. . . . .339
Table 61.EVG pin overview . . . . .339
Table 62.EXTI event input configurations and register control . . . . .341
Table 63.Masking functionality . . . . .344
Table 64.EXTI register map sections. . . . .345
Table 65.EXTI register map and reset values . . . . .354
Table 66.ADC input/output pins. . . . .358
Table 67.ADC internal input/output signals . . . . .359
Table 68.External triggers . . . . .359
Table 69.Latency between trigger and start of conversion . . . . .364
Table 70.Configuring the trigger polarity . . . . .371
Table 71.tSAR timings depending on resolution . . . . .373
Table 72.Analog watchdog comparison. . . . .382
Table 73.Analog watchdog channel selection . . . . .383
Table 74.ADC interrupts . . . . .389
Table 75.ADC register map and reset values . . . . .404
Table 76.COMP1 input plus assignment . . . . .408
Table 77.COMP1 input minus assignment . . . . .409
Table 78.Comparator behavior in the low power modes . . . . .412
Table 79.Interrupt control bits . . . . .412
Table 80.COMP register map and reset values. . . . .416
Table 81.Acquisition sequence summary . . . . .420
Table 82.Spread spectrum deviation versus AHB clock frequency. . . . .422
Table 83.I/O state depending on its mode and IODEF bit value . . . . .423
Table 84.Effect of low-power modes on TSC . . . . .425
Table 85.Interrupt control bits . . . . .425
Table 86.TSC register map and reset values . . . . .432
Table 87.RNG internal input/output signals . . . . .436
Table 88.RNG interrupt requests. . . . .442
Table 89.RNG configurations . . . . .443
Table 90.RNG register map and reset map. . . . .446
Table 91.AES internal input/output signals . . . . .448
Table 92.CTR mode initialization vector definition. . . . .465
Table 93.GCM last block definition . . . . .467
Table 94.Initialization of AES_IVRx registers in GCM mode . . . . .468
Table 95.Initialization of AES_IVRx registers in CCM mode . . . . .475
Table 96.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .480
Table 97.AES interrupt requests . . . . .483
Table 98.Processing latency for ECB, CBC and CTR. . . . .483
Table 99.Processing latency for GCM and CCM (in clock cycles). . . . .484
Table 100.AES register map and reset values . . . . .494
Table 101.Internal input/output signals . . . . .497
Table 102.PKA integer arithmetic functions list . . . . .498
Table 103.PKA prime field (Fp) elliptic curve functions list . . . . .498
Table 104.Montgomery parameter computation . . . . .503
Table 105.Modular addition . . . . .504
Table 106.Modular subtraction . . . . .504
Table 107.Montgomery multiplication . . . . .505
Table 108.Modular exponentiation (normal mode) . . . . .506
Table 109.Modular exponentiation (fast mode) . . . . .506
Table 110.Modular inversion . . . . .506
Table 111.Modular reduction . . . . .507
Table 112.Arithmetic addition . . . . .507
Table 113.Arithmetic subtraction . . . . .507
Table 114.Arithmetic multiplication . . . . .508
Table 115.Arithmetic comparison . . . . .508
Table 116.CRT exponentiation . . . . .509
Table 117.Point on elliptic curve Fp check . . . . .510
Table 118.ECC Fp scalar multiplication . . . . .510
Table 119.ECC Fp scalar multiplication (Fast Mode) . . . . .511
Table 120.ECDSA sign - Inputs . . . . .512
Table 121.ECDSA sign - Outputs . . . . .512
Table 122.Extended ECDSA sign (extra outputs) . . . . .513
Table 123.ECDSA verification (inputs) . . . . .513
Table 124.ECDSA verification (outputs) . . . . .513
Table 125.Family of supported curves for ECC operations . . . . .514
Table 126.Modular exponentiation computation times . . . . .516
Table 127.ECC scalar multiplication computation times . . . . .516
Table 128.ECDSA signature average computation times . . . . .516
Table 129.ECDSA verification average computation times . . . . .517
Table 130.Point on elliptic curve Fp check average computation times . . . . .517
Table 131.Montgomery parameters average computation times . . . . .517
Table 132.PKA interrupt requests . . . . .517
Table 133.PKA register map and reset values . . . . .521
Table 134.Behavior of timer outputs versus BRK/BRK2 inputs . . . . .564
Table 135.Break protection disarming conditions . . . . .566
Table 136.Counting direction versus encoder signals . . . . .572
Table 137.TIM1 internal trigger connection . . . . .589
Table 138.Output control bits for complementary OCx and OCxN channels with break feature . . . . .603
Table 139.TIM1 register map and reset values . . . . .619
Table 140.Counting direction versus encoder signals . . . . .655
Table 141.TIM2 internal trigger connection . . . . .673
Table 142.Output control bit for standard OCx channels . . . . .684
Table 143.TIM2 register map and reset values . . . . .691
Table 144.LPTIM features . . . . .695
Table 145.LPTIM1 external trigger connection . . . . .696
Table 146.LPTIM2 external trigger connection . . . . .696
Table 147.Prescaler division ratios . . . . .698
Table 148.Encoder counting scenarios . . . . .704
Table 149.Effect of low-power modes on the LPTIM . . . . .705
Table 150.Interrupt events . . . . .706
Table 151.LPTIM register map and reset values . . . . .717
Table 152.Effect of low-power modes on RTC . . . . .733
Table 153.Interrupt control bits . . . . .733
Table 154.RTC register map and reset values . . . . .757
Table 155.IWDG register map and reset values . . . . .767
Table 156.WWDG internal input/output signals . . . . .769
Table 157.WWDG register map and reset values . . . . .773
Table 158.I2C implementation . . . . .775
Table 159.I2C input/output pins . . . . .776
Table 160.I2C internal input/output signals . . . . .777
Table 161.Comparison of analog and digital filters . . . . .779
Table 162.I 2 C-bus and SMBus specification data setup and hold times . . . . .781
Table 163.I2C configuration . . . . .785
Table 164.I 2 C-bus and SMBus specification clock timings . . . . .796
Table 165.Timing settings for f I2CCLK of 8 MHz . . . . .806
Table 166.Timing settings for f I2CCLK of 16 MHz . . . . .806
Table 167.SMBus timeout specifications . . . . .808
Table 168.SMBus with PEC configuration . . . . .810
Table 169.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms . . . . .811
Table 170.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .811
Table 171.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .811
Table 172.Effect of low-power modes to I2C . . . . .821
Table 173.I2C interrupt requests . . . . .821
Table 174.I2C register map and reset values . . . . .836
Table 175.USART / LPUART features . . . . .839
Table 176.USART/UART input/output pins . . . . .842
Table 177.USART internal input/output signals . . . . .842
Table 178.Noise detection from sampled data . . . . .854
Table 179.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .857
Table 180.Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . .858
Table 181.USART frame formats . . . . .863
Table 182.Effect of low-power modes on the USART . . . . .886
Table 183.USART interrupt requests . . . . .887
Table 184.USART register map and reset values . . . . .921
Table 185.USART / LPUART features . . . . .925
Table 186.LPUART input/output pins . . . . .927
Table 187.LPUART internal input/output signals . . . . .927
Table 188.Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz . . . . .937
Table 189.Error calculation for programmed baud rates at fCK = 100 MHz . . . . .938
Table 190.Tolerance of the LPUART receiver . . . . .939
Table 192.Effect of low-power modes on the LPUART . . . . .950
Table 193.LPUART interrupt requests . . . . .951
Table 194.LPUART register map and reset values . . . . .974
Table 195.STM32WB15CC SPI implementation . . . . .977
Table 196.SPI interrupt requests . . . . .1001
Table 197.SPI register map and reset values . . . . .1010
Table 198.IPCC interface signals . . . . .1012
Table 199.Bits used for the communication . . . . .1013
Table 200.IPCC register map and reset values . . . . .1024
Table 201.HSEM internal input/output signals . . . . .1026
Table 202.Authorized AHB bus master IDs . . . . .1031
Table 203.HSEM register map and reset values . . . . .1037
Table 204.JTAG/Serial-wire debug port pins . . . . .1041
Table 205.Trace port pins . . . . .1042
Table 206.Single Wire Trace port pins . . . . .1042
Table 207.Trigger pins . . . . .1042

Table 208. JTAG-DP data registers . . . . . 1045
Table 209. Packet request . . . . . 1046
Table 210. ACK response . . . . . 1047
Table 211. Data transfer . . . . . 1047
Table 212. Debug port register map and reset values . . . . . 1055
Table 213. Access port register map and reset values . . . . . 1062
Table 214. CPU2 CTI inputs . . . . . 1063
Table 215. CPU2 CTI outputs . . . . . 1064
Table 216. CPU1 CTI inputs . . . . . 1064
Table 217. CPU1 CTI outputs . . . . . 1064
Table 218. CTI register map and reset values . . . . . 1080
Table 219. DBGMCU register map and reset values . . . . . 1089
Table 220. CPU2 processor ROM table . . . . . 1091
Table 221. CPU2 ROM table . . . . . 1091
Table 222. CPU2 processor ROM table register map and reset values . . . . . 1098
Table 223. CPU2 ROM table register map and reset values . . . . . 1104
Table 224. CPU2 DWT register map and reset values . . . . . 1116
Table 225. CPU2 BPU register map and reset values . . . . . 1125
Table 226. CPU1 ROM table . . . . . 1126
Table 227. CPU1 ROM table register map and reset values . . . . . 1133
Table 228. CPU1 DWT register map and reset values . . . . . 1145
Table 229. CPU1 ITM register map and reset values . . . . . 1154
Table 230. CPU1 FPB register map and reset values . . . . . 1161
Table 231. CPU1 TPIU register map and reset values . . . . . 1172
Table 232. Document revision history . . . . . 1179

List of figures

Figure 1.System architecture . . . . .53
Figure 2.Memory map . . . . .56
Figure 3.Sequential 16-bit instructions execution . . . . .69
Figure 4.Changing the Read protection (RDP) level . . . . .93
Figure 5.Radio system block diagram . . . . .121
Figure 6.CRC calculation unit block diagram . . . . .123
Figure 7.Power supply overview . . . . .130
Figure 8.Supply configurations . . . . .130
Figure 9.Brown-out reset waveform . . . . .135
Figure 10.PVD thresholds . . . . .136
Figure 11.CPU2 boot options . . . . .138
Figure 12.Low-power modes possible transitions . . . . .141
Figure 13.Real-time radio activity flags . . . . .156
Figure 14.Simplified diagram of the reset circuit . . . . .181
Figure 15.Clock tree . . . . .186
Figure 16.HSE clock sources . . . . .187
Figure 17.LSE clock sources . . . . .190
Figure 18.Three-volt or five-volt tolerant GPIO structure (TT or FT) . . . . .256
Figure 19.Input floating/pull up/pull down configurations . . . . .261
Figure 20.Output configuration . . . . .261
Figure 21.Alternate function configuration . . . . .262
Figure 22.High impedance-analog configuration . . . . .263
Figure 23.DMA block diagram . . . . .293
Figure 24.DMAMUX block diagram . . . . .316
Figure 25.Synchronization mode of the DMAMUX request line multiplexer channel . . . . .319
Figure 26.Event generation of the DMA request line multiplexer channel . . . . .319
Figure 27.Interrupt block diagram . . . . .330
Figure 28.EXTI block diagram . . . . .339
Figure 29.Configurable event trigger logic CPU wakeup . . . . .342
Figure 30.Direct event trigger logic CPU wakeup . . . . .343
Figure 31.ADC block diagram . . . . .358
Figure 32.ADC calibration . . . . .361
Figure 33.Calibration factor forcing . . . . .361
Figure 34.Enabling/disabling the ADC . . . . .362
Figure 35.ADC clock scheme . . . . .363
Figure 36.ADC connectivity . . . . .365
Figure 37.Analog-to-digital conversion time . . . . .370
Figure 38.ADC conversion timings . . . . .370
Figure 39.Stopping an ongoing conversion . . . . .371
Figure 40.Single conversions of a sequence, software trigger . . . . .374
Figure 41.Continuous conversion of a sequence, software trigger . . . . .374
Figure 42.Single conversions of a sequence, hardware trigger . . . . .375
Figure 43.Continuous conversions of a sequence, hardware trigger . . . . .375
Figure 44.Data alignment and resolution . . . . .376
Figure 45.Example of overrun (OVR) . . . . .377
Figure 46.Wait mode conversion (continuous mode, software trigger) . . . . .380
Figure 47.Behavior with WAIT = 0, AUTOFF = 1 . . . . .381
Figure 48.Behavior with WAIT = 1, AUTOFF = 1 . . . . .381
Figure 49.Analog watchdog guarded area . . . . .382
Figure 50.ADC_AWD1_OUT signal generation . . . . .384
Figure 51.ADC_AWD1_OUT signal generation (AWD flag not cleared by software) . . . . .384
Figure 52.ADC1_AWD_OUT signal generation (on a single channel) . . . . .384
Figure 53.Analog watchdog threshold update . . . . .385
Figure 54.Temperature sensor and VREFINT channel block diagram . . . . .386
Figure 55.VBAT channel block diagram . . . . .388
Figure 56.Comparator block diagram . . . . .408
Figure 57.Window mode . . . . .410
Figure 58.Comparator hysteresis . . . . .410
Figure 59.Comparator output blanking . . . . .411
Figure 60.TSC block diagram . . . . .418
Figure 61.Surface charge transfer analog I/O group structure . . . . .419
Figure 62.Sampling capacitor voltage variation . . . . .420
Figure 63.Charge transfer acquisition sequence . . . . .421
Figure 64.Spread spectrum variation principle . . . . .422
Figure 65.RNG block diagram . . . . .436
Figure 66.Entropy source model . . . . .437
Figure 67.RNG initialization overview . . . . .439
Figure 68.AES block diagram . . . . .448
Figure 69.ECB encryption and decryption principle . . . . .450
Figure 70.CBC encryption and decryption principle . . . . .451
Figure 71.CTR encryption and decryption principle . . . . .452
Figure 72.GCM encryption and authentication principle . . . . .453
Figure 73.GMAC authentication principle . . . . .453
Figure 74.CCM encryption and authentication principle . . . . .454
Figure 75.Encryption key derivation for ECB/CBC decryption (Mode 2). . . . .457
Figure 76.Example of suspend mode management . . . . .458
Figure 77.ECB encryption . . . . .459
Figure 78.ECB decryption . . . . .459
Figure 79.CBC encryption . . . . .460
Figure 80.CBC decryption . . . . .460
Figure 81.ECB/CBC encryption (Mode 1) . . . . .461
Figure 82.ECB/CBC decryption (Mode 3) . . . . .462
Figure 83.Message construction in CTR mode . . . . .464
Figure 84.CTR encryption . . . . .465
Figure 85.CTR decryption . . . . .465
Figure 86.Message construction in GCM . . . . .467
Figure 87.GCM authenticated encryption . . . . .468
Figure 88.Message construction in GMAC mode . . . . .472
Figure 89.GMAC authentication mode . . . . .472
Figure 90.Message construction in CCM mode . . . . .473
Figure 91.CCM mode authenticated encryption . . . . .475
Figure 92.128-bit block construction with respect to data swap . . . . .479
Figure 93.DMA transfer of a 128-bit data block during input phase . . . . .481
Figure 94.DMA transfer of a 128-bit data block during output phase . . . . .482
Figure 95.PKA block diagram . . . . .497
Figure 96.Advanced-control timer block diagram . . . . .524
Figure 97.Counter timing diagram with prescaler division change from 1 to 2 . . . . .526
Figure 98.Counter timing diagram with prescaler division change from 1 to 4 . . . . .526
Figure 99.Counter timing diagram, internal clock divided by 1 . . . . .528
Figure 100.Counter timing diagram, internal clock divided by 2 . . . . .528
Figure 101. Counter timing diagram, internal clock divided by 4 . . . . .529
Figure 102. Counter timing diagram, internal clock divided by N . . . . .529
Figure 103. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .530
Figure 104. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .530
Figure 105. Counter timing diagram, internal clock divided by 1 . . . . .532
Figure 106. Counter timing diagram, internal clock divided by 2 . . . . .532
Figure 107. Counter timing diagram, internal clock divided by 4 . . . . .533
Figure 108. Counter timing diagram, internal clock divided by N . . . . .533
Figure 109. Counter timing diagram, update event when repetition counter is not used . . . . .534
Figure 110. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .535
Figure 111. Counter timing diagram, internal clock divided by 2 . . . . .536
Figure 112. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .536
Figure 113. Counter timing diagram, internal clock divided by N . . . . .537
Figure 114. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .537
Figure 115. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .538
Figure 116. Update rate examples depending on mode and TIMx_RCR register settings . . . . .539
Figure 117. External trigger input block . . . . .540
Figure 118. TIM1 ETR input circuitry . . . . .540
Figure 119. Control circuit in normal mode, internal clock divided by 1 . . . . .541
Figure 120. TI2 external clock connection example . . . . .542
Figure 121. Control circuit in external clock mode 1 . . . . .543
Figure 122. External trigger input block . . . . .543
Figure 123. Control circuit in external clock mode 2 . . . . .544
Figure 124. Capture/compare channel (example: channel 1 input stage) . . . . .545
Figure 125. Capture/compare channel 1 main circuit . . . . .545
Figure 126. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .546
Figure 127. Output stage of capture/compare channel (channel 4) . . . . .546
Figure 128. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .547
Figure 129. PWM input mode timing . . . . .549
Figure 130. Output compare mode, toggle on OC1 . . . . .551
Figure 131. Edge-aligned PWM waveforms (ARR=8) . . . . .552
Figure 132. Center-aligned PWM waveforms (ARR=8) . . . . .553
Figure 133. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .555
Figure 134. Combined PWM mode on channel 1 and 3 . . . . .556
Figure 135. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .557
Figure 136. Complementary output with dead-time insertion . . . . .558
Figure 137. Dead-time waveforms with delay greater than the negative pulse . . . . .558
Figure 138. Dead-time waveforms with delay greater than the positive pulse . . . . .559
Figure 139. Break and Break2 circuitry overview . . . . .561
Figure 140. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .563
Figure 141. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .564
Figure 142. PWM output state following BRK assertion (OSSI=0) . . . . .565
Figure 143. Output redirection (BRK2 request not represented) . . . . .566
Figure 144. Clearing TIMx OCxREF . . . . .567
Figure 145. 6-step generation, COM example (OSSR=1) . . . . .568
Figure 146. Example of one pulse mode . . . . .569
Figure 147. Retriggerable one pulse mode . . . . .571
Figure 148. Example of counter operation in encoder interface mode . . . . .572
Figure 149. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .573
Figure 150. Measuring time interval between edges on 3 signals . . . . .574
Figure 151. Example of Hall sensor interface . . . . .576
Figure 152. Control circuit in reset mode . . . . .577
Figure 153. Control circuit in Gated mode . . . . .578
Figure 154. Control circuit in trigger mode . . . . .579
Figure 155. Control circuit in external clock mode 2 + trigger mode . . . . .580
Figure 156. General-purpose timer block diagram . . . . .623
Figure 157. Counter timing diagram with prescaler division change from 1 to 2 . . . . .625
Figure 158. Counter timing diagram with prescaler division change from 1 to 4 . . . . .625
Figure 159. Counter timing diagram, internal clock divided by 1 . . . . .626
Figure 160. Counter timing diagram, internal clock divided by 2 . . . . .627
Figure 161. Counter timing diagram, internal clock divided by 4 . . . . .627
Figure 162. Counter timing diagram, internal clock divided by N . . . . .628
Figure 163. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .628
Figure 164. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .629
Figure 165. Counter timing diagram, internal clock divided by 1 . . . . .630
Figure 166. Counter timing diagram, internal clock divided by 2 . . . . .630
Figure 167. Counter timing diagram, internal clock divided by 4 . . . . .631
Figure 168. Counter timing diagram, internal clock divided by N . . . . .631
Figure 169. Counter timing diagram, Update event . . . . .632
Figure 170. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .633
Figure 171. Counter timing diagram, internal clock divided by 2 . . . . .634
Figure 172. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .634
Figure 173. Counter timing diagram, internal clock divided by N . . . . .635
Figure 174. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .635
Figure 175. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .636
Figure 176. Control circuit in normal mode, internal clock divided by 1 . . . . .637
Figure 177. TI2 external clock connection example. . . . .637
Figure 178. Control circuit in external clock mode 1 . . . . .638
Figure 179. External trigger input block . . . . .639
Figure 180. Control circuit in external clock mode 2 . . . . .640
Figure 181. Capture/Compare channel (example: channel 1 input stage) . . . . .640
Figure 182. Capture/Compare channel 1 main circuit . . . . .641
Figure 183. Output stage of Capture/Compare channel (channel 1). . . . .641
Figure 184. PWM input mode timing . . . . .643
Figure 185. Output compare mode, toggle on OC1 . . . . .645
Figure 186. Edge-aligned PWM waveforms (ARR=8) . . . . .646
Figure 187. Center-aligned PWM waveforms (ARR=8). . . . .648
Figure 188. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .649
Figure 189. Combined PWM mode on channels 1 and 3 . . . . .650
Figure 190. Clearing TIMx_OCxREF . . . . .651
Figure 191. Example of one-pulse mode. . . . .652
Figure 192. Retriggerable one-pulse mode . . . . .654
Figure 193. Example of counter operation in encoder interface mode . . . . .655
Figure 194. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .656
Figure 195. Control circuit in reset mode . . . . .657
Figure 196. Control circuit in gated mode . . . . .658
Figure 197. Control circuit in trigger mode . . . . .659
Figure 198. Control circuit in external clock mode 2 + trigger mode . . . . .660
Figure 199. Master/Slave timer example . . . . .661
Figure 200. Master/slave connection example with 1 channel only timers . . . . .661
Figure 201. Gating TIM2 with OC1REF of TIM1 . . . . .662
Figure 202. Gating TIM2 with Enable of TIM1 . . . . .663
Figure 203. Triggering TIM2 with update of TIM1 . . . . .664
Figure 204. Triggering TIM2 with Enable of TIM1 . . . . .664
Figure 205. Low-power timer block diagram . . . . .695
Figure 206. Glitch filter timing diagram . . . . .697
Figure 207. LPTIM output waveform, single counting mode configuration . . . . .699
Figure 208. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set). . . . .		699
Figure 209. LPTIM output waveform, Continuous counting mode configuration . . . . .700
Figure 210. Waveform generation . . . . .701
Figure 211. Encoder mode counting sequence . . . . .705
Figure 212. RTC block diagram . . . . .720
Figure 213. Independent watchdog block diagram . . . . .759
Figure 214. Watchdog block diagram . . . . .769
Figure 215. Window watchdog timing diagram . . . . .770
Figure 216. Block diagram . . . . .776
Figure 217. I 2 C-bus protocol . . . . .778
Figure 218. Setup and hold timings . . . . .780
Figure 219. I2C initialization flow . . . . .782
Figure 220. Data reception . . . . .783
Figure 221. Data transmission . . . . .784
Figure 222. Target initialization flow . . . . .787
Figure 223. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .789
Figure 224. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .790
Figure 225. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .791
Figure 226. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .792
Figure 227. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .793
Figure 228. Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . .		793
Figure 229. Controller clock generation . . . . .795
Figure 230. Controller initialization flow . . . . .797
Figure 231. 10-bit address read access with HEAD10R = 0 . . . . .797
Figure 232. 10-bit address read access with HEAD10R = 1 . . . . .798
Figure 233. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .799
Figure 234. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .800
Figure 235. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		801
Figure 236. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .803
Figure 237. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .804
Figure 238. Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		805
Figure 239. Timeout intervals for t LOW:SEXT , t LOW:MEXT . . . . .809
Figure 240. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .812
Figure 241. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .813
Figure 242. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .814
Figure 243. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .815
Figure 244. Bus transfer diagrams for SMBus controller transmitter . . . . .816
Figure 245. Bus transfer diagrams for SMBus controller receiver . . . . .818
Figure 246. USART block diagram . . . . .840
Figure 247. Word length programming . . . . .843
Figure 248. Configurable stop bits . . . . .845
Figure 249. TC/TXE behavior when transmitting . . . . .848
Figure 250. Start bit detection when oversampling by 16 or 8. . . . .849
Figure 251. usart_ker_ck clock divider block diagram . . . . .852
Figure 252. Data sampling when oversampling by 16 . . . . .853
Figure 253.Data sampling when oversampling by 8 . . . . .854
Figure 254.Mute mode using Idle line detection . . . . .861
Figure 255.Mute mode using address mark detection . . . . .862
Figure 256.Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .865
Figure 257.Break detection in LIN mode vs. Framing error detection. . . . .866
Figure 258.USART example of synchronous master transmission. . . . .867
Figure 259.USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		867
Figure 260.USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		868
Figure 261.USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		869
Figure 262.ISO 7816-3 asynchronous protocol . . . . .871
Figure 263.Parity error detection using the 1.5 stop bits . . . . .873
Figure 264.IrDA SIR ENDEC block diagram. . . . .877
Figure 265.IrDA data modulation (3/16) - normal mode . . . . .877
Figure 266.Transmission using DMA . . . . .879
Figure 267.Reception using DMA . . . . .880
Figure 268.Hardware flow control between 2 USARTs . . . . .880
Figure 269.RS232 RTS flow control . . . . .881
Figure 270.RS232 CTS flow control . . . . .882
Figure 271.Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .885
Figure 272.Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		885
Figure 273.LPUART block diagram . . . . .926
Figure 274.LPUART word length programming . . . . .929
Figure 275.Configurable stop bits . . . . .931
Figure 276.TC/TXE behavior when transmitting . . . . .933
Figure 277.lpuart_ker_ck clock divider block diagram . . . . .936
Figure 278.Mute mode using Idle line detection . . . . .940
Figure 279.Mute mode using address mark detection . . . . .941
Figure 280.Transmission using DMA . . . . .943
Figure 281.Reception using DMA . . . . .944
Figure 282.Hardware flow control between 2 LPUARTs . . . . .945
Figure 283.RS232 RTS flow control . . . . .945
Figure 284.RS232 CTS flow control . . . . .946
Figure 285.Wake-up event verified (wake-up event = address match,
FIFO disabled) . . . . .		949
Figure 286.Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		949
Figure 287.SPI block diagram. . . . .977
Figure 288.Full-duplex single master/ single slave application. . . . .978
Figure 289.Half-duplex single master/ single slave application . . . . .979
Figure 290.Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		980
Figure 291.Master and three independent slaves. . . . .981
Figure 292.Multimaster application . . . . .982
Figure 293.Hardware/software slave select management . . . . .983
Figure 294.Data clock timing diagram . . . . .984
Figure 295.Data alignment when data length is not equal to 8-bit or 16-bit . . . . .985
Figure 296.Packing data in FIFO for transmission and reception. . . . .989
Figure 297.Master full-duplex communication . . . . .992
Figure 298. Slave full-duplex communication . . . . .993
Figure 299. Master full-duplex communication with CRC . . . . .994
Figure 300. Master full-duplex communication in packed mode . . . . .995
Figure 301. NSSP pulse generation in Motorola SPI master mode . . . . .998
Figure 302. TI mode transfer . . . . .999
Figure 303. IPCC block diagram . . . . .1012
Figure 304. IPCC Simplex channel mode transfer timing . . . . .1013
Figure 305. IPCC Simplex - Send procedure state diagram . . . . .1014
Figure 306. IPCC Simplex - Receive procedure state diagram . . . . .1015
Figure 307. IPCC Half-duplex channel mode transfer timing . . . . .1016
Figure 308. IPCC Half-duplex - Send procedure state diagram . . . . .1016
Figure 309. IPCC Half-duplex - Receive procedure state diagram . . . . .1017
Figure 310. HSEM block diagram . . . . .1026
Figure 311. Procedure state diagram . . . . .1027
Figure 312. Interrupt state diagram . . . . .1030
Figure 313. Block diagram of debug support infrastructure . . . . .1041
Figure 314. JTAG TAP state machine . . . . .1044
Figure 315. Debug and access port connections . . . . .1056
Figure 316. Embedded cross trigger . . . . .1063
Figure 317. Mapping trigger inputs to outputs . . . . .1065
Figure 318. Cross trigger configuration example . . . . .1066
Figure 319. CPU2 CoreSight™ topology . . . . .1092
Figure 320. CPU1 CoreSight™ topology . . . . .1127
Figure 321. Trace port interface unit (TPIU) . . . . .1162

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