35. Revision history

Updated Section 3.5: FLASH UID64, CPU2 secure SRAM2 areas, Section 6.1.1: Independent analog peripherals supply, Section 6.4.12: Auto wake-up from Low-power mode, Section 6.6.3: PWR control register 3 (PWR_CR3), Section 7.2: Clocks, External source, Section 7.2.2: HSI16 clock, Section 7.2.8: LSI2 clock, Section 7.4.1: RCC clock control register (RCC_CR), Section 7.4.29: RCC control/status register (RCC_CSR), Reading the temperature, Calculating the actual V _DDA voltage using the internal reference voltage, Section 16.3.3: Random number generation, Section 17.1: Introduction, Section 17.2: AES main features, Section 17.4.4: AES procedure to perform a cipher operation, Section 17.4.5: AES decryption round key preparation, Section 17.4.13: AES data registers and data swapping, Section 17.4.16: AES DMA interface, Section 17.4.17: AES error management, Section 32.5: Access ports, Example configurations, Section 32.10: CPU2 data watchpoint and trace unit (DWT), Section 32.14: CPU1 data watchpoint and trace unit (DWT) and Section 32.19: References.

Added note in Section 3.8: FLASH interrupts, Section 18.3.3: PKA reset and clocks, Table 149: Interrupt control bits.

Updated Table 2: Boot modes, Table 3: Flash memory - Single bank organization, Table 23: Functionalities depending on system operating mode, Table 37: RCC register map and reset values, Table 56: Wakeup interrupt table, Table 89: Processing latency for ECB, CBC and CTR, Table 117: Modular exponentiation computation times, Table 118: ECC scalar multiplication computation times, Table 119: ECDSA signature average computation times, Table 120: ECDSA verification average computation times, Table 120: ECDSA verification average computation times, Table 148: Effect of low-power modes on RTC, Table 197: CPU1 CTI inputs and Table 207: CPU1 ROM table.

Updated Figure 14: Clock tree, Figure 19: Three-volt or Five-volt tolerant GPIO structure (TT or FT), Figure 20: Input floating / pull up / pull down configurations, Figure 21: Output configuration, Figure 22: Alternate function configuration, Figure 23: High impedance-analog configuration, Figure 347: Embedded cross trigger and Figure 351: CPU1 CoreSight™ topology.

Removed former Table 88: DMA channel configuration for memory-to-AES data transfer and Table 89: DMA channel configuration for AES-to-memory data transfer.

Removed former Figure 20: Basic structure of a 5-Volt tolerant I/O port bit and Figure 347: Debugger connection to debug components.

Minor text edits across the whole document.

Added STM32WB30CE devices.

Updated Introduction , PCROP1A start address option bytes , PCROP1A end address option bytes , WRP Area A address option bytes , WRP Area B address option bytes , PCROP1B start address option bytes , PCROP1B end address option bytes , Section 3.10.5: Flash memory control register (FLASH_CR) , sections 3.10.8 to 3.10.13, Section 3.10.17: Flash memory CPU2 control register (FLASH_C2CR) , Section 8.3.2: I/O pin alternate function multiplexer and mapping , Calculating the actual V _DDA voltage using the internal reference voltage , Montgomery space and fast mode operations , Section 18.7.2: PKA status register (PKA_SR) , Section 18.7.2: PKA status register (PKA_SR) , Section 19.4.1: TIM1 control register 1 (TIM1_CR1) , Section 19.4.8: TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) , Section 19.4.20: TIM1 break and dead-time register (TIM1_BDTR) , Section 19.4.27: TIM1 alternate function option register 1 (TIM1_AF1) , Section 19.4.28: TIM1 Alternate function register 2 (TIM1_AF2) , Section 20.4.8: TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) , Section 22.2: LPTIM main features , Section 22.7.1: LPTIM interrupt and status register (LPTIM_ISR) , Section 22.7.2: LPTIM interrupt clear register (LPTIM_ICR) , Section 32.1: Introduction , Section 32.4.7: DP data link control register (DP_DLCR) , Section 32.5.1: AP control/status word register (AP_CSWR) , Section 32.5.5: AP base address register (AP_BASER) , Section 32.5.6: AP identification register (AP_IDR) , Section 32.8.2: DBGMCU configuration register (DBGMCU_CR) , Section 32.8.4: DBGMCU CPU2 APB1 peripheral freeze register 1 (DBGMCU_C2APB1FZR1) and Section 32.8.8: DBGMCU CPU2 APB2 peripheral freeze register (DBGMCU_C2APB2FZR) .

Updated Table 3: Flash memory - Single bank organization , Table 117: Modular exponentiation computation times , Table 122: Montgomery parameters average computation times , Table 197: CPU1 CTI inputs and Table 207: CPU1 ROM table .

Updated Figure 14: Clock tree , Figure 138: Control circuit in normal mode, internal clock divided by 1 , Figure 144: Capture/compare channel 1 main circuit , Figure 175: General-purpose timer block diagram , Figure 224: TIM16/TIM17 block diagram and Figure 238: Capture/compare channel 1 main circuit .

Added Note: to Section 7.4.3: RCC clock configuration register (RCC_CFGR) , Table 121: Point on elliptic curve Fp check average computation times , Table 139: LPTIM implementation and Section 21.3.18: Using timer output as trigger for other timers (TIM16/TIM17) .

Minor text edits across the whole document.

Updated Introduction , Related documents , Section 2.1: System architecture , Section 3.10.5: Flash memory control register (FLASH_CR) , Section 3.10.6: Flash memory ECC register (FLASH_ECCR) , Section 3.10.8: Flash memory PCROP zone A start address register (FLASH_PCROP1ASR) , Section 4.1: Introduction , Section 4.2: Main features , Polynomial programmability , Section 6.1.1: Independent analog peripherals supply , Entering Stop0 mode , Entering Stop2 mode , Section 6.6.2: PWR control register 2 (PWR_CR2) , Section 6.6.6: PWR status register 2 (PWR_SR2) , Section 7.2: Clocks , Section 7.4.1: RCC clock control register (RCC_CR) , Section 7.4.4: RCC PLL configuration register (RCC_PLLCFGR) , Section 9.2.13: SYSCFG CPU1 interrupt mask register 2 (SYSCFG_IMR2) , Section 9.2.15: SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2) , Section 12.4.4: DMAMUX request line multiplexer , Section 12.4.5: DMAMUX request generator , Section 15.3.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) , Triggered injection mode , Clock ratio constraint between ADC clock and AHB clock , Section 18.3.3: PKA reset and clocks , Montgomery space and fast mode operations , Enabling/disabling PKA , Using precomputed Montgomery parameters (PKA fast mode) , sections 18.7.2: PKA status register (PKA_SR) to 18.7.4: PKA RAM and Section 22.7.1: LPTIM interrupt and status register (LPTIM_ISR) .

Updated Figure 5: Radio system block diagram and Figure 14: Clock tree .

Updated Table 23: Functionalities depending on system operating mode , Table 33: PWR register map and reset values , Table 40: SYSCFG register map and reset values , Table 54: CPU1 vector table , Table 55: CPU2 vector table , Table 56: Wakeup interrupt table , Table 64: ADC input/output pins and Table 122: Montgomery parameters average computation times .

Added footnotes 1 and 2 to Table 1: STM32WB50CG/30CE memory map and peripheral register boundary addresses .

Removed former Section 6.2.3: Peripheral voltage monitoring (PVM) and Table 139: LPTIM implementation .

Minor text edits across the whole document.

Updated Section 3.5: FLASH UID64 , Section 5.2: CRC main features , Section 7.2.8: LSI2 clock , Section 7.2.12: Clock security system on LSE (LSECSS) , Section 19.3.16: Using the break function , Section 19.4.8: TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) , Section 20.4.8: TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) , Section 21.3.11: Using the break function , Section 24.3.14: Calibration clock output , Section 28.8.3: USART control register 2 (USART_CR2) and Section 32.8.1: DBGMCU identity code register (DBGMCU_IDCODE) .

Added Section 21.3.13: 6-step PWM generation .

Changed SCLK into CK throughout Section 28: Universal synchronous/asynchronous receiver transmitter (USART/UART) .

Minor text edits across the whole document.

Updated Figure 6: CRC calculation unit block diagram , Figure 115: Advanced-control timer block diagram , Figure 138: Control circuit in normal mode, internal clock divided by 1 , Figure 234: Control circuit in normal mode, internal clock divided by 1 , Figure 294: TC/TXE behavior when transmitting , Figure 295: Start bit detection when oversampling by 16 or 8 and Figure 303: USART example of synchronous master transmission .

Updated Table 200: DBGMCU register map and reset values .

Updated Section 3.3.1: Flash memory organization , Section 3.5: FLASH UID64 , DMA operation in different operating modes , Section 6.4.4: Exiting Low-power mode , Section 7.4.31: RCC clock HSE register (RCC_HSECR) , Section 15.3.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) , Section 16.2: RNG main features , Section 28.5.20: RS232 hardware flow control and RS485 Driver Enable , Section 28.8.4: USART control register 3 (USART_CR3) , Section 32.7.3: CTI application trigger set register (CTI_APPSETR) , and Section 32.8.1: DBGMCU identity code register (DBGMCU_IDCODE) .

Updated Figure 14: Clock tree . Figure 106: GCM authenticated encryption , Figure 270: Transfer bus diagrams for I2C slave transmitter (mandatory events only) , Figure 273: Transfer bus diagrams for I2C slave receiver (mandatory events only) , and Figure 280: Transfer bus diagrams for I2C master transmitter (mandatory events only) .

Updated Table 64: ADC input/output pins and Table 180: SPI register map and reset values .

Added Section 15.4: ADC in low-power mode , Section 33.4: Part number codification register , and Section 34: Important security notice .

Minor text edits across the whole document.

Updated Introduction , Section 4.1: Introduction , Section 4.2: Main features , Section 7.4.28: RCC backup domain control register (RCC_BDCR) , Section 7.4.29: RCC control/status register (RCC_CSR) , Section 7.4.31: RCC clock HSE register (RCC_HSECR) , Analog watchdog , and Section 32.8.2: DBGMCU configuration register (DBGMCU_CR) .

Updated Figure 14: Clock tree .

Minor text edits across the whole document.

Added Empty check and Caution in Section 3.3.6: Flash memory program and erase operations .

Updated Section 3.3.7: Flash main memory erase sequences , Section 3.3.8: Flash main memory programming sequences , note in Section 3.6.1: Read protection (RDP) , Section 3.10.4: Flash memory status register (FLASH_SR) , Section 3.10.5: Flash memory control register (FLASH_CR) , Section 3.10.19: Flash memory secure SRAM2 start address and CPU2 reset vector register (FLASH_SRRVR) , Section 6.2.2: Programmable voltage detector (PVD) , Section 7.1.2: System reset , Section 7.4.31: RCC clock HSE register (RCC_HSECR) , Converting a supply-relative ADC measurement to an absolute voltage value , Section 19.4.7: TIM1 capture/compare mode register 1 (TIM1_CCMR1) , Section 20.4.7: TIM2 capture/compare mode register 1 (TIM2_CCMR1) , Section 26.4: WWDG interrupts , Section 26.5.2: WWDG configuration register (WWDG_CFR) , Section 32.4.11: DP access port select register (DP_SELECTR) , and Section 32.7.3: CTI application trigger set register (CTI_APPSETR) .

Added footnote 2 to Table 9: Option bytes organization .

Updated Figure 109: Surface charge transfer analog I/O group structure , Figure 110: Sampling capacitor voltage variation , and Figure 259: Watchdog block diagram .

Updated Table 193: Debug port register map and reset values .

Minor text edits across the whole document.

Updated Introduction , Section 3.5: FLASH_UID64 , Section 3.10.16: Flash memory CPU2 status register (FLASH_C2SR) , Section 4.1: Introduction , Section 4.2: Main features , Entering Stop0 mode , Section 6.4.8: Stop1 mode , Entering Stop2 mode , Section 7.2.8: LSI2 clock , Section 7.2.19: Clock-out capability , Section 20.3.4: Charge transfer acquisition sequence , Section 19.3.22: Encoder interface mode , and Section 20.3.15: Encoder interface mode .

Updated Figure 2: Memory map , Figure 258: Independent watchdog block diagram , Figure 264: I2C initialization flow , and Figure 267: Slave initialization flow .

Minor text edits across the whole document.