10. Peripherals interconnect matrix

10.1 Introduction

Several peripherals have direct connections, enabling autonomous communication and/or synchronization between them. This saves CPU resources and, consequently, reduces power consumption. In addition, these hardware connections remove software latency and result in more predictable system design.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes.

10.2 Connection summary

Table 41. Peripherals interconnect matrix ^{(1) (2)}

1. Numbers in table are links to corresponding subsections of Section 10.3: Interconnection details .

2. The “-” symbol in grayed cells means no interconnect.

10.3 Interconnection details

10.3.1 From timer (TIM1/TIM2/TIM17) to timer (TIM1/TIM2)

Purpose

Some of the timers are linked together internally for synchronization or chaining.

When one timer is configured in Master Mode, it can reset, start, stop or clock the counter of another timer configured in Slave Mode. A description of the feature is provided in Section 19.3.26: Timer synchronization .

The modes of synchronization are detailed in:

• • Section 19.3.26: Timer synchronization for advanced-control timers (TIM1)
• • Section 20.3.18: Timers and external trigger synchronization for general-purpose timers (TIM2)

Triggering signals

The output (from Master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1) following a configurable timer event. The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.

The input and output signals for TIM1 are shown in Figure 115: Advanced-control timer block diagram .

The possible master/slave connections are given in:

• • Table 128: TIM1 internal trigger connection
• • Table 132: TIM2 internal trigger connection

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep.

10.3.2 From timer (TIM1/TIM2) and EXTI to ADC (ADC1)

Purpose

General-purpose timer TIM2, advanced-control timer TIM1 and EXTI can be used to generate an ADC triggering event.

TIMx synchronization is described in Section 19.3.27: ADC synchronization .

ADC synchronization is described in Section 16.4: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) .

Triggering signals

The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.

The input (to ADC) is on signals EXT[15:0] and JEXT[15:0].

The connection between timers and ADC is provided in:

• • Table 67: ADC1 - External triggers for regular channels
• • Table 68: ADC1 - External trigger for injected channels

Run, Sleep, Low-power run, Low-power sleep.

ADC1 can provide trigger event through watchdog signals to advanced-control timers (TIM1).

A description of the ADC analog watchdog setting is provided in Section 15.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) .

Trigger settings on the timer are provided in Section 19.3.4: External trigger input .

The output (from ADC) is on signals ADC_AWDx_OUT n = 1, 2, 3 (for ADC1) x = 1, 2, 3 (three watchdogs on ADC) and the input (to timer) on signal TIMx_ETR (external trigger).

Run, Sleep, Low-power run, Low-power sleep.

External clocks (HSE, LSE), internal clocks (LSI, MSI), microcontroller output clock (MCO), GPIO and RTC wakeup interrupt can be used as input to general-purpose timers (TIM16/17) channel 1.

This makes possible calibration of the HSI16/MSI system clocks (with TIM16 and LSE) or of the LSI (with TIM16 and HSE). This is also used to precisely measure LSI (with TIM16 and HSI16) or MSI (with TIM17 and HSI16) oscillator frequency.

When Low Speed External (LSE) oscillator is used, no additional hardware connections are required.

This feature is described in Section 7.2.20: Internal/external clock measurement with TIM16/TIM17 .

External clock LSE can be used as input to general-purpose timer (TIM2) on TIM2_ETR pin, see Section 7.2.20: Internal/external clock measurement with TIM16/TIM17 ..

Run, Sleep, Low-power run, Low-power sleep.

10.3.5 From RTC to low-power timers (LPTIM1/LPTIM2)

Purpose

RTC alarm A/B, RTC_TAMP2 input detection can be used as trigger to start LPTIM counters (LPTIM1/2).

Triggering signals

This trigger feature is described in Section 22.4.7: Trigger multiplexer (and following sections).

The input selection is described in Table 141: LPTIM1 external trigger connection and Table 142: LPTIM2 external trigger connection .

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep, Stop 0, Stop 1, Stop 2 (LPTIM1 only).

10.3.6 From internal analog to ADC1

Purpose

Internal temperature sensor (VTS), internal reference voltage (VREFINT) and VBAT monitoring channel are connected to ADC1 input channel.

This is according to:

• • Section 16.2: ADC main features
• • Section 16.3.8: Channel selection (CHSEL, SCANDIR, CHSELRMOD)
• • Section 16.9: Temperature sensor and internal reference voltage
• • Section 16.10: Battery voltage monitoring

Active power mode(s)

Run, Sleep, low-power run, Low-power sleep.

10.3.7 From system errors to timers (TIM1/TIM16/TIM17)

Purpose

CSS, CPU hard fault, RAM parity error, FLASH ECC double error detection, PVD can generate system errors in the form of timer break toward timers TIM1/TIM16/TIM17.

The purpose of the break function is to protect power switches driven by PWM signals generated by the timers.

List(s) of possible break source(s) are described in:

• • Section 19.3.16: Using the break function (TIM1)
• • Section 21.3.11: Using the break function (TIM16/TIM17)
• • Figure 224: TIM16/TIM17 block diagram

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep.

10.3.8 From timers (TIM16/TIM17) to IRTIM

Purpose

General-purpose timer (TIM16/TIM17) output channel TIMx_OC1 are used to generate the waveform of infrared signal output.

The functionality is described in Section 23: Infrared interface (IRTIM) .

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep.