4. Radio system
4.1 Introduction
The system is ultra low power compliant with the Bluetooth® core specification BLE5.4 and IEEE 802.15.4 standard.
The radio system consists of a 2.4 GHz RF front end and a Bluetooth® Low Energy (BLE) and IEEE 802.15.4 physical layer controller. The system is controlled from the CPU2 that contains the radio lower protocol software layers. Interface to the application running on the CPU2 is provided via mailbox message system.
4.2 Main features
- • 2.4 GHz RF transceiver supporting:
- – Bluetooth® BLE5.4 standard support
- – IEEE 802.15.4-2011 standard support
- • Programmable output power
- • RSSI
- • Integrated balun
- • Bluetooth® BLE5.4 features:
- – GAP: central, peripheral, observer and broadcaster roles
- – Simultaneous multiple role support
- – Master / slave support
- – ATT / GATT: client and server
4.3 Radio system functional description
4.3.1 General description
The block diagram of the Radio system is shown in Figure 5 .
Figure 5. Radio system block diagram
The block diagram illustrates the internal architecture of the radio system. At the top, 'Timer and Power control' and 'AGC' blocks are present. Below them, 'RF control' connects to a 'BLE controller' and an '802.15.4 MAC'. The 'BLE controller' is linked to 'Interrupt', 'Wakeup', 'AHB', and 'APB' interfaces, and it connects to 'BLE modulator' and 'BLE demodulator' blocks. The '802.15.4 MAC' is connected to 'APB', 'Interrupt', and 'Wakeup' interfaces, and it connects to '802.15.4 modulator' and '802.15.4 demodulator' blocks. These modulators connect to a 'Modulator' block, which in turn connects to a 'PLL' block. The 'PLL' block is connected to a 'PA' (Power Amplifier) block and a 'PA ramp generator' block. The 'PA' block is connected to an 'LNA' (Low Noise Amplifier) block. The 'LNA' block is connected to a 'BP filter' (Band Pass Filter) block. The 'BP filter' block is connected to two 'ADC' (Analog-to-Digital Converter) blocks. The 'ADC' blocks are connected to the 'AGC' block. The 'AGC' block is connected to the 'PA' block. The 'PA' block is connected to an 'RF1' pin and a 'See note' pin. The 'RF1' pin is connected to an external antenna. The 'See note' pin is connected to a 'Trimmed bias' block. The 'Trimmed bias' block is connected to a 'V DDRF ' pin. The 'V DDRF ' pin is connected to an external capacitor. The 'V DD ' pin is connected to three 'LDO' (Low Dropout Regulator) blocks. The 'LDO' blocks are connected to the 'PA' block and the 'Trimmed bias' block. The 'Max PA level' is indicated on the 'Trimmed bias' block. The 'HSE' (High Speed External) oscillator is connected to 'OSC_IN' and 'OSC_OUT' pins. The 'OSC_IN' pin is connected to a 32 MHz crystal. The 'OSC_OUT' pin is connected to an 'Adjust' capacitor. The 'HSE' block is connected to the 'PLL' block.
Note: on QFN packages V SS through exposed pad, and V SSRF pin must be connected to ground plane