RM0471-STM32WB50CG-30CE

Introduction

This document is addressed to application developers. It provides complete information on how to use the STM32WB50CG/30CE microcontroller memory and peripherals.

These multiprotocol wireless and ultra-low-power devices embed a powerful and ultra-low-power radio compliant with the Bluetooth ® Low Energy SIG specification 5.4 and with IEEE 802.15.4-2011. They contain a dedicated Arm ® Cortex ® -M0+ core for performing the real-time low layer operation, and include ST state of the art patented technology.

The STM32WB50CG provides value line microcontrollers with 1 Mbyte flash memory and 128 Kbyte SRAM.

The STM32WB30CE provides value line microcontrollers with 512 Kbyte flash memory and 96 Kbyte SRAM.

Available from STMicroelectronics website www.st.com :

For information on the Arm ® Cortex ® -M4 and Cortex ® -M0+ cores refer, to the corresponding technical reference manuals, available from the www.arm.com website.

For information on 802.15.4 refer to the IEEE website ( www.ieee.org ).

For information on Bluetooth ® refer to www.bluetooth.com .

Contents

1Documentation conventions . . . . .51
1.1General information . . . . .51
1.2List of abbreviations for registers . . . . .51
1.3Glossary . . . . .52
1.4Availability of peripherals . . . . .52
2System and memory overview . . . . .53
2.1System architecture . . . . .53
2.1.1S0: CPU1 (CPU1 Cortex®-M4) I-bus . . . . .54
2.1.2S1: CPU1 (CPU1 Cortex®-M4) D-bus . . . . .54
2.1.3S2: CPU1 (CPU1 Cortex®-M4) S-bus . . . . .54
2.1.4S3: CPU2 (Cortex®-M0+) S-bus . . . . .55
2.1.5S4: DMA-bus . . . . .55
2.1.6S6: Radio system-bus . . . . .55
2.1.7BusMatrix . . . . .55
2.2Memory organization . . . . .56
2.2.1Introduction . . . . .56
2.2.2Memory map and register boundary addresses . . . . .57
2.2.3Bit banding . . . . .61
2.3Boot configuration . . . . .61
2.4CPU2 boot . . . . .63
2.5CPU2 SRAM fetch disable . . . . .63
3Embedded flash memory (FLASH) . . . . .64
3.1Introduction . . . . .64
3.2FLASH main features . . . . .64
3.3FLASH functional description . . . . .65
3.3.1Flash memory organization . . . . .65
3.3.2Empty check . . . . .66
3.3.3Error code correction (ECC) . . . . .66
3.3.4Read access latency . . . . .66
3.3.5Adaptive real-time memory accelerator (ART Accelerator) . . . . .68
3.3.6Flash memory program and erase operations . . . . .71
3.3.7Flash main memory erase sequences . . . . .72
3.3.8Flash main memory programming sequences . . . . .74
3.4FLASH option bytes . . . . .79
3.4.1Option bytes description . . . . .79
3.4.2Option bytes programming . . . . .86
3.5FLASH UID64 . . . . .88
3.6Flash memory protection . . . . .89
3.6.1Read protection (RDP) . . . . .89
3.6.2Proprietary code readout protection (PCROP) . . . . .93
3.6.3Write protection (WRP) . . . . .94
3.6.4CPU2 security (ESE) . . . . .95
3.7FLASH program/erase suspension . . . . .96
3.8FLASH interrupts . . . . .97
3.9Register access protection . . . . .97
3.10FLASH registers . . . . .98
3.10.1Flash memory access control register (FLASH_ACR) . . . . .98
3.10.2Flash memory key register (FLASH_KEYR) . . . . .99
3.10.3Flash memory option key register (FLASH_OPTKEYR) . . . . .99
3.10.4Flash memory status register (FLASH_SR) . . . . .100
3.10.5Flash memory control register (FLASH_CR) . . . . .101
3.10.6Flash memory ECC register (FLASH_ECCR) . . . . .103
3.10.7Flash memory option register (FLASH_OPTR) . . . . .104
3.10.8Flash memory PCROP zone A start address register
(FLASH_PCROP1ASR) . . . . .		106
3.10.9Flash memory PCROP zone A end address register
(FLASH_PCROP1AER) . . . . .		107
3.10.10Flash memory WRP area A address register (FLASH_WRP1AR) . . . . .107
3.10.11Flash memory WRP area B address register (FLASH_WRP1BR) . . . . .108
3.10.12Flash memory PCROP zone B start address register
(FLASH_PCROP1BSR) . . . . .		108
3.10.13Flash memory PCROP zone B end address register
(FLASH_PCROP1BER) . . . . .		109
3.10.14Flash memory IPCC mailbox data buffer address register
(FLASH_IPCCBR) . . . . .		109
3.10.15Flash memory CPU2 access control register (FLASH_C2ACR) . . . . .109
3.10.16Flash memory CPU2 status register (FLASH_C2SR) . . . . .110
3.10.17Flash memory CPU2 control register (FLASH_C2CR) . . . . .112
3.10.18Secure flash memory start address register (FLASH_SFR) . . . . .113

3.10.19 Flash memory secure SRAM2 start address and CPU2 reset vector register (FLASH_SRRVR) . . . . . 114

3.10.20 FLASH register map . . . . . 116

4 Radio system . . . . . 118

4.1 Introduction . . . . . 118

4.2 Main features . . . . . 118

4.3 Radio system functional description . . . . . 119

4.3.1 General description . . . . . 119

5 Cyclic redundancy check calculation unit (CRC) . . . . . 120

5.1 Introduction . . . . . 120

5.2 CRC main features . . . . . 120

5.3 CRC functional description . . . . . 121

5.3.1 CRC block diagram . . . . . 121

5.3.2 CRC internal signals . . . . . 121

5.3.3 CRC operation . . . . . 121

5.4 CRC registers . . . . . 123

5.4.1 CRC data register (CRC_DR) . . . . . 123

5.4.2 CRC independent data register (CRC_IDR) . . . . . 123

5.4.3 CRC control register (CRC_CR) . . . . . 124

5.4.4 CRC initial value (CRC_INIT) . . . . . 125

5.4.5 CRC polynomial (CRC_POL) . . . . . 125

5.4.6 CRC register map . . . . . 126

6 Power control (PWR) . . . . . 127

6.1 Power supplies . . . . . 127

6.1.1 Independent analog peripherals supply . . . . . 128

6.1.2 Battery backup domain . . . . . 128

6.1.3 Voltage regulator . . . . . 130

6.2 Power supply supervisor . . . . . 130

6.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) . . . . . 130

6.2.2 Programmable voltage detector (PVD) . . . . . 131

6.3 CPU2 boot . . . . . 132

6.4 Low-power modes . . . . . 134

6.4.1 Run mode . . . . . 140

6.4.2Low-power run mode (LP run) . . . . .140
6.4.3Entering Low-power mode . . . . .141
6.4.4Exiting Low-power mode . . . . .141
6.4.5Sleep mode . . . . .142
6.4.6Low-power sleep mode (LP sleep) . . . . .143
6.4.7Stop0 mode . . . . .144
6.4.8Stop1 mode . . . . .146
6.4.9Stop2 mode . . . . .147
6.4.10Standby mode . . . . .149
6.4.11Shutdown mode . . . . .151
6.4.12Auto wake-up from Low-power mode . . . . .152
6.5Real-time radio information . . . . .153
6.6PWR registers . . . . .154
6.6.1PWR control register 1 (PWR_CR1) . . . . .154
6.6.2PWR control register 2 (PWR_CR2) . . . . .155
6.6.3PWR control register 3 (PWR_CR3) . . . . .156
6.6.4PWR control register 4 (PWR_CR4) . . . . .157
6.6.5PWR status register 1 (PWR_SR1) . . . . .158
6.6.6PWR status register 2 (PWR_SR2) . . . . .159
6.6.7PWR status clear register (PWR_SCR) . . . . .159
6.6.8PWR Port A pull-up control register (PWR_PUCRA) . . . . .160
6.6.9PWR Port A pull-down control register (PWR_PDCRA) . . . . .161
6.6.10PWR Port B pull-up control register (PWR_PUCRB) . . . . .161
6.6.11PWR Port B pull-down control register (PWR_PDCRB) . . . . .162
6.6.12PWR Port C pull-up control register (PWR_PUCRC) . . . . .162
6.6.13PWR Port C pull-down control register (PWR_PDCRC) . . . . .163
6.6.14PWR Port E pull-up control register (PWR_PUCRE) . . . . .163
6.6.15PWR Port E pull-down control register (PWR_PDCRE) . . . . .163
6.6.16PWR Port H pull-up control register (PWR_PUCRH) . . . . .164
6.6.17PWR Port H pull-down control register (PWR_PDCRH) . . . . .164
6.6.18PWR CPU2 control register 1 (PWR_C2CR1) . . . . .165
6.6.19PWR CPU2 control register 3 (PWR_C2CR3) . . . . .166
6.6.20PWR extended status and status clear register (PWR_EXTSCR) . . . . .167
6.6.21PWR register map and reset value table . . . . .169
7Reset and clock control (RCC) . . . . .171
7.1Reset . . . . .171
7.4.11RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . .207
7.4.12RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . .208
7.4.13RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .208
7.4.14RCC APB3 peripheral reset register (RCC_APB3RSTR) . . . . .209
7.4.15RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .210
7.4.16RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .211
7.4.17RCC AHB3 and AHB4 peripheral clock enable register
(RCC_AHB3ENR) . . . . .		212
7.4.18RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . .213
7.4.19RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . .213
7.4.20RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .214
7.4.21RCC AHB1 peripheral clocks enable in Sleep modes register
(RCC_AHB1SMENR) . . . . .		215
7.4.22RCC AHB2 peripheral clocks enable in Sleep modes register
(RCC_AHB2SMENR) . . . . .		216
7.4.23RCC AHB3 and AHB4 peripheral clocks enable in Sleep and Stop
modes register (RCC_AHB3SMENR) . . . . .		217
7.4.24RCC APB1 peripheral clocks enable in Sleep mode register 1
(RCC_APB1SMENR1) . . . . .		218
7.4.25RCC APB1 peripheral clocks enable in Sleep mode register 2
(RCC_APB1SMENR2) . . . . .		219
7.4.26RCC APB2 peripheral clocks enable in Sleep mode register
(RCC_APB2SMENR) . . . . .		219
7.4.27RCC peripherals independent clock configuration register
(RCC_CCIPR) . . . . .		220
7.4.28RCC backup domain control register (RCC_BDCR) . . . . .222
7.4.29RCC control/status register (RCC_CSR) . . . . .224
7.4.30RCC clock recovery RC register (RCC_CRRRCR) . . . . .226
7.4.31RCC clock HSE register (RCC_HSECR) . . . . .226
7.4.32RCC extended clock recovery register (RCC_EXTCFGR) . . . . .227
7.4.33RCC CPU2 AHB1 peripheral clock enable register
(RCC_C2AHB1ENR) . . . . .		230
7.4.34RCC CPU2 AHB2 peripheral clock enable register
(RCC_C2AHB2ENR) . . . . .		230
7.4.35RCC CPU2 AHB3 and AHB4 peripheral clock enable register
(RCC_C2AHB3ENR) . . . . .		231
7.4.36RCC CPU2 APB1 peripheral clock enable register 1
(RCC_C2APB1ENR1) . . . . .		232
7.4.37RCC CPU2 APB1 peripheral clock enable register 2
(RCC_C2APB1ENR2) . . . . .		233
7.4.38RCC CPU2 APB2 peripheral clock enable register (RCC_C2APB2ENR) . . . . .234
7.4.39RCC CPU2 APB3 peripheral clock enable register (RCC_C2APB3ENR) . . . . .235
7.4.40RCC CPU2 AHB1 peripheral clocks enable in Sleep modes register (RCC_C2AHB1SMENR) . . . . .235
7.4.41RCC CPU2 AHB2 peripheral clocks enable in Sleep modes register (RCC_C2AHB2SMENR) . . . . .236
7.4.42RCC CPU2 AHB3 and AHB4 peripheral clocks enable in Sleep mode register (RCC_C2AHB3SMENR) . . . . .237
7.4.43RCC CPU2 APB1 peripheral clocks enable in Sleep mode register 1 (RCC_C2APB1SMENR1) . . . . .238
7.4.44RCC CPU2 APB1 peripheral clocks enable in Sleep mode register 2 (RCC_C2APB1SMENR2) . . . . .239
7.4.45RCC CPU2 APB2 peripheral clocks enable in Sleep mode register (RCC_C2APB2SMENR) . . . . .240
7.4.46RCC CPU2 APB3 peripheral clock enable in Sleep mode register (RCC_C2APB3SMENR) . . . . .241
7.4.47RCC register map . . . . .242
8General-purpose I/Os (GPIO) . . . . .248
8.1Introduction . . . . .248
8.2GPIO main features . . . . .248
8.3GPIO functional description . . . . .248
8.3.1General-purpose I/O (GPIO) . . . . .251
8.3.2I/O pin alternate function multiplexer and mapping . . . . .251
8.3.3I/O port control registers . . . . .252
8.3.4I/O port data registers . . . . .252
8.3.5I/O data bitwise handling . . . . .252
8.3.6GPIO locking mechanism . . . . .253
8.3.7I/O alternate function input/output . . . . .253
8.3.8External interrupt/wake-up lines . . . . .253
8.3.9Input configuration . . . . .253
8.3.10Output configuration . . . . .254
8.3.11Alternate function configuration . . . . .255
8.3.12Analog configuration . . . . .255
8.3.13Using the LSE oscillator pins as GPIOs . . . . .256
8.3.14Using the GPIO pins in the RTC supply domain . . . . .256
8.3.15Using PH3 as GPIO . . . . .256
8.4GPIO registers . . . . .257
8.4.1GPIO port mode register (GPIOx_MODER)
(x = A to C and E and H) . . . . .		257
8.4.2GPIO port output type register (GPIOx_OTYPER)
(x = A to C and E and H) . . . . .		258
8.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to C and E and H) . . . . .		258
8.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to C and E and H) . . . . .		259
8.4.5GPIO port input data register (GPIOx_IDR)
(x = A to C and E and H) . . . . .		260
8.4.6GPIO port output data register (GPIOx_ODR)
(x = A to C and E and H) . . . . .		260
8.4.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to C and E and H) . . . . .		261
8.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to C and E and H) . . . . .		261
8.4.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to C and E and H) . . . . .		263
8.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to C and E and H) . . . . .		264
8.4.11GPIO port bit reset register (GPIOx_BRR) (x = A to C and E and H) . . . . .265
8.4.12GPIO register map . . . . .266
9System configuration controller (SYSCFG) . . . . .270
9.1SYSCFG main features . . . . .270
9.2SYSCFG registers . . . . .270
9.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .270
9.2.2SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .271
9.2.3SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		272
9.2.4SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . .		273
9.2.5SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . .		274
9.2.6SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . .		276
9.2.7SYSCFG SRAM2 control and status register (SYSCFG_SCSR) . . . . .277
9.2.8SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .278
9.2.9SYSCFG SRAM2 write protection register (SYSCFG_SWPR1) . . . . .279
9.2.10SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . .279
9.2.11SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2) . . .279
9.2.12SYSCFG CPU1 interrupt mask register 1 (SYSCFG_IMR1) . . . . .280
9.2.13SYSCFG CPU1 interrupt mask register 2 (SYSCFG_IMR2) . . . . .280
9.2.14SYSCFG CPU2 interrupt mask register 1 (SYSCFG_C2IMR1) . . . . .281
9.2.15SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2) . . . . .281
9.2.16SYSCFG secure IP control register (SYSCFG_SIPCR) . . . . .282
9.2.17SYSCFG register map . . . . .284
10Peripherals interconnect matrix . . . . .286
10.1Introduction . . . . .286
10.2Connection summary . . . . .286
10.3Interconnection details . . . . .287
10.3.1From timer (TIM1/TIM2/TIM17) to timer (TIM1/TIM2) . . . . .287
10.3.2From timer (TIM1/TIM2) and EXTI to ADC (ADC1) . . . . .287
10.3.3From ADC (ADC1) to timer (TIM1) . . . . .288
10.3.4From HSE, LSE, LSI, MSI, MCO, RTC to timers
(TIM2/TIM16/TIM17) . . . . .		288
10.3.5From RTC to low-power timers (LPTIM1/LPTIM2) . . . . .289
10.3.6From internal analog to ADC1 . . . . .289
10.3.7From system errors to timers (TIM1/TIM16/TIM17) . . . . .289
10.3.8From timers (TIM16/TIM17) to IRTIM . . . . .290
11Direct memory access controller (DMA) . . . . .291
11.1Introduction . . . . .291
11.2DMA main features . . . . .291
11.3DMA implementation . . . . .292
11.3.1DMA1 . . . . .292
11.3.2DMA request mapping . . . . .292
11.4DMA functional description . . . . .292
11.4.1DMA block diagram . . . . .292
11.4.2DMA pins and internal signals . . . . .293
11.4.3DMA transfers . . . . .293
11.4.4DMA arbitration . . . . .294
11.4.5DMA channels . . . . .294
11.4.6DMA data width, alignment, and endianness . . . . .298
11.4.7DMA error management . . . . .299
11.5DMA interrupts . . . . .300
11.6DMA registers . . . . .300
11.6.1DMA interrupt status register (DMA_ISR) . . . . .300
11.6.2DMA interrupt flag clear register (DMA_IFCR) . . . . .303
11.6.3DMA channel x configuration register (DMA_CCRx) . . . . .304
11.6.4DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .307
11.6.5DMA channel x peripheral address register (DMA_CPARx) . . . . .307
11.6.6DMA channel x memory address register (DMA_CMARx) . . . . .308
11.6.7DMA register map . . . . .308
12DMA request multiplexer (DMAMUX) . . . . .311
12.1Introduction . . . . .311
12.2DMAMUX main features . . . . .312
12.3DMAMUX implementation . . . . .312
12.3.1DMAMUX instantiation . . . . .312
12.3.2DMAMUX mapping . . . . .312
12.4DMAMUX functional description . . . . .315
12.4.1DMAMUX block diagram . . . . .315
12.4.2DMAMUX signals . . . . .316
12.4.3DMAMUX channels . . . . .316
12.4.4DMAMUX request line multiplexer . . . . .316
12.4.5DMAMUX request generator . . . . .319
12.5DMAMUX interrupts . . . . .320
12.6DMAMUX registers . . . . .321
12.6.1DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR) . . . . .321
12.6.2DMAMUX request line multiplexer interrupt channel status register (DMAMUX_CSR) . . . . .322
12.6.3DMAMUX request line multiplexer interrupt clear flag register (DMAMUX_CFR) . . . . .322
12.6.4DMAMUX request generator channel x configuration register (DMAMUX_RGxCR) . . . . .323
12.6.5DMAMUX request generator interrupt status register (DMAMUX_RGS) . . . . .324
12.6.6DMAMUX request generator interrupt clear flag register (DMAMUX_RGCFR) . . . . .324
12.6.7DMAMUX register map . . . . .325
13Nested vectored interrupt controller (NVIC) . . . . .327
15.3.1ADC block diagram . . . . .356
15.3.2ADC pins and internal signals . . . . .357
15.3.3ADC clocks . . . . .358
15.3.4ADC1 connectivity . . . . .360
15.3.5Slave AHB interface . . . . .361
15.3.6ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . . . . .361
15.3.7Single-ended and differential input channels . . . . .362
15.3.8Calibration (ADCAL, ADCALDIF, ADC_CALFACT) . . . . .362
15.3.9ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .365
15.3.10Constraints when writing the ADC control bits . . . . .366
15.3.11Channel selection (SQRx, JSQRx) . . . . .367
15.3.12Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .368
15.3.13Single conversion mode (CONT = 0) . . . . .368
15.3.14Continuous conversion mode (CONT = 1) . . . . .369
15.3.15Starting conversions (ADSTART, JADSTART) . . . . .370
15.3.16ADC timing . . . . .371
15.3.17Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .371
15.3.18Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .373
15.3.19Injected channel management . . . . .375
15.3.20Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .376
15.3.21Queue of context for injected conversions . . . . .377
15.3.22Programmable resolution (RES) - Fast conversion mode . . . . .385
15.3.23End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . . . .386
15.3.24End of conversion sequence (EOS, JEOS) . . . . .386
15.3.25Timing diagrams example (single/continuous modes, hardware/software triggers) . . . . .387
15.3.26Data management . . . . .389
15.3.27Dynamic low-power features . . . . .394
15.3.28Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . .399
15.3.29Oversampler . . . . .403
15.3.30Temperature sensor . . . . .408
15.3.31VBAT supply monitoring . . . . .410
15.3.32Monitoring the internal voltage reference . . . . .410
15.4ADC in low-power mode . . . . .412
15.5ADC interrupts . . . . .413
15.6ADC registers . . . . .414
15.6.1ADC interrupt and status register (ADC_ISR) . . . . .414
15.6.2ADC interrupt enable register (ADC_IER) . . . . .416
15.6.3ADC control register (ADC_CR) . . . . .418
15.6.4ADC configuration register (ADC_CFGR) . . . . .421
15.6.5ADC configuration register 2 (ADC_CFGR2) . . . . .425
15.6.6ADC sample time register 1 (ADC_SMPR1) . . . . .426
15.6.7ADC sample time register 2 (ADC_SMPR2) . . . . .427
15.6.8ADC watchdog threshold register 1 (ADC_TR1) . . . . .428
15.6.9ADC watchdog threshold register 2 (ADC_TR2) . . . . .428
15.6.10ADC watchdog threshold register 3 (ADC_TR3) . . . . .429
15.6.11ADC regular sequence register 1 (ADC_SQR1) . . . . .430
15.6.12ADC regular sequence register 2 (ADC_SQR2) . . . . .431
15.6.13ADC regular sequence register 3 (ADC_SQR3) . . . . .432
15.6.14ADC regular sequence register 4 (ADC_SQR4) . . . . .433
15.6.15ADC regular data register (ADC_DR) . . . . .433
15.6.16ADC injected sequence register (ADC_JSQR) . . . . .434
15.6.17ADC offset y register (ADC_OFRy) . . . . .436
15.6.18ADC injected channel y data register (ADC_JDRy) . . . . .437
15.6.19ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .437
15.6.20ADC analog watchdog 3 configuration register (ADC_AWD3CR) . . . . .438
15.6.21ADC differential mode selection register (ADC_DIFSEL) . . . . .438
15.6.22ADC calibration factors (ADC_CALFACT) . . . . .439
15.7ADC common registers . . . . .439
15.7.1ADC common status register (ADC_CSR) . . . . .439
15.7.2ADC common control register (ADC_CCR) . . . . .440
15.8ADC register map . . . . .442
16True random number generator (RNG) . . . . .445
16.1Introduction . . . . .445
16.2RNG main features . . . . .445
16.3RNG functional description . . . . .446
16.3.1RNG block diagram . . . . .446
16.3.2RNG internal signals . . . . .446
16.3.3Random number generation . . . . .447
16.3.4RNG initialization . . . . .449
16.3.5RNG operation . . . . .450
16.3.6RNG clocking . . . . .451
16.3.7Error management . . . . .451
16.3.8RNG low-power use . . . . .452
16.4RNG interrupts . . . . .453
16.5RNG processing time . . . . .453
16.6RNG entropy source validation . . . . .453
16.6.1Introduction . . . . .453
16.6.2Validation conditions . . . . .453
16.7RNG registers . . . . .454
16.7.1RNG control register (RNG_CR) . . . . .454
16.7.2RNG status register (RNG_SR) . . . . .454
16.7.3RNG data register (RNG_DR) . . . . .455
16.7.4RNG register map . . . . .456
17AES hardware accelerator (AES) . . . . .457
17.1Introduction . . . . .457
17.2AES main features . . . . .457
17.3AES implementation . . . . .457
17.4AES functional description . . . . .458
17.4.1AES block diagram . . . . .458
17.4.2AES internal signals . . . . .458
17.4.3AES cryptographic core . . . . .458
17.4.4AES procedure to perform a cipher operation . . . . .464
17.4.5AES decryption round key preparation . . . . .467
17.4.6AES ciphertext stealing and data padding . . . . .468
17.4.7AES task suspend and resume . . . . .468
17.4.8AES basic chaining modes (ECB, CBC) . . . . .469
17.4.9AES counter (CTR) mode . . . . .474
17.4.10AES Galois/counter mode (GCM) . . . . .476
17.4.11AES Galois message authentication code (GMAC) . . . . .481
17.4.12AES counter with CBC-MAC (CCM) . . . . .483
17.4.13AES data registers and data swapping . . . . .488
17.4.14AES key registers . . . . .490
17.4.15AES initialization vector registers . . . . .490
17.4.16AES DMA interface . . . . .491
18.4.2Montgomery parameter computation . . . . .513
18.4.3Modular addition . . . . .513
18.4.4Modular subtraction . . . . .514
18.4.5Modular and Montgomery multiplication . . . . .514
18.4.6Modular exponentiation . . . . .515
18.4.7Modular inversion . . . . .516
18.4.8Modular reduction . . . . .517
18.4.9Arithmetic addition . . . . .517
18.4.10Arithmetic subtraction . . . . .517
18.4.11Arithmetic multiplication . . . . .518
18.4.12Arithmetic comparison . . . . .518
18.4.13RSA CRT exponentiation . . . . .518
18.4.14Point on elliptic curve Fp check . . . . .519
18.4.15ECC Fp scalar multiplication . . . . .520
18.4.16ECDSA sign . . . . .521
18.4.17ECDSA verification . . . . .523
18.5Example of configurations and processing times . . . . .524
18.5.1Supported elliptic curves . . . . .524
18.5.2Computation times . . . . .526
18.6PKA interrupts . . . . .527
18.7PKA registers . . . . .528
18.7.1PKA control register (PKA_CR) . . . . .528
18.7.2PKA status register (PKA_SR) . . . . .529
18.7.3PKA clear flag register (PKA_CLRFR) . . . . .530
18.7.4PKA RAM . . . . .530
18.7.5PKA register map . . . . .531
19Advanced-control timer (TIM1) . . . . .532
19.1TIM1 introduction . . . . .532
19.2TIM1 main features . . . . .533
19.3TIM1 functional description . . . . .535
19.3.1Time-base unit . . . . .535
19.3.2Counter modes . . . . .537
19.3.3Repetition counter . . . . .548
19.3.4External trigger input . . . . .550
19.3.5Clock selection . . . . .551
19.4.10TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2) .....609
19.4.11TIM1 capture/compare enable register (TIM1_CCER) .....611
19.4.12TIM1 counter (TIM1_CNT) .....614
19.4.13TIM1 prescaler (TIM1_PSC) .....614
19.4.14TIM1 auto-reload register (TIM1_ARR) .....614
19.4.15TIM1 repetition counter register (TIM1_RCR) .....615
19.4.16TIM1 capture/compare register 1 (TIM1_CCR1) .....615
19.4.17TIM1 capture/compare register 2 (TIM1_CCR2) .....616
19.4.18TIM1 capture/compare register 3 (TIM1_CCR3) .....616
19.4.19TIM1 capture/compare register 4 (TIM1_CCR4) .....617
19.4.20TIM1 break and dead-time register (TIM1_BDTR) .....617
19.4.21TIM1 DMA control register (TIM1_DCR) .....621
19.4.22TIM1 DMA address for full transfer (TIM1_DMAR) .....622
19.4.23TIM1 option register 1 (TIM1_OR1) .....623
19.4.24TIM1 capture/compare mode register 3 (TIM1_CCMR3) .....623
19.4.25TIM1 capture/compare register 5 (TIM1_CCR5) .....624
19.4.26TIM1 capture/compare register 6 (TIM1_CCR6) .....625
19.4.27TIM1 alternate function option register 1 (TIM1_AF1) .....626
19.4.28TIM1 Alternate function register 2 (TIM1_AF2) .....627
19.4.29TIM1 timer input selection register (TIM1_TISEL) .....627
19.4.30TIM1 register map .....629
20General-purpose timer (TIM2) .....632
20.1TIM2 introduction .....632
20.2TIM2 main features .....632
20.3TIM2 functional description .....634
20.3.1Time-base unit .....634
20.3.2Counter modes .....636
20.4.17TIM2 capture/compare register 2 (TIM2_CCR2) . . . . .695
20.4.18TIM2 capture/compare register 3 (TIM2_CCR3) . . . . .696
20.4.19TIM2 capture/compare register 4 (TIM2_CCR4) . . . . .696
20.4.20TIM2 DMA control register (TIM2_DCR) . . . . .697
20.4.21TIM2 DMA address for full transfer (TIM2_DMAR) . . . . .698
20.4.22TIM2 option register 1 (TIM2_OR1) . . . . .698
20.4.23TIM2 alternate function option register 1 (TIM2_AF1) . . . . .698
20.4.24TIM2 timer input selection register (TIM2_TISEL) . . . . .699
20.4.25TIMx register map . . . . .700
21General-purpose timers (TIM16/TIM17) . . . . .703
21.1TIM16/TIM17 introduction . . . . .703
21.2TIM16/TIM17 main features . . . . .703
21.3TIM16/TIM17 functional description . . . . .705
21.3.1Time-base unit . . . . .705
21.3.2Counter modes . . . . .707
21.3.3Repetition counter . . . . .711
21.3.4Clock selection . . . . .712
21.3.5Capture/compare channels . . . . .714
21.3.6Input capture mode . . . . .716
21.3.7Forced output mode . . . . .717
21.3.8Output compare mode . . . . .717
21.3.9PWM mode . . . . .719
21.3.10Complementary outputs and dead-time insertion . . . . .720
21.3.11Using the break function . . . . .722
21.3.12Bidirectional break inputs . . . . .725
21.3.136-step PWM generation . . . . .726
21.3.14One-pulse mode . . . . .728
21.3.15UIF bit remapping . . . . .729
21.3.16Slave mode – combined reset + trigger mode . . . . .729
21.3.17DMA burst mode . . . . .729
21.3.18Using timer output as trigger for other timers (TIM16/TIM17) . . . . .730
21.3.19Debug mode . . . . .731
21.4TIM16/TIM17 registers . . . . .732
21.4.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .732
21.4.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .733
21.4.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .734
21.4.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .735
21.4.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .736
21.4.6TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 16 to 17) . . . . .		737
21.4.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . .		738
21.4.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . .740
21.4.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .742
21.4.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .743
21.4.11TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . .743
21.4.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .744
21.4.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .744
21.4.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .745
21.4.15TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .747
21.4.16TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . .748
21.4.17TIM16 option register 1 (TIM16_OR1) . . . . .749
21.4.18TIM16 alternate function register 1 (TIM16_AF1) . . . . .749
21.4.19TIM16 input selection register (TIM16_TISEL) . . . . .750
21.4.20TIM17 option register 1 (TIM17_OR1) . . . . .750
21.4.21TIM17 alternate function register 1 (TIM17_AF1) . . . . .750
21.4.22TIM17 input selection register (TIM17_TISEL) . . . . .751
21.4.23TIM16/TIM17 register map . . . . .752
22Low-power timer (LPTIM) . . . . .754
22.1Introduction . . . . .754
22.2LPTIM main features . . . . .754
22.3LPTIM implementation . . . . .755
22.4LPTIM functional description . . . . .755
22.4.1LPTIM block diagram . . . . .755
22.4.2LPTIM pins and internal signals . . . . .756
22.4.3LPTIM trigger mapping . . . . .756
22.4.4LPTIM reset and clocks . . . . .757
22.4.5Glitch filter . . . . .757
22.4.6Prescaler . . . . .758
22.4.7Trigger multiplexer . . . . .758
22.4.8Operating mode . . . . .759
22.4.9Timeout function . . . . .761
22.4.10Waveform generation . . . . .761
22.4.11Register update . . . . .762
22.4.12Counter mode . . . . .763
22.4.13Timer enable . . . . .763
22.4.14Timer counter reset . . . . .764
22.4.15Encoder mode . . . . .764
22.4.16Debug mode . . . . .766
22.5LPTIM low-power modes . . . . .766
22.6LPTIM interrupts . . . . .767
22.7LPTIM registers . . . . .767
22.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .768
22.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .769
22.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .769
22.7.4LPTIM configuration register (LPTIM_CFGR) . . . . .770
22.7.5LPTIM control register (LPTIM_CR) . . . . .773
22.7.6LPTIM compare register (LPTIM_CMP) . . . . .775
22.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .775
22.7.8LPTIM counter register (LPTIM_CNT) . . . . .776
22.7.9LPTIM register map . . . . .777
23Infrared interface (IRTIM) . . . . .778
24Real-time clock (RTC) . . . . .779
24.1Introduction . . . . .779
24.2RTC main features . . . . .780
24.3RTC functional description . . . . .781
24.3.1RTC block diagram . . . . .781
24.3.2Clock and prescalers . . . . .782
24.3.3Real-time clock and calendar . . . . .782
24.3.4Programmable alarms . . . . .783
24.3.5Periodic auto-wake-up . . . . .783
24.3.6RTC initialization and configuration . . . . .784
24.3.7Reading the calendar . . . . .785
24.3.8Resetting the RTC . . . . .786
24.3.9RTC synchronization . . . . .787
24.3.10RTC reference clock detection . . . . .787
24.3.11RTC smooth digital calibration . . . . .788
24.3.12Time-stamp function . . . . .790
24.3.13Tamper detection . . . . .791
24.3.14Calibration clock output . . . . .793
24.3.15Alarm output . . . . .793
24.4RTC low-power modes . . . . .794
24.5RTC interrupts . . . . .794
24.6RTC registers . . . . .795
24.6.1RTC time register (RTC_TR) . . . . .795
24.6.2RTC date register (RTC_DR) . . . . .796
24.6.3RTC control register (RTC_CR) . . . . .797
24.6.4RTC initialization and status register (RTC_ISR) . . . . .800
24.6.5RTC prescaler register (RTC_PRER) . . . . .803
24.6.6RTC wake-up timer register (RTC_WUTR) . . . . .804
24.6.7RTC alarm A register (RTC_ALRMAR) . . . . .805
24.6.8RTC alarm B register (RTC_ALRMBR) . . . . .806
24.6.9RTC write protection register (RTC_WPR) . . . . .807
24.6.10RTC sub second register (RTC_SSR) . . . . .807
24.6.11RTC shift control register (RTC_SHIFTR) . . . . .808
24.6.12RTC timestamp time register (RTC_TSTR) . . . . .809
24.6.13RTC timestamp date register (RTC_TSDR) . . . . .810
24.6.14RTC time-stamp sub second register (RTC_TSSSR) . . . . .811
24.6.15RTC calibration register (RTC_CALR) . . . . .812
24.6.16RTC tamper configuration register (RTC_TAMPCR) . . . . .813
24.6.17RTC alarm A sub second register (RTC_ALRMASSR) . . . . .815
24.6.18RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .816
24.6.19RTC option register (RTC_OR) . . . . .817
24.6.20RTC backup registers (RTC_BKPxR) . . . . .817
24.6.21RTC register map . . . . .818
25Independent watchdog (IWDG) . . . . .820
25.1Introduction . . . . .820
25.2IWDG main features . . . . .820
25.3IWDG functional description . . . . .820
25.3.1IWDG block diagram . . . . .820
25.3.2Window option . . . . .821
25.3.3Hardware watchdog . . . . .822
25.3.4Low-power freeze . . . . .822
25.3.5Register access protection . . . . .822
25.3.6Debug mode . . . . .822
25.4IWDG registers . . . . .823
25.4.1IWDG key register (IWDG_KR) . . . . .823
25.4.2IWDG prescaler register (IWDG_PR) . . . . .824
25.4.3IWDG reload register (IWDG_RLR) . . . . .825
25.4.4IWDG status register (IWDG_SR) . . . . .826
25.4.5IWDG window register (IWDG_WINR) . . . . .827
25.4.6IWDG register map . . . . .828
26System window watchdog (WWDG) . . . . .829
26.1Introduction . . . . .829
26.2WWDG main features . . . . .829
26.3WWDG functional description . . . . .829
26.3.1WWDG block diagram . . . . .830
26.3.2Enabling the watchdog . . . . .830
26.3.3Controlling the down-counter . . . . .830
26.3.4How to program the watchdog timeout . . . . .830
26.3.5Debug mode . . . . .832
26.4WWDG interrupts . . . . .832
26.5WWDG registers . . . . .832
26.5.1WWDG control register (WWDG_CR) . . . . .832
26.5.2WWDG configuration register (WWDG_CFR) . . . . .833
26.5.3WWDG status register (WWDG_SR) . . . . .834
26.5.4WWDG register map . . . . .834
27Inter-integrated circuit (I2C) interface . . . . .835
27.1Introduction . . . . .835
27.2I2C main features . . . . .835
27.3I2C implementation . . . . .836
27.4I2C functional description . . . . .836
27.4.1I2C block diagram . . . . .837
27.4.2I2C pins and internal signals . . . . .838
27.4.3I2C clock requirements . . . . .838
27.4.4Mode selection . . . . .838
27.4.5I2C initialization . . . . .839
27.4.6Software reset . . . . .843
27.4.7Data transfer . . . . .844
27.4.8I2C slave mode . . . . .846
27.4.9I2C master mode . . . . .855
27.4.10I2C_TIMINGR register configuration examples . . . . .866
27.4.11SMBus specific features . . . . .867
27.4.12SMBus initialization . . . . .870
27.4.13SMBus: I2C_TIMEOUTR register configuration examples . . . . .872
27.4.14SMBus slave mode . . . . .872
27.4.15Wake-up from Stop mode on address match . . . . .879
27.4.16Error conditions . . . . .880
27.4.17DMA requests . . . . .882
27.4.18Debug mode . . . . .882
27.5I2C low-power modes . . . . .883
27.6I2C interrupts . . . . .884
27.7I2C registers . . . . .885
27.7.1I2C control register 1 (I2C_CR1) . . . . .885
27.7.2I2C control register 2 (I2C_CR2) . . . . .887
27.7.3I2C own address 1 register (I2C_OAR1) . . . . .889
27.7.4I2C own address 2 register (I2C_OAR2) . . . . .890
27.7.5I2C timing register (I2C_TIMINGR) . . . . .891
27.7.6I2C timeout register (I2C_TIMEOUTR) . . . . .892
27.7.7I2C interrupt and status register (I2C_ISR) . . . . .893
27.7.8I2C interrupt clear register (I2C_ICR) . . . . .895
27.7.9I2C PEC register (I2C_PECR) . . . . .896
27.7.10I2C receive data register (I2C_RXDR) . . . . .897
27.7.11I2C transmit data register (I2C_TXDR) . . . . .897
27.7.12I2C register map . . . . .898
28Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .900
28.1USART introduction . . . . .900
28.2USART main features . . . . .901
28.3USART extended features . . . . .902
28.4USART implementation . . . . .902
28.5USART functional description . . . . .903
28.5.1USART block diagram . . . . .903
28.5.2USART signals . . . . .904
28.5.3USART character description . . . . .905
28.5.4USART FIFOs and thresholds . . . . .907
28.5.5USART transmitter . . . . .907
28.5.6USART receiver . . . . .911
28.5.7USART baud rate generation . . . . .918
28.5.8Tolerance of the USART receiver to clock deviation . . . . .919
28.5.9USART auto baud rate detection . . . . .921
28.5.10USART multiprocessor communication . . . . .923
28.5.11USART Modbus communication . . . . .925
28.5.12USART parity control . . . . .926
28.5.13USART LIN (local interconnection network) mode . . . . .927
28.5.14USART synchronous mode . . . . .929
28.5.15USART single-wire half-duplex communication . . . . .933
28.5.16USART receiver timeout . . . . .933
28.5.17USART smartcard mode . . . . .934
28.5.18USART IrDA SIR ENDEC block . . . . .938
28.5.19Continuous communication using USART and DMA . . . . .941
28.5.20RS232 hardware flow control and RS485 Driver Enable . . . . .943
28.5.21USART low-power management . . . . .946
28.6USART in low-power modes . . . . .949
28.7USART interrupts . . . . .950
28.8USART registers . . . . .951
28.8.1USART control register 1 (USART_CR1) . . . . .951
28.8.2USART control register 1 [alternate] (USART_CR1) . . . . .955
28.8.3USART control register 2 (USART_CR2) . . . . .958
28.8.4USART control register 3 (USART_CR3) . . . . .962
28.8.5USART baud rate register (USART_BRR) . . . . .967
28.8.6USART guard time and prescaler register (USART_GTPR) . . . . .967
28.8.7USART receiver timeout register (USART_RTOR) . . . . .968
28.8.8USART request register (USART_RQR) . . . . .969
28.8.9USART interrupt and status register (USART_ISR) . . . . .970
28.8.10USART interrupt and status register [alternate] (USART_ISR) . . . . .976
28.8.11USART interrupt flag clear register (USART_ICR) . . . . .981
28.8.12USART receive data register (USART_RDR) . . . . .983
28.8.13USART transmit data register (USART_TDR) . . . . .983
28.8.14USART prescaler register (USART_PRESC) . . . . .984
28.8.15USART register map . . . . .985
29Serial peripheral interface (SPI) . . . . .987
29.1Introduction . . . . .987
29.2SPI main features . . . . .987
29.3SPI implementation . . . . .988
29.4SPI functional description . . . . .988
29.4.1General description . . . . .988
29.4.2Communications between one master and one slave . . . . .989
29.4.3Standard multislave communication . . . . .991
29.4.4Multimaster communication . . . . .992
29.4.5Slave select (NSS) pin management . . . . .993
29.4.6Communication formats . . . . .994
29.4.7Configuration of SPI . . . . .996
29.4.8Procedure for enabling SPI . . . . .997
29.4.9Data transmission and reception procedures . . . . .997
29.4.10SPI status flags . . . . .1007
29.4.11SPI error flags . . . . .1008
29.4.12NSS pulse mode . . . . .1009
29.4.13TI mode . . . . .1009
29.4.14CRC calculation . . . . .1010
29.5SPI interrupts . . . . .1012
29.6SPI registers . . . . .1013
29.6.1SPI control register 1 (SPIx_CR1) . . . . .1013
29.6.2SPI control register 2 (SPIx_CR2) . . . . .1015
29.6.3SPI status register (SPIx_SR) . . . . .1017
29.6.4SPI data register (SPIx_DR) . . . . .1018
29.6.5SPI CRC polynomial register (SPIx_CRCPR) . . . . .1019
29.6.6SPI Rx CRC register (SPIx_RXCRCR) . . . . .1019
29.6.7SPI Tx CRC register (SPIx_TXCRCR) . . . . .1019
29.6.8SPI register map . . . . .1021
30Inter-processor communication controller (IPCC) . . . . .1022
30.1Introduction . . . . .1022
30.2IPCC main features . . . . .1022
30.3IPCC functional description . . . . .1022
30.3.1IPCC block diagram . . . . .1023
30.3.2IPCC Simplex channel mode . . . . .1023
30.3.3IPCC Half-duplex channel mode . . . . .1026
30.3.4IPCC interrupts . . . . .1029
30.4IPCC registers . . . . .1030
30.4.1IPCC processor 1 control register (IPCC_C1CR) . . . . .1030
30.4.2IPCC processor 1 mask register (IPCC_C1MR) . . . . .1030
30.4.3IPCC processor 1 status set clear register (IPCC_C1SCR) . . . . .1031
30.4.4IPCC processor 1 to processor 2 status register
(IPCC_C1TOC2SR) . . . . .		1032
30.4.5IPCC processor 2 control register (IPCC_C2CR) . . . . .1032
30.4.6IPCC processor 2 mask register (IPCC_C2MR) . . . . .1033
30.4.7IPCC processor 2 status set clear register (IPCC_C2SCR) . . . . .1033
30.4.8IPCC processor 2 to processor 1 status register
(IPCC_C2TOC1SR) . . . . .		1034
30.4.9IPCC register map . . . . .1035
31Hardware semaphore (HSEM) . . . . .1036
31.1Introduction . . . . .1036
31.2Main features . . . . .1036
31.3Functional description . . . . .1037
31.3.1HSEM block diagram . . . . .1037
31.3.2HSEM internal signals . . . . .1037
31.3.3HSEM lock procedures . . . . .1037
31.3.4HSEM write/read/read lock register address . . . . .1039
31.3.5HSEM unlock procedures . . . . .1039
31.3.6HSEM COREID semaphore clear . . . . .1040
31.3.7HSEM interrupts . . . . .1040
31.3.8AHB bus master ID verification . . . . .1042
31.4HSEM registers . . . . .1043
31.4.1HSEM register semaphore x (HSEM_Rx) . . . . .1043
31.4.2HSEM read lock register semaphore x (HSEM_RLRx) . . . . .1044
31.4.3HSEM interrupt enable register (HSEM_CnIER) . . . . .1045
31.4.4HSEM interrupt clear register (HSEM_CnICR) . . . . .1045
31.4.5HSEM interrupt status register (HSEM_CnISR) . . . . .1045

32 Debug support (DBG) . . . . . 1050

32.5.7Access port register map and reset values . . . . .1073
32.6Cross trigger interface (CTI) and matrix (CTM) . . . . .1074
32.7Cross trigger interface registers . . . . .1078
32.7.1CTI control register (CTI_CONTROLR) . . . . .1078
32.7.2CTI trigger acknowledge register (CTI_INTACKR) . . . . .1078
32.7.3CTI application trigger set register (CTI_APPSETR) . . . . .1078
32.7.4CTI application trigger clear register (CTI_APPCLEAR) . . . . .1079
32.7.5CTI application pulse register (CTI_APPPULSER) . . . . .1080
32.7.6CTI trigger In x enable register (CTI_INENRx) . . . . .1080
32.7.7CTI trigger out x enable register (CTI_OUTENRx) . . . . .1081
32.7.8CTI trigger in status register (CTI_TRGISTSR) . . . . .1081
32.7.9CTI trigger out status register (CTI_TRGOSTSR) . . . . .1082
32.7.10CTI channel in status register (CTI_CHINSTSR) . . . . .1082
32.7.11CTI channel out status register (CTI_CHOUTSTSR) . . . . .1082
32.7.12CTI channel gate register (CTI_GATER) . . . . .1083
32.7.13CTI claim tag set register (CTI_CLAIMSETR) . . . . .1083
32.7.14CTI claim tag clear register (CTI_CLAIMCLR) . . . . .1084
32.7.15CTI lock access register (CTI_LAR) . . . . .1084
32.7.16CTI lock status register (CTI_LSR) . . . . .1085
32.7.17CTI authentication status register (CTI_AUTHSTATR) . . . . .1085
32.7.18CTI device configuration register (CTI_DEVIDR) . . . . .1086
32.7.19CTI device type identifier register (CTI_DEVTYPE) . . . . .1086
32.7.20CTI CoreSight peripheral identity register 4 (CTI_PIDR4) . . . . .1087
32.7.21CTI CoreSight peripheral identity register 0 (CTI_PIDR0) . . . . .1087
32.7.22CTI CoreSight peripheral identity register 1 (CTI_PIDR1) . . . . .1087
32.7.23CTI CoreSight peripheral identity register 2 (CTI_PIDR2) . . . . .1088
32.7.24CTI CoreSight peripheral identity register 3 (CTI_PIDR3) . . . . .1088
32.7.25CTI CoreSight component identity register 0 (CTI_CIDR0) . . . . .1089
32.7.26CTI CoreSight peripheral identity register 1 (CTI_CIDR1) . . . . .1089
32.7.27CTI CoreSight component identity register 2 (CTI_CIDR2) . . . . .1090
32.7.28CTI CoreSight component identity register 3 (CTI_CIDR3) . . . . .1090
32.7.29CTI register map and reset values . . . . .1091
32.8Microcontroller debug unit (DBGMCU) . . . . .1094
32.8.1DBGMCU identity code register (DBGMCU_IDCODE) . . . . .1094
32.8.2DBGMCU configuration register (DBGMCU_CR) . . . . .1094
32.8.3DBGMCU CPU1 APB1 peripheral freeze register 1
(DBGMCU_APB1FZR1) . . . . .		1095
32.8.4DBGMCU CPU2 APB1 peripheral freeze register 1
(DBGMCU_C2APB1FZR1) .....		1096
32.8.5DBGMCU CPU1 APB1 peripheral freeze register 2
(DBGMCU_APB1FZR2) .....		1097
32.8.6DBGMCU CPU2 APB1 peripheral freeze register 2
(DBGMCU_C2APB1FZR2) .....		1098
32.8.7DBGMCU CPU1 APB2 peripheral freeze register
(DBGMCU_APB2FZR) .....		1098
32.8.8DBGMCU CPU2 APB2 peripheral freeze register
(DBGMCU_C2APB2FZR) .....		1099
32.8.9DBGMCU register map and reset values .....1100
32.9CPU2 ROM tables .....1102
32.9.1CPU2 ROM1 memory type register (C2ROM1_MEMTYPER) .....1104
32.9.2CPU2 ROM1 CoreSight peripheral identity register 4
(C2ROM1_PIDR4) .....		1104
32.9.3CPU2 ROM1 CoreSight peripheral identity register 0
(C2ROM1_PIDR0) .....		1104
32.9.4CPU2 ROM1 CoreSight peripheral identity register 1
(C2ROM1_PIDR1) .....		1105
32.9.5CPU2 ROM1 CoreSight peripheral identity register 2
(C2ROM1_PIDR2) .....		1105
32.9.6CPU2 ROM1 CoreSight peripheral identity register 3
(C2ROM1_PIDR3) .....		1106
32.9.7CPU2 ROM1 CoreSight component identity register 0
(C2ROM1_CIDR0) .....		1106
32.9.8CPU2 ROM1 CoreSight peripheral identity register 1
(C2ROM1_CIDR1) .....		1107
32.9.9CPU2 ROM1 CoreSight component identity register 2
(C2ROM1_CIDR2) .....		1107
32.9.10CPU2 ROM1 CoreSight component identity register 3
(C2ROM1_CIDR3) .....		1107
32.9.11CPU2 processor ROM table registers and reset values .....1109
32.9.12CPU2 ROM2 memory type register (C2ROM2_MEMTYPER) .....1110
32.9.13CPU2 ROM2 CoreSight peripheral identity register 4
(C2ROM2_PIDR4) .....		1110
32.9.14CPU2 ROM2 CoreSight peripheral identity register 0
(C2ROM2_PIDR0) .....		1110
32.9.15CPU2 ROM2 CoreSight peripheral identity register 1
(C2ROM2_PIDR1) .....		1111
32.9.16CPU2 ROM2 CoreSight peripheral identity register 2
(C2ROM2_PIDR2) .....		1111
32.9.17CPU2 ROM2 CoreSight peripheral identity register 3 (C2ROM2_PIDR3) .....1112
32.9.18CPU2 ROM2 CoreSight component identity register 0 (C2ROM2_CIDR0) .....1112
32.9.19CPU2 ROM2 CoreSight peripheral identity register 1 (C2ROM2_CIDR1) .....1113
32.9.20CPU2 ROM2 CoreSight component identity register 2 (C2ROM2_CIDR2) .....1113
32.9.21CPU2 ROM2 CoreSight component identity register 3 (C2ROM2_CIDR3) .....1113
32.9.22CPU2 ROM table register map and reset values .....1115
32.10CPU2 data watchpoint and trace unit (DWT) .....1116
32.10.1DWT control register (DWT_CTRLR) .....1116
32.10.2DWT cycle count register (DWT_CYCCNTR) .....1118
32.10.3DWT CPI count register (DWT_CPICNTR) .....1118
32.10.4DWT exception count register (DWT_EXCCNTR) .....1119
32.10.5DWT sleep count register (DWT_SLPNCNTR) .....1119
32.10.6DWT LSU count register (DWT_LSUCNTR) .....1120
32.10.7DWT fold count register (DWT_FOLDCNTR) .....1120
32.10.8DWT program counter sample register (DWT_PCSR) .....1120
32.10.9DWT comparator register x (DWT_COMPxR) .....1121
32.10.10DWT mask register x (DWT_MASKxR) .....1121
32.10.11DWT function register x (DWT_FUNCTxR) .....1121
32.10.12DWT CoreSight peripheral identity register 4 (DWT_PIDR4) .....1122
32.10.13DWT CoreSight peripheral identity register 0 (DWT_PIDR0) .....1123
32.10.14DWT CoreSight peripheral identity register 1 (DWT_PIDR1) .....1123
32.10.15DWT CoreSight peripheral identity register 2 (DWT_PIDR2) .....1124
32.10.16DWT CoreSight peripheral identity register 3 (DWT_PIDR3) .....1124
32.10.17DWT CoreSight component identity register 0 (DWT_CIDR0) .....1125
32.10.18DWT CoreSight peripheral identity register 1 (DWT_CIDR1) .....1125
32.10.19DWT CoreSight component identity register 2 (DWT_CIDR2) .....1125
32.10.20DWT CoreSight component identity register 3 (DWT_CIDR3) .....1126
32.10.21CPU2 DWT registers .....1127
32.11CPU2 breakpoint unit (PBU) .....1130
32.11.1BPU control register (BPU_CTRLR) .....1130
32.11.2BPU remap register (BPU_REMAPR) .....1130
32.11.3BPU comparator registers (BPU_COMPxR) .....1131
32.11.4BPU CoreSight peripheral identity register 4 (BPU_PIDR4) .....1131
32.11.5BPU CoreSight peripheral identity register 0 (BPU_PIDR0) . . . . .1132
32.11.6BPU CoreSight peripheral identity register 1 (BPU_PIDR1) . . . . .1132
32.11.7BPU CoreSight peripheral identity register 2 (BPU_PIDR2) . . . . .1132
32.11.8BPU CoreSight peripheral identity register 3 (BPU_PIDR3) . . . . .1133
32.11.9BPU CoreSight component identity register 0 (BPU_CIDR0) . . . . .1133
32.11.10BPU CoreSight peripheral identity register 1 (BPU_CIDR1) . . . . .1134
32.11.11BPU CoreSight component identity register 2 (BPU_CIDR2) . . . . .1134
32.11.12BPU CoreSight component identity register 3 (BPU_CIDR3) . . . . .1135
32.11.13CPU2 BPU register map and reset values . . . . .1136
32.12CPU2 cross trigger interface (CTI) . . . . .1137
32.13CPU1 ROM table . . . . .1137
32.13.1CPU1 ROM memory type register (C1ROM_MEMTYPER) . . . . .1138
32.13.2CPU1 ROM CoreSight peripheral identity register 4
(C1ROM_PIDR4) . . . . .		1139
32.13.3CPU1 ROM CoreSight peripheral identity register 0
(C1ROM_PIDR0) . . . . .		1139
32.13.4CPU1 ROM CoreSight peripheral identity register 1
(C1ROM_PIDR1) . . . . .		1140
32.13.5CPU1 ROM CoreSight peripheral identity register 2
(C1ROM_PIDR2) . . . . .		1140
32.13.6CPU1 ROM CoreSight peripheral identity register 3
(C1ROM_PIDR3) . . . . .		1141
32.13.7CPU1 ROM CoreSight component identity register 0
(C1ROM_CIDR0) . . . . .		1141
32.13.8CPU1 ROM CoreSight peripheral identity register 1
(C1ROM_CIDR1) . . . . .		1141
32.13.9CPU1 ROM CoreSight component identity register 2
(C1ROM_CIDR2) . . . . .		1142
32.13.10CPU1 ROM CoreSight component identity register 3
(C1ROM_CIDR3) . . . . .		1142
32.13.11CPU1 ROM table register map and reset values . . . . .1144
32.14CPU1 data watchpoint and trace unit (DWT) . . . . .1145
32.14.1DWT control register (DWT_CTRLR) . . . . .1145
32.14.2DWT cycle count register (DWT_CYCCNTR) . . . . .1147
32.14.3DWT CPI count register (DWT_CPICNTR) . . . . .1147
32.14.4DWT exception count register (DWT_EXCCNTR) . . . . .1148
32.14.5DWT sleep count register (DWT_SLP CNTR) . . . . .1148
32.14.6DWT LSU count register (DWT_LSUCNTR) . . . . .1149
32.14.7DWT fold count register (DWT_FOLDCNTR) . . . . .1149
32.14.8DWT program counter sample register (DWT_PCSR) . . . . .1149
32.14.9DWT comparator register x (DWT_COMPxR) . . . . .1150
32.14.10DWT mask register x (DWT_MASKxR) . . . . .1150
32.14.11DWT function register x (DWT_FUNCTxR) . . . . .1150
32.14.12DWT CoreSight peripheral identity register 4 (DWT_PIDR4) . . . . .1151
32.14.13DWT CoreSight peripheral identity register 0 (DWT_PIDR0) . . . . .1152
32.14.14DWT CoreSight peripheral identity register 1 (DWT_PIDR1) . . . . .1152
32.14.15DWT CoreSight peripheral identity register 2 (DWT_PIDR2) . . . . .1153
32.14.16DWT CoreSight peripheral identity register 3 (DWT_PIDR3) . . . . .1153
32.14.17DWT CoreSight component identity register 0 (DWT_CIDR0) . . . . .1154
32.14.18DWT CoreSight peripheral identity register 1 (DWT_CIDR1) . . . . .1154
32.14.19DWT CoreSight component identity register 2 (DWT_CIDR2) . . . . .1154
32.14.20DWT CoreSight component identity register 3 (DWT_CIDR3) . . . . .1155
32.14.21CPU1 DWT register map and reset values . . . . .1156
32.15CPU1 instrumentation trace macrocell (ITM) . . . . .1158
32.15.1ITM stimulus register x (ITM_STIMRx) . . . . .1158
32.15.2ITM trace enable register (ITM_TER) . . . . .1158
32.15.3ITM trace privilege register (ITM_TPR) . . . . .1159
32.15.4ITM trace control register (ITM_TCR) . . . . .1159
32.15.5ITM CoreSight peripheral identity register 4 (ITM_PIDR4) . . . . .1160
32.15.6ITM CoreSight peripheral identity register 0 (ITM_PIDR0) . . . . .1161
32.15.7ITM CoreSight peripheral identity register 1 (ITM_PIDR1) . . . . .1161
32.15.8ITM CoreSight peripheral identity register 2 (ITM_PIDR2) . . . . .1162
32.15.9ITM CoreSight peripheral identity register 3 (ITM_PIDR3) . . . . .1162
32.15.10ITM CoreSight component identity register 0 (ITM_CIDR0) . . . . .1163
32.15.11ITM CoreSight peripheral identity register 1 (ITM_CIDR1) . . . . .1163
32.15.12ITM CoreSight component identity register 2 (ITM_CIDR2) . . . . .1163
32.15.13ITM CoreSight component identity register 3 (ITM_CIDR3) . . . . .1164
32.15.14ITM register map and reset values . . . . .1165
32.16CPU1 breakpoint unit (FPB) . . . . .1166
32.16.1FPB control register (FPB_CTRLR) . . . . .1166
32.16.2FPB remap register (FPB_REMAPR) . . . . .1166
32.16.3FPB comparator registers (FPB_COMPxR) . . . . .1167
32.16.4FPB CoreSight peripheral identity register 4 (FPB_PIDR4) . . . . .1167
32.16.5FPB CoreSight peripheral identity register 0 (FPB_PIDR0) . . . . .1168
32.16.6FPB CoreSight peripheral identity register 1 (FPB_PIDR1) . . . . .1168
32.16.7FPB CoreSight peripheral identity register 2 (FPB_PIDR2) . . . . .1169
32.16.8FPB CoreSight peripheral identity register 3 (FPB_PIDR3) . . . . .1169
32.16.9FPB CoreSight component identity register 0 (FPB_CIDR0) . . . . .1170
32.16.10FPB CoreSight peripheral identity register 1 (FPB_CIDR1) . . . . .1170
32.16.11FPB CoreSight component identity register 2 (FPB_CIDR2) . . . . .1170
32.16.12FPB CoreSight component identity register 3 (FPB_CIDR3) . . . . .1171
32.16.13FPB register map and reset values . . . . .1172
32.17CPU1 trace port interface unit (TPIU) . . . . .1173
32.17.1TPIU supported port size register (TPIU_SSPSR) . . . . .1173
32.17.2TPIU current port size register (TPIU_CSPSR) . . . . .1173
32.17.3TPIU asynchronous clock prescaler register (TPIU_ACPR) . . . . .1174
32.17.4TPIU selected pin protocol register (TPIU_SPPR) . . . . .1174
32.17.5TPIU formatter and flush status register (TPIU_FFSR) . . . . .1175
32.17.6TPIU formatter and flush control register (TPIU_FFCR) . . . . .1175
32.17.7TPIU formatter synchronization counter register (TPIU_FSCR) . . . . .1176
32.17.8TPIU claim tag set register (TPIU_CLAIMSETR) . . . . .1176
32.17.9TPIU claim tag clear register (TPIU_CLAIMCLR) . . . . .1177
32.17.10TPIU device configuration register (TPIU_DEVIDR) . . . . .1177
32.17.11TPIU device type identifier register (TPIU_DEVTYPE) . . . . .1178
32.17.12TPIU CoreSight peripheral identity register 4 (TPIU_PIDR4) . . . . .1178
32.17.13TPIU CoreSight peripheral identity register 0 (TPIU_PIDR0) . . . . .1179
32.17.14TPIU CoreSight peripheral identity register 1 (TPIU_PIDR1) . . . . .1179
32.17.15TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) . . . . .1180
32.17.16TPIU CoreSight peripheral identity register 3 (TPIU_PIDR3) . . . . .1180
32.17.17TPIU CoreSight component identity register 0 (TPIU_CIDR0) . . . . .1181
32.17.18TPIU CoreSight peripheral identity register 1 (TPIU_CIDR1) . . . . .1181
32.17.19TPIU CoreSight component identity register 2 (TPIU_CIDR2) . . . . .1181
32.17.20TPIU CoreSight component identity register 3 (TPIU_CIDR3) . . . . .1182
32.17.21CPU1 TPIU register map and reset values . . . . .1183
32.18CPU1 cross trigger interface (CTI) . . . . .1185
32.19References . . . . .1185
33Device electronic signature . . . . .1186
33.1Unique device ID register (96 bits) . . . . .1186
33.2Memory size data register . . . . .1187
33.2.1Flash size data register . . . . .1187
33.3Package data register . . . . .1187

33.4 Part number codification register . . . . .1188

34 Important security notice . . . . . 1189

35 Revision history . . . . . 1190

List of tables

Table 1.STM32WB50CG/30CE memory map and peripheral register boundary addresses. . . . .58
Table 2.Boot modes. . . . .61
Table 3.Flash memory - Single bank organization . . . . .65
Table 4.Number of wait states vs, flash memory clock (HCLK4) frequency . . . . .67
Table 5.Page erase overview . . . . .72
Table 6.Mass erase overview . . . . .73
Table 7.Errors in page-based row programming . . . . .78
Table 8.Option bytes format . . . . .79
Table 9.Option bytes organization. . . . .79
Table 10.Option loading control. . . . .87
Table 11.UID64 organization. . . . .88
Table 12.Flash memory read protection status . . . . .89
Table 13.RDP regression from Level 1 to Level 0 and memory erase . . . . .91
Table 14.Access status vs. protection level and execution modes . . . . .92
Table 17.Flash memory interrupt requests . . . . .97
Table 18.Flash interface register map and reset values . . . . .116
Table 19.CRC internal input/output signals . . . . .121
Table 20.CRC register map and reset values . . . . .126
Table 21.Sub-system low power wake-up sources . . . . .135
Table 22.Low-power mode summary . . . . .137
Table 23.Functionalities depending on system operating mode . . . . .138
Table 24.Low-power run . . . . .141
Table 25.CPU CSTOP wake-up vs. system operating mode . . . . .142
Table 26.Sleep mode. . . . .143
Table 27.Low-power sleep. . . . .144
Table 28.Stop0 mode . . . . .146
Table 29.Stop1 mode . . . . .147
Table 30.Stop2 mode . . . . .149
Table 31.Standby mode. . . . .150
Table 32.Shutdown mode . . . . .152
Table 33.PWR register map and reset values. . . . .169
Table 34.Maximum clock source frequency . . . . .182
Table 35.Peripheral clock enable . . . . .188
Table 36.Single core Low power debug configurations. . . . .189
Table 37.RCC register map and reset values . . . . .242
Table 38.Port bit configuration table . . . . .250
Table 39.GPIO register map and reset values . . . . .266
Table 40.SYSCFG register map and reset values. . . . .284
Table 41.Peripherals interconnect matrix . . . . .286
Table 42.DMA1 implementation . . . . .292
Table 43.DMA internal input/output signals . . . . .293
Table 44.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .298
Table 45.DMA interrupt requests. . . . .300
Table 46.DMA register map and reset values . . . . .308
Table 47.DMAMUX instantiation . . . . .312
Table 48.DMAMUX: assignment of multiplexer inputs to resources . . . . .313
Table 49.DMAMUX: assignment of trigger inputs to resources. . . . .313
Table 50.DMAMUX: assignment of synchronization inputs to resources . . . . .314
Table 51.DMAMUX signals . . . . .316
Table 52.DMAMUX interrupts . . . . .320
Table 53.DMAMUX register map and reset values . . . . .325
Table 54.CPU1 vector table. . . . .329
Table 55.CPU2 vector table. . . . .332
Table 56.Wakeup interrupt table . . . . .334
Table 57.EXTI pin overview. . . . .337
Table 58.EVG pin overview . . . . .337
Table 59.EXTI event input configurations and register control . . . . .339
Table 60.Masking functionality . . . . .342
Table 61.EXTI register map sections. . . . .343
Table 62.EXTI register map and reset values . . . . .352
Table 63.ADC internal input/output signals . . . . .357
Table 64.ADC input/output pins. . . . .357
Table 65.Configuring the trigger polarity for regular external triggers . . . . .373
Table 66.Configuring the trigger polarity for injected external triggers . . . . .373
Table 67.ADC1 - External triggers for regular channels . . . . .374
Table 68.ADC1 - External trigger for injected channels. . . . .374
Table 69.TSAR timings depending on resolution . . . . .386
Table 70.Offset computation versus data resolution . . . . .389
Table 71.Analog watchdog channel selection . . . . .399
Table 72.Analog watchdog 1 comparison . . . . .400
Table 73.Analog watchdog 2 and 3 comparison . . . . .400
Table 74.Maximum output results versus N and M (gray cells indicate truncation). . . . .404
Table 75.Effect of low-power modes on the ADC . . . . .412
Table 76.ADC interrupts . . . . .413
Table 77.ADC register map and reset values . . . . .442
Table 78.ADC register map and reset values (master and slave ADC common registers) offset = 0x300 . . . . .444
Table 79.RNG internal input/output signals . . . . .446
Table 80.RNG interrupt requests. . . . .453
Table 81.RNG register map and reset map. . . . .456
Table 82.AES internal input/output signals . . . . .458
Table 83.CTR mode initialization vector definition. . . . .475
Table 84.GCM last block definition . . . . .477
Table 85.Initialization of AES_IVRx registers in GCM mode . . . . .478
Table 86.Initialization of AES_IVRx registers in CCM mode . . . . .485
Table 87.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .490
Table 88.AES interrupt requests . . . . .493
Table 89.Processing latency for ECB, CBC and CTR. . . . .493
Table 90.Processing latency for GCM and CCM (in clock cycles). . . . .494
Table 91.AES register map and reset values . . . . .504
Table 92.Internal input/output signals . . . . .507
Table 93.PKA integer arithmetic functions list . . . . .508
Table 94.PKA prime field (Fp) elliptic curve functions list . . . . .508
Table 95.Montgomery parameter computation . . . . .513
Table 96.Modular addition . . . . .514
Table 97.Modular subtraction . . . . .514
Table 98.Montgomery multiplication . . . . .515
Table 99.Modular exponentiation (normal mode) . . . . .516
Table 100.Modular exponentiation (fast mode). . . . .516
Table 101.Modular inversion . . . . .516
Table 102.Modular reduction . . . . .517
Table 103.Arithmetic addition . . . . .517
Table 104.Arithmetic subtraction . . . . .517
Table 105.Arithmetic multiplication . . . . .518
Table 106.Arithmetic comparison . . . . .518
Table 107.CRT exponentiation . . . . .519
Table 108.Point on elliptic curve Fp check . . . . .520
Table 109.ECC Fp scalar multiplication . . . . .520
Table 110.ECC Fp scalar multiplication (Fast Mode) . . . . .521
Table 111.ECDSA sign - Inputs . . . . .522
Table 112.ECDSA sign - Outputs . . . . .522
Table 113.Extended ECDSA sign (extra outputs) . . . . .523
Table 114.ECDSA verification (inputs) . . . . .523
Table 115.ECDSA verification (outputs) . . . . .523
Table 116.Family of supported curves for ECC operations . . . . .524
Table 117.Modular exponentiation computation times . . . . .526
Table 118.ECC scalar multiplication computation times . . . . .526
Table 119.ECDSA signature average computation times . . . . .526
Table 120.ECDSA verification average computation times . . . . .527
Table 121.Point on elliptic curve Fp check average computation times . . . . .527
Table 122.Montgomery parameters average computation times . . . . .527
Table 123.PKA interrupt requests . . . . .527
Table 124.PKA register map and reset values . . . . .531
Table 125.Behavior of timer outputs versus BRK/BRK2 inputs . . . . .574
Table 126.Break protection disarming conditions . . . . .576
Table 127.Counting direction versus encoder signals . . . . .582
Table 128.TIM1 internal trigger connection . . . . .599
Table 129.Output control bits for complementary OCx and OCxN channels with break feature . . . . .613
Table 130.TIM1 register map and reset values . . . . .629
Table 131.Counting direction versus encoder signals . . . . .665
Table 132.TIM2 internal trigger connection . . . . .682
Table 133.Output control bit for standard OCx channels . . . . .693
Table 134.TIM2 register map and reset values . . . . .700
Table 135.Break protection disarming conditions . . . . .725
Table 136.Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . .742
Table 137.TIM16/TIM17 register map and reset values . . . . .752
Table 138.LPTIM features . . . . .755
Table 139.LPTIM input/output pins . . . . .756
Table 140.LPTIM internal signals . . . . .756
Table 141.LPTIM1 external trigger connection . . . . .756
Table 142.LPTIM2 external trigger connection . . . . .756
Table 143.Prescaler division ratios . . . . .758
Table 144.Encoder counting scenarios . . . . .765
Table 145.Effect of low-power modes on the LPTIM . . . . .766
Table 146.Interrupt events . . . . .767
Table 147.LPTIM register map and reset values . . . . .777
Table 148.Effect of low-power modes on RTC . . . . .794
Table 149.Interrupt control bits . . . . .794
Table 150.RTC register map and reset values . . . . .818
Table 151.IWDG register map and reset values . . . . .828
Table 152.WWDG register map and reset values . . . . .834
Table 153.STM32WB50CG/30CE I2C implementation . . . . .836
Table 154.I2C input/output pins . . . . .838
Table 155.I2C internal input/output signals . . . . .838
Table 156.Comparison of analog vs. digital filters . . . . .840
Table 157.I2C-SMBus specification data setup and hold times . . . . .842
Table 158.I2C configuration . . . . .846
Table 159.I2C-SMBus specification clock timings . . . . .857
Table 160.Examples of timing settings for f I2CCLK = 8 MHz . . . . .867
Table 161.Examples of timing settings for f I2CCLK = 16 MHz . . . . .867
Table 162.SMBus timeout specifications . . . . .869
Table 163.SMBus with PEC configuration . . . . .871
Table 164.Examples of TIMEOUTA settings (max t TIMEOUT = 25 ms) . . . . .872
Table 165.Examples of TIMEOUTB settings . . . . .872
Table 166.Examples of TIMEOUTA settings (max t IDLE = 50 µs) . . . . .872
Table 167.Effect of low-power modes on the I2C . . . . .883
Table 168.I2C interrupt requests . . . . .884
Table 169.I2C register map and reset values . . . . .898
Table 170.USART features . . . . .902
Table 171.Noise detection from sampled data . . . . .917
Table 172.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .920
Table 173.Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . .921
Table 174.USART frame formats . . . . .926
Table 175.Effect of low-power modes on the USART . . . . .949
Table 176.USART interrupt requests . . . . .950
Table 177.USART register map and reset values . . . . .985
Table 178.SPI implementation . . . . .988
Table 179.SPI interrupt requests . . . . .1012
Table 180.SPI register map and reset values . . . . .1021
Table 181.IPCC interface signals . . . . .1023
Table 182.Bits used for the communication . . . . .1024
Table 183.IPCC register map and reset values . . . . .1035
Table 184.HSEM internal input/output signals . . . . .1037
Table 185.Authorized AHB bus master IDs . . . . .1042
Table 186.HSEM register map and reset values . . . . .1048
Table 187.JTAG/Serial-wire debug port pins . . . . .1052
Table 188.Single Wire Trace port pins . . . . .1052
Table 189.JTAG-DP data registers . . . . .1056
Table 190.Packet request . . . . .1057
Table 191.ACK response . . . . .1058
Table 192.Data transfer . . . . .1058
Table 193.Debug port register map and reset values . . . . .1066
Table 194.Access port register map and reset values . . . . .1073
Table 195.CPU2 CTI inputs . . . . .1074
Table 196.CPU2 CTI outputs . . . . .1075
Table 197.CPU1 CTI inputs . . . . .1075
Table 198.CPU1 CTI outputs . . . . .1075
Table 199.CTI register map and reset values . . . . .1091
Table 200.DBGMCU register map and reset values . . . . .1100
Table 201.CPU2 processor ROM table . . . . .1102
Table 202.CPU2 ROM table . . . . .1102
Table 203.CPU2 processor ROM table register map and reset values . . . . .1109
Table 204.CPU2 ROM table register map and reset values . . . . .1115
Table 205.CPU2 DWT register map and reset values . . . . .1127
Table 206.CPU2 BPU register map and reset values . . . . .1136
Table 207.CPU1 ROM table . . . . .1137
Table 208.CPU1 ROM table register map and reset values . . . . .1144
Table 209.CPU1 DWT register map and reset values . . . . .1156
Table 210.CPU1 ITM register map and reset values . . . . .1165
Table 211.CPU1 FPB register map and reset values . . . . .1172
Table 212.CPU1 TPIU register map and reset values . . . . .1183
Table 213.Document revision history . . . . .1190

List of figures

Figure 1.System architecture . . . . .54
Figure 2.Memory map . . . . .57
Figure 3.Sequential 16-bit instructions execution . . . . .69
Figure 4.Changing the Read protection (RDP) level . . . . .92
Figure 5.Radio system block diagram . . . . .119
Figure 6.CRC calculation unit block diagram . . . . .121
Figure 7.Power supply overview . . . . .128
Figure 8.Brown-out reset waveform . . . . .131
Figure 9.PVD thresholds . . . . .132
Figure 10.CPU2 boot options . . . . .133
Figure 11.Low-power modes possible transitions . . . . .136
Figure 12.Real-time radio activity flags . . . . .153
Figure 13.Simplified diagram of the reset circuit . . . . .172
Figure 14.Clock tree . . . . .176
Figure 15.HSE clock sources . . . . .177
Figure 16.LSE clock sources . . . . .180
Figure 17.Frequency measurement with TIM16 in capture mode . . . . .186
Figure 18.Frequency measurement with TIM17 in capture mode . . . . .186
Figure 19.Three-volt or Five-volt tolerant GPIO structure (TT or FT) . . . . .249
Figure 20.Input floating / pull up / pull down configurations . . . . .254
Figure 21.Output configuration . . . . .254
Figure 22.Alternate function configuration . . . . .255
Figure 23.High impedance-analog configuration . . . . .256
Figure 24.DMA block diagram . . . . .292
Figure 25.DMAMUX block diagram . . . . .315
Figure 26.Synchronization mode of the DMAMUX request line multiplexer channel . . . . .318
Figure 27.Event generation of the DMA request line multiplexer channel . . . . .318
Figure 28.Interrupt block diagram . . . . .328
Figure 29.EXTI block diagram . . . . .337
Figure 30.Configurable event trigger logic CPU wakeup . . . . .340
Figure 31.Direct event trigger logic CPU wakeup . . . . .341
Figure 32.ADC block diagram . . . . .356
Figure 33.ADC clock scheme . . . . .359
Figure 34.ADC1 connectivity . . . . .360
Figure 35.ADC calibration . . . . .363
Figure 36.Updating the ADC calibration factor . . . . .364
Figure 37.Mixing single-ended and differential channels . . . . .364
Figure 38.Enabling / disabling the ADC . . . . .366
Figure 39.Analog to digital conversion time . . . . .371
Figure 40.Stopping ongoing regular conversions . . . . .372
Figure 41.Stopping ongoing regular and injected conversions . . . . .372
Figure 42.Injected conversion latency . . . . .376
Figure 43.Example of JSQR queue of context (sequence change) . . . . .379
Figure 44.Example of JSQR queue of context (trigger change) . . . . .379
Figure 45.Example of JSQR queue of context with overflow before conversion . . . . .380
Figure 46.Example of JSQR queue of context with overflow during conversion . . . . .380
Figure 47.Example of JSQR queue of context with empty queue (case JQM = 0) . . . . .381
Figure 48.Example of JSQR queue of context with empty queue (case JQM = 1) . . . . .382
Figure 49.Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs during an ongoing conversion . . . . .		382
Figure 50.Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . .		383
Figure 51.Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs outside an ongoing conversion . . . . .		383
Figure 52.Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 1) . . . . .384
Figure 53.Flushing JSQR queue of context by setting ADDIS = 1 (JQM = 0). . . . .384
Figure 54.Flushing JSQR queue of context by setting ADDIS = 1 (JQM = 1). . . . .385
Figure 55.Single conversions of a sequence, software trigger . . . . .387
Figure 56.Continuous conversion of a sequence, software trigger. . . . .387
Figure 57.Single conversions of a sequence, hardware trigger . . . . .388
Figure 58.Continuous conversions of a sequence, hardware trigger . . . . .388
Figure 59.Right alignment (offset disabled, unsigned value) . . . . .390
Figure 60.Right alignment (offset enabled, signed value). . . . .391
Figure 61.Left alignment (offset disabled, unsigned value) . . . . .391
Figure 62.Left alignment (offset enabled, signed value). . . . .392
Figure 63.Example of overrun (OVR) . . . . .393
Figure 64.AUTODLY = 1, regular conversion in continuous mode, software trigger . . . . .396
Figure 65.AUTODLY = 1, regular HW conversions interrupted by injected conversions
(DISCEN = 0; JDISCEN = 0) . . . . .		396
Figure 66.AUTODLY = 1, regular HW conversions interrupted by injected conversions . . . . .
(DISCEN = 1, JDISCEN = 1) . . . . .		397
Figure 67.AUTODLY = 1, regular continuous conversions interrupted by injected conversions . . . . .398
Figure 68.AUTODLY = 1 in auto- injected mode (JAUTO = 1) . . . . .398
Figure 69.Analog watchdog guarded area . . . . .399
Figure 70.ADCy_AWDx_OUT signal generation (on all regular channels). . . . .401
Figure 71.ADCy_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . .402
Figure 72.ADCy_AWDx_OUT signal generation (on a single regular channel) . . . . .402
Figure 73.ADCy_AWDx_OUT signal generation (on all injected channels) . . . . .402
Figure 74.20-bit to 16-bit result truncation . . . . .403
Figure 75.Numerical example with 5-bit shift and rounding . . . . .403
Figure 76.Triggered regular oversampling mode (TROVS bit = 1). . . . .405
Figure 77.Regular oversampling modes (4x ratio) . . . . .406
Figure 78.Regular and injected oversampling modes used simultaneously . . . . .407
Figure 79.Triggered regular oversampling with injection . . . . .407
Figure 80.Oversampling in auto-injected mode . . . . .408
Figure 81.Temperature sensor channel block diagram . . . . .409
Figure 82.VBAT channel block diagram . . . . .410
Figure 83.VREFINT channel block diagram . . . . .411
Figure 84.RNG block diagram . . . . .446
Figure 85.Entropy source model. . . . .447
Figure 86.RNG initialization overview . . . . .450
Figure 87.AES block diagram . . . . .458
Figure 88.ECB encryption and decryption principle . . . . .460
Figure 89.CBC encryption and decryption principle . . . . .461
Figure 90.CTR encryption and decryption principle . . . . .462
Figure 91.GCM encryption and authentication principle . . . . .463
Figure 92.GMAC authentication principle . . . . .463
Figure 93.CCM encryption and authentication principle . . . . .464
Figure 94.Encryption key derivation for ECB/CBC decryption (Mode 2). . . . .467
Figure 95.Example of suspend mode management . . . . .468
Figure 96.ECB encryption . . . . .469
Figure 97.ECB decryption . . . . .469
Figure 98.CBC encryption . . . . .470
Figure 99.CBC decryption . . . . .470
Figure 100.ECB/CBC encryption (Mode 1) . . . . .471
Figure 101.ECB/CBC decryption (Mode 3) . . . . .472
Figure 102.Message construction in CTR mode . . . . .474
Figure 103.CTR encryption . . . . .475
Figure 104.CTR decryption . . . . .475
Figure 105.Message construction in GCM . . . . .477
Figure 106.GCM authenticated encryption . . . . .478
Figure 107.Message construction in GMAC mode . . . . .482
Figure 108.GMAC authentication mode . . . . .482
Figure 109.Message construction in CCM mode . . . . .483
Figure 110.CCM mode authenticated encryption . . . . .485
Figure 111.128-bit block construction with respect to data swap . . . . .489
Figure 112.DMA transfer of a 128-bit data block during input phase . . . . .491
Figure 113.DMA transfer of a 128-bit data block during output phase . . . . .492
Figure 114.PKA block diagram . . . . .507
Figure 115.Advanced-control timer block diagram . . . . .534
Figure 116.Counter timing diagram with prescaler division change from 1 to 2 . . . . .536
Figure 117.Counter timing diagram with prescaler division change from 1 to 4 . . . . .536
Figure 118.Counter timing diagram, internal clock divided by 1 . . . . .538
Figure 119.Counter timing diagram, internal clock divided by 2 . . . . .538
Figure 120.Counter timing diagram, internal clock divided by 4 . . . . .539
Figure 121.Counter timing diagram, internal clock divided by N . . . . .539
Figure 122.Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .540
Figure 123.Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .540
Figure 124.Counter timing diagram, internal clock divided by 1 . . . . .542
Figure 125.Counter timing diagram, internal clock divided by 2 . . . . .542
Figure 126.Counter timing diagram, internal clock divided by 4 . . . . .543
Figure 127.Counter timing diagram, internal clock divided by N . . . . .543
Figure 128.Counter timing diagram, update event when repetition counter is not used . . . . .544
Figure 129.Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .545
Figure 130.Counter timing diagram, internal clock divided by 2 . . . . .546
Figure 131.Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .546
Figure 132.Counter timing diagram, internal clock divided by N . . . . .547
Figure 133.Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .547
Figure 134.Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .548
Figure 135.Update rate examples depending on mode and TIMx_RCR register settings . . . . .549
Figure 136.External trigger input block . . . . .550
Figure 137.TIM1 ETR input circuitry . . . . .550
Figure 138.Control circuit in normal mode, internal clock divided by 1 . . . . .551
Figure 139.TI2 external clock connection example . . . . .552
Figure 140.Control circuit in external clock mode 1 . . . . .553
Figure 141.External trigger input block . . . . .553
Figure 142.Control circuit in external clock mode 2 . . . . .554
Figure 143.Capture/compare channel (example: channel 1 input stage) . . . . .555
Figure 144.Capture/compare channel 1 main circuit . . . . .555
Figure 145.Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .556
Figure 146.Output stage of capture/compare channel (channel 4) . . . . .556
Figure 147. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .557
Figure 148. PWM input mode timing . . . . .559
Figure 149. Output compare mode, toggle on OC1 . . . . .561
Figure 150. Edge-aligned PWM waveforms (ARR=8) . . . . .562
Figure 151. Center-aligned PWM waveforms (ARR=8) . . . . .563
Figure 152. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .565
Figure 153. Combined PWM mode on channel 1 and 3 . . . . .566
Figure 154. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .567
Figure 155. Complementary output with dead-time insertion . . . . .568
Figure 156. Dead-time waveforms with delay greater than the negative pulse . . . . .568
Figure 157. Dead-time waveforms with delay greater than the positive pulse . . . . .569
Figure 158. Break and Break2 circuitry overview . . . . .571
Figure 159. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .573
Figure 160. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .574
Figure 161. PWM output state following BRK assertion (OSSI=0) . . . . .575
Figure 162. Output redirection (BRK2 request not represented) . . . . .576
Figure 163. Clearing TIMx OCxREF . . . . .577
Figure 164. 6-step generation, COM example (OSSR=1) . . . . .578
Figure 165. Example of one pulse mode . . . . .579
Figure 166. Retriggerable one pulse mode . . . . .581
Figure 167. Example of counter operation in encoder interface mode . . . . .582
Figure 168. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .583
Figure 169. Measuring time interval between edges on 3 signals . . . . .584
Figure 170. Example of Hall sensor interface . . . . .586
Figure 171. Control circuit in reset mode . . . . .587
Figure 172. Control circuit in Gated mode . . . . .588
Figure 173. Control circuit in trigger mode . . . . .589
Figure 174. Control circuit in external clock mode 2 + trigger mode . . . . .590
Figure 175. General-purpose timer block diagram . . . . .633
Figure 176. Counter timing diagram with prescaler division change from 1 to 2 . . . . .635
Figure 177. Counter timing diagram with prescaler division change from 1 to 4 . . . . .635
Figure 178. Counter timing diagram, internal clock divided by 1 . . . . .636
Figure 179. Counter timing diagram, internal clock divided by 2 . . . . .637
Figure 180. Counter timing diagram, internal clock divided by 4 . . . . .637
Figure 181. Counter timing diagram, internal clock divided by N . . . . .638
Figure 182. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .638
Figure 183. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) . . . . .639
Figure 184. Counter timing diagram, internal clock divided by 1 . . . . .640
Figure 185. Counter timing diagram, internal clock divided by 2 . . . . .640
Figure 186. Counter timing diagram, internal clock divided by 4 . . . . .641
Figure 187. Counter timing diagram, internal clock divided by N . . . . .641
Figure 188. Counter timing diagram, Update event . . . . .642
Figure 189. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .643
Figure 190. Counter timing diagram, internal clock divided by 2 . . . . .644
Figure 191. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .644
Figure 192. Counter timing diagram, internal clock divided by N . . . . .645
Figure 193. Counter timing diagram, Update event with ARPE=1 (counter underflow) . . . . .645
Figure 194. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .646
Figure 195. Control circuit in normal mode, internal clock divided by 1 . . . . .647
Figure 196. TI2 external clock connection example . . . . .647
Figure 197. Control circuit in external clock mode 1 . . . . .648
Figure 198. External trigger input block . . . . .649
Figure 199. Control circuit in external clock mode 2 . . . . .650
Figure 200. Capture/Compare channel (example: channel 1 input stage) . . . . .650
Figure 201. Capture/Compare channel 1 main circuit . . . . .651
Figure 202. Output stage of Capture/Compare channel (channel 1) . . . . .651
Figure 203. PWM input mode timing . . . . .653
Figure 204. Output compare mode, toggle on OC1 . . . . .655
Figure 205. Edge-aligned PWM waveforms (ARR=8) . . . . .656
Figure 206. Center-aligned PWM waveforms (ARR=8) . . . . .658
Figure 207. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .659
Figure 208. Combined PWM mode on channels 1 and 3 . . . . .660
Figure 209. Clearing TIMx_OCxREF . . . . .661
Figure 210. Example of one-pulse mode . . . . .662
Figure 211. Retriggerable one-pulse mode . . . . .664
Figure 212. Example of counter operation in encoder interface mode . . . . .665
Figure 213. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .666
Figure 214. Control circuit in reset mode . . . . .667
Figure 215. Control circuit in gated mode . . . . .668
Figure 216. Control circuit in trigger mode . . . . .669
Figure 217. Control circuit in external clock mode 2 + trigger mode . . . . .670
Figure 218. Master/Slave timer example . . . . .670
Figure 219. Master/slave connection example with 1 channel only timers . . . . .671
Figure 220. Gating TIM2 with OC1REF of TIM1 . . . . .672
Figure 221. Gating TIM2 with Enable of TIM1 . . . . .673
Figure 222. Triggering TIM2 with update of TIM1 . . . . .673
Figure 223. Triggering TIM2 with Enable of TIM1 . . . . .674
Figure 224. TIM16/TIM17 block diagram . . . . .704
Figure 225. Counter timing diagram with prescaler division change from 1 to 2 . . . . .706
Figure 226. Counter timing diagram with prescaler division change from 1 to 4 . . . . .706
Figure 227. Counter timing diagram, internal clock divided by 1 . . . . .708
Figure 228. Counter timing diagram, internal clock divided by 2 . . . . .708
Figure 229. Counter timing diagram, internal clock divided by 4 . . . . .709
Figure 230. Counter timing diagram, internal clock divided by N . . . . .709
Figure 231. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .710
Figure 232. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .710
Figure 233. Update rate examples depending on mode and TIMx_RCR register settings . . . . .712
Figure 234. Control circuit in normal mode, internal clock divided by 1 . . . . .713
Figure 235. TI2 external clock connection example . . . . .713
Figure 236. Control circuit in external clock mode 1 . . . . .714
Figure 237. Capture/compare channel (example: channel 1 input stage) . . . . .715
Figure 238. Capture/compare channel 1 main circuit . . . . .715
Figure 239. Output stage of capture/compare channel (channel 1) . . . . .716
Figure 240. Output compare mode, toggle on OC1 . . . . .719
Figure 241. Edge-aligned PWM waveforms (ARR=8) . . . . .720
Figure 242. Complementary output with dead-time insertion . . . . .721
Figure 243. Dead-time waveforms with delay greater than the negative pulse . . . . .721
Figure 244. Dead-time waveforms with delay greater than the positive pulse . . . . .722
Figure 245. Output behavior in response to a break . . . . .724
Figure 246. Output redirection . . . . .726
Figure 247. 6-step generation, COM example (OSSR=1) . . . . .727
Figure 248. Example of one pulse mode . . . . .728
Figure 249.Low-power timer block diagram . . . . .755
Figure 250.Glitch filter timing diagram . . . . .758
Figure 251.LPTIM output waveform, single counting mode configuration . . . . .759
Figure 252.LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set). . . . .		760
Figure 253.LPTIM output waveform, Continuous counting mode configuration . . . . .760
Figure 254.Waveform generation . . . . .762
Figure 255.Encoder mode counting sequence . . . . .766
Figure 256.IRTIM internal hardware connections with TIM16 and TIM17 . . . . .778
Figure 257.RTC block diagram . . . . .781
Figure 258.Independent watchdog block diagram . . . . .820
Figure 259.Watchdog block diagram . . . . .830
Figure 260.Window watchdog timing diagram . . . . .831
Figure 261.I2C block diagram . . . . .837
Figure 262.I2C bus protocol . . . . .839
Figure 263.Setup and hold timings . . . . .841
Figure 264.I2C initialization flow . . . . .843
Figure 265.Data reception . . . . .844
Figure 266.Data transmission . . . . .845
Figure 267.Slave initialization flow . . . . .848
Figure 268.Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0. . . . .850
Figure 269.Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1. . . . .851
Figure 270.Transfer bus diagrams for I2C slave transmitter (mandatory events only). . . . .852
Figure 271.Transfer sequence flow for slave receiver with NOSTRETCH = 0 . . . . .853
Figure 272.Transfer sequence flow for slave receiver with NOSTRETCH = 1 . . . . .854
Figure 273.Transfer bus diagrams for I2C slave receiver
(mandatory events only) . . . . .		854
Figure 274.Master clock generation . . . . .856
Figure 275.Master initialization flow . . . . .858
Figure 276.10-bit address read access with HEAD10R = 0 . . . . .858
Figure 277.10-bit address read access with HEAD10R = 1 . . . . .859
Figure 278.Transfer sequence flow for I2C master transmitter for N ≤ 255 bytes . . . . .860
Figure 279.Transfer sequence flow for I2C master transmitter for N > 255 bytes . . . . .861
Figure 280.Transfer bus diagrams for I2C master transmitter
(mandatory events only) . . . . .		862
Figure 281.Transfer sequence flow for I2C master receiver for N ≤ 255 bytes . . . . .864
Figure 282.Transfer sequence flow for I2C master receiver for N > 255 bytes . . . . .865
Figure 283.Transfer bus diagrams for I2C master receiver
(mandatory events only) . . . . .		866
Figure 284.Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .870
Figure 285.Transfer sequence flow for SMBus slave transmitter N bytes + PEC. . . . .873
Figure 286.Transfer bus diagrams for SMBus slave transmitter (SBC = 1) . . . . .874
Figure 287.Transfer sequence flow for SMBus slave receiver N bytes + PEC. . . . .875
Figure 288.Bus transfer diagrams for SMBus slave receiver (SBC = 1). . . . .876
Figure 289.Bus transfer diagrams for SMBus master transmitter. . . . .877
Figure 290.Bus transfer diagrams for SMBus master receiver . . . . .879
Figure 291.USART block diagram . . . . .903
Figure 292.Word length programming . . . . .906
Figure 293.Configurable stop bits . . . . .908
Figure 294.TC/TXE behavior when transmitting . . . . .911
Figure 295.Start bit detection when oversampling by 16 or 8. . . . .912
Figure 296.usart_ker_ck clock divider block diagram. . . . .915
Figure 297.Data sampling when oversampling by 16 . . . . .916
Figure 298.Data sampling when oversampling by 8 . . . . .917
Figure 299.Mute mode using Idle line detection . . . . .924
Figure 300.Mute mode using address mark detection . . . . .925
Figure 301.Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .928
Figure 302.Break detection in LIN mode vs. Framing error detection. . . . .929
Figure 303.USART example of synchronous master transmission. . . . .930
Figure 304.USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		930
Figure 305.USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		931
Figure 306.USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		932
Figure 307.ISO 7816-3 asynchronous protocol . . . . .934
Figure 308.Parity error detection using the 1.5 stop bits . . . . .936
Figure 309.IrDA SIR ENDEC block diagram. . . . .940
Figure 310.IrDA data modulation (3/16) - normal mode . . . . .940
Figure 311.Transmission using DMA . . . . .942
Figure 312.Reception using DMA . . . . .943
Figure 313.Hardware flow control between 2 USARTs . . . . .943
Figure 314.RS232 RTS flow control . . . . .944
Figure 315.RS232 CTS flow control . . . . .945
Figure 316.Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .948
Figure 317.Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		948
Figure 318.SPI block diagram. . . . .988
Figure 319.Full-duplex single master/ single slave application. . . . .989
Figure 320.Half-duplex single master/ single slave application . . . . .990
Figure 321.Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		991
Figure 322.Master and three independent slaves. . . . .992
Figure 323.Multimaster application . . . . .993
Figure 324.Hardware/software slave select management . . . . .994
Figure 325.Data clock timing diagram . . . . .995
Figure 326.Data alignment when data length is not equal to 8-bit or 16-bit . . . . .996
Figure 327.Packing data in FIFO for transmission and reception. . . . .1000
Figure 328.Master full-duplex communication . . . . .1003
Figure 329.Slave full-duplex communication . . . . .1004
Figure 330.Master full-duplex communication with CRC . . . . .1005
Figure 331.Master full-duplex communication in packed mode . . . . .1006
Figure 332.NSSP pulse generation in Motorola SPI master mode. . . . .1009
Figure 333.TI mode transfer . . . . .1010
Figure 334.IPCC block diagram . . . . .1023
Figure 335.IPCC Simplex channel mode transfer timing . . . . .1024
Figure 336.IPCC Simplex - Send procedure state diagram . . . . .1025
Figure 337.IPCC Simplex - Receive procedure state diagram . . . . .1026
Figure 338.IPCC Half-duplex channel mode transfer timing. . . . .1027
Figure 339.IPCC Half-duplex - Send procedure state diagram . . . . .1027
Figure 340.IPCC Half-duplex - Receive procedure state diagram . . . . .1028
Figure 341.HSEM block diagram . . . . .1037
Figure 342.Procedure state diagram . . . . .1038
Figure 343.Interrupt state diagram . . . . .1041
Figure 344. Block diagram of debug support infrastructure . . . . .1052
Figure 345. JTAG TAP state machine . . . . .1055
Figure 346. Debug and access port connections. . . . .1067
Figure 347. Embedded cross trigger . . . . .1074
Figure 348. Mapping trigger inputs to outputs . . . . .1076
Figure 349. Cross trigger configuration example . . . . .1077
Figure 350. CPU2 CoreSight™ topology . . . . .1103
Figure 351. CPU1 CoreSight™ topology . . . . .1138
Figure 352. Trace port interface unit (TPIU) . . . . .1173

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