67. Revision history

Table 642. Document revision history

DateRevisionChanges
30-Oct-20191Initial release.
24-Jun-20202

Added STM43H730xB microcontrollers.
Added Section 1.5: Availability of security features .

Section 4: Embedded Flash memory (FLASH)
Added STM32H730xB devices and changed user Flash memory density to “up to 1 Mbyte” to take into account 128 Kbyte and 512 Kbyte devices.
Updated Table 16: FLASH recommended number of wait states and programming delay .

Section 5: Secure memory management (SMM)
Changed part numbers on which the Secure memory management is available to STM32H73x.

Section 6: Power control (PWR)
Replace voltage regulator by LDO voltage regulator in the whole chapter.
Replaced Run mode by Run and Autonomous modes in Section : LDO voltage regulator , Section 6.4.3: PWR external supply and Section 6.6.3: Power control modes .
In Section 6.4.4: Backup domain , updated list of GPIOs whose use is restricted when \( V_{DD} \) is higher than the PDR threshold.
Updated Section 6.6.3: Power control modes .
Updated Section 6.7.8: Stop mode .
Added note to DBP bit in PWR control register 1 (PWR_CR1) .

Section 8: Reset and clock control (RCC)
Updated max HSE frequency in Section 8.1: RCC main features .
Updated Section : External crystal/ceramic resonator .
Updated Table 56: Kernel clock distribution overview . Changed 500 MHz and 250 MHz to 550 MHz and 275 MHz in Figure 49: Core and bus clock generation .
Updated internal signal names in Figure 50: Kernel clock distribution for SAIs and SPDIFRX .
Changed SPDIFSEL into SPDIFRXSEL and IS2123SEL into SPI123SEL in Figure 52: Kernel clock distribution for SPIs and SPI/I2S .
Changed OSPISEL into OCTOSPISEL, OSPI[2:1]EN/OSPI[2:1]LEN into OCTOSPI[2:1]EN/OCTOSPI[2:1]LPEN, and updated internal signal names in Figure 56: Kernel clock distribution for SDMMC, OCTOSPI and FMC .
Updated Figure 57: Kernel clock distribution for USB (2) .
Renamed SWPMI-related bits in Figure 59: Kernel clock distribution for ADCs, SWPMI, RNG and FDCAN (2) .
Renamed LPTIM internal signals in Figure 60: Kernel clock distribution for LPTIMs and HDMI-CEC (2) .
Updated HSECSSON bit description in RCC source control register (RCC_CR) .

Table 642. Document revision history (continued)

DateRevisionChanges
24-Jun-20202 (continued)

Section 8: Reset and clock control (RCC) (continued)
Replaced TMPSENS by DTS in RCC_APB4RSTR/ENR/LPENR and RCC_D3AMR and in RCC_C1_APB4ENR/LPENR.
Renamed SPDIFSEL into SPDIFRXSEL and SWPSEL into SWPMISEL in RCC domain 2 kernel clock configuration register (RCC_D2CCIP1R) .
Renamed OSPISEL into OCTOSPISEL in RCC domain 1 kernel clock configuration register (RCC_D1CCIPR) , renamed OCTO[2:1]RST into OCTOSPI[2:1]RST in RCC AHB3 reset register (RCC_AHB3RSTR) , OSPI[2:1]EN into OCTOSPI[2:1]EN in RCC AHB3 clock register (RCC_AHB3ENR) , and OSPI[2:1]LEN into OCTOSPI[2:1]LPEN in RCC AHB3 Sleep clock register (RCC_AHB3LPENR) . Renamed SWPRST into SWPMIRST in RCC APB1 peripheral reset register (RCC_APB1HRSTR) , SWPEN into SWPMIEN in WPMIRST in RCC APB1 clock register (RCC_APB1HENR) , and SWPLPEN into SWPMILPEN in RCC APB1 clock register (RCC_APB1LENR) .
Updated DIVR2EN, DIVQ2EN, DIVP2EN, DIVR1EN of RCC PLLs Configuration Register (RCC_PLLCFGR) .

Section 13: Block interconnect.
In Table 94: Peripherals interconnect matrix details , change PTPx and PPS into eth_ptp_trgx and eth_ptp_pps_out, respectively.

Section 12: System configuration controller (SYSCFG)
Added note related to PC3SO, PC2SO, PA1SO and PA0SO reset value and updated BOOSTVDDSEL bit description in Section 12.4.1: SYSCFG peripheral mode configuration register (SYSCFG_PMCR) .

Section 15: Direct memory access controller (DMA)
Bit 20 of DMA stream x configuration register (DMA_SxCR) changed from reserved to TRBUFF for the products listed.

Section 17: DMA request multiplexer (DMAMUX)
Updated Section 17.4.4: DMAMUX request line multiplexer .

Section 24: Flexible memory controller (FMC)
Updated Section : General transaction rules to clarify the behavior of the FMC when the AXI transaction data size is different from the device data width and add the case of unaligned addresses.
Replaced FMC_CLK by fmc_ker_ck in the formulas of Section : WAIT management in asynchronous accesses .

Section 25: Octo-SPI interface (OCTOSPI)
Updated Section 25.2: OCTOSPI main features and Section 25.3: OCTOSPI implementation .
Updated WRAP support part in Section 25.4.6: Specific features .
Updated Section 25.4.10: OCTOSPI Memory-mapped mode .
Updated Section : Sending the instruction only once (SIOO) .
Modified ABORT and EN bit description in Section 25.7.1: OCTOSPI control register (OCTOSPI_CR) , FLEVEL bit description in Section 25.7.6: OCTOSPI status register (OCTOSPI_SR) and DLYBYP bit in Section 25.7.2: OCTOSPI device configuration register 1 (OCTOSPI_DCR1) .

Table 642. Document revision history (continued)

DateRevisionChanges
24-Jun-20202 (continued)

Section 26: OCTOSPI I/O manager (OCTOSPIM)
Updated ports for pin assignment from 3 to 2.

Section 28: Analog-to-digital converters (ADC1/ADC2)
Added adc_sclk in Figure 160: ADC block diagram and Table 221: ADC input/output pins and removed V REF+ and V REF- ranges from this table.
Updated Section 28.4.3: ADC clocks .
Updated Section : ADC overrun (OVR, OVRMOD) . Added case of FIFO overflow in Section : Managing a sequence of conversion without using the DMA .
Updated Section : Single ADC operating modes support when oversampling to remove the mention that the offset correction is not supported in oversampling mode.
Updated RES[2:0] bitfield definition in Section 28.6.4: ADC configuration register (ADC_CFGR) . Replaced adc_hclk by adc_hclk in CKMODE[1:0] bitfield definition of Section 28.7.2: ADC common control register (ADCx_CCR) (x=1/2) .

Section 29: Analog-to-digital converters (ADC3)
Added description of output data and formula to compute the converted value in Section 29.4.7: Single-ended and differential input channels .
Updated Section : ADC overrun (OVR, OVRMOD) and Added case of FIFO overflow in Section : Managing a sequence of conversions without using the DMA .
Added SMP19[2:0] in Section 29.6.7: ADC sample time register 2 (ADC_SMPR2) .
Added note to OFFSETy_CH[4:0] in Section 29.6.17: ADC offset y register (ADC_OF Ry) .

Section 30: Digital temperature sensor (DTS)
Removed EN pin from Figure 284: Temperature sensor functional block diagram .
Updated formula to calculate the temperature when PCLK is used in Section 30.3.7: Temperature measurement principles .
Removed startup time value from Section 30.3.11: On-off control and ready flag .
Removed TS1_EN of Temperature sensor configuration register 1 (DTS_CFGR1) and replaced list of triggers in TS1_INTRIG_SEL[3:0] by a reference to Table Trigger configuration in DTS_CFGR1 .

Section 31: Digital-to-analog converter (DAC)
Removed DAC acronym in Section 31.4.9: Noise generation and Section 31.4.10: Triangle-wave generation .
Updated the way to stop LSI clock in Section 31.4.11: DAC channel modes/Section : Sample and hold mode .
In TSEL1/2 of Section 31.7.1: DAC control register (DAC_CR) , changed internal trigger signal names from dac_ch1_trigx/dac_ch2_trigx to dac_ch1_trgx/dac_ch2_trgx.

Table 642. Document revision history (continued)

DateRevisionChanges
24-Jun-20202 (continued)

Section 32: Voltage reference buffer (VREFBUF)
Updated VRS in Section 32.3.1: VREFBUF control and status register (VREFBUF_CSR) .
Updated TRIM in Section 32.3.2: VREFBUF calibration control register (VREFBUF_CCR) .

Section 37: Parallel synchronous slave interface (PSSI)
Updated Figure 326: PSSI block diagram and Figure 327: Top-level block diagram .

Section 38: LCD-TFT display controller (LTDC)
Updated Figure 333: LTDC block diagram and Figure : Example of synchronous timings configuration .

Section 39: True random number generator (RNG)
Updated Section 39.1: Introduction .
Updated Section 39.3.3: Random number generation .
Updated Figure 339: NIST SP800-90B entropy source model and Figure 340: RNG initialization overview .
Updated Section 39.6: RNG entropy source validation and Section 39.6.3: Data collection .

Section 43: Advanced-control timers (TIM1/TIM8)
Updated Figure 400: Control circuit in external clock mode 2 .
Updated Section 43.4.20: TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) .
Updated BKINP, BKCMP1P and BKCMP2P bit descriptions in TIMx_AF1 registers, and BK2INP in TIMx_AF2.

Section 44: General-purpose timers (TIM2/TIM3/TIM4/TIM5/TIM23/TIM24)
Updated Figure 433: General-purpose timer block diagram .
Updated Figure 457: Control circuit in external clock mode 2 .
Updated Figure 459: Capture/Compare channel 1 main circuit .
Updated Figure 460: Output stage of Capture/Compare channel (channel 1) .
Updated Section 44.4.2: TIMx control register 2 (TIMx_CR2)(x = 2 to 5, 23, 24) and Section 44.4.7: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 5, 23, 24) .
Updated Table 356: Output control bit for standard OCx channels .

Table 642. Document revision history (continued)

DateRevisionChanges
24-Jun-20202 (continued)

Section 45: General-purpose timers (TIM12/TIM13/TIM14)
Updated Figure 484: General-purpose timer block diagram (TIM13/TIM14) .
Updated Figure 497: Capture/compare channel 1 main circuit and Figure 498: Output stage of capture/compare channel (channel 1) .
Updated Section 45.3.6: PWM input mode (only for TIM12) .
Added Section 45.3.18: Using timer output as trigger for other timers (TIM13/TIM14) . Updated Section 45.4.2: TIM12 control register 2 (TIM12_CR2) and Section 45.4.7: TIM12 capture/compare mode register 1 [alternate] (TIM12_CCMR1) . Updated Section 45.5.5: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 13 to 14) and Table 361: Output control bit for standard OCx channels .

Section 46: General-purpose timers (TIM15/TIM16/TIM17)
Updated note below Figure 509: TIM15 block diagram and modified Figure 510: TIM16/TIM17 block diagram .
Updated Figure 524: Capture/compare channel 1 main circuit , Figure 525: Output stage of capture/compare channel (channel 1) and Figure 526: Output stage of capture/compare channel (channel 2 for TIM15) .
Updated Section 46.4.7: PWM input mode (only for TIM15) .
Updated Section 46.4.13: Using the break function and Figure 534: Break circuitry overview .
Added Section 46.4.24: Using timer output as trigger for other timers (TIM16/TIM17) .
Updated Section 46.4.13: Using the break function and Figure 534: Break circuitry overview .
Updated Section 46.5.2: TIM15 control register 2 (TIM15_CR2) , Section 46.5.7: TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) and Table 365: Output control bits for complementary OCx and OCxN channels with break feature (TIM15) .
Updated Table 368: TIM16/TIM17 register map and reset values .

Section 48: Low-power timer (LPTIM)
Updated Section 48.2: LPTIM main features and Section 48.4.4: LPTIM reset and clocks .
Updated Section 48.4.5: Glitch filter .
Updated Section 48.7.4: LPTIM configuration register (LPTIM_CFGR) .

Section 49: System window watchdog (WWDG)
Updated Section 49.4.3: Enabling the watchdog .

Section 53: Universal synchronous/asynchronous receiver transmitter (USART/UART)
Updated decimal and hexadecimal notation for values in Section : How to derive USARTDIV from USART_BRR register values .
Updated SBKF bit description in Section 53.8.10: USART interrupt and status register [alternate] (USART_ISR) .
Updated PSC[7:0] bitfield description in Section 53.8.6: USART guard time and prescaler register (USART_GTPR) .

Table 642. Document revision history (continued)

DateRevisionChanges
24-Jun-20202 (continued)

Section 54: Low-power universal asynchronous receiver transmitter (LPUART)
Added Section 54.3: LPUART implementation .
Updated SBKF bit description in Section 54.7.7: LPUART interrupt and status register [alternate] (LPUART_ISR) .

Section 55: Serial peripheral interface (SPI)
Updated Section 55.2: SPI main features , Section 55.3: SPI implementation and Section 55.4.2: SPI signals
Updated Section 55.4.5: Standard multi-slave communication , Section 55.4.7: Slave select (SS) pin management , Section 55.4.8: Communication formats , Section 55.4.9: Configuration of SPI , Section 55.4.10: Procedure for enabling SPI and Section 55.4.11: SPI data transmission and reception procedures .
Updated Figure 653: Packing data in FIFO for transmission and reception .
Updated Section 55.5.1: TI mode , Section 55.5.2: SPI error flags and Section 55.5.3: CRC computation .
Updated Section 55.7: SPI wakeup and interrupts .
Updated Section 55.11.6: SPI/I2S status register (SPI_SR) , Section 55.11.3: SPI configuration register 1 (SPI_CFG1) , Section 55.11.4: SPI configuration register 2 (SPI_CFG2) , Section 55.11.6: SPI/I2S status register (SPI_SR) , Section 55.11.8: SPI/I2S transmit data register (SPI_TXDR) , Section 55.11.9: SPI/I2S receive data register (SPI_RXDR) , Section 55.11.10: SPI polynomial register (SPI_CRCPOLY) , Section 55.11.11: SPI transmitter CRC register (SPI_TXCRC) , Section 55.11.12: SPI receiver CRC register (SPI_RXCRC) and Section 55.11.13: SPI underrun data register (SPI_UDRDR) .
Updated Table 441: SPI register map and reset values .

Section 58: Single wire protocol master interface (SWPMI)
Modified name of bit and register to select SWPMI in Section Figure 716.: SWPMI block diagram .
Replaced SWPSCR of RCC_D2CCIP1R by SWPSEL of RCC_CDCCIP1R in Figure 716: SWPMI block diagram .

Section 63: Ethernet (ETH): media access control (MAC) with DMA controller
Replaced ptp_pps_o internal signal by eth_ptp_pps_out, ptp_aux_ts_trig_i by eth_ptp_trgx (where x = 0 to 3) and ptp_aux_trig_i[x] by eth_ptp_trgx in IEEE 1588 auxiliary snapshots .
Updated ARPEN bit description in Operating mode configuration register (ETH_MACCR) .
Removed sentence “This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input” from System time nanoseconds register (ETH_MACSTNR) , System time seconds update register (ETH_MACSTSUR) and System time nanoseconds update register (ETH_MACSTNUR) register descriptions.

Section 66: Device electronic signature
Added Section 66.3: Line identifier .

Table 642. Document revision history (continued)

DateRevisionChanges
13-Dec-20213

Added errata sheet in the list of reference documents as well as mention that patents apply to the microcontrollers on document cover page.

Section 2: Memory and bus architecture
Updated Section : Embedded bootloader .
Updated DFSDM1 base address in Table 7: Register boundary addresses .

Section 4: Embedded Flash memory (FLASH)
Added note indicating the only sections 0 to 3 are available on 512 Kbyte devices in Table 15: Flash memory organization (STM32H723/733 and STM32H725/735 devices) .
Better specified the registers reset by System reset in Section 8.4.2: System reset .
Section 4.4.7: Description of boot address option bytes .
Updated FAIL_ECC_ADDR[14:0] description in FLASH ECC fail address (FLASH_ECC_FAR) .

Section 6: Power control (PWR)
Updated Figure 18: Power supply overview .
Added note on VDDLDO in Table 28: PWR input/output signals connected to package pins or balls .
Updated Section : VCORE supplied in Bypass mode (LDO and SMPS OFF) .
Added Section : How to exit from Run* mode .

Section 8: Reset and clock control (RCC)
Updated VREFRST bit description In RCC APB4 peripheral reset register (RCC_APB4RSTR) and VREFEN bit description in RCC APB4 clock register (RCC_APB4ENR) to mention VREFBUF.
Updated RCC reset status register (RCC_RSR) , RCC APB1 Low Sleep clock register (RCC_APB1LLPENR) and RCC APB2 Sleep clock register (RCC_APB2LPENR) reset values.

Section 9: Clock recovery system (CRS)
Added note relative to the trimming step size in Section : FELIM value .
Modified CRS control register (CRS_CR) reset value.

Section 10: Hardware semaphore (HSEM)
Updated Section 10.3.2: HSEM internal signals , Section 10.3.3: HSEM lock procedures , Section 10.3.5: HSEM unlock procedures , Section 10.3.6: HSEM MASTERID semaphore clear , Section 10.3.7: HSEM interrupts and Section 10.3.8: AHB bus master ID verification .
Updated HSEM register semaphore x (HSEM_Rx) , HSEM read lock register semaphore x (HSEM_RLRx) and HSEM interrupt status register (HSEM_MISR) .

Table 642. Document revision history (continued)

DateRevisionChanges
13-Dec-20213 (continued)

Section 12: System configuration controller (SYSCFG)
Updated BOOSTVDDSEL description and added note related to PC3SO, PC2SO, PA1SO and PA0SO reset value in SYSCFG peripheral mode configuration register (SYSCFG_PMCR) .

Section 13: Block interconnect
Updated TIM23/TIM24 in Table 92: Peripherals interconnect matrix (D2 domain) .

Section 19: Nested vectored interrupt controller (NVIC)
Replaced UART9_IT_OR_UART9_WKUP by UART9 in Table 140: NVIC .

Section 20: Extended interrupt and event controller (EXTI)
Remove note 4 related to WKUP sources in Table 143: EXTI Event input mapping .

Section 14: MDMA controller (MDMA)
Removed SM bit in MDMA channel x control register (MDMA_CxCR) .

Section 17: DMA request multiplexer (DMAMUX)
Updated Section 17.4.4: DMAMUX request line multiplexer .

Section 18: Chrom-Art Accelerator controller (DMA2D)
Updated Section 18.3.2: DMA2D internal signals .

Section 21: Cyclic redundancy check calculation unit (CRC)
Added note in Section : Polynomial programmability to clarify what are even and odd polynomials.
Added CRC register access granularity in Section 21.2: CRC main features and Section 21.4: CRC registers .
Updated Figure 97: CRC calculation unit block diagram .

Section 25: Octo-SPI interface (OCTOSPI)
Renamed DDR mode into DTR, Status-polling into Automatic status-polling, nCS and CS pins into NCS, and nCLK into NCLK.
Updated Section 25.2: OCTOSPI main features , all block diagram and extended CSHT in Table 209: OCTOSPI implementation
Updated Section : Dual-quad configuration . Added new note after Figure 146 , Figure 147 , and Figure 148 .
Updated Section 25.4.8: OCTOSPI Indirect mode . Updated note at the beginning of Section 25.4.10: OCTOSPI Memory-mapped mode . Updated Section 25.4.14: OCTOSPI Regular-command mode configuration .
Added Section 25.5: Address alignment and data number
Renamed DQM bit into DMM and updated FSEL bit in OCTOSPI control register (OCTOSPI_CR) .
Updated DEVSIZE description in OCTOSPI device configuration register 1 (OCTOSPI_DCR1) .
Updated REFRESH description in OCTOSPI device configuration register 4 (OCTOSPI_DCR4) .

Table 642. Document revision history (continued)

DateRevisionChanges
13-Dec-20213 (continued)

Section 26: OCTOSPI I/O manager (OCTOSPIM)
Added Table 214: OCTOSPIM implementation .
Updated Section 26.4.3: OCTOSPIM multiplexed mode .
Changed nCS into NCS in Section : Pin mapping in Multiplexed mode , and in Section 26.5.2: OCTOSPIM Port n configuration register (OCTOSPIM_PnCR) .
Changed CLKn into NCLK in Section 26.5.2: OCTOSPIM Port n configuration register (OCTOSPIM_PnCR) .
Updated Section 26.4.3: OCTOSPIM multiplexed mode and OCTOSPIM control register (OCTOSPIM_CR) .

Section 27: Delay block (DLYB)
Updated Section 27.3.3: General description .
Updated Section 27.3.4: Delay line length configuration procedure .
Updated Section 27.3.5: Output clock phase configuration procedure .

Section 28: Analog-to-digital converters (ADC1/ADC2)
Remove ADC supply requirements from Table 221: ADC input/output pins
Added Section : Constraints between ADC clocks .
Updated Figure 193: Example of overrun (OVRMOD = 0) , Figure 199: AUTDLY=1 in auto- injected mode (JAUTO=1) , Figure 208: Regular and injected oversampling modes used simultaneously , and Figure 209: Triggered regular oversampling with injection .
Replaced ADCx_CCR by ADCx_CDR in Section : Regular simultaneous mode with independent injected .

Section 29: Analog-to-digital converters (ADC3)
Remove ADC supply requirements from Table 240: ADC input/output pins .
Added data register FIFO depth in Table 239: ADC features .
Added Section : Constraints between ADC clocks .
Reworded Section : Offset compensation .
Updated Figure 262: Example of overrun (OVRMOD = 0) , Figure 268: AUTODLY = 1 in auto- injected mode (JAUTO = 1) , Figure 278: Regular and injected oversampling modes used simultaneously , and Figure 279: Triggered regular oversampling with injection .
Updated Section : Calculating the actual V REF+ voltage using the internal reference voltage and Section : Converting a supply-relative ADC measurement to an absolute voltage value .
Updated Figure 276: Triggered regular oversampling mode (TROVS bit = 1) .
Suppressed ADC common status register (ADC_CSR) . Updated and ADC common control register (ADC_CCR) address offset.
Updated master ADC in Table 252: ADC global register map .

Section 32: Voltage reference buffer (VREFBUF)
Updated Section 32.2: VREFBUF functional description .

Table 642. Document revision history (continued)

DateRevisionChanges
13-Dec-20213 (continued)

Section 30: Digital temperature sensor (DTS)
Updated Figure 284: Temperature sensor functional block diagram .
Updated signals to which ts1_trg0 to 3 are connected in Table 257: Trigger configuration . Changed TS1_T0[1:0] = 01 definition to 130 °C in Temperature sensor T0 value register 1 (DTS_T0VALR1) .
Updated TS1_LITTHD bitfield description in Temperature sensor interrupt threshold register 1 (DTS_ITR1) .

Section 39: True random number generator (RNG)
Updated Section 39.5: RNG processing time .
Updated CLKDIV[3:0] description in RNG control register (RNG_CR) .

Section 40: Cryptographic processor (CRYP)
Updated Figure 342: AES-ECB mode overview , Figure 343: AES-CBC mode overview , Figure 344: AES-CTR mode overview , Figure 345: AES-GCM mode overview , Figure 346: AES-GMAC mode overview , Figure 347: AES-CCM mode overview , Figure 357: Message construction for the Counter mode , Figure 361: Message construction for the Galois Message Authentication Code mode , Figure 362: Message construction for the Counter with CBC-MAC mode .
Updated Table 323: Counter mode initialization vector , Table 325: GCM mode IV registers initialization , Table 326: CCM mode IV registers initialization .
Updated introduction of Section 40.4.16: CRYP data registers and data swapping , Section 40.4.17: CRYP key registers and Section 40.4.18: CRYP initialization vector registers . Updated all CRYP_KxLR/RR and CRYP_IVxLR/RR register descriptions.

Section 43: Advanced-control timers (TIM1/TIM8)
Updated Figure 396: Control circuit in normal mode, internal clock divided by 1 .
Added note in Section 43.3.16: Using the break function .
Updated OC1PE bit in TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 1, 8) .

Section 45: General-purpose timers (TIM12/TIM13/TIM14)
Updated Figure 495: Control circuit in external clock mode 1 .
Updated OC1PE bit in TIM12 capture/compare mode register 1 [alternate] (TIM12_CCMR1) and TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 13 to 14) .

Section 46: General-purpose timers (TIM15/TIM16/TIM17)
Updated Figure 520: Control circuit in normal mode, internal clock divided by 1 .
Added Section 46.4.15: 6-step PWM generation .
Added note in Section 46.4.13: Using the break function .
Suppressed CC2DE bit in TIM15 DMA/interrupt enable register (TIM15_DIER) .
Updated TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) and TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 16 to 17) .

Table 642. Document revision history (continued)

DateRevisionChanges
13-Dec-20213 (continued)

Section 48: Low-power timer (LPTIM)
Updated Section 48.2: LPTIM main features and Section 48.4.4: LPTIM reset and clocks . Added note to Section 48.4.7: Trigger multiplexer . Updated Section 48.4.15: Encoder mode .
Updated LPTIM interrupt and status register (LPTIM_ISR) , LPTIM interrupt clear register (LPTIM_ICR) and LPTIM configuration register (LPTIM_CFGR) .

Section 53: Universal synchronous/asynchronous receiver transmitter (USART/UART)
Renamed SCLK pin into CK in the whole section.
Added wakeup from Stop in Section 53.2: USART main features .
Updated Figure 623: RS232 RTS flow control and Figure 624: RS232 CTS flow control to replace nRTS and nCTS by RTS and CTS, respectively.
Updated Table 427: Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz .
Removed mention that usart_wkup interrupt is not mandatory when wakeup event is detected from Section 53.5.21: USART low-power management .
Added Section 53.6: USART in low-power modes .
Updated Section 53.7: USART interrupts .
Updated ADD[7:0] bitfield descriptions in USART control register 2 (USART_CR2) .
Updated EOBF and ABRE bit descriptions in USART interrupt and status register [alternate] (USART_ISR) . Updated ABRRQ bit description in USART request register (USART_RQR) .

Section 54: Low-power universal asynchronous receiver transmitter (LPUART)
Renamed SCLK pin to CK in the whole section.
Removed mention that lpuart_wkup interrupt is not mandatory when wakeup event is detected in Section 54.4.14: LPUART low-power management .
Added Section 54.5: LPUART in low-power modes .
Updated Section 54.6: LPUART interrupts .
Updated ABRE bit and ADD[7:0] bitfield description in LPUART control register 2 (LPUART_CR2) .

Section 55: Serial peripheral interface (SPI)
Updated Section : Data handling via RxFIFO and TxFIFO and Section 55.5.3: CRC computation .

Section 56: Serial audio interface (SAI)
Added Table 449: TDM frame configuration examples .
In Section 56.4.12: SPDIF output , replaced \( F_{\text{SAI\_CK\_x}} \) by \( F_{\text{sai\_x\_ker\_ck}} \) in the formula enabling to compute the bit rate.
Added note related to bitfield usage depending on Dx line availability in SAI PDM delay register (SAI_PDMPLY) .

Table 642. Document revision history (continued)

DateRevisionChanges
13-Dec-20213 (continued)

Section 57: SPDIF receiver interface (SPDIFRX)
Added note in about RCC capabilities in Section 57.2: SPDIFRX main features , Table 458: Minimum spdifrx_ker_ck frequency versus audio sampling rate .
Updated Figure 698: SPDIFRX block diagram , Figure 703: SPDIFRX decoder and Figure 704: Noise filtering and edge detection .

Section 60: Secure digital input/output MultiMediaCard interface (SDMMC)
Updated transmit FIFO and receive FIFO descriptions in Section : Data FIFO .
Updated SDMMC clock control register (SDMMC_CLKCR) , updated DBLOCKSIZE[3:0] in SDMMC data control register (SDMMC_DCTRL) .
Updated Table 498: SDMMC register map .

Section 61: Controller area network with flexible data rate (FDCAN)
Replaced host by user throughout the section.
Updated Software calibration and Clock calibration active .

Section 62: USB on-the-go high-speed (OTG_HS)
Updated access types for:

  • – Added ODDFRM bit in OTG host channel x characteristics register (OTG_HCCHARx)
  • – REMWAKE + BESL[3:0] in OTG core LPM configuration register (OTG_GLPMCFG) ,
  • – STALL in OTG device OUT endpoint x control register (OTG_DOEPCTLx) and RXDPID(r) / TUPCNT[1:0] in OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx) .

Section 63: Ethernet (ETH): media access control (MAC) with DMA controller
Table 543: Ethernet peripheral pins :

  • – Renamed ETH_RDX and ETH_TX port names into ETH_RXD and ETH_TXD, respectively.
  • – Added CRS_DV input.
Updated Section 63.5.3: Packet filtering .
Reworked Section 63.5.4: IEEE 1588 timestamp support .
Updated Section 63.5.5: Checksum offload engine .
Section 63.5.6: TCP segmentation offload :
  • – Added Section : DMA operation with TSO feature
  • – Renamed section Enabling the TSO feature into Section : Building the Descriptor and the packet for the TSO feature and section updated.
Updated Section 63.5.7: IPv4 ARP offload , Section 63.5.8: Loopback , Section 63.5.9: Flow control and Section 63.5.10: MAC management counters .
Added MDIO Clause 45 in Section : SMA functional overview . Updated Section : MII management write operations . Added in Section : Preamble suppression , Section : Trailing clocks and back-to-back transactions and Section : Interrupt for MDIO transaction completion .
Updated Section 63.6.2: Media independent interface (MII) and Section 63.6.3: Reduced media independent interface (RMII) .
Section 63.7: Ethernet low-power modes deeply reworked.

Table 642. Document revision history (continued)

DateRevisionChanges
13-Dec-20213 (continued)

Section 63: Ethernet (ETH): media access control (MAC) with DMA controller (continued)

Updated DMA initialization sequence in Section 63.9.1: DMA initialization .

Updated Section 63.9.3: MAC initialization and Section 63.9.5: Stopping and starting transmission .

Added Section 63.9.6: Programming guidelines for switching to new descriptor list in RxDMA , Section 63.9.7: Programming guidelines for switching the AHB clock frequency and Section 63.9.10: Programming guidelines for PTP offload feature .

Updated Section 63.9.11: Programming guidelines for Energy Efficient Ethernet (EEE) and Section 63.9.13: Programming guidelines for TSO .

Updated Table 580: TDES2 normal descriptor (read format) , Table 581: TDES3 normal descriptor (read format) , Table 585: TDES3 normal descriptor (write-back format) and Table 589: TDES3 context descriptor .

Updated Figure 842: Receive normal descriptor (read format) as well as Table 590: RDES0 normal descriptor (read format) and Table 593: RDES3 normal descriptor (read format) .

Updated Figure 843: Receive normal descriptor (write-back format) as well as Table 597: RDES3 normal descriptor (write-back format) .

Updated Table 601: RDES3 context descriptor .

Section 63.11.2: Ethernet DMA registers:

  • – Several registers updated (register reset value changed, bitfields added or description updated, bit access modified).
  • – Removed MMCIE/MMCRSIPIS and GPIIS/GPIIE from Figure 845: Generation of ETH_DMAISR flags .

Section 63.11.3: Ethernet MTL registers:

  • – several registers updated (bitfield description updated or bit access modified).

Section 63.11.4: Ethernet MAC and MMC registers:

  • – Several registers updated (register reset value changed, bitfields added or description updated, bit access modified).
  • – Added VLAN inclusion register (ETH_MACVIR) .
  • – Moved Table Timestamp snapshot dependency on register bits from Timestamp control Register (ETH_MACTSCR) to Section : Clock types .
  • – Updated System time seconds update register (ETH_MACSTSUR) and System time nanoseconds update register (ETH_MACSTNUR) .

Section 65: Debug infrastructure

Removed 100 kΩ pull-up requirement in Section : Serial wire debug port .

Updated PRESCALER[12:0] bitfield description in SWO current output divisor register (SWO_CODR) .

Index

A

ADC_AWD2CR .....1085,1193
ADC_AWD3CR .....1086,1193
ADC_CALFACT .....1089,1195
ADC_CALFACT2 .....1089
ADC_CCR .....1195
ADC_CFGR .....1067,1174
ADC_CFGR2 .....1071,1178
ADC_CR .....1062,1170
ADC_DIFSEL .....1088,1194
ADC_DR .....1081,1188
ADC_HTR1 .....1076
ADC_HTR2 .....1087
ADC_HTR3 .....1088
ADC_IER .....1060,1168
ADC_ISR .....1057,1166
ADC_JDRy .....1085,1192
ADC_JSQR .....1082,1188
ADC_LTR1 .....1075
ADC_LTR2 .....1086
ADC_LTR3 .....1087
ADC_OFRy .....1084,1191
ADC_PCSEL .....1075
ADC_SMPR1 .....1073,1181
ADC_SMPR2 .....1074,1181
ADC_SQR1 .....1077,1184
ADC_SQR2 .....1078,1185
ADC_SQR3 .....1079,1186
ADC_SQR4 .....1080,1187
ADC_TR1 .....1182
ADC_TR2 .....1183
ADC_TR3 .....1184
ADCx_CCR .....1092
ADCx_CDR .....1095
ADCx_CDR2 .....1095
ADCx_CSR .....1090
AP_BASE .....3138
AP_CSW .....3137
AP_IDR .....3139
AXI_COMP_ID_0 .....116
AXI_COMP_ID_1 .....117
AXI_COMP_ID_2 .....117
AXI_COMP_ID_3 .....118
AXI_INIx_FN_MOD .....122
AXI_INIx_FN_MOD_AHB .....121
AXI_INIx_FN_MOD2 .....120
AXI_INIx_READ_QOS .....121
AXI_INIx_WRITE_QOS .....122
AXI_PERIPH_ID_0114
AXI_PERIPH_ID_1115
AXI_PERIPH_ID_2115
AXI_PERIPH_ID_3116
AXI_PERIPH_ID_4114
AXI_TARGx_FN_MOD120
AXI_TARGx_FN_MOD_ISS_BM118
AXI_TARGx_FN_MOD_LB119
AXI_TARGx_FN_MOD2119

B

BDMA_CCRx662
BDMA_CM0ARx667
BDMA_CM1ARx668
BDMA_CNDTRx666
BDMA_CPARx666
BDMA_IFCR661
BDMA_ISR658

C

CEC_CFGR3109
CEC_CR3108
CEC_IER3113
CEC_ISR3111
CEC_RXDR3111
CEC_TXDR3111
COMP_CFGR11268
COMP_CFGR21270
COMP_ICFR1267
COMP_OR1268
COMP_SR1267
CORDIC_CSR794
CORDIC_RDATA797
CORDIC_WDATA796
CRC_CR777
CRC_DR776
CRC_IDR776
CRC_INIT778
CRC_POL778
CRS_CFGR490
CRS_CR489
CRS_ICR493
CRS_ISR491
CRYP_CR1493
CRYP_CSGCMCCMxR1505
CRYP_CSGCMxR1506
CRYP_DIN1496
CRYP_DMACR1497
CRYP_DOUT1497
CRYP_IMSCR1498
CRYP_IV0LR1503
CRYP_IV0RR1504
CRYP_IV1LR1504
CRYP_IV1RR1505
CRYP_K0LR1500
CRYP_K0RR1500
CRYP_K1LR1501
CRYP_K1RR1501
CRYP_K2LR1502
CRYP_K2RR1502
CRYP_K3LR1503
CRYP_K3RR1503
CRYP_MISR1499
CRYP_RISR1498
CRYP_SR1495
CSTF_AUTHSTAT3170
CSTF_CIDR03174
CSTF_CIDR13174
CSTF_CIDR23174
CSTF_CIDR33175
CSTF_CLAIMCLR3169
CSTF_CLAIMSET3168
CSTF_CTRL3167
CSTF_DEVID3171
CSTF_DEVTYPE3171
CSTF_LAR3169
CSTF_LSR3170
CSTF_PIDR03172
CSTF_PIDR13172
CSTF_PIDR23173
CSTF_PIDR33173
CSTF_PIDR43172
CSTF_PRIORITY3168
CTI_APPCLEAR3153
CTI_APPPULSE3154
CTI_APPSET3153
CTI_AUTHSTAT3160
CTI_CHINSTS3156
CTI_CHOUTSTS3157
CTI_CIDR03163
CTI_CIDR13164
CTI_CIDR23164
CTI_CIDR33164
CTI_CLAIMCLR3158
CTI_CLAIMSET3158
CTI_CONTROL3152
CTI_DEVID3160
CTI_DEVTYPE3161
CTI_GATE3157
CTI_INENx3154
CTI_INTACK3152
CTI_LAR3159
CTI_LSR3159
CTI_OUTENx3155
CTI_PIDR03162
CTI_PIDR13162
CTI_PIDR23162
CTI_PIDR33163
CTI_PIDR43161
CTI_TRGISTS3156
CTI_TRGOSTS3156
D
DAC_CCR1248
DAC_CR1237
DAC_DHR12L11241
DAC_DHR12L21243
DAC_DHR12LD1244
DAC_DHR12R11241
DAC_DHR12R21242
DAC_DHR12RD1244
DAC_DHR8R11242
DAC_DHR8R21243
DAC_DHR8RD1245
DAC_DOR11245
DAC_DOR21246
DAC_MCR1248
DAC_SHHR1251
DAC_SHRR1251
DAC_SHSR11250
DAC_SHSR21250
DAC_SR1246
DAC_SWTRGR1240
DBGMCU_APB1HFZ13232
DBGMCU_APB1LFZ13231
DBGMCU_APB2FZ13233
DBGMCU_APB3FZ13230
DBGMCU_APB4FZ13233
DBGMCU_CIDR03236
DBGMCU_CIDR13237
DBGMCU_CIDR23237
DBGMCU_CIDR33237
DBGMCU_CR3229
DBGMCU_IDC3229
DBGMCU_PIDR03235
DBGMCU_PIDR13235
DBGMCU_PIDR23235
DBGMCU_PIDR33236
DBGMCU_PIDR43234
DCMI_CR1365
DCMI_CWSIZE1373
DCMI_CWSTRT1373
DCMI_DR1374
DCMI_ESCR1371
DCMI_ESUR .....1372
DCMI_ICR .....1371
DCMI_IER .....1369
DCMI_MIS .....1370
DCMI_RIS .....1368
DCMI_SR .....1367
DFSDM_CHyAWSCDR .....1326
DFSDM_CHyCFGR1 .....1323
DFSDM_CHyCFGR2 .....1325
DFSDM_CHyDATINR .....1327
DFSDM_CHyDLYR .....1328
DFSDM_CHyWDATR .....1327
DFSDM_FLTxAWCFR .....1341
DFSDM_FLTxAWHTR .....1339
DFSDM_FLTxAWLTR .....1339
DFSDM_FLTxAWSR .....1340
DFSDM_FLTxCNVTIMR .....1342
DFSDM_FLTxCR1 .....1329
DFSDM_FLTxCR2 .....1332
DFSDM_FLTxEXMAX .....1341
DFSDM_FLTxEXMIN .....1342
DFSDM_FLTxFCR .....1336
DFSDM_FLTxICR .....1335
DFSDM_FLTxISR .....1333
DFSDM_FLTxJCHGR .....1336
DFSDM_FLTxJDATAR .....1337
DFSDM_FLTxRDATAR .....1338
DLYB_CFGR .....973
DLYB_CR .....972
DMA_HIFCR .....636
DMA_HISR .....635
DMA_LIFCR .....636
DMA_LISR .....634
DMA_SxCR .....637
DMA_SxFCR .....642
DMA_SxM0AR .....641
DMA_SxM1AR .....641
DMA_SxNDTR .....640
DMA_SxPAR .....641
DMA2D_AMTCR .....727
DMA2D_BGCLUTy .....728
DMA2D_BGC MAR .....722
DMA2D_BGCOLR .....721
DMA2D_BGMAR .....715
DMA2D_BGOR .....715
DMA2D_BGPFCCR .....719
DMA2D_CR .....710
DMA2D_FGCLUTy .....727
DMA2D_FGC MAR .....721
DMA2D_FGCOLR .....718
DMA2D_FGMAR .....714
DMA2D_FGOR .....714

DMA2D_FGPFCCR . . . . .716
DMA2D_IFCR . . . . .713
DMA2D_ISR . . . . .712
DMA2D_LWR . . . . .726
DMA2D_NLR . . . . .726
DMA2D_OCOLR . . . . .723
DMA2D_OMAR . . . . .725
DMA2D_OOR . . . . .725
DMA2D_OPFCCR . . . . .722
DMAMUX_CxCR . . . . .683
DMAMUX_RGCFR . . . . .689
DMAMUX1_CFR . . . . .686
DMAMUX1_CSR . . . . .685
DMAMUX1_CxCR . . . . .683
DMAMUX1_RGCFR . . . . .689
DMAMUX1_RGSR . . . . .688
DMAMUX1_RGxCR . . . . .687
DMAMUX2_CFR . . . . .686
DMAMUX2_CSR . . . . .685
DMAMUX2_CxCR . . . . .684
DMAMUX2_RGCFR . . . . .690
DMAMUX2_RGSR . . . . .689
DMAMUX2_RGxCR . . . . .687
DP_ABORT . . . . .3127
DP_CTRL/STAT . . . . .3128
DP_DLCR . . . . .3130
DP_DLPIDR . . . . .3131
DP_PIDR . . . . .3126
DP_RDBUFF . . . . .3133
DP_RESEND . . . . .3132
DP_SELECT . . . . .3132
DP_TARGETID . . . . .3131
DP_TARGETSEL . . . . .3133
DTS_CFGR1 . . . . .1209
DTS_DR . . . . .1211
DTS_ICIFR . . . . .1214
DTS_ITENR . . . . .1213
DTS_ITR1 . . . . .1211
DTS_OR . . . . .1215
DTS_RAMPVALR . . . . .1210
DTS_SR . . . . .1212
DTS_TOVALR1 . . . . .1210

E

ETF_AUTHSTAT . . . . .3192
ETF_BUFWM . . . . .3186
ETF_CBUFLVL . . . . .3185
ETF_CIDR0 . . . . .3195
ETF_CIDR1 . . . . .3196
ETF_CIDR2 . . . . .3196
ETF_CIDR3 . . . . .3196

ST logo
ST logo
ETF_CLAIMCLR .....3190
ETF_CLAIMSET .....3190
ETF_CTL .....3183
ETF_DEVID .....3192
ETF_DEVTYPE .....3193
ETF_FFCR .....3187
ETF_FFSR .....3186
ETF_LAR .....3191
ETF_LBUFLVL .....3185
ETF_LSR .....3191
ETF_MODE .....3184
ETF_PIDR0 .....3194
ETF_PIDR1 .....3194
ETF_PIDR2 .....3194
ETF_PIDR3 .....3195
ETF_PIDR4 .....3193
ETF_PSCR .....3189
ETF_RRD .....3181
ETF_RRP .....3181
ETF_RSZ .....3179
ETF_RWD .....3184
ETF_RWP .....3182
ETF_STS .....3180
ETF_TRG .....3182
ETH_DMACCARXBR .....2981
ETH_DMACCARXDR .....2980
ETH_DMACCATXBR .....2981
ETH_DMACCATXDR .....2980
ETH_DMACCR .....2966
ETH_DMACIER .....2975
ETH_DMACMFCR .....2984
ETH_DMACRXCR .....2969
ETH_DMACRXDLAR .....2972
ETH_DMACRXDTPR .....2974
ETH_DMACRXIWTR .....2979
ETH_DMACRXRLR .....2975
ETH_DMACSR .....2981
ETH_DMACTXCR .....2967
ETH_DMACTXDLAR .....2971
ETH_DMACTXDTPR .....2973
ETH_DMACTXRLR .....2974
ETH_DMADSR .....2965
ETH_DMAISR .....2965
ETH_DMAMR .....2962
ETH_DMASBMR .....2964
ETH_MAC1USTCR .....3028
ETH_MACA0HR .....3042
ETH_MACACR .....3074
ETH_MACARPAR .....3041
ETH_MACATSNR .....3075
ETH_MACATSSR .....3075
ETH_MACAxHR .....3043
ETH_MACAxLR . . . . .3042
ETH_MACCR . . . . .3000
ETH_MACCSRSWCR . . . . .3041
ETH_MACDR . . . . .3029
ETH_MACECR . . . . .3005
ETH_MACHT0R . . . . .3009
ETH_MACHT1R . . . . .3010
ETH_MACHWF0R . . . . .3030
ETH_MACHWF1R . . . . .3032
ETH_MACHWF2R . . . . .3035
ETH_MACHWF3R . . . . .3037
ETH_MACIER . . . . .3021
ETH_MACISR . . . . .3019
ETH_MACIVIR . . . . .3015
ETH_MACL3A00R . . . . .3058
ETH_MACL3A01R . . . . .3063
ETH_MACL3A10R . . . . .3058
ETH_MACL3A11R . . . . .3063
ETH_MACL3A20R . . . . .3059
ETH_MACL3A21R . . . . .3064
ETH_MACL3A30R . . . . .3059
ETH_MACL3A31R . . . . .3064
ETH_MACL3L4C0R . . . . .3055
ETH_MACL3L4C1R . . . . .3060
ETH_MACL4A0R . . . . .3057
ETH_MACL4A1R . . . . .3062
ETH_MACLCSR . . . . .3025
ETH_MACLETR . . . . .3028
ETH_MACLMIR . . . . .3085
ETH_MACLTCR . . . . .3027
ETH_MACMDIOAR . . . . .3038
ETH_MACMDIODR . . . . .3040
ETH_MACPCSR . . . . .3023
ETH_MACPFR . . . . .3006
ETH_MACPOCR . . . . .3083
ETH_MACPPSCR . . . . .3077,3079
ETH_MACPPSIR . . . . .3082
ETH_MACPPSTTNR . . . . .3081
ETH_MACPPSTTSR . . . . .3081
ETH_MACPPSWR . . . . .3083
ETH_MACQTXFCR . . . . .3016
ETH_MACRWKPFR . . . . .3025
ETH_MACRXFCR . . . . .3018
ETH_MACRXTXSR . . . . .3022
ETH_MACSPI0R . . . . .3084
ETH_MACSPI1R . . . . .3085
ETH_MACSPI2R . . . . .3085
ETH_MACSSIR . . . . .3067
ETH_MACSTNR . . . . .3069
ETH_MACSTNUR . . . . .3070
ETH_MACSTSR . . . . .3069
ETH_MACSTSUR . . . . .3070
ETH_MACTSAR .....3071
ETH_MACTSCR .....3065
ETH_MACTSEACR .....3076
ETH_MACTSECNR .....3077
ETH_MACTSIACR .....3076
ETH_MACTSICNR .....3077
ETH_MACTSSR .....3072
ETH_MACTXTSSNR .....3073
ETH_MACTXTSSSR .....3074
ETH_MACVHTR .....3013
ETH_MACVIR .....3014
ETH_MACVR .....3029
ETH_MACVTR .....3011
ETH_MACWTR .....3008
ETH_MMC_CONTROL .....3044
ETH_MMC_RX_INTERRUPT .....3045
ETH_MMC_RX_INTERRUPT_MASK .....3048
ETH_MMC_TX_INTERRUPT .....3046
ETH_MMC_TX_INTERRUPT_MASK .....3049
ETH_MTLISR .....2989
ETH_MTLOMR .....2988
ETH_MTLQICSR .....2992
ETH_MTLRXQDR .....2997
ETH_MTLRXQMPOCR .....2996
ETH_MTLRXQOMR .....2994
ETH_MTLTXQDR .....2991
ETH_MTLTXQOMR .....2989
ETH_MTLTXQUR .....2990
ETH_RX_ALIGNMENT_ERROR_PACKETS .....3052
ETH_RX_CRC_ERROR_PACKETS .....3051
ETH_RX_LPI_TRAN_CNTR .....3054
ETH_RX_LPI_USEC_CNTR .....3054
ETH_RX_UNICAST_PACKETS_GOOD .....3052
ETH_TX_LPI_TRAN_CNTR .....3053
ETH_TX_LPI_USEC_CNTR .....3053
ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS .....3050
ETH_TX_PACKET_COUNT_GOOD .....3051
ETH_TX_SINGLE_COLLISION_GOOD_PACKETS .....3050
EXTI_CPUEMR1 .....765
EXTI_CPUEMR2 .....767
EXTI_CPUEMR3 .....769
EXTI_CPUIMR1 .....764
EXTI_CPUIMR2 .....766
EXTI_CPUIMR3 .....768
EXTI_CPUPR1 .....765
EXTI_CPUPR2 .....767
EXTI_CPUPR3 .....769
EXTI_D3PCR1H .....757
EXTI_D3PCR1L .....757
EXTI_D3PCR2H .....761
EXTI_D3PCR2L .....761
EXTI_D3PCR3H .....764
EXTI_D3PMR1 .....756
EXTI_D3PMR2 .....760
EXTI_D3PMR3 .....763
EXTI_FTSR1 .....755
EXTI_FTSR2 .....759
EXTI_FTSR3 .....762
EXTI_RTSR1 .....755
EXTI_RTSR2 .....758
EXTI_RTSR3 .....762
EXTI_SWIER1 .....756
EXTI_SWIER2 .....759
EXTI_SWIER3 .....763
F
FDCAN_CCCR .....2569
FDCAN_CCU_CCFG .....2628
FDCAN_CCU_CREL .....2628
FDCAN_CCU_CSTAT .....2630
FDCAN_CCU_CWD .....2630
FDCAN_CCU_IE .....2632
FDCAN_CCU_IR .....2631
FDCAN_CREL .....2566
FDCAN_DBTP .....2566
FDCAN_ECR .....2574
FDCAN_ENDN .....2566
FDCAN_GFC .....2585
FDCAN_HPMS .....2588
FDCAN_IE .....2581
FDCAN_ILE .....2584
FDCAN_ILS .....2583
FDCAN_IR .....2578
FDCAN_NBTP .....2571
FDCAN_NDAT1 .....2588
FDCAN_NDAT2 .....2589
FDCAN_PSR .....2575
FDCAN_RWD .....2568
FDCAN_RXBC .....2591
FDCAN_RXESC .....2594
FDCAN_RXF0A .....2591
FDCAN_RXF0C .....2589
FDCAN_RXF0S .....2590
FDCAN_RXF1A .....2593
FDCAN_RXF1C .....2592
FDCAN_RXF1S .....2592
FDCAN_SIDFC .....2586
FDCAN_TDCR .....2577
FDCAN_TEST .....2567
FDCAN_TOCC .....2573
FDCAN_TOCV .....2574
FDCAN_TSCC .....2572
FDCAN_TSCV .....2572
FDCAN_TTCPT2623
FDCAN_TTCSM2624
FDCAN_TTCTC2623
FDCAN_TTGTP2613
FDCAN_TTIE2616
FDCAN_TTILS2618
FDCAN_TTIR2614
FDCAN_TTLGT2622
FDCAN_TTMLM2609
FDCAN_TTOCF2607
FDCAN_TTOCN2611
FDCAN_TTOST2620
FDCAN_TTRMC2606
FDCAN_TTTMC2606
FDCAN_TTTMK2613
FDCAN_TTTS2624
FDCAN_TURCF2610
FDCAN_TURNA2622
FDCAN_TXBAR2598
FDCAN_TXBC2595
FDCAN_TXBCF2600
FDCAN_TXBCIE2600
FDCAN_TXBCR2599
FDCAN_TXBRP2597
FDCAN_TXBTIE2600
FDCAN_TXBTO2599
FDCAN_TXEFA2602
FDCAN_TXEFC2601
FDCAN_TXEFS2602
FDCAN_TXESC2597
FDCAN_TXFQS2596
FDCAN_XIDAM2587
FDCAN_XIDFC2586
FLASH_ACR194
FLASH_BOOT_CUR213
FLASH_BOOT_PRG214
FLASH_CCR203
FLASH_CR195
FLASH_CRCCR214
FLASH_CRCDATAR217
FLASH_CRCEADDR216
FLASH_CRCSADDR216
FLASH_ECC_FAR217
FLASH_KEYR194
FLASH_OPTCCR209
FLASH_OPTCR204
FLASH_OPTKEYR195
FLASH_OPTSR_CUR205
FLASH_OPTSR_PRG207
FLASH_OPTSR2_CUR218
FLASH_OPTSR2_PRG218
FLASH_PRAR_CUR210
FLASH_PRAR_PRG .....210
FLASH_SCAR_CUR .....211
FLASH_SCAR_PRG .....212
FLASH_SR .....200
FLASH_WPSN_CUR .....212
FLASH_WPSN_PRG .....213
FMAC_CR .....821
FMAC_PARAM .....820
FMAC_RDATA .....824
FMAC_SR .....822
FMAC_WDATA .....823
FMAC_X1BUFCFG .....818
FMAC_X2BUFCFG .....818
FMAC_YBUFCFG .....819
FMC_BCRx .....867
FMC_BTRx .....871
FMC_BWTRx .....874
FMC_ECCR .....887
FMC_PATT .....886
FMC_PCR .....882
FMC_PMEM .....885
FMC_SDCMR .....902
FMC_SDCRx .....899
FMC_SDRTR .....903
FMC_SDSR .....905
FMC_SDTRx .....900
FMC_SR .....883

G

GPIOx_AFRH .....523
GPIOx_AFRL .....522
GPIOx_BSRR .....521
GPIOx_IDR .....520
GPIOx_LCKR .....521
GPIOx_MODER .....518
GPIOx_ODR .....520
GPIOx_OSPEEDR .....519
GPIOx_OTYPER .....518
GPIOx_PUPDR .....519

H

HASH_CR .....1523
HASH_CSRx .....1530
HASH_DIN .....1525
HASH_HRAx .....1527
HASH_HRx .....1527-1528
HASH_IMR .....1528
HASH_SR .....1529
HASH_STR .....1526
HSEM_CR .....505
HSEM_ICR .....504
HSEM_IER .....503
HSEM_ISR .....504
HSEM_KEYR .....505
HSEM_MISR .....504
HSEM_RLRx .....502
HSEM_Rx .....501

I

I2C_CR1 .....2040
I2C_CR2 .....2043
I2C_ICR .....2051
I2C_ISR .....2049
I2C_OAR1 .....2045
I2C_OAR2 .....2046
I2C_PECR .....2052
I2C_RXDR .....2053
I2C_TIMEOUTR .....2048
I2C_TIMINGR .....2047
I2C_TXDR .....2053
IWDG_KR .....1936
IWDG_PR .....1937
IWDG_RLR .....1938
IWDG_SR .....1939
IWDG_WINR .....1940

L

LPTIM_ARR .....1920
LPTIM_CFGR .....1915
LPTIM_CFGR2 .....1921
LPTIM_CMP .....1920
LPTIM_CNT .....1921
LPTIM_CR .....1918
LPTIM_ICR .....1914
LPTIM_IER .....1914
LPTIM_ISR .....1913
LPUART_BRR .....2182
LPUART_CR1 .....2171,2174
LPUART_CR2 .....2177
LPUART_CR3 .....2179
LPUART_ICR .....2191
LPUART_ISR .....2183,2188
LPUART_PRESC .....2193
LPUART_RDR .....2192
LPUART_RQR .....2183
LPUART_TDR .....2192
LTDC_AWCR .....1406
LTDC_BCCR .....1409
LTDC_BPCR .....1405
LTDC_CDSR .....1413
LTDC_CPSR .....1412
LTDC_GCR .....1407

LTDC_ICR ..... 1411
LTDC_IER ..... 1410
LTDC_ISR ..... 1411
LTDC_LIPCR ..... 1412
LTDC_LxBFCR ..... 1419
LTDC_LxCACR ..... 1418
LTDC_LxCFBAR ..... 1421
LTDC_LxCFBLNR ..... 1422
LTDC_LxCFBLR ..... 1421
LTDC_LxCKCR ..... 1417
LTDC_LxCLUTWR ..... 1422
LTDC_LxCR ..... 1414
LTDC_LxDCCR ..... 1419
LTDC_LxPFCR ..... 1417
LTDC_LxWHPER ..... 1414
LTDC_LxWVPER ..... 1416
LTDC_SRCR ..... 1409
LTDC_SSCR ..... 1404
LTDC_TWCR ..... 1407

M

M7_CPUROM_CIDR0 ..... 3246
M7_CPUROM_CIDR1 ..... 3246
M7_CPUROM_CIDR2 ..... 3246
M7_CPUROM_CIDR3 ..... 3247
M7_CPUROM_MEMTYPE ..... 3243
M7_CPUROM_PIDR0 ..... 3244
M7_CPUROM_PIDR1 ..... 3244
M7_CPUROM_PIDR2 ..... 3245
M7_CPUROM_PIDR3 ..... 3245
M7_CPUROM_PIDR4 ..... 3244
M7_DWT_CIDR0 ..... 3262
M7_DWT_CIDR1 ..... 3262
M7_DWT_CIDR2 ..... 3263
M7_DWT_CIDR3 ..... 3263
M7_DWT_COMPx ..... 3258
M7_DWT_CPICNT ..... 3256
M7_DWT_CTRL ..... 3254
M7_DWT_CYCCNT ..... 3256
M7_DWT_EXCCNT ..... 3256
M7_DWT_FOLDCNT ..... 3257
M7_DWT_FUNCTx ..... 3259
M7_DWT_LSUCNT ..... 3257
M7_DWT_MASKx ..... 3258
M7_DWT_PCSR ..... 3258
M7_DWT_PIDR0 ..... 3260
M7_DWT_PIDR1 ..... 3261
M7_DWT_PIDR2 ..... 3261
M7_DWT_PIDR3 ..... 3262
M7_DWT_PIDR4 ..... 3260
M7_DWT_SLP CNT ..... 3257

M7_ETM_AUTHSTAT3303
M7_ETM_CCCTL3288
M7_ETM_CIDR03307
M7_ETM_CIDR13307
M7_ETM_CIDR23308
M7_ETM_CIDR33308
M7_ETM_CLAIMCLR3302
M7_ETM_CLAIMSET3301
M7_ETM_CNTRLDV3290
M7_ETM_CONFIG3284
M7_ETM_DEVARCH3304
M7_ETM_DEVTYPE3304
M7_ETM_EVENTCTL03285
M7_ETM_EVENTCTL13285
M7_ETM_IDR03293
M7_ETM_IDR13294
M7_ETM_IDR103291
M7_ETM_IDR113292
M7_ETM_IDR123292
M7_ETM_IDR133292
M7_ETM_IDR23294
M7_ETM_IDR33295
M7_ETM_IDR43296
M7_ETM_IDR53297
M7_ETM_IDR83291
M7_ETM_IDR93291
M7_ETM_IMSPEC03293
M7_ETM_LAR3302
M7_ETM_LSR3303
M7_ETM_PDC3300
M7_ETM_PDS3301
M7_ETM_PIDR03305
M7_ETM_PIDR13306
M7_ETM_PIDR23306
M7_ETM_PIDR33307
M7_ETM_PIDR43305
M7_ETM_PRGCTL3282
M7_ETM_PROCSEL3283
M7_ETM_RSCTL23297
M7_ETM_RSCTL33298
M7_ETM_SSCC03299
M7_ETM_SSCS03299
M7_ETM_SSPIC03300
M7_ETM_STALLCTL3286
M7_ETM_STAT3283
M7_ETM_SYNCP3287
M7_ETM_TRACEID3288
M7_ETM_TSCTL3287
M7_ETM_VICTL3288
M7_ETM_VIPCSSCTL3290
M7_ETM_VISSCTL3289
M7_FPB_CIDR03279
M7_FPB_CIDR13279
M7_FPB_CIDR23280
M7_FPB_CIDR33280
M7_FPB_COMPx3276
M7_FPB_CTRL3275
M7_FPB_PIDR03277
M7_FPB_PIDR13278
M7_FPB_PIDR23278
M7_FPB_PIDR33279
M7_FPB_PIDR43277
M7_FPB_REMAP3276
M7_ITM_CIDR03272
M7_ITM_CIDR13272
M7_ITM_CIDR23272
M7_ITM_CIDR33273
M7_ITM_PIDR03270
M7_ITM_PIDR13270
M7_ITM_PIDR23271
M7_ITM_PIDR33271
M7_ITM_PIDR43270
M7_ITM_STIMx3267
M7_ITM_TCR3268
M7_ITM_TER3267
M7_ITM_TPR3268
M7_PPBROM_CIDR03251
M7_PPBROM_CIDR13251
M7_PPBROM_CIDR23251
M7_PPBROM_CIDR33252
M7_PPBROM_MEMTYPE3248
M7_PPBROM_PIDR03249
M7_PPBROM_PIDR13249
M7_PPBROM_PIDR23250
M7_PPBROM_PIDR33250
M7_PPBROM_PIDR43248
MDIOS_CLRFR2417
MDIOS_CR2414
MDIOS_CRDFR2416
MDIOS_CWRFR2415
MDIOS_DINRx2417
MDIOS_DOUTrx2418
MDIOS_RDFR2415
MDIOS_SR2416
MDIOS_WRFR2415
MDMA_CxBNDTR606
MDMA_CxBRUR608
MDMA_CxCR600
MDMA_CxDAR608
MDMA_CxESR599
MDMA_CxIFCR599
MDMA_CxISR597
MDMA_CxLAR609
MDMA_CxMAR611
MDMA_CxMDR .....611
MDMA_CxSAR .....607
MDMA_CxTBR .....610
MDMA_CxTCR .....602
MDMA_GISR0 .....597

O

OCTOSPI_ABR .....951
OCTOSPI_AR .....945
OCTOSPI_CCR .....948
OCTOSPI_CR .....937
OCTOSPI_DCR1 .....939
OCTOSPI_DCR2 .....941
OCTOSPI_DCR3 .....942
OCTOSPI_DCR4 .....943
OCTOSPI_DLR .....945
OCTOSPI_DR .....946
OCTOSPI_FCR .....944
OCTOSPI_HLCR .....959
OCTOSPI_IR .....951
OCTOSPI_LPTR .....952
OCTOSPI_PIR .....947
OCTOSPI_PSMAR .....947
OCTOSPI_PSMKR .....946
OCTOSPI_SR .....943
OCTOSPI_TCR .....950
OCTOSPI_WABR .....959
OCTOSPI_WCCR .....956
OCTOSPI_WIR .....958
OCTOSPI_WPABR .....955
OCTOSPI_WPCCR .....952
OCTOSPI_WPIR .....955
OCTOSPI_WPTCR .....954
OCTOSPI_WTCR .....958
OCTOSPIM_CR .....966
OCTOSPIM_PnCR .....966
OPAMP_OR .....1288
OPAMP1_CSR .....1285
OPAMP1_HSOTR .....1288
OPAMP1_OTR .....1287
OPAMP2_CSR .....1288
OPAMP2_HSOTR .....1291
OPAMP2_OTR .....1290
OTFDEC_ICR .....1549
OTFDEC_IER .....1550
OTFDEC_ISR .....1548
OTFDEC_RxCFGGR .....1544
OTFDEC_RxENDADDR .....1545
OTFDEC_RxKEYR0 .....1547
OTFDEC_RxKEYR1 .....1547
OTFDEC_RxKEYR2 .....1547
OTFDEC_RxKEYR31548
OTFDEC_RxNONCER01546
OTFDEC_RxNONCER11546
OTFDEC2_RxSTARTADDR1545
OTG_CID2692
OTG_DAINT2722
OTG_DAINTMSK2723
OTG_DCFG2715
OTG_DCTL2717
OTG_DEACHINT2726
OTG_DEACHINTMSK2727
OTG_DIEPCTLx2730
OTG_DIEPDMAx2734
OTG_DIEPEMPMSK2726
OTG_DIEPINTx2732
OTG_DIEPMSK2720
OTG_DIEPTSIZ02734
OTG_DIEPTSIZx2735
OTG_DIEPTXF02688
OTG_DIEPTXFx2696
OTG_DOEPCTL02736
OTG_DOEPCTLx2741
OTG_DOEPDMAx2741
OTG_DOEPINTx2738
OTG_DOEPMSK2721
OTG_DOEPTSIZ02740
OTG_DOEPTSIZx2744
OTG_DSTS2719
OTG_DTHRCTL2725
OTG_DTXFSTSx2735
OTG_DVBUSDIS2724
OTG_DVBUSPULSE2724
OTG_GAHBCFG2669
OTG_GCCFG2690
OTG_GINTMSK2680
OTG_GINTSTS2676
OTG_GLPMLCFG2692
OTG_GOTGCTL2664
OTG_GOTGINT2667
OTG_GRSTCTL2673
OTG_GRXFSIZ2688
OTG_GRXSTSP2686-2687
OTG_GRXSTSR2684-2685
OTG_GUSBCFG2670
OTG_HAINT2701
OTG_HAINTMSK2701
OTG_HCCHARx2705
OTG_HCDMABx2714
OTG_HCDMASGx2713
OTG_HCDMAx2713
OTG_HCFG2697
OTG_HCINTMSKx2708
OTG_HCINTx2707
OTG_HCSPLTx2706
OTG_HCTSIZSGx2711
OTG_HCTSIZx2710
OTG_HFIR2698
OTG_HFLBADDR2702
OTG_HFNUM2699
OTG_HNPTXFSIZ2688
OTG_HNPTXSTS2689
OTG_HPRT2702
OTG_HPTXFSIZ2696
OTG_HPTXSTS2700
OTG_HS_DIEPEACHMSK12727
OTG_HS_DOEPEACHMSK12728
OTG_PCGCTL2745

P

PSSI_CR1384
PSSI_DR1389
PSSI_ICR1388
PSSI_IER1387
PSSI_MIS1387
PSSI_RIS1386
PSSI_SR1386
PWR_CPUCR289
PWR_CR1283
PWR_CR2286
PWR_CR3287
PWR_CSR1285
PWR_D3CR291
PWR_WKUPCR292
PWR_WKUPEPR293
PWR_WKUPFR292

R

RAMECC_IER147
RAMECC_MxCR148
RAMECC_MxFAR149
RAMECC_MxFDRH150
RAMECC_MxFDRL149
RAMECC_MxFECR150
RAMECC_MxSR148
RCC_AHB1ENR434
RCC_AHB1LPENR455
RCC_AHB1RSTR411
RCC_AHB2ENR436
RCC_AHB2LPENR457
RCC_AHB3LPENR453
RCC_AHB3RSTR409
RCC_AHB4LPENR459
RCC_AHB4RSTR414
RCC_APB1HENR .....445
RCC_APB1HLPENR .....466
RCC_APB1HRSTR .....420
RCC_APB1LENR .....441
RCC_APB1LPENR .....462
RCC_APB1LRSTR .....417
RCC_APB2LPENR .....468
RCC_APB2RSTR .....422
RCC_APB3LPENR .....461
RCC_APB3RSTR .....416
RCC_APB4LPENR .....471
RCC_APB4RSTR .....424
RCC_BDCR .....406
RCC_CFGR) .....370
RCC_CICR .....404
RCC_CIER .....400
RCC_CIFR .....402
RCC_CR .....363
RCC_CRRCR .....368
RCC_CSICFGR .....369
RCC_CSR .....408
RCC_D1AHB1ENR .....432
RCC_D1APB1ENR .....440
RCC_D1CCIPR .....391
RCC_D1CFGR .....373
RCC_D2AHB2RSTR .....412
RCC_D2APB2ENR .....447
RCC_D2CCIP1R .....393
RCC_D2CCIP2R .....395
RCC_D2CFGR .....375
RCC_D3AHB1ENR .....438
RCC_D3AMR .....427
RCC_D3APB1ENR .....450
RCC_D3CCIPR .....397
RCC_D3CFGR .....376
RCC_GCR .....426
RCC_HSICFGR .....367
RCC_PLL1DIVR .....382
RCC_PLL1FRACR .....384
RCC_PLL2DIVR .....385
RCC_PLL2FRACR .....387
RCC_PLL3DIVR .....388
RCC_PLL3FRACR .....390
RCC_PLLCFGR .....379
RCC_PLLCKSELR .....377
RCC_RSR .....430
RNG_CR .....1436
RNG_DR .....1440
RNG_HTCR .....1440
RNG_SR .....1439
RTC_ALRMAR .....1972
RTC_ALRMASSR .....1983
RTC_ALRMBR .....1973
RTC_ALRMBSSR .....1984
RTC_BKPxR .....1985
RTC_CALR .....1979
RTC_CR .....1964
RTC_DR .....1962
RTC_ISR .....1967
RTC_OR .....1985
RTC_PRER .....1970
RTC_SHIFTTR .....1975
RTC_SSR .....1974
RTC_TAFCR .....1980
RTC_TR .....1961
RTC_TSDR .....1977
RTC_TSSSR .....1978
RTC_TSTR .....1976
RTC_WPR .....1974
RTC_WUTR .....1971

S

SAI_ACLRFR .....2335
SAI_ACR1 .....2314
SAI_ACR2 .....2320
SAI_ADR .....2337
SAI_AFRCCR .....2324
SAI_AIM .....2328
SAI_ASLOTR .....2326
SAI_ASR .....2331
SAI_BCLRFR .....2336
SAI_BCR1 .....2317
SAI_BCR2 .....2322
SAI_BDR .....2338
SAI_BFRCCR .....2325
SAI_BIM .....2330
SAI_BSLOTR .....2327
SAI_BSR .....2333
SAI_GCR .....2314
SAI_PDMCR .....2338
SAI_PDMPLY .....2339
SDMMC_ACKTIMER .....2495
SDMMC_ARGR .....2480
SDMMC_CLKCR .....2478
SDMMC_CMDR .....2480
SDMMC_DCNTR .....2486
SDMMC_DCTRL .....2485
SDMMC_DLENR .....2484
SDMMC_DTIMER .....2483
SDMMC_FIFORx .....2495
SDMMC_ICR .....2490
SDMMC_IDMABASE0R .....2497
SDMMC_IDMABASE1R .....2498
SDMMC_IDMABSIZER .....2497
SDMMC_IDMACTLRLR .....2496
SDMMC_MASKR .....2492
SDMMC_POWER .....2477
SDMMC_RESPCMDR .....2482
SDMMC_RESPxR .....2483
SDMMC_STAR .....2487
SMPMI_IER .....2402
SPDIFRX_CR .....2368
SPDIFRX_CSR .....2376
SPDIFRX_DIR .....2376
SPDIFRX_FMT0_DR .....2374
SPDIFRX_FMT1_DR .....2374
SPDIFRX_FMT2_DR .....2375
SPDIFRX_IFCR .....2373
SPDIFRX_IMR .....2370
SPDIFRX_SR .....2371
SPI_CFG1 .....2257
SPI_CFG2 .....2260
SPI_CR1 .....2255
SPI_CR2 .....2257
SPI_CRCPOLY .....2268
SPI_I2SCFGR .....2270
SPI_IER .....2262
SPI_IFCR .....2266
SPI_RXCRC .....2269
SPI_RXDR .....2267
SPI_SR .....2263
SPI_TXCRC .....2268
SPI_TXDR .....2267
SPI_UDRDR .....2270
SWO_AUTHSTAT .....3221
SWO_CIDR0 .....3225
SWO_CIDR1 .....3225
SWO_CIDR2 .....3226
SWO_CIDR3 .....3226
SWO_CLAIMCLR .....3219
SWO_CLAIMSET .....3219
SWO_CODR .....3217
SWO_DEVID .....3222
SWO_DEVTYPE .....3222
SWO_FFSR .....3218
SWO_LAR .....3220
SWO_LSR .....3220
SWO_PIDR0 .....3223
SWO_PIDR1 .....3224
SWO_PIDR2 .....3224
SWO_PIDR3 .....3225
SWO_PIDR4 .....3223
SWO_SPPR .....3218
SWPMI_BRR .....2399
SWPMI_CR .....2398
SWPMI_ICR .....2401
SWPMI_ISR .....2400
SWPMI_OR .....2405
SWPMI_RDR .....2404
SWPMI_RFL .....2404
SWPMI_TDR .....2404
SYSCFG_ADCBKP .....538
SYSCFG_CCCR .....537
SYSCFG_CCCSR .....536
SYSCFG_CCVR .....537
SYSCFG_CFGR .....533
SYSCFG_EXTICR1 .....530
SYSCFG_EXTICR2 .....530
SYSCFG_EXTICR3 .....532
SYSCFG_EXTICR4 .....533
SYSCFG_PKGR .....538
SYSCFG_PMCR .....528
SYSCFG_UR0 .....540
SYSCFG_UR11 .....543
SYSCFG_UR12 .....543
SYSCFG_UR13 .....544
SYSCFG_UR14 .....545
SYSCFG_UR15 .....546
SYSCFG_UR16 .....547
SYSCFG_UR17 .....547
SYSCFG_UR18 .....548
SYSCFG_UR2 .....540
SYSCFG_UR3 .....541
SYSCFG_UR4 .....541
SYSCFG_UR5 .....541
SYSCFG_UR6 .....542
SYSCFG_UR7 .....542
SYSROM_CIDR0 .....3145
SYSROM_CIDR1 .....3145
SYSROM_CIDR2 .....3146
SYSROM_CIDR3 .....3146
SYSROM_MEMTYPE .....3143
SYSROM_PIDR0 .....3143
SYSROM_PIDR1 .....3144
SYSROM_PIDR2 .....3144
SYSROM_PIDR3 .....3145
SYSROM_PIDR4 .....3143

T

TIM1_AF1 .....1647
TIM1_AF2 .....1649
TIM1_TISEL .....1654
TIM12_ARR .....1777
TIM12_CCER .....1775
TIM12_CCMR1 .....1771-1772
TIM12_CCR1 .....1777
TIM12_CCR2 .....1778
TIM12_CNT .....1776
TIM12_CR1 .....1765
TIM12_CR2 .....1766
TIM12_DIER .....1769
TIM12_EGR .....1770
TIM12_PSC .....1777
TIM12_SMCR .....1767
TIM12_SR .....1769
TIM12_TISEL .....1778
TIM13_TISEL .....1790
TIM14_TISEL .....1790
TIM15_AF1 .....1855
TIM15_ARR .....1849
TIM15_BDTR .....1851
TIM15_CCER .....1846
TIM15_CCMR1 .....1842-1843
TIM15_CCR1 .....1850
TIM15_CCR2 .....1851
TIM15_CNT .....1849
TIM15_CR1 .....1834
TIM15_CR2 .....1835
TIM15_DCR .....1854
TIM15_DIER .....1838
TIM15_DMAR .....1854
TIM15_EGR .....1841
TIM15_PSC .....1849
TIM15_RCR .....1850
TIM15_SMCR .....1837
TIM15_SR .....1839
TIM15_TISEL .....1856
TIM16_AF1 .....1877
TIM16_TISEL .....1878
TIM17_AF1 .....1879
TIM17_TISEL .....1880
TIM2_AF1 .....1729
TIM2_TISEL .....1731
TIM23_AF1 .....1730
TIM23_TISEL .....1735
TIM24_AF1 .....1731
TIM24_TISEL .....1735
TIM3_AF1 .....1729
TIM3_TISEL .....1732
TIM4_AF1 .....1730
TIM4_TISEL .....1733
TIM5_AF1 .....1730
TIM5_TISEL .....1734
TIM8_AF1 .....1650
TIM8_AF2 .....1652
TIM8_TISEL .....1654
TIMx_ARR .....1636,1725, 1789, 1871, 1894
TIMx_BDTR .....1639,1873
TIMx_CCER1633,1722, 1787, 1868
TIMx_CCMR11626-1627, 1716, 1718, 1784-1785, 1865-1866
TIMx_CCMR21630-1631, 1720-1721
TIMx_CCMR31645
TIMx_CCR11637,1725, 1789, 1872
TIMx_CCR21638,1726
TIMx_CCR31638,1726
TIMx_CCR41639,1727
TIMx_CCR51646
TIMx_CCR61647
TIMx_CNT1636,1723-1724, 1788, 1870, 1893
TIMx_CR11615,1706, 1781, 1860, 1890
TIMx_CR21616,1707, 1861, 1892
TIMx_DCR1643,1728, 1876
TIMx_DIER1621,1713, 1782, 1862, 1892
TIMx_DMAR1644,1728, 1876
TIMx_EGR1625,1715, 1783, 1864, 1893
TIMx_PSC1636,1724, 1789, 1871, 1894
TIMx_RCR1637,1872
TIMx_SMCR1619,1709
TIMx_SR1623,1714, 1782, 1863, 1893
TPIU_AUTHSTAT3209
TPIU_CIDR03213
TPIU_CIDR13213
TPIU_CIDR23214
TPIU_CIDR33214
TPIU_CLAIMCLR3208
TPIU_CLAIMSET3207
TPIU_CURPSIZE3200
TPIU_CURTPM3204
TPIU_DEVID3210
TPIU_DEVTYPE3211
TPIU_FFCR3206
TPIU_FFSR3205
TPIU_FSCR3207
TPIU_LAR3208
TPIU_LSR3209
TPIU_PIDR03211
TPIU_PIDR13212
TPIU_PIDR23212
TPIU_PIDR33213
TPIU_PIDR43211
TPIU_SUPPSIZE3200
TPIU_SUPTPM3203
TPIU_SUPTRGM3201
TPIU_TPRCR3205
TPIU_TRGCNT3202
TPIU_TRGMULT3202

U

USART_BRR2123
USART_CR1 .....409,2107, 2111
USART_CR2 .....2114
USART_CR3 .....2118
USART_GTPR .....2123
USART_ICR .....2137
USART_ISR .....2126,2132
USART_PRESC .....2140
USART_RDR .....2139
USART_RQR .....2125
USART_RTOR .....2124
USART_TDR .....2139
V
VREFBUF_CCR .....1257
VREFBUF_CSR .....1256
W
WWDG_CFR .....1930
WWDG_CR .....1929
WWDG_SR .....1930

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